From: Deepak M <m.deepak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Deepak M <m.deepak@intel.com>
Subject: [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT
Date: Fri, 4 Dec 2015 19:47:38 +0530 [thread overview]
Message-ID: <1449238659-12473-2-git-send-email-m.deepak@intel.com> (raw)
In-Reply-To: <1449238659-12473-1-git-send-email-m.deepak@intel.com>
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the
correct value here.
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd2699..009f474 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {
#define BXT_DSI_PLL_RATIO_MAX 0x7D
#define BXT_DSI_PLL_RATIO_MIN 0x22
#define BXT_DSI_PLL_RATIO_MASK 0xFF
-#define BXT_REF_CLOCK_KHZ 19500
+#define BXT_REF_CLOCK_KHZ 19200
#define BXT_DSI_PLL_ENABLE 0x46080
#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
--
1.9.1
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next prev parent reply other threads:[~2015-12-04 8:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-04 14:17 [PATCH 1/3] drm/i915: Add DPI FIFO empty status check Deepak M
2015-12-04 9:49 ` Ville Syrjälä
2015-12-04 9:55 ` Deepak, M
2015-12-04 16:11 ` [PATCH] " Deepak M
2015-12-04 11:26 ` Ville Syrjälä
2015-12-09 11:35 ` Deepak M
2015-12-09 14:34 ` Ville Syrjälä
2015-12-10 9:08 ` Daniel Vetter
2016-01-22 8:31 ` Jani Nikula
2015-12-04 14:17 ` Deepak M [this message]
2015-12-04 9:55 ` [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT Ville Syrjälä
2015-12-04 16:22 ` Daniel Vetter
2015-12-04 16:25 ` Deepak, M
2015-12-04 17:20 ` Ville Syrjälä
2015-12-04 14:17 ` [PATCH 3/3] drm/i915: Use the ceil value for the additional clk divider Deepak M
2015-12-04 11:51 ` Ville Syrjälä
2015-12-04 16:59 ` Deepak, M
2016-01-20 11:06 ` [PATCH 1/3] drm/i915: Add DPI FIFO empty status check Mika Kahola
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