[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Bartlomiej Zolnierkiewicz]

Hi,

This patch series adds generic cpufreq-dt driver support for
Exynos542x/5800 (using the new CPU clock type which allows it).

It has been tested on Exynos5422 based ODROID-XU3 Lite board.

Depends on:
- next-20151124 branch of linux-next kernel tree

Changes since v3:
- switched to using cpufreq-dt driver
- updated patch descriptions to cover Exynos5422 support
- added Acked-by from Sylwester to clock driver patches

Changes since v2:
- ported over next-20151124 branch
- integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3
  (from Anand Moon)
- added regulator supply properties for ODROID-XU3 Lite and
  ODROID-XU4 in patch #2
- ported CPU OPPs to operating-points-v2 (from Ben Gamari)
- added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben
  Gamari)
- added "cpufreq: arm-big-little: accept operating-points-v2
  nodes" patch (from Ben Gamari)
- renamed OPP nodes as opp@<opp-hz>

Changes since v1:
- added CPU cluster regulator supply properties to
  exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts,
  exynos5420-smdk5420.dts and exynos5800-peach-pi.dts

Changes over Thomas' original v12 code:
- split Exynos5420 and Exynos5800 support
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
- disabled cpufreq if big.LITTLE switcher support is enabled
- enhanced arm_big_little[_dt] driver with CPU cluster regulator
  support
- fixed CPU clock configuration data for Exynos5800
- fixed CPU operating points setup for Exynos5800
- added CPU cluster regulator supplies for ODROID-XU3 board

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (3):
  ARM: dts: Exynos542x/5800: add cluster regulator supply properties
  clk: samsung: exynos5422/5800: fix cpu clock configuration data
  ARM: dts: Exynos5800: fix CPU OPP

Ben Gamari (1):
  ARM: dts: Exynos5422: fix OPP tables

Thomas Abraham (4):
  clk: samsung: exynos5420: add cpu clock configuration data and
    instantiate cpu clock
  ARM: dts: Exynos5420: add CPU OPP and regulator supply property
  ARM: Exynos: use generic cpufreq driver for Exynos5420
  ARM: Exynos: use generic cpufreq driver for Exynos5422/5800

 arch/arm/boot/dts/exynos5420-arndale-octa.dts   |   8 ++
 arch/arm/boot/dts/exynos5420-peach-pit.dts      |   8 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |   8 ++
 arch/arm/boot/dts/exynos5420.dtsi               | 122 ++++++++++++++++++
 arch/arm/boot/dts/exynos5422-cpus.dtsi          |  10 ++
 arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts |   8 ++
 arch/arm/boot/dts/exynos5422-odroidxu3.dts      |   8 ++
 arch/arm/boot/dts/exynos5422-odroidxu4.dts      |   8 ++
 arch/arm/boot/dts/exynos5800-peach-pi.dts       |   8 ++
 arch/arm/boot/dts/exynos5800.dtsi               | 165 ++++++++++++++++++++++++
 arch/arm/mach-exynos/exynos.c                   |   4 +
 drivers/clk/samsung/clk-exynos5420.c            |  88 ++++++++++++-
 include/dt-bindings/clock/exynos5420.h          |   2 +
 13 files changed, 445 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Bartlomiej Zolnierkiewicz]

Hi,

This patch series adds generic cpufreq-dt driver support for
Exynos542x/5800 (using the new CPU clock type which allows it).

It has been tested on Exynos5422 based ODROID-XU3 Lite board.

Depends on:
- next-20151124 branch of linux-next kernel tree

Changes since v3:
- switched to using cpufreq-dt driver
- updated patch descriptions to cover Exynos5422 support
- added Acked-by from Sylwester to clock driver patches

Changes since v2:
- ported over next-20151124 branch
- integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3
  (from Anand Moon)
- added regulator supply properties for ODROID-XU3 Lite and
  ODROID-XU4 in patch #2
- ported CPU OPPs to operating-points-v2 (from Ben Gamari)
- added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben
  Gamari)
- added "cpufreq: arm-big-little: accept operating-points-v2
  nodes" patch (from Ben Gamari)
- renamed OPP nodes as opp@<opp-hz>

Changes since v1:
- added CPU cluster regulator supply properties to
  exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts,
  exynos5420-smdk5420.dts and exynos5800-peach-pi.dts

Changes over Thomas' original v12 code:
- split Exynos5420 and Exynos5800 support
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
- disabled cpufreq if big.LITTLE switcher support is enabled
- enhanced arm_big_little[_dt] driver with CPU cluster regulator
  support
- fixed CPU clock configuration data for Exynos5800
- fixed CPU operating points setup for Exynos5800
- added CPU cluster regulator supplies for ODROID-XU3 board

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (3):
  ARM: dts: Exynos542x/5800: add cluster regulator supply properties
  clk: samsung: exynos5422/5800: fix cpu clock configuration data
  ARM: dts: Exynos5800: fix CPU OPP

Ben Gamari (1):
  ARM: dts: Exynos5422: fix OPP tables

Thomas Abraham (4):
  clk: samsung: exynos5420: add cpu clock configuration data and
    instantiate cpu clock
  ARM: dts: Exynos5420: add CPU OPP and regulator supply property
  ARM: Exynos: use generic cpufreq driver for Exynos5420
  ARM: Exynos: use generic cpufreq driver for Exynos5422/5800

 arch/arm/boot/dts/exynos5420-arndale-octa.dts   |   8 ++
 arch/arm/boot/dts/exynos5420-peach-pit.dts      |   8 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |   8 ++
 arch/arm/boot/dts/exynos5420.dtsi               | 122 ++++++++++++++++++
 arch/arm/boot/dts/exynos5422-cpus.dtsi          |  10 ++
 arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts |   8 ++
 arch/arm/boot/dts/exynos5422-odroidxu3.dts      |   8 ++
 arch/arm/boot/dts/exynos5422-odroidxu4.dts      |   8 ++
 arch/arm/boot/dts/exynos5800-peach-pi.dts       |   8 ++
 arch/arm/boot/dts/exynos5800.dtsi               | 165 ++++++++++++++++++++++++
 arch/arm/mach-exynos/exynos.c                   |   4 +
 drivers/clk/samsung/clk-exynos5420.c            |  88 ++++++++++++-
 include/dt-bindings/clock/exynos5420.h          |   2 +
 13 files changed, 445 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Bartlomiej Zolnierkiewicz]

Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
 arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
 arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
 arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
 arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
 arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
 7 files changed, 56 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 4ecef69..4229641 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -52,6 +52,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &usbdrd_dwc3_1 {
 	dr_mode = "host";
 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..30f146b 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -676,6 +676,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &i2c_2 {
 	status = "okay";
 	samsung,i2c-sda-delay = <100>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..fdfe4e6 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -423,3 +423,11 @@
 &usbdrd_phy1 {
 	vbus-supply = <&usb301_vbus_reg>;
 };
+
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 2ae1cf4..0bfd981 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -54,6 +54,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &pwm {
 	/*
 	 * PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 432406d..b19561c 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -53,6 +53,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &i2c_0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 2faf886..bdc7106 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -32,6 +32,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &pwm {
 	/*
 	 * PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7b018e4..03ff1ceb 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -638,6 +638,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &i2c_2 {
 	status = "okay";
 	samsung,i2c-sda-delay = <100>;
-- 
1.9.1

[PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Bartlomiej Zolnierkiewicz]

Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
 arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
 arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
 arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
 arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
 arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
 7 files changed, 56 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 4ecef69..4229641 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -52,6 +52,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &usbdrd_dwc3_1 {
 	dr_mode = "host";
 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..30f146b 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -676,6 +676,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &i2c_2 {
 	status = "okay";
 	samsung,i2c-sda-delay = <100>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..fdfe4e6 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -423,3 +423,11 @@
 &usbdrd_phy1 {
 	vbus-supply = <&usb301_vbus_reg>;
 };
+
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 2ae1cf4..0bfd981 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -54,6 +54,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &pwm {
 	/*
 	 * PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 432406d..b19561c 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -53,6 +53,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &i2c_0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 2faf886..bdc7106 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -32,6 +32,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &pwm {
 	/*
 	 * PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7b018e4..03ff1ceb 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -638,6 +638,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &i2c_2 {
 	status = "okay";
 	samsung,i2c-sda-delay = <100>;
-- 
1.9.1

Re: [PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> Add cluster regulator supply properties as a preparation to
> adding generic cpufreq-dt driver support for Exynos542x and
> Exynos5800 based boards.
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

That's Javier's old email, not working any more. I think he same applies
to Mike's in CC-list.

> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
>  7 files changed, 56 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> index 4ecef69..4229641 100644
> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> @@ -52,6 +52,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &usbdrd_dwc3_1 {
>  	dr_mode = "host";
>  };
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 35cfb07..30f146b 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -676,6 +676,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index ac35aef..fdfe4e6 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -423,3 +423,11 @@
>  &usbdrd_phy1 {
>  	vbus-supply = <&usb301_vbus_reg>;
>  };
> +
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> index 2ae1cf4..0bfd981 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> @@ -54,6 +54,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> index 432406d..b19561c 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -53,6 +53,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &i2c_0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> index 2faf886..bdc7106 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> @@ -32,6 +32,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +

How about putting these Odroid changes in exynos5422-odroidxu3-common.dtsi?

Best regards,
Krzysztof

[PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> Add cluster regulator supply properties as a preparation to
> adding generic cpufreq-dt driver support for Exynos542x and
> Exynos5800 based boards.
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

That's Javier's old email, not working any more. I think he same applies
to Mike's in CC-list.

> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
>  7 files changed, 56 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> index 4ecef69..4229641 100644
> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> @@ -52,6 +52,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &usbdrd_dwc3_1 {
>  	dr_mode = "host";
>  };
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 35cfb07..30f146b 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -676,6 +676,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index ac35aef..fdfe4e6 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -423,3 +423,11 @@
>  &usbdrd_phy1 {
>  	vbus-supply = <&usb301_vbus_reg>;
>  };
> +
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> index 2ae1cf4..0bfd981 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> @@ -54,6 +54,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> index 432406d..b19561c 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -53,6 +53,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &i2c_0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> index 2faf886..bdc7106 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> @@ -32,6 +32,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +

How about putting these Odroid changes in exynos5422-odroidxu3-common.dtsi?

Best regards,
Krzysztof

Re: [PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Markus Reichl]

Hi,

tested the patch successfully on Odroid-XU4.

Thanks
--
Markus

Am 07.12.2015 um 19:18 schrieb Bartlomiej Zolnierkiewicz:
> Add cluster regulator supply properties as a preparation to
> adding generic cpufreq-dt driver support for Exynos542x and
> Exynos5800 based boards.
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
>  7 files changed, 56 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> index 4ecef69..4229641 100644
> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> @@ -52,6 +52,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &usbdrd_dwc3_1 {
>  	dr_mode = "host";
>  };
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 35cfb07..30f146b 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -676,6 +676,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index ac35aef..fdfe4e6 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -423,3 +423,11 @@
>  &usbdrd_phy1 {
>  	vbus-supply = <&usb301_vbus_reg>;
>  };
> +
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> index 2ae1cf4..0bfd981 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> @@ -54,6 +54,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> index 432406d..b19561c 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -53,6 +53,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &i2c_0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> index 2faf886..bdc7106 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> @@ -32,6 +32,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> index 7b018e4..03ff1ceb 100644
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> @@ -638,6 +638,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> 


-- 
Markus Reichl

[PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Markus Reichl]

Hi,

tested the patch successfully on Odroid-XU4.

Thanks
--
Markus

Am 07.12.2015 um 19:18 schrieb Bartlomiej Zolnierkiewicz:
> Add cluster regulator supply properties as a preparation to
> adding generic cpufreq-dt driver support for Exynos542x and
> Exynos5800 based boards.
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
>  7 files changed, 56 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> index 4ecef69..4229641 100644
> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> @@ -52,6 +52,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &usbdrd_dwc3_1 {
>  	dr_mode = "host";
>  };
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 35cfb07..30f146b 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -676,6 +676,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index ac35aef..fdfe4e6 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -423,3 +423,11 @@
>  &usbdrd_phy1 {
>  	vbus-supply = <&usb301_vbus_reg>;
>  };
> +
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> index 2ae1cf4..0bfd981 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> @@ -54,6 +54,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> index 432406d..b19561c 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -53,6 +53,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &i2c_0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> index 2faf886..bdc7106 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> @@ -32,6 +32,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> index 7b018e4..03ff1ceb 100644
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> @@ -638,6 +638,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> 


-- 
Markus Reichl

Re: [PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties

[Markus Reichl]

Hi,

tested the patch successfully on Odroid-XU4.

Thanks
--
Markus

Am 07.12.2015 um 19:18 schrieb Bartlomiej Zolnierkiewicz:
> Add cluster regulator supply properties as a preparation to
> adding generic cpufreq-dt driver support for Exynos542x and
> Exynos5800 based boards.
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420-arndale-octa.dts   | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-peach-pit.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts       | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5422-odroidxu4.dts      | 8 ++++++++
>  arch/arm/boot/dts/exynos5800-peach-pi.dts       | 8 ++++++++
>  7 files changed, 56 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> index 4ecef69..4229641 100644
> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> @@ -52,6 +52,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &usbdrd_dwc3_1 {
>  	dr_mode = "host";
>  };
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 35cfb07..30f146b 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -676,6 +676,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index ac35aef..fdfe4e6 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -423,3 +423,11 @@
>  &usbdrd_phy1 {
>  	vbus-supply = <&usb301_vbus_reg>;
>  };
> +
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> index 2ae1cf4..0bfd981 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> @@ -54,6 +54,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> index 432406d..b19561c 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -53,6 +53,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &i2c_0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> index 2faf886..bdc7106 100644
> --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
> @@ -32,6 +32,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
>  &pwm {
>  	/*
>  	 * PWM 0 -- fan
> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> index 7b018e4..03ff1ceb 100644
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> @@ -638,6 +638,14 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&buck2_reg>;
> +};
> +
> +&cpu4 {
> +	cpu-supply = <&buck6_reg>;
> +};
> +
>  &i2c_2 {
>  	status = "okay";
>  	samsung,i2c-sda-delay = <100>;
> 


-- 
Markus Reichl

[PATCH v4 2/8] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c   | 58 ++++++++++++++++++++++++++++++++--
 include/dt-bindings/clock/exynos5420.h |  2 ++
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 #define APLL_LOCK		0x0
 #define APLL_CON0		0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 	MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 
-	MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
-	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+	MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 
 	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
 		KPLL_CON0, NULL),
 };
 
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)			\
+		((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\
+		 ((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
+	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
+	{  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
+	{  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
+	{  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
+	{  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
+	{  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk)					\
+		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
+	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
+	{ 1100000, E5420_KFC_DIV(3, 5, 2), },
+	{ 1000000, E5420_KFC_DIV(3, 5, 2), },
+	{  900000, E5420_KFC_DIV(3, 5, 2), },
+	{  800000, E5420_KFC_DIV(3, 5, 2), },
+	{  700000, E5420_KFC_DIV(3, 4, 2), },
+	{  600000, E5420_KFC_DIV(3, 4, 2), },
+	{  500000, E5420_KFC_DIV(3, 4, 2), },
+	{  400000, E5420_KFC_DIV(3, 3, 2), },
+	{  300000, E5420_KFC_DIV(3, 3, 2), },
+	{  200000, E5420_KFC_DIV(3, 3, 2), },
+	{  0 },
+};
+
 static const struct of_device_id ext_clk_match[] __initconst = {
 	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
 	{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
 				ARRAY_SIZE(exynos5800_gate_clks));
 	}
 
+	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+		mout_cpu_p[0], mout_cpu_p[1], 0x200,
+		exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+		mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+		exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
 	exynos5420_clk_sleep_init();
 
 	samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -25,6 +25,8 @@
 #define CLK_FOUT_MPLL		10
 #define CLK_FOUT_BPLL		11
 #define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_UART0		128
-- 
1.9.1

[PATCH v4 2/8] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c   | 58 ++++++++++++++++++++++++++++++++--
 include/dt-bindings/clock/exynos5420.h |  2 ++
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 #define APLL_LOCK		0x0
 #define APLL_CON0		0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 	MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 
-	MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
-	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+	MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 
 	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
 		KPLL_CON0, NULL),
 };
 
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)			\
+		((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\
+		 ((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
+	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
+	{  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
+	{  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
+	{  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
+	{  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
+	{  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
+	{  0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk)					\
+		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
+	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
+	{ 1100000, E5420_KFC_DIV(3, 5, 2), },
+	{ 1000000, E5420_KFC_DIV(3, 5, 2), },
+	{  900000, E5420_KFC_DIV(3, 5, 2), },
+	{  800000, E5420_KFC_DIV(3, 5, 2), },
+	{  700000, E5420_KFC_DIV(3, 4, 2), },
+	{  600000, E5420_KFC_DIV(3, 4, 2), },
+	{  500000, E5420_KFC_DIV(3, 4, 2), },
+	{  400000, E5420_KFC_DIV(3, 3, 2), },
+	{  300000, E5420_KFC_DIV(3, 3, 2), },
+	{  200000, E5420_KFC_DIV(3, 3, 2), },
+	{  0 },
+};
+
 static const struct of_device_id ext_clk_match[] __initconst = {
 	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
 	{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
 				ARRAY_SIZE(exynos5800_gate_clks));
 	}
 
+	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+		mout_cpu_p[0], mout_cpu_p[1], 0x200,
+		exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+		mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+		exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
 	exynos5420_clk_sleep_init();
 
 	samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -25,6 +25,8 @@
 #define CLK_FOUT_MPLL		10
 #define CLK_FOUT_BPLL		11
 #define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_UART0		128
-- 
1.9.1

[PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

For Exynos5420 platforms, add CPU operating points for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.

Changes by Bartlomiej:
- split Exynos5420 support from the original patch

Changes by Ben Gamari:
- Port to operating-points-v2

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 122 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..f8f70a5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
 		usbdrdphy1 = &usbdrd_phy1;
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00@1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <1212500>;
+			clock-latency-ns = <140000>;
+		};
+		opp02@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <1175000>;
+			clock-latency-ns = <140000>;
+		};
+		opp03@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1137500>;
+			clock-latency-ns = <140000>;
+		};
+		opp04@1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <1112500>;
+			clock-latency-ns = <140000>;
+		};
+		opp05@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1062500>;
+			clock-latency-ns = <140000>;
+		};
+		opp06@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1037500>;
+			clock-latency-ns = <140000>;
+		};
+		opp07@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1012500>;
+			clock-latency-ns = <140000>;
+		};
+		opp08@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = < 987500>;
+			clock-latency-ns = <140000>;
+		};
+		opp09@900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = < 962500>;
+			clock-latency-ns = <140000>;
+		};
+		opp10@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = < 937500>;
+			clock-latency-ns = <140000>;
+		};
+		opp11@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = < 912500>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
+	cpu1_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1275000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1212500>;
+			clock-latency-ns = <140000>;
+		};
+		opp02@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1162500>;
+			clock-latency-ns = <140000>;
+		};
+		opp03@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1112500>;
+			clock-latency-ns = <140000>;
+		};
+		opp04@900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1062500>;
+			clock-latency-ns = <140000>;
+		};
+		opp05@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1025000>;
+			clock-latency-ns = <140000>;
+		};
+		opp06@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <975000>;
+			clock-latency-ns = <140000>;
+		};
+		opp07@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <937500>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -58,8 +168,11 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu-cluster.0";
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu1: cpu@1 {
@@ -68,6 +181,7 @@
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu2: cpu@2 {
@@ -76,6 +190,7 @@
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu3: cpu@3 {
@@ -84,14 +199,18 @@
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu4: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-names = "cpu-cluster.1";
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 
 		cpu5: cpu@101 {
@@ -100,6 +219,7 @@
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 
 		cpu6: cpu@102 {
@@ -108,6 +228,7 @@
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 
 		cpu7: cpu@103 {
@@ -116,6 +237,7 @@
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 	};
 
-- 
1.9.1

[PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

For Exynos5420 platforms, add CPU operating points for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.

Changes by Bartlomiej:
- split Exynos5420 support from the original patch

Changes by Ben Gamari:
- Port to operating-points-v2

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 122 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..f8f70a5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
 		usbdrdphy1 = &usbdrd_phy1;
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 at 1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01 at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <1212500>;
+			clock-latency-ns = <140000>;
+		};
+		opp02 at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <1175000>;
+			clock-latency-ns = <140000>;
+		};
+		opp03 at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1137500>;
+			clock-latency-ns = <140000>;
+		};
+		opp04 at 1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <1112500>;
+			clock-latency-ns = <140000>;
+		};
+		opp05 at 1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1062500>;
+			clock-latency-ns = <140000>;
+		};
+		opp06 at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1037500>;
+			clock-latency-ns = <140000>;
+		};
+		opp07 at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1012500>;
+			clock-latency-ns = <140000>;
+		};
+		opp08 at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = < 987500>;
+			clock-latency-ns = <140000>;
+		};
+		opp09 at 900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = < 962500>;
+			clock-latency-ns = <140000>;
+		};
+		opp10 at 800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = < 937500>;
+			clock-latency-ns = <140000>;
+		};
+		opp11 at 700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = < 912500>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
+	cpu1_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 at 1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1275000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01 at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1212500>;
+			clock-latency-ns = <140000>;
+		};
+		opp02 at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1162500>;
+			clock-latency-ns = <140000>;
+		};
+		opp03 at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1112500>;
+			clock-latency-ns = <140000>;
+		};
+		opp04 at 900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1062500>;
+			clock-latency-ns = <140000>;
+		};
+		opp05 at 800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1025000>;
+			clock-latency-ns = <140000>;
+		};
+		opp06 at 700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <975000>;
+			clock-latency-ns = <140000>;
+		};
+		opp07 at 600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <937500>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -58,8 +168,11 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu-cluster.0";
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu1: cpu at 1 {
@@ -68,6 +181,7 @@
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu2: cpu at 2 {
@@ -76,6 +190,7 @@
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu3: cpu at 3 {
@@ -84,14 +199,18 @@
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu4: cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-names = "cpu-cluster.1";
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 
 		cpu5: cpu at 101 {
@@ -100,6 +219,7 @@
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 
 		cpu6: cpu at 102 {
@@ -108,6 +228,7 @@
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 
 		cpu7: cpu at 103 {
@@ -116,6 +237,7 @@
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cpu1_opp_table>;
 		};
 	};
 
-- 
1.9.1

Re: [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Viresh Kumar]

On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00@1300000000 {

This should be just opp@1300000000, you don't need 00/01/02... anymore
now. Same for the other patch as well..

Fix that in other patches in this series and you also need to fix it
for arch/arm/boot/dts/exynos4212.dtsi based on what I see in
linux-next.

-- 
viresh

[PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Viresh Kumar]

On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00 at 1300000000 {

This should be just opp at 1300000000, you don't need 00/01/02... anymore
now. Same for the other patch as well..

Fix that in other patches in this series and you also need to fix it
for arch/arm/boot/dts/exynos4212.dtsi based on what I see in
linux-next.

-- 
viresh

Re: [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Viresh Kumar]

On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00@1300000000 {

This should be just opp@1300000000, you don't need 00/01/02... anymore
now. Same for the other patch as well..

Fix that in other patches in this series and you also need to fix it
for arch/arm/boot/dts/exynos4212.dtsi based on what I see in
linux-next.

-- 
viresh

Re: [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
> 
> For Exynos5420 platforms, add CPU operating points for
> migrating from Exynos specific cpufreq driver to using
> generic cpufreq driver.
> 
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
> 
> Changes by Ben Gamari:
> - Port to operating-points-v2
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>

Sachin's address does not work neither.

> Cc: Thomas Abraham <thomas.ab@samsung.com>

Thomas' SoB disappeared.

I see that you directly re-used Thomas' values for voltages and
frequencies. For Exynos5420 we could go down to 200 MHz (for both cores)
but this can be fine-tuned per-board later.

Best regards,
Krzysztof


> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 122 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 122 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 48a0a55..f8f70a5 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -50,6 +50,116 @@
>  		usbdrdphy1 = &usbdrd_phy1;
>  	};
>  
> +	cpu0_opp_table: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00@1800000000 {
> +			opp-hz = /bits/ 64 <1800000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <1212500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <1175000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <1137500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04@1400000000 {
> +			opp-hz = /bits/ 64 <1400000000>;
> +			opp-microvolt = <1112500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05@1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1062500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06@1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1037500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07@1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1012500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp08@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = < 987500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp09@900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = < 962500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp10@800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = < 937500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp11@700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = < 912500>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00@1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1275000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01@1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1212500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02@1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1162500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1112500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04@900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1062500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05@800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <1025000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06@700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <975000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07@600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <937500>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -58,8 +168,11 @@
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0x0>;
> +			clocks = <&clock CLK_ARM_CLK>;
> +			clock-names = "cpu-cluster.0";
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -68,6 +181,7 @@
>  			reg = <0x1>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu2: cpu@2 {
> @@ -76,6 +190,7 @@
>  			reg = <0x2>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu3: cpu@3 {
> @@ -84,14 +199,18 @@
>  			reg = <0x3>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu4: cpu@100 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x100>;
> +			clocks = <&clock CLK_KFC_CLK>;
> +			clock-names = "cpu-cluster.1";
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  
>  		cpu5: cpu@101 {
> @@ -100,6 +219,7 @@
>  			reg = <0x101>;
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  
>  		cpu6: cpu@102 {
> @@ -108,6 +228,7 @@
>  			reg = <0x102>;
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  
>  		cpu7: cpu@103 {
> @@ -116,6 +237,7 @@
>  			reg = <0x103>;
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  	};
>  
> 

[PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
> 
> For Exynos5420 platforms, add CPU operating points for
> migrating from Exynos specific cpufreq driver to using
> generic cpufreq driver.
> 
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
> 
> Changes by Ben Gamari:
> - Port to operating-points-v2
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>

Sachin's address does not work neither.

> Cc: Thomas Abraham <thomas.ab@samsung.com>

Thomas' SoB disappeared.

I see that you directly re-used Thomas' values for voltages and
frequencies. For Exynos5420 we could go down to 200 MHz (for both cores)
but this can be fine-tuned per-board later.

Best regards,
Krzysztof


> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 122 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 122 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 48a0a55..f8f70a5 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -50,6 +50,116 @@
>  		usbdrdphy1 = &usbdrd_phy1;
>  	};
>  
> +	cpu0_opp_table: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00 at 1800000000 {
> +			opp-hz = /bits/ 64 <1800000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01 at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <1212500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02 at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <1175000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03 at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <1137500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04 at 1400000000 {
> +			opp-hz = /bits/ 64 <1400000000>;
> +			opp-microvolt = <1112500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05 at 1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1062500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06 at 1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1037500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07 at 1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1012500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp08 at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = < 987500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp09 at 900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = < 962500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp10 at 800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = < 937500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp11 at 700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = < 912500>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00 at 1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1275000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01 at 1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1212500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02 at 1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1162500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03 at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1112500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04 at 900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1062500>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05 at 800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <1025000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06 at 700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <975000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07 at 600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <937500>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -58,8 +168,11 @@
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0x0>;
> +			clocks = <&clock CLK_ARM_CLK>;
> +			clock-names = "cpu-cluster.0";
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu1: cpu at 1 {
> @@ -68,6 +181,7 @@
>  			reg = <0x1>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu2: cpu at 2 {
> @@ -76,6 +190,7 @@
>  			reg = <0x2>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu3: cpu at 3 {
> @@ -84,14 +199,18 @@
>  			reg = <0x3>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>  		};
>  
>  		cpu4: cpu at 100 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a7";
>  			reg = <0x100>;
> +			clocks = <&clock CLK_KFC_CLK>;
> +			clock-names = "cpu-cluster.1";
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  
>  		cpu5: cpu at 101 {
> @@ -100,6 +219,7 @@
>  			reg = <0x101>;
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  
>  		cpu6: cpu at 102 {
> @@ -108,6 +228,7 @@
>  			reg = <0x102>;
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  
>  		cpu7: cpu at 103 {
> @@ -116,6 +237,7 @@
>  			reg = <0x103>;
>  			clock-frequency = <1000000000>;
>  			cci-control-port = <&cci_control0>;
> +			operating-points-v2 = <&cpu1_opp_table>;
>  		};
>  	};
>  
> 

[PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
- switch to using cpufreq-dt driver

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/mach-exynos/exynos.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
 	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
 	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
 	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
 	{ /* sentinel */ }
 };
 
-- 
1.9.1

[PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
- switch to using cpufreq-dt driver

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/mach-exynos/exynos.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
 	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
 	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
 	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
 	{ /* sentinel */ }
 };
 
-- 
1.9.1

Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
> 
> The new CPU clock type allows the use of cpufreq-dt driver
> for Exynos5420.
> 
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
> - disable cpufreq if big.LITTLE switcher support is enabled
> - switch to using cpufreq-dt driver
> 
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/mach-exynos/exynos.c | 3 +++
>  1 file changed, 3 insertions(+)

I think this is actually now your patch, not Thomas any more. :)

> 
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 1c47aee..7a89c9d 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
>  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
>  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
>  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> +#ifndef CONFIG_BL_SWITCHER
> +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
> +#endif

Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?

Best regards,
Krzysztof

[PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
> 
> The new CPU clock type allows the use of cpufreq-dt driver
> for Exynos5420.
> 
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
> - disable cpufreq if big.LITTLE switcher support is enabled
> - switch to using cpufreq-dt driver
> 
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/mach-exynos/exynos.c | 3 +++
>  1 file changed, 3 insertions(+)

I think this is actually now your patch, not Thomas any more. :)

> 
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 1c47aee..7a89c9d 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
>  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
>  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
>  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> +#ifndef CONFIG_BL_SWITCHER
> +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
> +#endif

Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?

Best regards,
Krzysztof

Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Bartlomiej Zolnierkiewicz]

Hi,

On Tuesday, December 08, 2015 04:36:12 PM Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> > From: Thomas Abraham <thomas.ab@samsung.com>
> > 
> > The new CPU clock type allows the use of cpufreq-dt driver
> > for Exynos5420.
> > 
> > Changes by Bartlomiej:
> > - split Exynos5420 support from the original patch
> > - disable cpufreq if big.LITTLE switcher support is enabled
> > - switch to using cpufreq-dt driver
> > 
> > Cc: Tomasz Figa <tomasz.figa@gmail.com>
> > Cc: Kukjin Kim <kgene.kim@samsung.com>
> > Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> > Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> > Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> > ---
> >  arch/arm/mach-exynos/exynos.c | 3 +++
> >  1 file changed, 3 insertions(+)
> 
> I think this is actually now your patch, not Thomas any more. :)

It seems so, I'll update the patch.

> > diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> > index 1c47aee..7a89c9d 100644
> > --- a/arch/arm/mach-exynos/exynos.c
> > +++ b/arch/arm/mach-exynos/exynos.c
> > @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
> >  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
> >  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
> >  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> > +#ifndef CONFIG_BL_SWITCHER
> > +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
> > +#endif
> 
> Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?

ARM_DT_BL_CPUFREQ is not relevant here (it requires to be explicitly
enabled by platform code, just like cpufreq-dt) and the dependency on
!BL_SWITCHER is needed because when BL_SWITCHER is enabled big and
LITTLE cores are grouped in pairs and presented as "virtual" CPUs to
the system:

...
[    0.002630] CPU0: update cpu_capacity 448
[    0.002646] CPU0: thread -1, cpu 0, socket 1, mpidr 80000100
[    0.002835] Setting up static identity map for 0x40008280 - 0x400082d8
[    0.003106] ARM CCI driver probed
[    0.003351] Exynos MCPM support installed
[    0.045350] CPU1: update cpu_capacity 448
[    0.045358] CPU1: thread -1, cpu 1, socket 1, mpidr 80000101
[    0.060326] CPU2: update cpu_capacity 448
[    0.060334] CPU2: thread -1, cpu 2, socket 1, mpidr 80000102
[    0.075326] CPU3: update cpu_capacity 448
[    0.075334] CPU3: thread -1, cpu 3, socket 1, mpidr 80000103
[    0.090337] CPU4: update cpu_capacity 1535
[    0.090345] CPU4: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.105314] CPU5: update cpu_capacity 1535
[    0.105321] CPU5: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.120338] CPU6: update cpu_capacity 1535
[    0.120345] CPU6: thread -1, cpu 2, socket 0, mpidr 80000002
[    0.135330] CPU7: update cpu_capacity 1535
[    0.135338] CPU7: thread -1, cpu 3, socket 0, mpidr 80000003
[    0.135466] Brought up 8 CPUs
...
[    3.027498] big.LITTLE switcher initializing
[    3.031761] CPU0 paired with CPU7
[    3.035055] CPU1 paired with CPU6
[    3.038332] CPU2 paired with CPU5
[    3.041598] CPU3 paired with CPU4
[    3.044930] GIC ID for CPU 0 cluster 1 is 4
[    3.049078] GIC ID for CPU 1 cluster 1 is 5
[    3.053258] GIC ID for CPU 2 cluster 1 is 6
[    3.057370] GIC ID for CPU 3 cluster 1 is 7
[    3.061558] GIC ID for CPU 0 cluster 0 is 0
[    3.083336] IRQ53 no longer affine to CPU4
[    3.084336] CPU4: shutdown
[    3.107059] GIC ID for CPU 1 cluster 0 is 1
[    3.123303] IRQ54 no longer affine to CPU5
[    3.124213] CPU5: shutdown
[    3.146387] GIC ID for CPU 2 cluster 0 is 2
[    3.158143] cpu cpu0: 1100 MHz, 1250 mV --> 900 MHz, 1100 mV
[    3.168228] IRQ55 no longer affine to CPU6
[    3.169135] CPU6: shutdown
[    3.191485] GIC ID for CPU 3 cluster 0 is 3
[    3.208264] IRQ56 no longer affine to CPU7
[    3.209166] CPU7: shutdown
[    3.236752] big.LITTLE switcher initialized
...

Only arm_big_little_dt driver knows how to handle this setup
correctly.  cpufreq-dt just treats "virtual" CPUs as a LITTLE
ones.  Thus when "virtual CPU"'s current core is switched to
a big one cpufreq-dt is unable to update its voltage.

[ I tried using BL_SWITCHER_DUMMY_IF functionality to simulate
  this with:

	echo 0,0 > /dev/b.L_switcher

  but it doesn't seem to work for some reason (from looking at
  arch/arm/common/bL_switcher_dummy_if.c code it seems that at
  least "bL_switcher_write" line should get logged but it does
  not happen). ]

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

[PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Bartlomiej Zolnierkiewicz]

Hi,

On Tuesday, December 08, 2015 04:36:12 PM Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> > From: Thomas Abraham <thomas.ab@samsung.com>
> > 
> > The new CPU clock type allows the use of cpufreq-dt driver
> > for Exynos5420.
> > 
> > Changes by Bartlomiej:
> > - split Exynos5420 support from the original patch
> > - disable cpufreq if big.LITTLE switcher support is enabled
> > - switch to using cpufreq-dt driver
> > 
> > Cc: Tomasz Figa <tomasz.figa@gmail.com>
> > Cc: Kukjin Kim <kgene.kim@samsung.com>
> > Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> > Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> > Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> > ---
> >  arch/arm/mach-exynos/exynos.c | 3 +++
> >  1 file changed, 3 insertions(+)
> 
> I think this is actually now your patch, not Thomas any more. :)

It seems so, I'll update the patch.

> > diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> > index 1c47aee..7a89c9d 100644
> > --- a/arch/arm/mach-exynos/exynos.c
> > +++ b/arch/arm/mach-exynos/exynos.c
> > @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
> >  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
> >  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
> >  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> > +#ifndef CONFIG_BL_SWITCHER
> > +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
> > +#endif
> 
> Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?

ARM_DT_BL_CPUFREQ is not relevant here (it requires to be explicitly
enabled by platform code, just like cpufreq-dt) and the dependency on
!BL_SWITCHER is needed because when BL_SWITCHER is enabled big and
LITTLE cores are grouped in pairs and presented as "virtual" CPUs to
the system:

...
[    0.002630] CPU0: update cpu_capacity 448
[    0.002646] CPU0: thread -1, cpu 0, socket 1, mpidr 80000100
[    0.002835] Setting up static identity map for 0x40008280 - 0x400082d8
[    0.003106] ARM CCI driver probed
[    0.003351] Exynos MCPM support installed
[    0.045350] CPU1: update cpu_capacity 448
[    0.045358] CPU1: thread -1, cpu 1, socket 1, mpidr 80000101
[    0.060326] CPU2: update cpu_capacity 448
[    0.060334] CPU2: thread -1, cpu 2, socket 1, mpidr 80000102
[    0.075326] CPU3: update cpu_capacity 448
[    0.075334] CPU3: thread -1, cpu 3, socket 1, mpidr 80000103
[    0.090337] CPU4: update cpu_capacity 1535
[    0.090345] CPU4: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.105314] CPU5: update cpu_capacity 1535
[    0.105321] CPU5: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.120338] CPU6: update cpu_capacity 1535
[    0.120345] CPU6: thread -1, cpu 2, socket 0, mpidr 80000002
[    0.135330] CPU7: update cpu_capacity 1535
[    0.135338] CPU7: thread -1, cpu 3, socket 0, mpidr 80000003
[    0.135466] Brought up 8 CPUs
...
[    3.027498] big.LITTLE switcher initializing
[    3.031761] CPU0 paired with CPU7
[    3.035055] CPU1 paired with CPU6
[    3.038332] CPU2 paired with CPU5
[    3.041598] CPU3 paired with CPU4
[    3.044930] GIC ID for CPU 0 cluster 1 is 4
[    3.049078] GIC ID for CPU 1 cluster 1 is 5
[    3.053258] GIC ID for CPU 2 cluster 1 is 6
[    3.057370] GIC ID for CPU 3 cluster 1 is 7
[    3.061558] GIC ID for CPU 0 cluster 0 is 0
[    3.083336] IRQ53 no longer affine to CPU4
[    3.084336] CPU4: shutdown
[    3.107059] GIC ID for CPU 1 cluster 0 is 1
[    3.123303] IRQ54 no longer affine to CPU5
[    3.124213] CPU5: shutdown
[    3.146387] GIC ID for CPU 2 cluster 0 is 2
[    3.158143] cpu cpu0: 1100 MHz, 1250 mV --> 900 MHz, 1100 mV
[    3.168228] IRQ55 no longer affine to CPU6
[    3.169135] CPU6: shutdown
[    3.191485] GIC ID for CPU 3 cluster 0 is 3
[    3.208264] IRQ56 no longer affine to CPU7
[    3.209166] CPU7: shutdown
[    3.236752] big.LITTLE switcher initialized
...

Only arm_big_little_dt driver knows how to handle this setup
correctly.  cpufreq-dt just treats "virtual" CPUs as a LITTLE
ones.  Thus when "virtual CPU"'s current core is switched to
a big one cpufreq-dt is unable to update its voltage.

[ I tried using BL_SWITCHER_DUMMY_IF functionality to simulate
  this with:

	echo 0,0 > /dev/b.L_switcher

  but it doesn't seem to work for some reason (from looking at
  arch/arm/common/bL_switcher_dummy_if.c code it seems that at
  least "bL_switcher_write" line should get logged but it does
  not happen). ]

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Krzysztof Kozlowski]

On 10.12.2015 23:18, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> On Tuesday, December 08, 2015 04:36:12 PM Krzysztof Kozlowski wrote:
>> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>>> From: Thomas Abraham <thomas.ab@samsung.com>
>>>
>>> The new CPU clock type allows the use of cpufreq-dt driver
>>> for Exynos5420.
>>>
>>> Changes by Bartlomiej:
>>> - split Exynos5420 support from the original patch
>>> - disable cpufreq if big.LITTLE switcher support is enabled
>>> - switch to using cpufreq-dt driver
>>>
>>> Cc: Tomasz Figa <tomasz.figa@gmail.com>
>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/exynos.c | 3 +++
>>>  1 file changed, 3 insertions(+)
>>
>> I think this is actually now your patch, not Thomas any more. :)
> 
> It seems so, I'll update the patch.
> 
>>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>>> index 1c47aee..7a89c9d 100644
>>> --- a/arch/arm/mach-exynos/exynos.c
>>> +++ b/arch/arm/mach-exynos/exynos.c
>>> @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
>>>  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
>>>  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
>>>  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
>>> +#ifndef CONFIG_BL_SWITCHER
>>> +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
>>> +#endif
>>
>> Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?
> 
> ARM_DT_BL_CPUFREQ is not relevant here (it requires to be explicitly
> enabled by platform code, just like cpufreq-dt) and the dependency on
> !BL_SWITCHER is needed because when BL_SWITCHER is enabled big and
> LITTLE cores are grouped in pairs and presented as "virtual" CPUs to
> the system:
> 
> ...
> [    0.002630] CPU0: update cpu_capacity 448
> [    0.002646] CPU0: thread -1, cpu 0, socket 1, mpidr 80000100
> [    0.002835] Setting up static identity map for 0x40008280 - 0x400082d8
> [    0.003106] ARM CCI driver probed
> [    0.003351] Exynos MCPM support installed
> [    0.045350] CPU1: update cpu_capacity 448
> [    0.045358] CPU1: thread -1, cpu 1, socket 1, mpidr 80000101
> [    0.060326] CPU2: update cpu_capacity 448
> [    0.060334] CPU2: thread -1, cpu 2, socket 1, mpidr 80000102
> [    0.075326] CPU3: update cpu_capacity 448
> [    0.075334] CPU3: thread -1, cpu 3, socket 1, mpidr 80000103
> [    0.090337] CPU4: update cpu_capacity 1535
> [    0.090345] CPU4: thread -1, cpu 0, socket 0, mpidr 80000000
> [    0.105314] CPU5: update cpu_capacity 1535
> [    0.105321] CPU5: thread -1, cpu 1, socket 0, mpidr 80000001
> [    0.120338] CPU6: update cpu_capacity 1535
> [    0.120345] CPU6: thread -1, cpu 2, socket 0, mpidr 80000002
> [    0.135330] CPU7: update cpu_capacity 1535
> [    0.135338] CPU7: thread -1, cpu 3, socket 0, mpidr 80000003
> [    0.135466] Brought up 8 CPUs
> ...
> [    3.027498] big.LITTLE switcher initializing
> [    3.031761] CPU0 paired with CPU7
> [    3.035055] CPU1 paired with CPU6
> [    3.038332] CPU2 paired with CPU5
> [    3.041598] CPU3 paired with CPU4
> [    3.044930] GIC ID for CPU 0 cluster 1 is 4
> [    3.049078] GIC ID for CPU 1 cluster 1 is 5
> [    3.053258] GIC ID for CPU 2 cluster 1 is 6
> [    3.057370] GIC ID for CPU 3 cluster 1 is 7
> [    3.061558] GIC ID for CPU 0 cluster 0 is 0
> [    3.083336] IRQ53 no longer affine to CPU4
> [    3.084336] CPU4: shutdown
> [    3.107059] GIC ID for CPU 1 cluster 0 is 1
> [    3.123303] IRQ54 no longer affine to CPU5
> [    3.124213] CPU5: shutdown
> [    3.146387] GIC ID for CPU 2 cluster 0 is 2
> [    3.158143] cpu cpu0: 1100 MHz, 1250 mV --> 900 MHz, 1100 mV
> [    3.168228] IRQ55 no longer affine to CPU6
> [    3.169135] CPU6: shutdown
> [    3.191485] GIC ID for CPU 3 cluster 0 is 3
> [    3.208264] IRQ56 no longer affine to CPU7
> [    3.209166] CPU7: shutdown
> [    3.236752] big.LITTLE switcher initialized
> ...
> 
> Only arm_big_little_dt driver knows how to handle this setup
> correctly.  cpufreq-dt just treats "virtual" CPUs as a LITTLE
> ones.  Thus when "virtual CPU"'s current core is switched to
> a big one cpufreq-dt is unable to update its voltage.
> 
> [ I tried using BL_SWITCHER_DUMMY_IF functionality to simulate
>   this with:
> 
> 	echo 0,0 > /dev/b.L_switcher
> 
>   but it doesn't seem to work for some reason (from looking at
>   arch/arm/common/bL_switcher_dummy_if.c code it seems that at
>   least "bL_switcher_write" line should get logged but it does
>   not happen). ]

Thank you for explanation, seems good approach.

Best regards,
Krzysztof

[PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

[Krzysztof Kozlowski]

On 10.12.2015 23:18, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> On Tuesday, December 08, 2015 04:36:12 PM Krzysztof Kozlowski wrote:
>> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>>> From: Thomas Abraham <thomas.ab@samsung.com>
>>>
>>> The new CPU clock type allows the use of cpufreq-dt driver
>>> for Exynos5420.
>>>
>>> Changes by Bartlomiej:
>>> - split Exynos5420 support from the original patch
>>> - disable cpufreq if big.LITTLE switcher support is enabled
>>> - switch to using cpufreq-dt driver
>>>
>>> Cc: Tomasz Figa <tomasz.figa@gmail.com>
>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/exynos.c | 3 +++
>>>  1 file changed, 3 insertions(+)
>>
>> I think this is actually now your patch, not Thomas any more. :)
> 
> It seems so, I'll update the patch.
> 
>>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>>> index 1c47aee..7a89c9d 100644
>>> --- a/arch/arm/mach-exynos/exynos.c
>>> +++ b/arch/arm/mach-exynos/exynos.c
>>> @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
>>>  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
>>>  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
>>>  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
>>> +#ifndef CONFIG_BL_SWITCHER
>>> +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
>>> +#endif
>>
>> Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?
> 
> ARM_DT_BL_CPUFREQ is not relevant here (it requires to be explicitly
> enabled by platform code, just like cpufreq-dt) and the dependency on
> !BL_SWITCHER is needed because when BL_SWITCHER is enabled big and
> LITTLE cores are grouped in pairs and presented as "virtual" CPUs to
> the system:
> 
> ...
> [    0.002630] CPU0: update cpu_capacity 448
> [    0.002646] CPU0: thread -1, cpu 0, socket 1, mpidr 80000100
> [    0.002835] Setting up static identity map for 0x40008280 - 0x400082d8
> [    0.003106] ARM CCI driver probed
> [    0.003351] Exynos MCPM support installed
> [    0.045350] CPU1: update cpu_capacity 448
> [    0.045358] CPU1: thread -1, cpu 1, socket 1, mpidr 80000101
> [    0.060326] CPU2: update cpu_capacity 448
> [    0.060334] CPU2: thread -1, cpu 2, socket 1, mpidr 80000102
> [    0.075326] CPU3: update cpu_capacity 448
> [    0.075334] CPU3: thread -1, cpu 3, socket 1, mpidr 80000103
> [    0.090337] CPU4: update cpu_capacity 1535
> [    0.090345] CPU4: thread -1, cpu 0, socket 0, mpidr 80000000
> [    0.105314] CPU5: update cpu_capacity 1535
> [    0.105321] CPU5: thread -1, cpu 1, socket 0, mpidr 80000001
> [    0.120338] CPU6: update cpu_capacity 1535
> [    0.120345] CPU6: thread -1, cpu 2, socket 0, mpidr 80000002
> [    0.135330] CPU7: update cpu_capacity 1535
> [    0.135338] CPU7: thread -1, cpu 3, socket 0, mpidr 80000003
> [    0.135466] Brought up 8 CPUs
> ...
> [    3.027498] big.LITTLE switcher initializing
> [    3.031761] CPU0 paired with CPU7
> [    3.035055] CPU1 paired with CPU6
> [    3.038332] CPU2 paired with CPU5
> [    3.041598] CPU3 paired with CPU4
> [    3.044930] GIC ID for CPU 0 cluster 1 is 4
> [    3.049078] GIC ID for CPU 1 cluster 1 is 5
> [    3.053258] GIC ID for CPU 2 cluster 1 is 6
> [    3.057370] GIC ID for CPU 3 cluster 1 is 7
> [    3.061558] GIC ID for CPU 0 cluster 0 is 0
> [    3.083336] IRQ53 no longer affine to CPU4
> [    3.084336] CPU4: shutdown
> [    3.107059] GIC ID for CPU 1 cluster 0 is 1
> [    3.123303] IRQ54 no longer affine to CPU5
> [    3.124213] CPU5: shutdown
> [    3.146387] GIC ID for CPU 2 cluster 0 is 2
> [    3.158143] cpu cpu0: 1100 MHz, 1250 mV --> 900 MHz, 1100 mV
> [    3.168228] IRQ55 no longer affine to CPU6
> [    3.169135] CPU6: shutdown
> [    3.191485] GIC ID for CPU 3 cluster 0 is 3
> [    3.208264] IRQ56 no longer affine to CPU7
> [    3.209166] CPU7: shutdown
> [    3.236752] big.LITTLE switcher initialized
> ...
> 
> Only arm_big_little_dt driver knows how to handle this setup
> correctly.  cpufreq-dt just treats "virtual" CPUs as a LITTLE
> ones.  Thus when "virtual CPU"'s current core is switched to
> a big one cpufreq-dt is unable to update its voltage.
> 
> [ I tried using BL_SWITCHER_DUMMY_IF functionality to simulate
>   this with:
> 
> 	echo 0,0 > /dev/b.L_switcher
> 
>   but it doesn't seem to work for some reason (from looking at
>   arch/arm/common/bL_switcher_dummy_if.c code it seems that at
>   least "bL_switcher_write" line should get logged but it does
>   not happen). ]

Thank you for explanation, seems good approach.

Best regards,
Krzysztof

[PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock configuration data

[Bartlomiej Zolnierkiewicz]

Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
 	{  0 },
 };
 
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+	{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+	{  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+	{  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+	{  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+	{  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+	{  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  0 },
+};
+
 #define E5420_KFC_DIV(kpll, pclk, aclk)					\
 		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
 
 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+	{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
 	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
 				ARRAY_SIZE(exynos5800_gate_clks));
 	}
 
-	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
-		mout_cpu_p[0], mout_cpu_p[1], 0x200,
-		exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	if (soc == EXYNOS5420) {
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	} else {
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+	}
 	exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
 		mout_kfc_p[0], mout_kfc_p[1], 0x28200,
 		exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
-- 
1.9.1

[PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock configuration data

[Bartlomiej Zolnierkiewicz]

Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
 	{  0 },
 };
 
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+	{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+	{  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+	{  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+	{  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+	{  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+	{  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  0 },
+};
+
 #define E5420_KFC_DIV(kpll, pclk, aclk)					\
 		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
 
 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+	{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
 	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
 				ARRAY_SIZE(exynos5800_gate_clks));
 	}
 
-	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
-		mout_cpu_p[0], mout_cpu_p[1], 0x200,
-		exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	if (soc == EXYNOS5420) {
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	} else {
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+	}
 	exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
 		mout_kfc_p[0], mout_kfc_p[1], 0x28200,
 		exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
-- 
1.9.1

[PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP

[Bartlomiej Zolnierkiewicz]

Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.

Based on Hardkernel's kernel for ODROID-XU3 board.

Changes by Ben Gamari:
- Port to operating-points-v2

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5800.dtsi | 165 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 165 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..e417218 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,8 +17,173 @@
 
 / {
 	compatible = "samsung,exynos5800", "samsung,exynos5";
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00@1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp02@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp03@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp04@1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp05@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp06@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp07@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp08@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp09@900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp10@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp11@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp12@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp13@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp14@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp15@300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp16@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
+	cpu1_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp02@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp03@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp04@900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp05@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp06@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp07@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp08@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp09@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp10@300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp11@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+	};
 };
 
+&cpu0 { operating-points-v2 = <&cpu0_opp_table>; };
+&cpu1 { operating-points-v2 = <&cpu0_opp_table>; };
+&cpu2 { operating-points-v2 = <&cpu0_opp_table>; };
+&cpu3 { operating-points-v2 = <&cpu0_opp_table>; };
+
+&cpu4 { operating-points-v2 = <&cpu1_opp_table>; };
+&cpu5 { operating-points-v2 = <&cpu1_opp_table>; };
+&cpu6 { operating-points-v2 = <&cpu1_opp_table>; };
+&cpu7 { operating-points-v2 = <&cpu1_opp_table>; };
+
 &clock {
 	compatible = "samsung,exynos5800-clock";
 };
-- 
1.9.1

[PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP

[Bartlomiej Zolnierkiewicz]

Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.

Based on Hardkernel's kernel for ODROID-XU3 board.

Changes by Ben Gamari:
- Port to operating-points-v2

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5800.dtsi | 165 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 165 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..e417218 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,8 +17,173 @@
 
 / {
 	compatible = "samsung,exynos5800", "samsung,exynos5";
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 at 1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01 at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp02 at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp03 at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp04 at 1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp05 at 1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp06 at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp07 at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp08 at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp09 at 900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp10 at 800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp11 at 700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp12 at 600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp13 at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp14 at 400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp15 at 300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp16 at 200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+	};
+
+	cpu1_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 at 1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp01 at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp02 at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
+		};
+		opp03 at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp04 at 900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp05 at 800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <140000>;
+		};
+		opp06 at 700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp07 at 600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp08 at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp09 at 400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <140000>;
+		};
+		opp10 at 300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+		opp11 at 200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <140000>;
+		};
+	};
 };
 
+&cpu0 { operating-points-v2 = <&cpu0_opp_table>; };
+&cpu1 { operating-points-v2 = <&cpu0_opp_table>; };
+&cpu2 { operating-points-v2 = <&cpu0_opp_table>; };
+&cpu3 { operating-points-v2 = <&cpu0_opp_table>; };
+
+&cpu4 { operating-points-v2 = <&cpu1_opp_table>; };
+&cpu5 { operating-points-v2 = <&cpu1_opp_table>; };
+&cpu6 { operating-points-v2 = <&cpu1_opp_table>; };
+&cpu7 { operating-points-v2 = <&cpu1_opp_table>; };
+
 &clock {
 	compatible = "samsung,exynos5800-clock";
 };
-- 
1.9.1

Re: [PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> Fix CPU operating points for Exynos5800 (it use different
> voltages than Exynos5420 and supports additional frequencies).
> However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
> 1400MHz OPP (for A7 cores) for now as they are not available
> on all boards.
> 
> Based on Hardkernel's kernel for ODROID-XU3 board.
> 
> Changes by Ben Gamari:
> - Port to operating-points-v2
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5800.dtsi | 165 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 165 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
> index c0bb356..e417218 100644
> --- a/arch/arm/boot/dts/exynos5800.dtsi
> +++ b/arch/arm/boot/dts/exynos5800.dtsi
> @@ -17,8 +17,173 @@
>  
>  / {
>  	compatible = "samsung,exynos5800", "samsung,exynos5";
> +
> +	cpu0_opp_table: opp_table0 {

This includes exynos5420.dtsi, so override by label instead of
duplicating full path.

In the same time you don't have to duplicate all data - just override
what you want:
	&cpu0_opp_table {
		opp00@1800000000 {
			opp-microvolt = <1250000>;
		};
	};

That should be sufficient I think.

> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00@1800000000 {
> +			opp-hz = /bits/ 64 <1800000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04@1400000000 {
> +			opp-hz = /bits/ 64 <1400000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05@1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06@1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07@1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp08@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp09@900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp10@800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp11@700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp12@600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp13@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp14@400000000 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp15@300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp16@200000000 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00@1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01@1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02@1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04@900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05@800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06@700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07@600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp08@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp09@400000000 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp10@300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp11@200000000 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
>  };
>  
> +&cpu0 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu1 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu2 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu3 { operating-points-v2 = <&cpu0_opp_table>; };
> +
> +&cpu4 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu5 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu6 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu7 { operating-points-v2 = <&cpu1_opp_table>; };
> +

Why? These are set by exynos5420.dtsi already, aren't they?

Best regards,
Krzysztof

[PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> Fix CPU operating points for Exynos5800 (it use different
> voltages than Exynos5420 and supports additional frequencies).
> However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
> 1400MHz OPP (for A7 cores) for now as they are not available
> on all boards.
> 
> Based on Hardkernel's kernel for ODROID-XU3 board.
> 
> Changes by Ben Gamari:
> - Port to operating-points-v2
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5800.dtsi | 165 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 165 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
> index c0bb356..e417218 100644
> --- a/arch/arm/boot/dts/exynos5800.dtsi
> +++ b/arch/arm/boot/dts/exynos5800.dtsi
> @@ -17,8 +17,173 @@
>  
>  / {
>  	compatible = "samsung,exynos5800", "samsung,exynos5";
> +
> +	cpu0_opp_table: opp_table0 {

This includes exynos5420.dtsi, so override by label instead of
duplicating full path.

In the same time you don't have to duplicate all data - just override
what you want:
	&cpu0_opp_table {
		opp00 at 1800000000 {
			opp-microvolt = <1250000>;
		};
	};

That should be sufficient I think.

> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00 at 1800000000 {
> +			opp-hz = /bits/ 64 <1800000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01 at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02 at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03 at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04 at 1400000000 {
> +			opp-hz = /bits/ 64 <1400000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05 at 1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06 at 1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07 at 1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp08 at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp09 at 900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp10 at 800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp11 at 700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp12 at 600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp13 at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp14 at 400000000 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp15 at 300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp16 at 200000000 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
> +
> +	cpu1_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp00 at 1300000000 {
> +			opp-hz = /bits/ 64 <1300000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp01 at 1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp02 at 1100000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			opp-microvolt = <1250000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp03 at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp04 at 900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp05 at 800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp06 at 700000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp07 at 600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp08 at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp09 at 400000000 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp10 at 300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +		opp11 at 200000000 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <140000>;
> +		};
> +	};
>  };
>  
> +&cpu0 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu1 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu2 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu3 { operating-points-v2 = <&cpu0_opp_table>; };
> +
> +&cpu4 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu5 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu6 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu7 { operating-points-v2 = <&cpu1_opp_table>; };
> +

Why? These are set by exynos5420.dtsi already, aren't they?

Best regards,
Krzysztof

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Bartlomiej Zolnierkiewicz]

From: Ben Gamari <ben@smart-cactus.org>

The Exynos 5422 is identical to the 5800 except for the fact that it
boots from the A7 cores. Consequently, the core numbering is different:
cores 0-3 are A7s whereas 4-7 are A15s.

We can reuse the device tree of the 5800 for the 5422 but we must take
care to override the OPP tables and CPU clocks.  These are otherwise
inherited from the exynos5800 devicetree, which has the CPU clusters
reversed compared to the 5422. This results in the A15 cores only
reaching 1.4GHz, the maximum rate of the KFC clock.

Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index b7f60c8..9a5131d 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -20,8 +20,10 @@
 	device_type = "cpu";
 	compatible = "arm,cortex-a7";
 	reg = <0x100>;
+	clocks = <&clock CLK_KFC_CLK>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu1 {
@@ -30,6 +32,7 @@
 	reg = <0x101>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu2 {
@@ -38,6 +41,7 @@
 	reg = <0x102>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu3 {
@@ -46,14 +50,17 @@
 	reg = <0x103>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu4 {
 	device_type = "cpu";
 	compatible = "arm,cortex-a15";
 	reg = <0x0>;
+	clocks = <&clock CLK_ARM_CLK>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &cpu5 {
@@ -62,6 +69,7 @@
 	reg = <0x1>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &cpu6 {
@@ -70,6 +78,7 @@
 	reg = <0x2>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &cpu7 {
@@ -78,4 +87,5 @@
 	reg = <0x3>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
-- 
1.9.1

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Bartlomiej Zolnierkiewicz]

From: Ben Gamari <ben@smart-cactus.org>

The Exynos 5422 is identical to the 5800 except for the fact that it
boots from the A7 cores. Consequently, the core numbering is different:
cores 0-3 are A7s whereas 4-7 are A15s.

We can reuse the device tree of the 5800 for the 5422 but we must take
care to override the OPP tables and CPU clocks.  These are otherwise
inherited from the exynos5800 devicetree, which has the CPU clusters
reversed compared to the 5422. This results in the A15 cores only
reaching 1.4GHz, the maximum rate of the KFC clock.

Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index b7f60c8..9a5131d 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -20,8 +20,10 @@
 	device_type = "cpu";
 	compatible = "arm,cortex-a7";
 	reg = <0x100>;
+	clocks = <&clock CLK_KFC_CLK>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu1 {
@@ -30,6 +32,7 @@
 	reg = <0x101>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu2 {
@@ -38,6 +41,7 @@
 	reg = <0x102>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu3 {
@@ -46,14 +50,17 @@
 	reg = <0x103>;
 	clock-frequency = <1000000000>;
 	cci-control-port = <&cci_control0>;
+	operating-points-v2 = <&cpu1_opp_table>;
 };
 
 &cpu4 {
 	device_type = "cpu";
 	compatible = "arm,cortex-a15";
 	reg = <0x0>;
+	clocks = <&clock CLK_ARM_CLK>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &cpu5 {
@@ -62,6 +69,7 @@
 	reg = <0x1>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &cpu6 {
@@ -70,6 +78,7 @@
 	reg = <0x2>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
 
 &cpu7 {
@@ -78,4 +87,5 @@
 	reg = <0x3>;
 	clock-frequency = <1800000000>;
 	cci-control-port = <&cci_control1>;
+	operating-points-v2 = <&cpu0_opp_table>;
 };
-- 
1.9.1

Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Ben Gamari <ben@smart-cactus.org>
> 
> The Exynos 5422 is identical to the 5800 except for the fact that it
> boots from the A7 cores. Consequently, the core numbering is different:
> cores 0-3 are A7s whereas 4-7 are A15s.
> 
> We can reuse the device tree of the 5800 for the 5422 but we must take
> care to override the OPP tables and CPU clocks.  These are otherwise
> inherited from the exynos5800 devicetree, which has the CPU clusters
> reversed compared to the 5422. This results in the A15 cores only
> reaching 1.4GHz, the maximum rate of the KFC clock.
> 
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 

This looks like a very-non-atomic way of handling a change. You added
opp tables to exynos5420 before so at that time they will be applied to
Odroid XU3 family which uses different CPU order. After that you are
fixing the tables to proper CPU order. Direct bisectability probably
won't be an issue because all of DTS would go to separate branch... but
the logic behind confuses.

I think this should be squashed into 3/8.

Best regards,
Krzysztof

> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> index b7f60c8..9a5131d 100644
> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> @@ -20,8 +20,10 @@
>  	device_type = "cpu";
>  	compatible = "arm,cortex-a7";
>  	reg = <0x100>;
> +	clocks = <&clock CLK_KFC_CLK>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu1 {
> @@ -30,6 +32,7 @@
>  	reg = <0x101>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu2 {
> @@ -38,6 +41,7 @@
>  	reg = <0x102>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu3 {
> @@ -46,14 +50,17 @@
>  	reg = <0x103>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu4 {
>  	device_type = "cpu";
>  	compatible = "arm,cortex-a15";
>  	reg = <0x0>;
> +	clocks = <&clock CLK_ARM_CLK>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
>  
>  &cpu5 {
> @@ -62,6 +69,7 @@
>  	reg = <0x1>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
>  
>  &cpu6 {
> @@ -70,6 +78,7 @@
>  	reg = <0x2>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
>  
>  &cpu7 {
> @@ -78,4 +87,5 @@
>  	reg = <0x3>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
> 

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Krzysztof Kozlowski]

On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> From: Ben Gamari <ben@smart-cactus.org>
> 
> The Exynos 5422 is identical to the 5800 except for the fact that it
> boots from the A7 cores. Consequently, the core numbering is different:
> cores 0-3 are A7s whereas 4-7 are A15s.
> 
> We can reuse the device tree of the 5800 for the 5422 but we must take
> care to override the OPP tables and CPU clocks.  These are otherwise
> inherited from the exynos5800 devicetree, which has the CPU clusters
> reversed compared to the 5422. This results in the A15 cores only
> reaching 1.4GHz, the maximum rate of the KFC clock.
> 
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 

This looks like a very-non-atomic way of handling a change. You added
opp tables to exynos5420 before so at that time they will be applied to
Odroid XU3 family which uses different CPU order. After that you are
fixing the tables to proper CPU order. Direct bisectability probably
won't be an issue because all of DTS would go to separate branch... but
the logic behind confuses.

I think this should be squashed into 3/8.

Best regards,
Krzysztof

> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> index b7f60c8..9a5131d 100644
> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> @@ -20,8 +20,10 @@
>  	device_type = "cpu";
>  	compatible = "arm,cortex-a7";
>  	reg = <0x100>;
> +	clocks = <&clock CLK_KFC_CLK>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu1 {
> @@ -30,6 +32,7 @@
>  	reg = <0x101>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu2 {
> @@ -38,6 +41,7 @@
>  	reg = <0x102>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu3 {
> @@ -46,14 +50,17 @@
>  	reg = <0x103>;
>  	clock-frequency = <1000000000>;
>  	cci-control-port = <&cci_control0>;
> +	operating-points-v2 = <&cpu1_opp_table>;
>  };
>  
>  &cpu4 {
>  	device_type = "cpu";
>  	compatible = "arm,cortex-a15";
>  	reg = <0x0>;
> +	clocks = <&clock CLK_ARM_CLK>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
>  
>  &cpu5 {
> @@ -62,6 +69,7 @@
>  	reg = <0x1>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
>  
>  &cpu6 {
> @@ -70,6 +78,7 @@
>  	reg = <0x2>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
>  
>  &cpu7 {
> @@ -78,4 +87,5 @@
>  	reg = <0x3>;
>  	clock-frequency = <1800000000>;
>  	cci-control-port = <&cci_control1>;
> +	operating-points-v2 = <&cpu0_opp_table>;
>  };
> 

Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Javier Martinez Canillas]

Hello Krzysztof,

On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>> From: Ben Gamari <ben@smart-cactus.org>
>>
>> The Exynos 5422 is identical to the 5800 except for the fact that it
>> boots from the A7 cores. Consequently, the core numbering is different:
>> cores 0-3 are A7s whereas 4-7 are A15s.
>>
>> We can reuse the device tree of the 5800 for the 5422 but we must take
>> care to override the OPP tables and CPU clocks.  These are otherwise
>> inherited from the exynos5800 devicetree, which has the CPU clusters
>> reversed compared to the 5422. This results in the A15 cores only
>> reaching 1.4GHz, the maximum rate of the KFC clock.
>>
>> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
>> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
> 
> This looks like a very-non-atomic way of handling a change. You added
> opp tables to exynos5420 before so at that time they will be applied to
> Odroid XU3 family which uses different CPU order. After that you are
> fixing the tables to proper CPU order. Direct bisectability probably
> won't be an issue because all of DTS would go to separate branch... but
> the logic behind confuses.
> 

Agreed.

> I think this should be squashed into 3/8.
> 

I think the patch should be split in two changes, the CPUs device nodes
having the wrong clock for clusters is a bug and has to be fixed in a
patch before adding the OPP tables and the OPP tables changes should be
separated and merged with patch 3/8 as you suggest.

> Best regards,
> Krzysztof
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Javier Martinez Canillas]

Hello Krzysztof,

On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>> From: Ben Gamari <ben@smart-cactus.org>
>>
>> The Exynos 5422 is identical to the 5800 except for the fact that it
>> boots from the A7 cores. Consequently, the core numbering is different:
>> cores 0-3 are A7s whereas 4-7 are A15s.
>>
>> We can reuse the device tree of the 5800 for the 5422 but we must take
>> care to override the OPP tables and CPU clocks.  These are otherwise
>> inherited from the exynos5800 devicetree, which has the CPU clusters
>> reversed compared to the 5422. This results in the A15 cores only
>> reaching 1.4GHz, the maximum rate of the KFC clock.
>>
>> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
>> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
> 
> This looks like a very-non-atomic way of handling a change. You added
> opp tables to exynos5420 before so at that time they will be applied to
> Odroid XU3 family which uses different CPU order. After that you are
> fixing the tables to proper CPU order. Direct bisectability probably
> won't be an issue because all of DTS would go to separate branch... but
> the logic behind confuses.
> 

Agreed.

> I think this should be squashed into 3/8.
> 

I think the patch should be split in two changes, the CPUs device nodes
having the wrong clock for clusters is a bug and has to be fixed in a
patch before adding the OPP tables and the OPP tables changes should be
separated and merged with patch 3/8 as you suggest.

> Best regards,
> Krzysztof
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Krzysztof Kozlowski]

On 08.12.2015 22:41, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
>> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>>> From: Ben Gamari <ben@smart-cactus.org>
>>>
>>> The Exynos 5422 is identical to the 5800 except for the fact that it
>>> boots from the A7 cores. Consequently, the core numbering is different:
>>> cores 0-3 are A7s whereas 4-7 are A15s.
>>>
>>> We can reuse the device tree of the 5800 for the 5422 but we must take
>>> care to override the OPP tables and CPU clocks.  These are otherwise
>>> inherited from the exynos5800 devicetree, which has the CPU clusters
>>> reversed compared to the 5422. This results in the A15 cores only
>>> reaching 1.4GHz, the maximum rate of the KFC clock.
>>>
>>> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
>>> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>> ---
>>>  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>
>> This looks like a very-non-atomic way of handling a change. You added
>> opp tables to exynos5420 before so at that time they will be applied to
>> Odroid XU3 family which uses different CPU order. After that you are
>> fixing the tables to proper CPU order. Direct bisectability probably
>> won't be an issue because all of DTS would go to separate branch... but
>> the logic behind confuses.
>>
> 
> Agreed.
> 
>> I think this should be squashed into 3/8.
>>
> 
> I think the patch should be split in two changes, the CPUs device nodes
> having the wrong clock for clusters is a bug and has to be fixed in a
> patch before adding the OPP tables and the OPP tables changes should be
> separated and merged with patch 3/8 as you suggest.

I don't get the point about wrong clock (bug). Where is the bug? Beside
of course what was introduced in 3/8 and it is not valid for reversed
cluster order.

Best regards,
Krzysztof

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Krzysztof Kozlowski]

On 08.12.2015 22:41, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
>> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>>> From: Ben Gamari <ben@smart-cactus.org>
>>>
>>> The Exynos 5422 is identical to the 5800 except for the fact that it
>>> boots from the A7 cores. Consequently, the core numbering is different:
>>> cores 0-3 are A7s whereas 4-7 are A15s.
>>>
>>> We can reuse the device tree of the 5800 for the 5422 but we must take
>>> care to override the OPP tables and CPU clocks.  These are otherwise
>>> inherited from the exynos5800 devicetree, which has the CPU clusters
>>> reversed compared to the 5422. This results in the A15 cores only
>>> reaching 1.4GHz, the maximum rate of the KFC clock.
>>>
>>> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
>>> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>> ---
>>>  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>
>> This looks like a very-non-atomic way of handling a change. You added
>> opp tables to exynos5420 before so at that time they will be applied to
>> Odroid XU3 family which uses different CPU order. After that you are
>> fixing the tables to proper CPU order. Direct bisectability probably
>> won't be an issue because all of DTS would go to separate branch... but
>> the logic behind confuses.
>>
> 
> Agreed.
> 
>> I think this should be squashed into 3/8.
>>
> 
> I think the patch should be split in two changes, the CPUs device nodes
> having the wrong clock for clusters is a bug and has to be fixed in a
> patch before adding the OPP tables and the OPP tables changes should be
> separated and merged with patch 3/8 as you suggest.

I don't get the point about wrong clock (bug). Where is the bug? Beside
of course what was introduced in 3/8 and it is not valid for reversed
cluster order.

Best regards,
Krzysztof

Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Javier Martinez Canillas]

Hello Krzysztof,

On 12/08/2015 09:34 PM, Krzysztof Kozlowski wrote:
> On 08.12.2015 22:41, Javier Martinez Canillas wrote:
>> On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
>>>
>>> This looks like a very-non-atomic way of handling a change. You added
>>> opp tables to exynos5420 before so at that time they will be applied to
>>> Odroid XU3 family which uses different CPU order. After that you are
>>> fixing the tables to proper CPU order. Direct bisectability probably
>>> won't be an issue because all of DTS would go to separate branch... but
>>> the logic behind confuses.
>>>
>>
>> Agreed.
>>
>>> I think this should be squashed into 3/8.
>>>
>>
>> I think the patch should be split in two changes, the CPUs device nodes
>> having the wrong clock for clusters is a bug and has to be fixed in a
>> patch before adding the OPP tables and the OPP tables changes should be
>> separated and merged with patch 3/8 as you suggest.
> 
> I don't get the point about wrong clock (bug). Where is the bug? Beside
> of course what was introduced in 3/8 and it is not valid for reversed
> cluster order.
>

You are absolutely correct, for some reason I thought that the CLK_ARM_CLK
and CLK_KFC_CLK clocks were already defined in the cpu0 and cpu4 nodes from
exynos5420.dtsi and commit df09df6f9ac3 ("ARM: dts: add exynos5422-cpus.dtsi
to correct cpu order") missed that when reversing the cores for Exynos5422.

But on a second look to patch 3/8, I see that the clocks are defined in that
patch so I agree that $SUBJECT should just be squashed with 3/8 without doing
any split. Sorry for the noise.

> Best regards,
> Krzysztof
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Javier Martinez Canillas]

Hello Krzysztof,

On 12/08/2015 09:34 PM, Krzysztof Kozlowski wrote:
> On 08.12.2015 22:41, Javier Martinez Canillas wrote:
>> On 12/08/2015 05:13 AM, Krzysztof Kozlowski wrote:
>>>
>>> This looks like a very-non-atomic way of handling a change. You added
>>> opp tables to exynos5420 before so at that time they will be applied to
>>> Odroid XU3 family which uses different CPU order. After that you are
>>> fixing the tables to proper CPU order. Direct bisectability probably
>>> won't be an issue because all of DTS would go to separate branch... but
>>> the logic behind confuses.
>>>
>>
>> Agreed.
>>
>>> I think this should be squashed into 3/8.
>>>
>>
>> I think the patch should be split in two changes, the CPUs device nodes
>> having the wrong clock for clusters is a bug and has to be fixed in a
>> patch before adding the OPP tables and the OPP tables changes should be
>> separated and merged with patch 3/8 as you suggest.
> 
> I don't get the point about wrong clock (bug). Where is the bug? Beside
> of course what was introduced in 3/8 and it is not valid for reversed
> cluster order.
>

You are absolutely correct, for some reason I thought that the CLK_ARM_CLK
and CLK_KFC_CLK clocks were already defined in the cpu0 and cpu4 nodes from
exynos5420.dtsi and commit df09df6f9ac3 ("ARM: dts: add exynos5422-cpus.dtsi
to correct cpu order") missed that when reversing the cores for Exynos5422.

But on a second look to patch 3/8, I see that the clocks are defined in that
patch so I agree that $SUBJECT should just be squashed with 3/8 without doing
any split. Sorry for the noise.

> Best regards,
> Krzysztof
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Bartlomiej Zolnierkiewicz]

Hi,

On Tuesday, December 08, 2015 05:13:26 PM Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> > From: Ben Gamari <ben@smart-cactus.org>
> > 
> > The Exynos 5422 is identical to the 5800 except for the fact that it
> > boots from the A7 cores. Consequently, the core numbering is different:
> > cores 0-3 are A7s whereas 4-7 are A15s.
> > 
> > We can reuse the device tree of the 5800 for the 5422 but we must take
> > care to override the OPP tables and CPU clocks.  These are otherwise
> > inherited from the exynos5800 devicetree, which has the CPU clusters
> > reversed compared to the 5422. This results in the A15 cores only
> > reaching 1.4GHz, the maximum rate of the KFC clock.
> > 
> > Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> > Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> > Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> > ---
> >  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> 
> This looks like a very-non-atomic way of handling a change. You added
> opp tables to exynos5420 before so at that time they will be applied to
> Odroid XU3 family which uses different CPU order. After that you are
> fixing the tables to proper CPU order. Direct bisectability probably
> won't be an issue because all of DTS would go to separate branch... but
> the logic behind confuses.

It was done this way to preserve original authorship of changes and
bisectability should not be affected unless patch #8 is merged before
patch #7.

> I think this should be squashed into 3/8.

OK.

> Best regards,
> Krzysztof

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables

[Bartlomiej Zolnierkiewicz]

Hi,

On Tuesday, December 08, 2015 05:13:26 PM Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> > From: Ben Gamari <ben@smart-cactus.org>
> > 
> > The Exynos 5422 is identical to the 5800 except for the fact that it
> > boots from the A7 cores. Consequently, the core numbering is different:
> > cores 0-3 are A7s whereas 4-7 are A15s.
> > 
> > We can reuse the device tree of the 5800 for the 5422 but we must take
> > care to override the OPP tables and CPU clocks.  These are otherwise
> > inherited from the exynos5800 devicetree, which has the CPU clusters
> > reversed compared to the 5422. This results in the A15 cores only
> > reaching 1.4GHz, the maximum rate of the KFC clock.
> > 
> > Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> > Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> > Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> > ---
> >  arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> 
> This looks like a very-non-atomic way of handling a change. You added
> opp tables to exynos5420 before so at that time they will be applied to
> Odroid XU3 family which uses different CPU order. After that you are
> fixing the tables to proper CPU order. Direct bisectability probably
> won't be an issue because all of DTS would go to separate branch... but
> the logic behind confuses.

It was done this way to preserve original authorship of changes and
bisectability should not be affected unless patch #8 is merged before
patch #7.

> I think this should be squashed into 3/8.

OK.

> Best regards,
> Krzysztof

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

[PATCH v4 8/8] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.

Changes by Bartlomiej:
- split Exynos5800 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
- switch to using cpufreq-dt driver

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/mach-exynos/exynos.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
 	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
 #ifndef CONFIG_BL_SWITCHER
 	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+	{ .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
 #endif
 	{ /* sentinel */ }
 };
-- 
1.9.1

[PATCH v4 8/8] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800

[Bartlomiej Zolnierkiewicz]

From: Thomas Abraham <thomas.ab@samsung.com>

The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.

Changes by Bartlomiej:
- split Exynos5800 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
- switch to using cpufreq-dt driver

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 arch/arm/mach-exynos/exynos.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
 	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
 #ifndef CONFIG_BL_SWITCHER
 	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+	{ .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
 #endif
 	{ /* sentinel */ }
 };
-- 
1.9.1

Re: [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Viresh Kumar]

On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> Hi,
> 
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
> 
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.

Excellent work Bartlomiej. Thanks a lot for adapting cpufreq-dt for
this. Really appreciate it :)

-- 
viresh

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Viresh Kumar]

On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> Hi,
> 
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
> 
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.

Excellent work Bartlomiej. Thanks a lot for adapting cpufreq-dt for
this. Really appreciate it :)

-- 
viresh

Re: [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Viresh Kumar]

On 08-12-15, 11:47, Viresh Kumar wrote:
> On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> > Hi,
> > 
> > This patch series adds generic cpufreq-dt driver support for
> > Exynos542x/5800 (using the new CPU clock type which allows it).
> > 
> > It has been tested on Exynos5422 based ODROID-XU3 Lite board.
> 
> Excellent work Bartlomiej. Thanks a lot for adapting cpufreq-dt for
> this. Really appreciate it :)

You fix the oppXX@ problem and add my

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

for the entire series. Good work.

-- 
viresh

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Viresh Kumar]

On 08-12-15, 11:47, Viresh Kumar wrote:
> On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> > Hi,
> > 
> > This patch series adds generic cpufreq-dt driver support for
> > Exynos542x/5800 (using the new CPU clock type which allows it).
> > 
> > It has been tested on Exynos5422 based ODROID-XU3 Lite board.
> 
> Excellent work Bartlomiej. Thanks a lot for adapting cpufreq-dt for
> this. Really appreciate it :)

You fix the oppXX@ problem and add my

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

for the entire series. Good work.

-- 
viresh

Re: [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Javier Martinez Canillas]

Hello Bartlomiej,

On 12/07/2015 03:18 PM, Bartlomiej Zolnierkiewicz wrote:
> Hi,
> 
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
> 
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>

I tested on an Exynos5800 Peach Pi and all governors are working
as expected on both the Cortex-A7 and Cortex-A15 cores.

So for the whole series:

Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

[Javier Martinez Canillas]

Hello Bartlomiej,

On 12/07/2015 03:18 PM, Bartlomiej Zolnierkiewicz wrote:
> Hi,
> 
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
> 
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>

I tested on an Exynos5800 Peach Pi and all governors are working
as expected on both the Cortex-A7 and Cortex-A15 cores.

So for the whole series:

Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America