[PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the
DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
the respective (already existing) SYSC Power Domains. Fortunately these
Power Domains were never powered down, as they are parents of the Power
Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
adding SYSC Power Domain support later.

Question for the ARM/DT people: What are the DT bindings for
Cortex-A15/A7/A57/A53 L2 cache controllers?
Everybody just seems to use "cache" for the compatible values...

Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
(http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
and received some fixes. You can find more detailed changelogs in the
individual patches).

This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
r8a7795/salvator-x.

Thanks!

Geert Uytterhoeven (6):
  ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes
  ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes
  ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node
  arm64: renesas: r8a7795: Add L2 cache-controller nodes

 arch/arm/boot/dts/r8a73a4.dtsi           | 19 +++++++++++++++++++
 arch/arm/boot/dts/r8a7790.dtsi           | 22 ++++++++++++++++++++++
 arch/arm/boot/dts/r8a7791.dtsi           | 10 ++++++++++
 arch/arm/boot/dts/r8a7793.dtsi           |  9 +++++++++
 arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
 6 files changed, 83 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the
DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
the respective (already existing) SYSC Power Domains. Fortunately these
Power Domains were never powered down, as they are parents of the Power
Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
adding SYSC Power Domain support later.

Question for the ARM/DT people: What are the DT bindings for
Cortex-A15/A7/A57/A53 L2 cache controllers?
Everybody just seems to use "cache" for the compatible values...

Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
(http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
and received some fixes. You can find more detailed changelogs in the
individual patches).

This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
r8a7795/salvator-x.

Thanks!

Geert Uytterhoeven (6):
  ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes
  ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes
  ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node
  arm64: renesas: r8a7795: Add L2 cache-controller nodes

 arch/arm/boot/dts/r8a73a4.dtsi           | 19 +++++++++++++++++++
 arch/arm/boot/dts/r8a7790.dtsi           | 22 ++++++++++++++++++++++
 arch/arm/boot/dts/r8a7791.dtsi           | 10 ++++++++++
 arch/arm/boot/dts/r8a7793.dtsi           |  9 +++++++++
 arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
 6 files changed, 83 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the
DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
the respective (already existing) SYSC Power Domains. Fortunately these
Power Domains were never powered down, as they are parents of the Power
Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
adding SYSC Power Domain support later.

Question for the ARM/DT people: What are the DT bindings for
Cortex-A15/A7/A57/A53 L2 cache controllers?
Everybody just seems to use "cache" for the compatible values...

Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
(http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
and received some fixes. You can find more detailed changelogs in the
individual patches).

This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
r8a7795/salvator-x.

Thanks!

Geert Uytterhoeven (6):
  ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes
  ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes
  ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node
  arm64: renesas: r8a7795: Add L2 cache-controller nodes

 arch/arm/boot/dts/r8a73a4.dtsi           | 19 +++++++++++++++++++
 arch/arm/boot/dts/r8a7790.dtsi           | 22 ++++++++++++++++++++++
 arch/arm/boot/dts/r8a7791.dtsi           | 10 ++++++++++
 arch/arm/boot/dts/r8a7793.dtsi           |  9 +++++++++
 arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
 6 files changed, 83 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v2 1/6] ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM. It requires the
following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A15/A7 L2 cache controllers?

v2:
  - New.
---
 arch/arm/boot/dts/r8a73a4.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 86fab56cd6314df7..73f7ea3cb2209a00 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -45,6 +46,24 @@
 			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc1: memory-controller@e6790000 {
 		compatible = "renesas,dbsc-r8a73a4";
 		reg = <0 0xe6790000 0 0x10000>;
-- 
1.9.1

[PATCH v2 1/6] ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM. It requires the
following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A15/A7 L2 cache controllers?

v2:
  - New.
---
 arch/arm/boot/dts/r8a73a4.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 86fab56cd6314df7..73f7ea3cb2209a00 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -45,6 +46,24 @@
 			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc1: memory-controller@e6790000 {
 		compatible = "renesas,dbsc-r8a73a4";
 		reg = <0 0xe6790000 0 0x10000>;
-- 
1.9.1

[PATCH v2 1/6] ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM. It requires the
following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A15/A7 L2 cache controllers?

v2:
  - New.
---
 arch/arm/boot/dts/r8a73a4.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 86fab56cd6314df7..73f7ea3cb2209a00 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -45,6 +46,24 @@
 			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc1: memory-controller at e6790000 {
 		compatible = "renesas,dbsc-r8a73a4";
 		reg = <0 0xe6790000 0 0x10000>;
-- 
1.9.1

[PATCH v2 2/6] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 1 cycle.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A15/A7 L2 cache controllers?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 caches into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7790.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 6cfd0dc79bbec067..ef5d46faef0c5975 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -52,6 +52,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7790_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu2: cpu@2 {
@@ -74,6 +76,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu3: cpu@3 {
@@ -81,6 +84,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu4: cpu@4 {
@@ -88,6 +92,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu5: cpu@5 {
@@ -95,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu6: cpu@6 {
@@ -102,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu7: cpu@7 {
@@ -109,9 +116,24 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 1>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 2/6] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 1 cycle.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A15/A7 L2 cache controllers?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 caches into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7790.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 6cfd0dc79bbec067..ef5d46faef0c5975 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -52,6 +52,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7790_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu2: cpu@2 {
@@ -74,6 +76,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu3: cpu@3 {
@@ -81,6 +84,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu4: cpu@4 {
@@ -88,6 +92,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu5: cpu@5 {
@@ -95,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu6: cpu@6 {
@@ -102,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu7: cpu@7 {
@@ -109,9 +116,24 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 1>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 2/6] ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 1 cycle.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A15/A7 L2 cache controllers?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 caches into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7790.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 6cfd0dc79bbec067..ef5d46faef0c5975 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -52,6 +52,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7790_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu2: cpu at 2 {
@@ -74,6 +76,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu3: cpu at 3 {
@@ -81,6 +84,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu4: cpu at 4 {
@@ -88,6 +92,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu5: cpu at 5 {
@@ -95,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu6: cpu at 6 {
@@ -102,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu7: cpu at 7 {
@@ -109,9 +116,24 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 1>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 3/6] ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 0 cycles.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1487d92e1b21a175..24e036b51647bb6f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7791_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -66,9 +67,18 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1500000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 3/6] ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 0 cycles.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1487d92e1b21a175..24e036b51647bb6f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7791_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -66,9 +67,18 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1500000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 3/6] ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 0 cycles.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1487d92e1b21a175..24e036b51647bb6f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7791_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -66,9 +67,18 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1500000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 4/6] ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 0 cycles.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPU to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7793.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 33205ecb2a596979..59f8a4fcda1dee95 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -42,9 +42,18 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 4/6] ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 0 cycles.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPU to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7793.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 33205ecb2a596979..59f8a4fcda1dee95 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -42,9 +42,18 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 4/6] ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 0 cycles.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPU to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7793.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 33205ecb2a596979..59f8a4fcda1dee95 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -42,9 +42,18 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 0>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 5/6] ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A7 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 56acafbb70dc7bc9..1b53495b9c95611c 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu@1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 5/6] ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
What are the DT bindings for a Cortex-A7 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 56acafbb70dc7bc9..1b53495b9c95611c 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu@1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

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[PATCH v2 5/6] ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for a Cortex-A7 L2 cache controller?

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 56acafbb70dc7bc9..1b53495b9c95611c 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu at 1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 1 cycles,

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A57/A53 L2 cache controllers?

v2:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 816400c1bee604db..30063546c7e9bbea 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -35,9 +35,24 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
 			device_type = "cpu";
+			next-level-cache = <&L2_CA57>;
 		};
 	};
 
+	L2_CA57: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 1>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA53: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
1.9.1

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 1 cycles,

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A57/A53 L2 cache controllers?

v2:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 816400c1bee604db..30063546c7e9bbea 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -35,9 +35,24 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
 			device_type = "cpu";
+			next-level-cache = <&L2_CA57>;
 		};
 	};
 
+	L2_CA57: cache-controller@0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 1>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA53: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
1.9.1

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways), and requires the following settings:
  - Tag RAM latency: 3 cycles,
  - Data RAM latency: 4 cycles,
  - Data RAM setup: 1 cycles,

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
What are the DT bindings for Cortex-A57/A53 L2 cache controllers?

v2:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 816400c1bee604db..30063546c7e9bbea 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -35,9 +35,24 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
 			device_type = "cpu";
+			next-level-cache = <&L2_CA57>;
 		};
 	};
 
+	L2_CA57: cache-controller at 0 {
+		compatible = "cache";
+		arm,data-latency = <4 4 1>;
+		arm,tag-latency = <3 3 3>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA53: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
1.9.1

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 07/12/15 18:24, Geert Uytterhoeven wrote:
> Add device nodes for the L2 caches, and link the CPU node to its L2
> cache node.
>
> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
> 128 KiB x 16 ways), and requires the following settings:
>    - Tag RAM latency: 3 cycles,
>    - Data RAM latency: 4 cycles,
>    - Data RAM setup: 1 cycles,
>
> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
> 32 KiB x 16 ways).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> What are the DT bindings for Cortex-A57/A53 L2 cache controllers?
>

There's no special binding specific to cpus. Yes the generic binding
should be fine as we don't have to deal with their configuration in the
kernel and assumed to be all preconfigured by early secure boot code.

> v2:
>    - New.
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index 816400c1bee604db..30063546c7e9bbea 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -35,9 +35,24 @@
>   			compatible = "arm,cortex-a57", "arm,armv8";
>   			reg = <0x0>;
>   			device_type = "cpu";
> +			next-level-cache = <&L2_CA57>;
>   		};
>   	};
>
> +	L2_CA57: cache-controller@0 {
> +		compatible = "cache";
> +		arm,data-latency = <4 4 1>;
> +		arm,tag-latency = <3 3 3>;

Interesting, only PL2xx/3xx cache controller driver reads this from the
DT and configures the controller. The integrated L2 found in
A15/A7/A57/A53 needs doesn't make use of these values from the DT.

I assume these values are tested and configured by boot loaders before
entering Linux. I am not objecting to their presence here but I am
mentioning that it's mostly of no use for Linux as software running at
higher EL might not allow these configuration to be modified.

-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 07/12/15 18:24, Geert Uytterhoeven wrote:
> Add device nodes for the L2 caches, and link the CPU node to its L2
> cache node.
>
> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
> 128 KiB x 16 ways), and requires the following settings:
>    - Tag RAM latency: 3 cycles,
>    - Data RAM latency: 4 cycles,
>    - Data RAM setup: 1 cycles,
>
> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
> 32 KiB x 16 ways).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> What are the DT bindings for Cortex-A57/A53 L2 cache controllers?
>

There's no special binding specific to cpus. Yes the generic binding
should be fine as we don't have to deal with their configuration in the
kernel and assumed to be all preconfigured by early secure boot code.

> v2:
>    - New.
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index 816400c1bee604db..30063546c7e9bbea 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -35,9 +35,24 @@
>   			compatible = "arm,cortex-a57", "arm,armv8";
>   			reg = <0x0>;
>   			device_type = "cpu";
> +			next-level-cache = <&L2_CA57>;
>   		};
>   	};
>
> +	L2_CA57: cache-controller@0 {
> +		compatible = "cache";
> +		arm,data-latency = <4 4 1>;
> +		arm,tag-latency = <3 3 3>;

Interesting, only PL2xx/3xx cache controller driver reads this from the
DT and configures the controller. The integrated L2 found in
A15/A7/A57/A53 needs doesn't make use of these values from the DT.

I assume these values are tested and configured by boot loaders before
entering Linux. I am not objecting to their presence here but I am
mentioning that it's mostly of no use for Linux as software running at
higher EL might not allow these configuration to be modified.

-- 
Regards,
Sudeep

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 07/12/15 18:24, Geert Uytterhoeven wrote:
> Add device nodes for the L2 caches, and link the CPU node to its L2
> cache node.
>
> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
> 128 KiB x 16 ways), and requires the following settings:
>    - Tag RAM latency: 3 cycles,
>    - Data RAM latency: 4 cycles,
>    - Data RAM setup: 1 cycles,
>
> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
> 32 KiB x 16 ways).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> What are the DT bindings for Cortex-A57/A53 L2 cache controllers?
>

There's no special binding specific to cpus. Yes the generic binding
should be fine as we don't have to deal with their configuration in the
kernel and assumed to be all preconfigured by early secure boot code.

> v2:
>    - New.
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index 816400c1bee604db..30063546c7e9bbea 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -35,9 +35,24 @@
>   			compatible = "arm,cortex-a57", "arm,armv8";
>   			reg = <0x0>;
>   			device_type = "cpu";
> +			next-level-cache = <&L2_CA57>;
>   		};
>   	};
>
> +	L2_CA57: cache-controller at 0 {
> +		compatible = "cache";
> +		arm,data-latency = <4 4 1>;
> +		arm,tag-latency = <3 3 3>;

Interesting, only PL2xx/3xx cache controller driver reads this from the
DT and configures the controller. The integrated L2 found in
A15/A7/A57/A53 needs doesn't make use of these values from the DT.

I assume these values are tested and configured by boot loaders before
entering Linux. I am not objecting to their presence here but I am
mentioning that it's mostly of no use for Linux as software running at
higher EL might not allow these configuration to be modified.

-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> 
> On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >+	L2_CA57: cache-controller@0 {
> >+		compatible = "cache";
> >+		arm,data-latency = <4 4 1>;
> >+		arm,tag-latency = <3 3 3>;
> 
> Interesting, only PL2xx/3xx cache controller driver reads this from the
> DT and configures the controller. The integrated L2 found in
> A15/A7/A57/A53 needs doesn't make use of these values from the DT.

These properties seem to be from l2cc.txt, which really only corresponds
to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.

I don't see that these are necessary at all.

Thanks,
Mark.

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> 
> On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >+	L2_CA57: cache-controller@0 {
> >+		compatible = "cache";
> >+		arm,data-latency = <4 4 1>;
> >+		arm,tag-latency = <3 3 3>;
> 
> Interesting, only PL2xx/3xx cache controller driver reads this from the
> DT and configures the controller. The integrated L2 found in
> A15/A7/A57/A53 needs doesn't make use of these values from the DT.

These properties seem to be from l2cc.txt, which really only corresponds
to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.

I don't see that these are necessary at all.

Thanks,
Mark.

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> 
> On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >+	L2_CA57: cache-controller at 0 {
> >+		compatible = "cache";
> >+		arm,data-latency = <4 4 1>;
> >+		arm,tag-latency = <3 3 3>;
> 
> Interesting, only PL2xx/3xx cache controller driver reads this from the
> DT and configures the controller. The integrated L2 found in
> A15/A7/A57/A53 needs doesn't make use of these values from the DT.

These properties seem to be from l2cc.txt, which really only corresponds
to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.

I don't see that these are necessary at all.

Thanks,
Mark.

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Mark,

On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>> >+    L2_CA57: cache-controller@0 {
>> >+            compatible = "cache";
>> >+            arm,data-latency = <4 4 1>;
>> >+            arm,tag-latency = <3 3 3>;
>>
>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>> DT and configures the controller. The integrated L2 found in
>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>
> These properties seem to be from l2cc.txt, which really only corresponds
> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>
> I don't see that these are necessary at all.

The datasheet does mention the data/tag RAM latencies/setup values, so
I put them in DT using the properties I could fine.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Mark,

On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>> >+    L2_CA57: cache-controller@0 {
>> >+            compatible = "cache";
>> >+            arm,data-latency = <4 4 1>;
>> >+            arm,tag-latency = <3 3 3>;
>>
>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>> DT and configures the controller. The integrated L2 found in
>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>
> These properties seem to be from l2cc.txt, which really only corresponds
> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>
> I don't see that these are necessary at all.

The datasheet does mention the data/tag RAM latencies/setup values, so
I put them in DT using the properties I could fine.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
--
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[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Mark,

On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>> >+    L2_CA57: cache-controller at 0 {
>> >+            compatible = "cache";
>> >+            arm,data-latency = <4 4 1>;
>> >+            arm,tag-latency = <3 3 3>;
>>
>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>> DT and configures the controller. The integrated L2 found in
>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>
> These properties seem to be from l2cc.txt, which really only corresponds
> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>
> I don't see that these are necessary at all.

The datasheet does mention the data/tag RAM latencies/setup values, so
I put them in DT using the properties I could fine.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Dirk Behme]

On 07.12.2015 20:03, Mark Rutland wrote:
> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>
>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>> +	L2_CA57: cache-controller@0 {
>>> +		compatible = "cache";
>>> +		arm,data-latency = <4 4 1>;
>>> +		arm,tag-latency = <3 3 3>;
>>
>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>> DT and configures the controller. The integrated L2 found in
>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>
> These properties seem to be from l2cc.txt, which really only corresponds
> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>
> I don't see that these are necessary at all.


What's about a documentation patch like [1], then?


For what is the arm64 dts entry

cpu@0 {
	...
	next-level-cache = <&L2_0>;
};

L2_0: l2-cache0 {
	compatible = "cache";
};

good for at all, then?


Best regards

Dirk


[1]

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt 
b/Documentation/devicetree/bindings/arm/l2cc.txt
index 06c88a4..f687aed 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -1,12 +1,18 @@
  * ARM L2 Cache Controller

-ARM cores often have a separate level 2 cache controller. There are 
various
+ARM 32-bit cores often have a separate level 2 cache controller. 
There are various
  implementations of the L2 cache controller with compatible 
programming models.
  Some of the properties that are just prefixed "cache-*" are taken 
from section
  3.7.3 of the ePAPR v1.1 specification which can be found at:
 
https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf

-The ARM L2 cache representation in the device tree should be done as 
follows:
+ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 
cache which
+doesn't make use of any values from the kernel device tree. There is no
+L2 cache configuration done in the kernel. The L2 cache is assumed to be
+preconfigured by early secure boot code.
+
+The ARM L2 cache representation for 32-bit cores in the device tree 
should be done
+as follows:

  Required properties:

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Dirk Behme]

On 07.12.2015 20:03, Mark Rutland wrote:
> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>
>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>> +	L2_CA57: cache-controller@0 {
>>> +		compatible = "cache";
>>> +		arm,data-latency = <4 4 1>;
>>> +		arm,tag-latency = <3 3 3>;
>>
>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>> DT and configures the controller. The integrated L2 found in
>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>
> These properties seem to be from l2cc.txt, which really only corresponds
> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>
> I don't see that these are necessary at all.


What's about a documentation patch like [1], then?


For what is the arm64 dts entry

cpu@0 {
	...
	next-level-cache = <&L2_0>;
};

L2_0: l2-cache0 {
	compatible = "cache";
};

good for at all, then?


Best regards

Dirk


[1]

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt 
b/Documentation/devicetree/bindings/arm/l2cc.txt
index 06c88a4..f687aed 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -1,12 +1,18 @@
  * ARM L2 Cache Controller

-ARM cores often have a separate level 2 cache controller. There are 
various
+ARM 32-bit cores often have a separate level 2 cache controller. 
There are various
  implementations of the L2 cache controller with compatible 
programming models.
  Some of the properties that are just prefixed "cache-*" are taken 
from section
  3.7.3 of the ePAPR v1.1 specification which can be found at:
 
https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf

-The ARM L2 cache representation in the device tree should be done as 
follows:
+ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 
cache which
+doesn't make use of any values from the kernel device tree. There is no
+L2 cache configuration done in the kernel. The L2 cache is assumed to be
+preconfigured by early secure boot code.
+
+The ARM L2 cache representation for 32-bit cores in the device tree 
should be done
+as follows:

  Required properties:

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Dirk Behme]

On 07.12.2015 20:03, Mark Rutland wrote:
> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>
>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>> +	L2_CA57: cache-controller at 0 {
>>> +		compatible = "cache";
>>> +		arm,data-latency = <4 4 1>;
>>> +		arm,tag-latency = <3 3 3>;
>>
>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>> DT and configures the controller. The integrated L2 found in
>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>
> These properties seem to be from l2cc.txt, which really only corresponds
> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>
> I don't see that these are necessary at all.


What's about a documentation patch like [1], then?


For what is the arm64 dts entry

cpu at 0 {
	...
	next-level-cache = <&L2_0>;
};

L2_0: l2-cache0 {
	compatible = "cache";
};

good for at all, then?


Best regards

Dirk


[1]

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt 
b/Documentation/devicetree/bindings/arm/l2cc.txt
index 06c88a4..f687aed 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -1,12 +1,18 @@
  * ARM L2 Cache Controller

-ARM cores often have a separate level 2 cache controller. There are 
various
+ARM 32-bit cores often have a separate level 2 cache controller. 
There are various
  implementations of the L2 cache controller with compatible 
programming models.
  Some of the properties that are just prefixed "cache-*" are taken 
from section
  3.7.3 of the ePAPR v1.1 specification which can be found at:
 
https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf

-The ARM L2 cache representation in the device tree should be done as 
follows:
+ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 
cache which
+doesn't make use of any values from the kernel device tree. There is no
+L2 cache configuration done in the kernel. The L2 cache is assumed to be
+preconfigured by early secure boot code.
+
+The ARM L2 cache representation for 32-bit cores in the device tree 
should be done
+as follows:

  Required properties:

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 08/12/15 18:50, Dirk Behme wrote:
> On 07.12.2015 20:03, Mark Rutland wrote:
>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>>
>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>>> +    L2_CA57: cache-controller@0 {
>>>> +        compatible = "cache";
>>>> +        arm,data-latency = <4 4 1>;
>>>> +        arm,tag-latency = <3 3 3>;
>>>
>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>> DT and configures the controller. The integrated L2 found in
>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>
>> These properties seem to be from l2cc.txt, which really only corresponds
>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>
>> I don't see that these are necessary at all.
>
>
> What's about a documentation patch like [1], then?
>
>
> For what is the arm64 dts entry
>
> cpu@0 {
>      ...
>      next-level-cache = <&L2_0>;
> };
>
> L2_0: l2-cache0 {
>      compatible = "cache";
> };
>
> good for at all, then?
>
>
> Best regards
>
> Dirk
>
>
> [1]
>
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
> b/Documentation/devicetree/bindings/arm/l2cc.txt
> index 06c88a4..f687aed 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -1,12 +1,18 @@
>   * ARM L2 Cache Controller
>
> -ARM cores often have a separate level 2 cache controller. There are
> various
> +ARM 32-bit cores often have a separate level 2 cache controller. There
> are various
>   implementations of the L2 cache controller with compatible programming
> models.
>   Some of the properties that are just prefixed "cache-*" are taken from
> section
>   3.7.3 of the ePAPR v1.1 specification which can be found at:
>
> https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
>
>
> -The ARM L2 cache representation in the device tree should be done as
> follows:
> +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 cache which

A15 and A7 are 32-bit cores, so you can't generalize it.
IMO you can just specify that this binding is applicable for separate L2
cache controllers.

-- 
-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 08/12/15 18:50, Dirk Behme wrote:
> On 07.12.2015 20:03, Mark Rutland wrote:
>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>>
>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>>> +    L2_CA57: cache-controller@0 {
>>>> +        compatible = "cache";
>>>> +        arm,data-latency = <4 4 1>;
>>>> +        arm,tag-latency = <3 3 3>;
>>>
>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>> DT and configures the controller. The integrated L2 found in
>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>
>> These properties seem to be from l2cc.txt, which really only corresponds
>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>
>> I don't see that these are necessary at all.
>
>
> What's about a documentation patch like [1], then?
>
>
> For what is the arm64 dts entry
>
> cpu@0 {
>      ...
>      next-level-cache = <&L2_0>;
> };
>
> L2_0: l2-cache0 {
>      compatible = "cache";
> };
>
> good for at all, then?
>
>
> Best regards
>
> Dirk
>
>
> [1]
>
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
> b/Documentation/devicetree/bindings/arm/l2cc.txt
> index 06c88a4..f687aed 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -1,12 +1,18 @@
>   * ARM L2 Cache Controller
>
> -ARM cores often have a separate level 2 cache controller. There are
> various
> +ARM 32-bit cores often have a separate level 2 cache controller. There
> are various
>   implementations of the L2 cache controller with compatible programming
> models.
>   Some of the properties that are just prefixed "cache-*" are taken from
> section
>   3.7.3 of the ePAPR v1.1 specification which can be found at:
>
> https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
>
>
> -The ARM L2 cache representation in the device tree should be done as
> follows:
> +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 cache which

A15 and A7 are 32-bit cores, so you can't generalize it.
IMO you can just specify that this binding is applicable for separate L2
cache controllers.

-- 
-- 
Regards,
Sudeep

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 08/12/15 18:50, Dirk Behme wrote:
> On 07.12.2015 20:03, Mark Rutland wrote:
>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>>
>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>>> +    L2_CA57: cache-controller at 0 {
>>>> +        compatible = "cache";
>>>> +        arm,data-latency = <4 4 1>;
>>>> +        arm,tag-latency = <3 3 3>;
>>>
>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>> DT and configures the controller. The integrated L2 found in
>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>
>> These properties seem to be from l2cc.txt, which really only corresponds
>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>
>> I don't see that these are necessary at all.
>
>
> What's about a documentation patch like [1], then?
>
>
> For what is the arm64 dts entry
>
> cpu at 0 {
>      ...
>      next-level-cache = <&L2_0>;
> };
>
> L2_0: l2-cache0 {
>      compatible = "cache";
> };
>
> good for at all, then?
>
>
> Best regards
>
> Dirk
>
>
> [1]
>
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
> b/Documentation/devicetree/bindings/arm/l2cc.txt
> index 06c88a4..f687aed 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -1,12 +1,18 @@
>   * ARM L2 Cache Controller
>
> -ARM cores often have a separate level 2 cache controller. There are
> various
> +ARM 32-bit cores often have a separate level 2 cache controller. There
> are various
>   implementations of the L2 cache controller with compatible programming
> models.
>   Some of the properties that are just prefixed "cache-*" are taken from
> section
>   3.7.3 of the ePAPR v1.1 specification which can be found at:
>
> https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
>
>
> -The ARM L2 cache representation in the device tree should be done as
> follows:
> +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 cache which

A15 and A7 are 32-bit cores, so you can't generalize it.
IMO you can just specify that this binding is applicable for separate L2
cache controllers.

-- 
-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote:
> On 07.12.2015 20:03, Mark Rutland wrote:
> >On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> >>
> >>On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >>>+	L2_CA57: cache-controller@0 {
> >>>+		compatible = "cache";
> >>>+		arm,data-latency = <4 4 1>;
> >>>+		arm,tag-latency = <3 3 3>;
> >>
> >>Interesting, only PL2xx/3xx cache controller driver reads this from the
> >>DT and configures the controller. The integrated L2 found in
> >>A15/A7/A57/A53 needs doesn't make use of these values from the DT.
> >
> >These properties seem to be from l2cc.txt, which really only corresponds
> >to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
> >
> >I don't see that these are necessary at all.
> 
> 
> What's about a documentation patch like [1], then?

I think it would be better to s/l2cc/l2x0/, and to make it clear that
the document only applies to the variants listed above.

If ePAPR doesn't cover the other cases, we should document those
separately.

> For what is the arm64 dts entry
> 
> cpu@0 {
> 	...
> 	next-level-cache = <&L2_0>;
> };
> 
> L2_0: l2-cache0 {
> 	compatible = "cache";
> };
> 
> good for at all, then?

With the other properties from ePAPR you can acquire information on the
geometry of the cache, which cannot be acquired from architected
registers.

Thanks,
Mark.

> [1]
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
> b/Documentation/devicetree/bindings/arm/l2cc.txt
> index 06c88a4..f687aed 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -1,12 +1,18 @@
>  * ARM L2 Cache Controller
> 
> -ARM cores often have a separate level 2 cache controller. There are
> various
> +ARM 32-bit cores often have a separate level 2 cache controller.
> There are various
>  implementations of the L2 cache controller with compatible
> programming models.
>  Some of the properties that are just prefixed "cache-*" are taken
> from section
>  3.7.3 of the ePAPR v1.1 specification which can be found at:
> 
> https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
> 
> -The ARM L2 cache representation in the device tree should be done
> as follows:
> +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2
> cache which
> +doesn't make use of any values from the kernel device tree. There is no
> +L2 cache configuration done in the kernel. The L2 cache is assumed to be
> +preconfigured by early secure boot code.
> +
> +The ARM L2 cache representation for 32-bit cores in the device tree
> should be done
> +as follows:
> 
>  Required properties:
> 
> 

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote:
> On 07.12.2015 20:03, Mark Rutland wrote:
> >On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> >>
> >>On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >>>+	L2_CA57: cache-controller@0 {
> >>>+		compatible = "cache";
> >>>+		arm,data-latency = <4 4 1>;
> >>>+		arm,tag-latency = <3 3 3>;
> >>
> >>Interesting, only PL2xx/3xx cache controller driver reads this from the
> >>DT and configures the controller. The integrated L2 found in
> >>A15/A7/A57/A53 needs doesn't make use of these values from the DT.
> >
> >These properties seem to be from l2cc.txt, which really only corresponds
> >to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
> >
> >I don't see that these are necessary at all.
> 
> 
> What's about a documentation patch like [1], then?

I think it would be better to s/l2cc/l2x0/, and to make it clear that
the document only applies to the variants listed above.

If ePAPR doesn't cover the other cases, we should document those
separately.

> For what is the arm64 dts entry
> 
> cpu@0 {
> 	...
> 	next-level-cache = <&L2_0>;
> };
> 
> L2_0: l2-cache0 {
> 	compatible = "cache";
> };
> 
> good for at all, then?

With the other properties from ePAPR you can acquire information on the
geometry of the cache, which cannot be acquired from architected
registers.

Thanks,
Mark.

> [1]
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
> b/Documentation/devicetree/bindings/arm/l2cc.txt
> index 06c88a4..f687aed 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -1,12 +1,18 @@
>  * ARM L2 Cache Controller
> 
> -ARM cores often have a separate level 2 cache controller. There are
> various
> +ARM 32-bit cores often have a separate level 2 cache controller.
> There are various
>  implementations of the L2 cache controller with compatible
> programming models.
>  Some of the properties that are just prefixed "cache-*" are taken
> from section
>  3.7.3 of the ePAPR v1.1 specification which can be found at:
> 
> https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
> 
> -The ARM L2 cache representation in the device tree should be done
> as follows:
> +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2
> cache which
> +doesn't make use of any values from the kernel device tree. There is no
> +L2 cache configuration done in the kernel. The L2 cache is assumed to be
> +preconfigured by early secure boot code.
> +
> +The ARM L2 cache representation for 32-bit cores in the device tree
> should be done
> +as follows:
> 
>  Required properties:
> 
> 

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote:
> On 07.12.2015 20:03, Mark Rutland wrote:
> >On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> >>
> >>On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >>>+	L2_CA57: cache-controller at 0 {
> >>>+		compatible = "cache";
> >>>+		arm,data-latency = <4 4 1>;
> >>>+		arm,tag-latency = <3 3 3>;
> >>
> >>Interesting, only PL2xx/3xx cache controller driver reads this from the
> >>DT and configures the controller. The integrated L2 found in
> >>A15/A7/A57/A53 needs doesn't make use of these values from the DT.
> >
> >These properties seem to be from l2cc.txt, which really only corresponds
> >to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
> >
> >I don't see that these are necessary at all.
> 
> 
> What's about a documentation patch like [1], then?

I think it would be better to s/l2cc/l2x0/, and to make it clear that
the document only applies to the variants listed above.

If ePAPR doesn't cover the other cases, we should document those
separately.

> For what is the arm64 dts entry
> 
> cpu at 0 {
> 	...
> 	next-level-cache = <&L2_0>;
> };
> 
> L2_0: l2-cache0 {
> 	compatible = "cache";
> };
> 
> good for at all, then?

With the other properties from ePAPR you can acquire information on the
geometry of the cache, which cannot be acquired from architected
registers.

Thanks,
Mark.

> [1]
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
> b/Documentation/devicetree/bindings/arm/l2cc.txt
> index 06c88a4..f687aed 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -1,12 +1,18 @@
>  * ARM L2 Cache Controller
> 
> -ARM cores often have a separate level 2 cache controller. There are
> various
> +ARM 32-bit cores often have a separate level 2 cache controller.
> There are various
>  implementations of the L2 cache controller with compatible
> programming models.
>  Some of the properties that are just prefixed "cache-*" are taken
> from section
>  3.7.3 of the ePAPR v1.1 specification which can be found at:
> 
> https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
> 
> -The ARM L2 cache representation in the device tree should be done
> as follows:
> +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2
> cache which
> +doesn't make use of any values from the kernel device tree. There is no
> +L2 cache configuration done in the kernel. The L2 cache is assumed to be
> +preconfigured by early secure boot code.
> +
> +The ARM L2 cache representation for 32-bit cores in the device tree
> should be done
> +as follows:
> 
>  Required properties:
> 
> 

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Dirk Behme]

On 08.12.2015 20:16, Mark Rutland wrote:
> On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote:
>> On 07.12.2015 20:03, Mark Rutland wrote:
>>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>>>
>>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>>>> +	L2_CA57: cache-controller@0 {
>>>>> +		compatible = "cache";
>>>>> +		arm,data-latency = <4 4 1>;
>>>>> +		arm,tag-latency = <3 3 3>;
>>>>
>>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>>> DT and configures the controller. The integrated L2 found in
>>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>>
>>> These properties seem to be from l2cc.txt, which really only corresponds
>>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>>
>>> I don't see that these are necessary at all.
>>
>>
>> What's about a documentation patch like [1], then?
>
> I think it would be better to s/l2cc/l2x0/, and to make it clear that
> the document only applies to the variants listed above.
>
> If ePAPR doesn't cover the other cases, we should document those
> separately.


Ok, thanks, I'll have a look to it.


>> For what is the arm64 dts entry
>>
>> cpu@0 {
>> 	...
>> 	next-level-cache = <&L2_0>;
>> };
>>
>> L2_0: l2-cache0 {
>> 	compatible = "cache";
>> };
>>
>> good for at all, then?
>
> With the other properties from ePAPR you can acquire information on the
> geometry of the cache, which cannot be acquired from architected
> registers.


Just for my understanding: Yes, if other properties from ePAPR like 
geometry of the cache are added to the device tree l2 cache entries 
then it makes sense to have them.

But an "empty" entry like the one given in the example above doesn't 
make much sense and could be removed without loosing any functionality?

It looks to me that most of the L2 entries we have in 
arch/arm64/boot/dts are such "empty" entries.

Is this understanding correct?

Best regards

Dirk

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Dirk Behme]

On 08.12.2015 20:16, Mark Rutland wrote:
> On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote:
>> On 07.12.2015 20:03, Mark Rutland wrote:
>>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>>>
>>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>>>> +	L2_CA57: cache-controller@0 {
>>>>> +		compatible = "cache";
>>>>> +		arm,data-latency = <4 4 1>;
>>>>> +		arm,tag-latency = <3 3 3>;
>>>>
>>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>>> DT and configures the controller. The integrated L2 found in
>>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>>
>>> These properties seem to be from l2cc.txt, which really only corresponds
>>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>>
>>> I don't see that these are necessary at all.
>>
>>
>> What's about a documentation patch like [1], then?
>
> I think it would be better to s/l2cc/l2x0/, and to make it clear that
> the document only applies to the variants listed above.
>
> If ePAPR doesn't cover the other cases, we should document those
> separately.


Ok, thanks, I'll have a look to it.


>> For what is the arm64 dts entry
>>
>> cpu@0 {
>> 	...
>> 	next-level-cache = <&L2_0>;
>> };
>>
>> L2_0: l2-cache0 {
>> 	compatible = "cache";
>> };
>>
>> good for at all, then?
>
> With the other properties from ePAPR you can acquire information on the
> geometry of the cache, which cannot be acquired from architected
> registers.


Just for my understanding: Yes, if other properties from ePAPR like 
geometry of the cache are added to the device tree l2 cache entries 
then it makes sense to have them.

But an "empty" entry like the one given in the example above doesn't 
make much sense and could be removed without loosing any functionality?

It looks to me that most of the L2 entries we have in 
arch/arm64/boot/dts are such "empty" entries.

Is this understanding correct?

Best regards

Dirk

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Dirk Behme]

On 08.12.2015 20:16, Mark Rutland wrote:
> On Tue, Dec 08, 2015 at 07:50:38PM +0100, Dirk Behme wrote:
>> On 07.12.2015 20:03, Mark Rutland wrote:
>>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>>>
>>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>>>> +	L2_CA57: cache-controller at 0 {
>>>>> +		compatible = "cache";
>>>>> +		arm,data-latency = <4 4 1>;
>>>>> +		arm,tag-latency = <3 3 3>;
>>>>
>>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>>> DT and configures the controller. The integrated L2 found in
>>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>>
>>> These properties seem to be from l2cc.txt, which really only corresponds
>>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>>
>>> I don't see that these are necessary at all.
>>
>>
>> What's about a documentation patch like [1], then?
>
> I think it would be better to s/l2cc/l2x0/, and to make it clear that
> the document only applies to the variants listed above.
>
> If ePAPR doesn't cover the other cases, we should document those
> separately.


Ok, thanks, I'll have a look to it.


>> For what is the arm64 dts entry
>>
>> cpu at 0 {
>> 	...
>> 	next-level-cache = <&L2_0>;
>> };
>>
>> L2_0: l2-cache0 {
>> 	compatible = "cache";
>> };
>>
>> good for at all, then?
>
> With the other properties from ePAPR you can acquire information on the
> geometry of the cache, which cannot be acquired from architected
> registers.


Just for my understanding: Yes, if other properties from ePAPR like 
geometry of the cache are added to the device tree l2 cache entries 
then it makes sense to have them.

But an "empty" entry like the one given in the example above doesn't 
make much sense and could be removed without loosing any functionality?

It looks to me that most of the L2 entries we have in 
arch/arm64/boot/dts are such "empty" entries.

Is this understanding correct?

Best regards

Dirk

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 09/12/15 16:58, Dirk Behme wrote:
> On 08.12.2015 20:16, Mark Rutland wrote:

[...]

>>
>> With the other properties from ePAPR you can acquire information on the
>> geometry of the cache, which cannot be acquired from architected
>> registers.
>
>
> Just for my understanding: Yes, if other properties from ePAPR like
> geometry of the cache are added to the device tree l2 cache entries then
> it makes sense to have them.
>
> But an "empty" entry like the one given in the example above doesn't
> make much sense and could be removed without loosing any functionality?
>

No they are required to detect the cache hierarchy as there's no
architectural way of detecting the same.

> It looks to me that most of the L2 entries we have in
> arch/arm64/boot/dts are such "empty" entries.
>

True *so far*, we have not seen a case where we need to override the
values read in a architectural way.

-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 09/12/15 16:58, Dirk Behme wrote:
> On 08.12.2015 20:16, Mark Rutland wrote:

[...]

>>
>> With the other properties from ePAPR you can acquire information on the
>> geometry of the cache, which cannot be acquired from architected
>> registers.
>
>
> Just for my understanding: Yes, if other properties from ePAPR like
> geometry of the cache are added to the device tree l2 cache entries then
> it makes sense to have them.
>
> But an "empty" entry like the one given in the example above doesn't
> make much sense and could be removed without loosing any functionality?
>

No they are required to detect the cache hierarchy as there's no
architectural way of detecting the same.

> It looks to me that most of the L2 entries we have in
> arch/arm64/boot/dts are such "empty" entries.
>

True *so far*, we have not seen a case where we need to override the
values read in a architectural way.

-- 
Regards,
Sudeep

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 09/12/15 16:58, Dirk Behme wrote:
> On 08.12.2015 20:16, Mark Rutland wrote:

[...]

>>
>> With the other properties from ePAPR you can acquire information on the
>> geometry of the cache, which cannot be acquired from architected
>> registers.
>
>
> Just for my understanding: Yes, if other properties from ePAPR like
> geometry of the cache are added to the device tree l2 cache entries then
> it makes sense to have them.
>
> But an "empty" entry like the one given in the example above doesn't
> make much sense and could be removed without loosing any functionality?
>

No they are required to detect the cache hierarchy as there's no
architectural way of detecting the same.

> It looks to me that most of the L2 entries we have in
> arch/arm64/boot/dts are such "empty" entries.
>

True *so far*, we have not seen a case where we need to override the
values read in a architectural way.

-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote:
> >>For what is the arm64 dts entry
> >>
> >>cpu@0 {
> >>	...
> >>	next-level-cache = <&L2_0>;
> >>};
> >>
> >>L2_0: l2-cache0 {
> >>	compatible = "cache";
> >>};
> >>
> >>good for at all, then?
> >
> >With the other properties from ePAPR you can acquire information on the
> >geometry of the cache, which cannot be acquired from architected
> >registers.
> 
> 
> Just for my understanding: Yes, if other properties from ePAPR like
> geometry of the cache are added to the device tree l2 cache entries
> then it makes sense to have them.
> 
> But an "empty" entry like the one given in the example above doesn't
> make much sense and could be removed without loosing any
> functionality?
> 
> It looks to me that most of the L2 entries we have in
> arch/arm64/boot/dts are such "empty" entries.
>
> Is this understanding correct?

You are mostly correct, just missing some history.

It was previously (erroneously) assumed that the cache geometry could be
derived from architected registers used for set/way maintenance.
However, we knew that this did not describe how those caches were linked
to each other (e.g. which CPU shared with level x cache). So the
description in DT was required to provide that.

Now, we all know that the geometry is necessary too. Those DTs should be
fixed.

Sudeep, do you know what's happening on that front?

Thanks,
Mark.

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote:
> >>For what is the arm64 dts entry
> >>
> >>cpu@0 {
> >>	...
> >>	next-level-cache = <&L2_0>;
> >>};
> >>
> >>L2_0: l2-cache0 {
> >>	compatible = "cache";
> >>};
> >>
> >>good for at all, then?
> >
> >With the other properties from ePAPR you can acquire information on the
> >geometry of the cache, which cannot be acquired from architected
> >registers.
> 
> 
> Just for my understanding: Yes, if other properties from ePAPR like
> geometry of the cache are added to the device tree l2 cache entries
> then it makes sense to have them.
> 
> But an "empty" entry like the one given in the example above doesn't
> make much sense and could be removed without loosing any
> functionality?
> 
> It looks to me that most of the L2 entries we have in
> arch/arm64/boot/dts are such "empty" entries.
>
> Is this understanding correct?

You are mostly correct, just missing some history.

It was previously (erroneously) assumed that the cache geometry could be
derived from architected registers used for set/way maintenance.
However, we knew that this did not describe how those caches were linked
to each other (e.g. which CPU shared with level x cache). So the
description in DT was required to provide that.

Now, we all know that the geometry is necessary too. Those DTs should be
fixed.

Sudeep, do you know what's happening on that front?

Thanks,
Mark.

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Mark Rutland]

On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote:
> >>For what is the arm64 dts entry
> >>
> >>cpu at 0 {
> >>	...
> >>	next-level-cache = <&L2_0>;
> >>};
> >>
> >>L2_0: l2-cache0 {
> >>	compatible = "cache";
> >>};
> >>
> >>good for at all, then?
> >
> >With the other properties from ePAPR you can acquire information on the
> >geometry of the cache, which cannot be acquired from architected
> >registers.
> 
> 
> Just for my understanding: Yes, if other properties from ePAPR like
> geometry of the cache are added to the device tree l2 cache entries
> then it makes sense to have them.
> 
> But an "empty" entry like the one given in the example above doesn't
> make much sense and could be removed without loosing any
> functionality?
> 
> It looks to me that most of the L2 entries we have in
> arch/arm64/boot/dts are such "empty" entries.
>
> Is this understanding correct?

You are mostly correct, just missing some history.

It was previously (erroneously) assumed that the cache geometry could be
derived from architected registers used for set/way maintenance.
However, we knew that this did not describe how those caches were linked
to each other (e.g. which CPU shared with level x cache). So the
description in DT was required to provide that.

Now, we all know that the geometry is necessary too. Those DTs should be
fixed.

Sudeep, do you know what's happening on that front?

Thanks,
Mark.

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 09/12/15 17:21, Mark Rutland wrote:
> On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote:
>>>> For what is the arm64 dts entry
>>>>
>>>> cpu@0 {
>>>> 	...
>>>> 	next-level-cache = <&L2_0>;
>>>> };
>>>>
>>>> L2_0: l2-cache0 {
>>>> 	compatible = "cache";
>>>> };
>>>>
>>>> good for at all, then?
>>>
>>> With the other properties from ePAPR you can acquire information on the
>>> geometry of the cache, which cannot be acquired from architected
>>> registers.
>>
>>
>> Just for my understanding: Yes, if other properties from ePAPR like
>> geometry of the cache are added to the device tree l2 cache entries
>> then it makes sense to have them.
>>
>> But an "empty" entry like the one given in the example above doesn't
>> make much sense and could be removed without loosing any
>> functionality?
>>
>> It looks to me that most of the L2 entries we have in
>> arch/arm64/boot/dts are such "empty" entries.
>>
>> Is this understanding correct?
>
> You are mostly correct, just missing some history.
>
> It was previously (erroneously) assumed that the cache geometry could be
> derived from architected registers used for set/way maintenance.
> However, we knew that this did not describe how those caches were linked
> to each other (e.g. which CPU shared with level x cache). So the
> description in DT was required to provide that.
>
> Now, we all know that the geometry is necessary too. Those DTs should be
> fixed.
>
> Sudeep, do you know what's happening on that front?
>

No updates yet. I thought Alex Van Brunt would pick that. I have a patch
for PPC which never got tested/reviewed. It moves PPC code to reuse the
generic cacheinfo. If I can revive that and look into ways of moving it
to core code.

-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 09/12/15 17:21, Mark Rutland wrote:
> On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote:
>>>> For what is the arm64 dts entry
>>>>
>>>> cpu@0 {
>>>> 	...
>>>> 	next-level-cache = <&L2_0>;
>>>> };
>>>>
>>>> L2_0: l2-cache0 {
>>>> 	compatible = "cache";
>>>> };
>>>>
>>>> good for at all, then?
>>>
>>> With the other properties from ePAPR you can acquire information on the
>>> geometry of the cache, which cannot be acquired from architected
>>> registers.
>>
>>
>> Just for my understanding: Yes, if other properties from ePAPR like
>> geometry of the cache are added to the device tree l2 cache entries
>> then it makes sense to have them.
>>
>> But an "empty" entry like the one given in the example above doesn't
>> make much sense and could be removed without loosing any
>> functionality?
>>
>> It looks to me that most of the L2 entries we have in
>> arch/arm64/boot/dts are such "empty" entries.
>>
>> Is this understanding correct?
>
> You are mostly correct, just missing some history.
>
> It was previously (erroneously) assumed that the cache geometry could be
> derived from architected registers used for set/way maintenance.
> However, we knew that this did not describe how those caches were linked
> to each other (e.g. which CPU shared with level x cache). So the
> description in DT was required to provide that.
>
> Now, we all know that the geometry is necessary too. Those DTs should be
> fixed.
>
> Sudeep, do you know what's happening on that front?
>

No updates yet. I thought Alex Van Brunt would pick that. I have a patch
for PPC which never got tested/reviewed. It moves PPC code to reuse the
generic cacheinfo. If I can revive that and look into ways of moving it
to core code.

-- 
Regards,
Sudeep

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Sudeep Holla]

On 09/12/15 17:21, Mark Rutland wrote:
> On Wed, Dec 09, 2015 at 05:58:38PM +0100, Dirk Behme wrote:
>>>> For what is the arm64 dts entry
>>>>
>>>> cpu at 0 {
>>>> 	...
>>>> 	next-level-cache = <&L2_0>;
>>>> };
>>>>
>>>> L2_0: l2-cache0 {
>>>> 	compatible = "cache";
>>>> };
>>>>
>>>> good for at all, then?
>>>
>>> With the other properties from ePAPR you can acquire information on the
>>> geometry of the cache, which cannot be acquired from architected
>>> registers.
>>
>>
>> Just for my understanding: Yes, if other properties from ePAPR like
>> geometry of the cache are added to the device tree l2 cache entries
>> then it makes sense to have them.
>>
>> But an "empty" entry like the one given in the example above doesn't
>> make much sense and could be removed without loosing any
>> functionality?
>>
>> It looks to me that most of the L2 entries we have in
>> arch/arm64/boot/dts are such "empty" entries.
>>
>> Is this understanding correct?
>
> You are mostly correct, just missing some history.
>
> It was previously (erroneously) assumed that the cache geometry could be
> derived from architected registers used for set/way maintenance.
> However, we knew that this did not describe how those caches were linked
> to each other (e.g. which CPU shared with level x cache). So the
> description in DT was required to provide that.
>
> Now, we all know that the geometry is necessary too. Those DTs should be
> fixed.
>
> Sudeep, do you know what's happening on that front?
>

No updates yet. I thought Alex Van Brunt would pick that. I have a patch
for PPC which never got tested/reviewed. It moves PPC code to reuse the
generic cacheinfo. If I can revive that and look into ways of moving it
to core code.

-- 
Regards,
Sudeep

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Mark,

On Mon, Dec 7, 2015 at 9:18 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote:
>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>> >+    L2_CA57: cache-controller@0 {
>>> >+            compatible = "cache";
>>> >+            arm,data-latency = <4 4 1>;
>>> >+            arm,tag-latency = <3 3 3>;
>>>
>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>> DT and configures the controller. The integrated L2 found in
>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>
>> These properties seem to be from l2cc.txt, which really only corresponds
>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>
>> I don't see that these are necessary at all.
>
> The datasheet does mention the data/tag RAM latencies/setup values, so
> I put them in DT using the properties I could fine.

Furthermore these values are different for different SoCs in the same family
(e.g. r8a7790 vs. other R-Car Gen2 members), even though they seem to
have the same Cortex-A15 cores.

So to me these look like properties we want to document in the DTS...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Mark,

On Mon, Dec 7, 2015 at 9:18 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote:
>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>> >+    L2_CA57: cache-controller@0 {
>>> >+            compatible = "cache";
>>> >+            arm,data-latency = <4 4 1>;
>>> >+            arm,tag-latency = <3 3 3>;
>>>
>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>> DT and configures the controller. The integrated L2 found in
>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>
>> These properties seem to be from l2cc.txt, which really only corresponds
>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>
>> I don't see that these are necessary at all.
>
> The datasheet does mention the data/tag RAM latencies/setup values, so
> I put them in DT using the properties I could fine.

Furthermore these values are different for different SoCs in the same family
(e.g. r8a7790 vs. other R-Car Gen2 members), even though they seem to
have the same Cortex-A15 cores.

So to me these look like properties we want to document in the DTS...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Mark,

On Mon, Dec 7, 2015 at 9:18 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Dec 7, 2015 at 8:03 PM, Mark Rutland <mark.rutland@arm.com> wrote:
>> On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
>>> On 07/12/15 18:24, Geert Uytterhoeven wrote:
>>> >+    L2_CA57: cache-controller at 0 {
>>> >+            compatible = "cache";
>>> >+            arm,data-latency = <4 4 1>;
>>> >+            arm,tag-latency = <3 3 3>;
>>>
>>> Interesting, only PL2xx/3xx cache controller driver reads this from the
>>> DT and configures the controller. The integrated L2 found in
>>> A15/A7/A57/A53 needs doesn't make use of these values from the DT.
>>
>> These properties seem to be from l2cc.txt, which really only corresponds
>> to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.
>>
>> I don't see that these are necessary at all.
>
> The datasheet does mention the data/tag RAM latencies/setup values, so
> I put them in DT using the properties I could fine.

Furthermore these values are different for different SoCs in the same family
(e.g. r8a7790 vs. other R-Car Gen2 members), even though they seem to
have the same Cortex-A15 cores.

So to me these look like properties we want to document in the DTS...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Simon Horman]

Hi Geert,

On Mon, Dec 07, 2015 at 07:24:13PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds the missing L2 cache-controller nodes to the
> DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
> them.
> 
> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
> the respective (already existing) SYSC Power Domains. Fortunately these
> Power Domains were never powered down, as they are parents of the Power
> Domains containing CPU cores. This may change in the future.
> 
> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
> adding SYSC Power Domain support later.
> 
> Question for the ARM/DT people: What are the DT bindings for
> Cortex-A15/A7/A57/A53 L2 cache controllers?
> Everybody just seems to use "cache" for the compatible values...
> 
> Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
> ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
> (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
> and received some fixes. You can find more detailed changelogs in the
> individual patches).
> 
> This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
> r8a7795/salvator-x.

Sorry for loosing track of this until now.

It seems to me that the Gen-2 changes could be applied, is that correct?
It also seems to me that there was inconclusive discussion regarding
the r8a7795 change, is that also correct.

> 
> Thanks!
> 
> Geert Uytterhoeven (6):
>   ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes
>   ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes
>   ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node
>   arm64: renesas: r8a7795: Add L2 cache-controller nodes
> 
>  arch/arm/boot/dts/r8a73a4.dtsi           | 19 +++++++++++++++++++
>  arch/arm/boot/dts/r8a7790.dtsi           | 22 ++++++++++++++++++++++
>  arch/arm/boot/dts/r8a7791.dtsi           | 10 ++++++++++
>  arch/arm/boot/dts/r8a7793.dtsi           |  9 +++++++++
>  arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
>  6 files changed, 83 insertions(+)
> 
> -- 
> 1.9.1
> 
> Gr{oetje,eeting}s,
> 
> 						Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> 							    -- Linus Torvalds
> 

Re: [PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Simon Horman]

Hi Geert,

On Mon, Dec 07, 2015 at 07:24:13PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds the missing L2 cache-controller nodes to the
> DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
> them.
> 
> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
> the respective (already existing) SYSC Power Domains. Fortunately these
> Power Domains were never powered down, as they are parents of the Power
> Domains containing CPU cores. This may change in the future.
> 
> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
> adding SYSC Power Domain support later.
> 
> Question for the ARM/DT people: What are the DT bindings for
> Cortex-A15/A7/A57/A53 L2 cache controllers?
> Everybody just seems to use "cache" for the compatible values...
> 
> Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
> ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
> (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
> and received some fixes. You can find more detailed changelogs in the
> individual patches).
> 
> This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
> r8a7795/salvator-x.

Sorry for loosing track of this until now.

It seems to me that the Gen-2 changes could be applied, is that correct?
It also seems to me that there was inconclusive discussion regarding
the r8a7795 change, is that also correct.

> 
> Thanks!
> 
> Geert Uytterhoeven (6):
>   ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes
>   ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes
>   ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node
>   arm64: renesas: r8a7795: Add L2 cache-controller nodes
> 
>  arch/arm/boot/dts/r8a73a4.dtsi           | 19 +++++++++++++++++++
>  arch/arm/boot/dts/r8a7790.dtsi           | 22 ++++++++++++++++++++++
>  arch/arm/boot/dts/r8a7791.dtsi           | 10 ++++++++++
>  arch/arm/boot/dts/r8a7793.dtsi           |  9 +++++++++
>  arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
>  6 files changed, 83 insertions(+)
> 
> -- 
> 1.9.1
> 
> Gr{oetje,eeting}s,
> 
> 						Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> 							    -- Linus Torvalds
> 

[PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Simon Horman]

Hi Geert,

On Mon, Dec 07, 2015 at 07:24:13PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds the missing L2 cache-controller nodes to the
> DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
> them.
> 
> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
> the respective (already existing) SYSC Power Domains. Fortunately these
> Power Domains were never powered down, as they are parents of the Power
> Domains containing CPU cores. This may change in the future.
> 
> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
> adding SYSC Power Domain support later.
> 
> Question for the ARM/DT people: What are the DT bindings for
> Cortex-A15/A7/A57/A53 L2 cache controllers?
> Everybody just seems to use "cache" for the compatible values...
> 
> Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
> ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
> (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
> and received some fixes. You can find more detailed changelogs in the
> individual patches).
> 
> This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
> r8a7795/salvator-x.

Sorry for loosing track of this until now.

It seems to me that the Gen-2 changes could be applied, is that correct?
It also seems to me that there was inconclusive discussion regarding
the r8a7795 change, is that also correct.

> 
> Thanks!
> 
> Geert Uytterhoeven (6):
>   ARM: shmobile: r8a73a4 dtsi: Add L2 cache-controller nodes
>   ARM: shmobile: r8a7790 dtsi: Add L2 cache-controller nodes
>   ARM: shmobile: r8a7791 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7793 dtsi: Add L2 cache-controller node
>   ARM: shmobile: r8a7794 dtsi: Add L2 cache-controller node
>   arm64: renesas: r8a7795: Add L2 cache-controller nodes
> 
>  arch/arm/boot/dts/r8a73a4.dtsi           | 19 +++++++++++++++++++
>  arch/arm/boot/dts/r8a7790.dtsi           | 22 ++++++++++++++++++++++
>  arch/arm/boot/dts/r8a7791.dtsi           | 10 ++++++++++
>  arch/arm/boot/dts/r8a7793.dtsi           |  9 +++++++++
>  arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++++++++++++++
>  6 files changed, 83 insertions(+)
> 
> -- 
> 1.9.1
> 
> Gr{oetje,eeting}s,
> 
> 						Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> 							    -- Linus Torvalds
> 

Re: [PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Simon,

On Mon, Feb 15, 2016 at 2:58 AM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, Dec 07, 2015 at 07:24:13PM +0100, Geert Uytterhoeven wrote:
>> This patch series adds the missing L2 cache-controller nodes to the
>> DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
>> them.
>>
>> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
>> the respective (already existing) SYSC Power Domains. Fortunately these
>> Power Domains were never powered down, as they are parents of the Power
>> Domains containing CPU cores. This may change in the future.
>>
>> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
>> adding SYSC Power Domain support later.
>>
>> Question for the ARM/DT people: What are the DT bindings for
>> Cortex-A15/A7/A57/A53 L2 cache controllers?
>> Everybody just seems to use "cache" for the compatible values...
>>
>> Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
>> ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
>> (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
>> and received some fixes. You can find more detailed changelogs in the
>> individual patches).
>>
>> This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
>> r8a7795/salvator-x.
>
> Sorry for loosing track of this until now.
>
> It seems to me that the Gen-2 changes could be applied, is that correct?

And APE6 :-)

> It also seems to me that there was inconclusive discussion regarding
> the r8a7795 change, is that also correct.

There was discussion (for all SoCs) about the presence of the arm,data-latency
and arm,tag-latency properties. Given the mess^H^H^H^H presence or
absence of virtualization they may or may not be valid...

I think the way forward (keeping the dependency for SYSC PM Domains in mind) is
to apply the series, after removing the controversial latency properties.

Should I resend, or can/will you handle that?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Simon,

On Mon, Feb 15, 2016 at 2:58 AM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, Dec 07, 2015 at 07:24:13PM +0100, Geert Uytterhoeven wrote:
>> This patch series adds the missing L2 cache-controller nodes to the
>> DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
>> them.
>>
>> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
>> the respective (already existing) SYSC Power Domains. Fortunately these
>> Power Domains were never powered down, as they are parents of the Power
>> Domains containing CPU cores. This may change in the future.
>>
>> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
>> adding SYSC Power Domain support later.
>>
>> Question for the ARM/DT people: What are the DT bindings for
>> Cortex-A15/A7/A57/A53 L2 cache controllers?
>> Everybody just seems to use "cache" for the compatible values...
>>
>> Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
>> ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
>> (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
>> and received some fixes. You can find more detailed changelogs in the
>> individual patches).
>>
>> This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
>> r8a7795/salvator-x.
>
> Sorry for loosing track of this until now.
>
> It seems to me that the Gen-2 changes could be applied, is that correct?

And APE6 :-)

> It also seems to me that there was inconclusive discussion regarding
> the r8a7795 change, is that also correct.

There was discussion (for all SoCs) about the presence of the arm,data-latency
and arm,tag-latency properties. Given the mess^H^H^H^H presence or
absence of virtualization they may or may not be valid...

I think the way forward (keeping the dependency for SYSC PM Domains in mind) is
to apply the series, after removing the controversial latency properties.

Should I resend, or can/will you handle that?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 0/6] ARM/arm64 : shmobile/renesas: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Hi Simon,

On Mon, Feb 15, 2016 at 2:58 AM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, Dec 07, 2015 at 07:24:13PM +0100, Geert Uytterhoeven wrote:
>> This patch series adds the missing L2 cache-controller nodes to the
>> DTSes for various Renesas ARM-based SoCs, and links the CPU nodes to
>> them.
>>
>> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
>> the respective (already existing) SYSC Power Domains. Fortunately these
>> Power Domains were never powered down, as they are parents of the Power
>> Domains containing CPU cores. This may change in the future.
>>
>> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
>> adding SYSC Power Domain support later.
>>
>> Question for the ARM/DT people: What are the DT bindings for
>> Cortex-A15/A7/A57/A53 L2 cache controllers?
>> Everybody just seems to use "cache" for the compatible values...
>>
>> Patches 2-5 were extracted from series "[PATCH/RFC 00/15]
>> ARM: shmobile: R-Car: Add SYSC PM Domain DT Support",
>> (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/348742.html)
>> and received some fixes. You can find more detailed changelogs in the
>> individual patches).
>>
>> This has been tested on r8a73a4/ape6evm, r8a7791/koelsch, and
>> r8a7795/salvator-x.
>
> Sorry for loosing track of this until now.
>
> It seems to me that the Gen-2 changes could be applied, is that correct?

And APE6 :-)

> It also seems to me that there was inconclusive discussion regarding
> the r8a7795 change, is that also correct.

There was discussion (for all SoCs) about the presence of the arm,data-latency
and arm,tag-latency properties. Given the mess^H^H^H^H presence or
absence of virtualization they may or may not be valid...

I think the way forward (keeping the dependency for SYSC PM Domains in mind) is
to apply the series, after removing the controversial latency properties.

Should I resend, or can/will you handle that?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds