* [PATCH v1 0/8] This serial of patches add dts/pinctrl/clock-tree/doc for rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, devicetree, Michael Turquette, linux-gpio, Stephen Boyd, Linus Walleij, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, linux-clk, Xing Zheng platform, with these patches, my evb board could boot into initramfs. Jeffy Chen (8): pinctrl: rockchip: add support for the rk3228 clk: rockchip: add dt-binding header for rk3228 rockchip: add clock controller for rk3228 dt-bindings: add documentation of rk3228 clock controller clk: rockchip: allow more than 2 parents for cpuclk ARM: rockchip: enable support for RK3228 SoCs ARM: dts: rockchip: add core rk3228 dtsi ARM: dts: rockchip: add rk3228-evb board .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++ .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3228-evb.dts | 56 ++ arch/arm/boot/dts/rk3228.dtsi | 478 +++++++++++++ arch/arm/mach-rockchip/rockchip.c | 1 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-cpu.c | 4 +- drivers/clk/rockchip/clk-rk3228.c | 762 +++++++++++++++++++++ drivers/clk/rockchip/clk.h | 11 +- drivers/pinctrl/pinctrl-rockchip.c | 53 ++ include/dt-bindings/clock/rk3228-cru.h | 220 ++++++ 12 files changed, 1644 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt create mode 100644 arch/arm/boot/dts/rk3228-evb.dts create mode 100644 arch/arm/boot/dts/rk3228.dtsi create mode 100644 drivers/clk/rockchip/clk-rk3228.c create mode 100644 include/dt-bindings/clock/rk3228-cru.h -- 2.1.4 ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 0/8] This serial of patches add dts/pinctrl/clock-tree/doc for rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel platform, with these patches, my evb board could boot into initramfs. Jeffy Chen (8): pinctrl: rockchip: add support for the rk3228 clk: rockchip: add dt-binding header for rk3228 rockchip: add clock controller for rk3228 dt-bindings: add documentation of rk3228 clock controller clk: rockchip: allow more than 2 parents for cpuclk ARM: rockchip: enable support for RK3228 SoCs ARM: dts: rockchip: add core rk3228 dtsi ARM: dts: rockchip: add rk3228-evb board .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++ .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3228-evb.dts | 56 ++ arch/arm/boot/dts/rk3228.dtsi | 478 +++++++++++++ arch/arm/mach-rockchip/rockchip.c | 1 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-cpu.c | 4 +- drivers/clk/rockchip/clk-rk3228.c | 762 +++++++++++++++++++++ drivers/clk/rockchip/clk.h | 11 +- drivers/pinctrl/pinctrl-rockchip.c | 53 ++ include/dt-bindings/clock/rk3228-cru.h | 220 ++++++ 12 files changed, 1644 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt create mode 100644 arch/arm/boot/dts/rk3228-evb.dts create mode 100644 arch/arm/boot/dts/rk3228.dtsi create mode 100644 drivers/clk/rockchip/clk-rk3228.c create mode 100644 include/dt-bindings/clock/rk3228-cru.h -- 2.1.4 ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 9:04 ` Jeffy Chen -1 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, devicetree, linux-gpio, Linus Walleij, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland The pinctrl of rk3228 is much the same as rk3288's, but without pmu. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- drivers/pinctrl/pinctrl-rockchip.c | 53 ++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 391ef4b..0cd701b 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" + "rockchip,rk3368-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a065112..faab36e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3228_PULL_OFFSET 0x100 + +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_PULL_OFFSET; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; +} + +#define RK3228_DRV_GRF_OFFSET 0x200 + +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_DRV_GRF_OFFSET; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3228_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, +}; + static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -2220,6 +2271,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = (void *)&rk3188_pin_ctrl }, + { .compatible = "rockchip,rk3228-pinctrl", + .data = (void *)&rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel The pinctrl of rk3228 is much the same as rk3288's, but without pmu. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- drivers/pinctrl/pinctrl-rockchip.c | 53 ++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 391ef4b..0cd701b 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" + "rockchip,rk3368-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a065112..faab36e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3228_PULL_OFFSET 0x100 + +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_PULL_OFFSET; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; +} + +#define RK3228_DRV_GRF_OFFSET 0x200 + +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_DRV_GRF_OFFSET; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3228_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, +}; + static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -2220,6 +2271,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = (void *)&rk3188_pin_ctrl }, + { .compatible = "rockchip,rk3228-pinctrl", + .data = (void *)&rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 11:30 ` Heiko Stübner -1 siblings, 0 replies; 58+ messages in thread From: Heiko Stübner @ 2015-12-09 11:30 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, linux-gpio, Linus Walleij, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Jeffy, Am Mittwoch, 9. Dezember 2015, 17:04:06 schrieb Jeffy Chen: > The pinctrl of rk3228 is much the same as rk3288's, but > without pmu. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> After verifying the offset and register-layout values with the TRM Reviewed-by: Heiko Stuebner <heiko@sntech.de> I just love how that still seems to fit for new socs ;-) Thanks Heiko > --- > > .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- > drivers/pinctrl/pinctrl-rockchip.c | 53 > ++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index > 391ef4b..0cd701b 100644 > --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. > Required properties for iomux controller: > - compatible: one of "rockchip,rk2928-pinctrl", > "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", > "rockchip,rk3188-pinctrl" > - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" > + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" > + "rockchip,rk3368-pinctrl" > - rockchip,grf: phandle referencing a syscon providing the > "general register files" > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c > b/drivers/pinctrl/pinctrl-rockchip.c index a065112..faab36e 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct > rockchip_pin_bank *bank, } > } > > +#define RK3228_PULL_OFFSET 0x100 > + > +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_PULL_OFFSET; > + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; > + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); > + *bit *= RK3188_PULL_BITS_PER_PIN; > +} > + > +#define RK3228_DRV_GRF_OFFSET 0x200 > + > +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_DRV_GRF_OFFSET; > + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; > + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); > + *bit *= RK3288_DRV_BITS_PER_PIN; > +} > + > #define RK3368_PULL_GRF_OFFSET 0x100 > #define RK3368_PULL_PMU_OFFSET 0x10 > > @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { > .pull_calc_reg = rk3188_calc_pull_reg_and_bit, > }; > > +static struct rockchip_pin_bank rk3228_pin_banks[] = { > + PIN_BANK(0, 32, "gpio0"), > + PIN_BANK(1, 32, "gpio1"), > + PIN_BANK(2, 32, "gpio2"), > + PIN_BANK(3, 32, "gpio3"), > +}; > + > +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { > + .pin_banks = rk3228_pin_banks, > + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), > + .label = "RK3228-GPIO", > + .type = RK3288, > + .grf_mux_offset = 0x0, > + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, > + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, > +}; > + > static struct rockchip_pin_bank rk3288_pin_banks[] = { > PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, > IOMUX_SOURCE_PMU, > @@ -2220,6 +2271,8 @@ static const struct of_device_id > rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, > { .compatible = "rockchip,rk3188-pinctrl", > .data = (void *)&rk3188_pin_ctrl }, > + { .compatible = "rockchip,rk3228-pinctrl", > + .data = (void *)&rk3228_pin_ctrl }, > { .compatible = "rockchip,rk3288-pinctrl", > .data = (void *)&rk3288_pin_ctrl }, > { .compatible = "rockchip,rk3368-pinctrl", ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 @ 2015-12-09 11:30 ` Heiko Stübner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stübner @ 2015-12-09 11:30 UTC (permalink / raw) To: linux-arm-kernel Hi Jeffy, Am Mittwoch, 9. Dezember 2015, 17:04:06 schrieb Jeffy Chen: > The pinctrl of rk3228 is much the same as rk3288's, but > without pmu. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> After verifying the offset and register-layout values with the TRM Reviewed-by: Heiko Stuebner <heiko@sntech.de> I just love how that still seems to fit for new socs ;-) Thanks Heiko > --- > > .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- > drivers/pinctrl/pinctrl-rockchip.c | 53 > ++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index > 391ef4b..0cd701b 100644 > --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. > Required properties for iomux controller: > - compatible: one of "rockchip,rk2928-pinctrl", > "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", > "rockchip,rk3188-pinctrl" > - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" > + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" > + "rockchip,rk3368-pinctrl" > - rockchip,grf: phandle referencing a syscon providing the > "general register files" > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c > b/drivers/pinctrl/pinctrl-rockchip.c index a065112..faab36e 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct > rockchip_pin_bank *bank, } > } > > +#define RK3228_PULL_OFFSET 0x100 > + > +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_PULL_OFFSET; > + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; > + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); > + *bit *= RK3188_PULL_BITS_PER_PIN; > +} > + > +#define RK3228_DRV_GRF_OFFSET 0x200 > + > +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_DRV_GRF_OFFSET; > + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; > + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); > + *bit *= RK3288_DRV_BITS_PER_PIN; > +} > + > #define RK3368_PULL_GRF_OFFSET 0x100 > #define RK3368_PULL_PMU_OFFSET 0x10 > > @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { > .pull_calc_reg = rk3188_calc_pull_reg_and_bit, > }; > > +static struct rockchip_pin_bank rk3228_pin_banks[] = { > + PIN_BANK(0, 32, "gpio0"), > + PIN_BANK(1, 32, "gpio1"), > + PIN_BANK(2, 32, "gpio2"), > + PIN_BANK(3, 32, "gpio3"), > +}; > + > +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { > + .pin_banks = rk3228_pin_banks, > + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), > + .label = "RK3228-GPIO", > + .type = RK3288, > + .grf_mux_offset = 0x0, > + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, > + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, > +}; > + > static struct rockchip_pin_bank rk3288_pin_banks[] = { > PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, > IOMUX_SOURCE_PMU, > @@ -2220,6 +2271,8 @@ static const struct of_device_id > rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, > { .compatible = "rockchip,rk3188-pinctrl", > .data = (void *)&rk3188_pin_ctrl }, > + { .compatible = "rockchip,rk3228-pinctrl", > + .data = (void *)&rk3228_pin_ctrl }, > { .compatible = "rockchip,rk3288-pinctrl", > .data = (void *)&rk3288_pin_ctrl }, > { .compatible = "rockchip,rk3368-pinctrl", ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 20:09 ` Rob Herring -1 siblings, 0 replies; 58+ messages in thread From: Rob Herring @ 2015-12-09 20:09 UTC (permalink / raw) To: Jeffy Chen Cc: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, linux-gpio, Linus Walleij, Kumar Gala, Ian Campbell, Pawel Moll, Mark Rutland On Wed, Dec 09, 2015 at 05:04:06PM +0800, Jeffy Chen wrote: > The pinctrl of rk3228 is much the same as rk3288's, but > without pmu. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > --- > > .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- For the binding: Acked-by: Rob Herring <robh@kernel.org> > drivers/pinctrl/pinctrl-rockchip.c | 53 ++++++++++++++++++++++ > 2 files changed, 55 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > index 391ef4b..0cd701b 100644 > --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. > Required properties for iomux controller: > - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" > "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" > - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" > + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" > + "rockchip,rk3368-pinctrl" > - rockchip,grf: phandle referencing a syscon providing the > "general register files" > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c > index a065112..faab36e 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, > } > } > > +#define RK3228_PULL_OFFSET 0x100 > + > +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_PULL_OFFSET; > + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; > + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); > + *bit *= RK3188_PULL_BITS_PER_PIN; > +} > + > +#define RK3228_DRV_GRF_OFFSET 0x200 > + > +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_DRV_GRF_OFFSET; > + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; > + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); > + *bit *= RK3288_DRV_BITS_PER_PIN; > +} > + > #define RK3368_PULL_GRF_OFFSET 0x100 > #define RK3368_PULL_PMU_OFFSET 0x10 > > @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { > .pull_calc_reg = rk3188_calc_pull_reg_and_bit, > }; > > +static struct rockchip_pin_bank rk3228_pin_banks[] = { > + PIN_BANK(0, 32, "gpio0"), > + PIN_BANK(1, 32, "gpio1"), > + PIN_BANK(2, 32, "gpio2"), > + PIN_BANK(3, 32, "gpio3"), > +}; > + > +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { > + .pin_banks = rk3228_pin_banks, > + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), > + .label = "RK3228-GPIO", > + .type = RK3288, > + .grf_mux_offset = 0x0, > + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, > + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, > +}; > + > static struct rockchip_pin_bank rk3288_pin_banks[] = { > PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, > IOMUX_SOURCE_PMU, > @@ -2220,6 +2271,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { > .data = (void *)&rk3066b_pin_ctrl }, > { .compatible = "rockchip,rk3188-pinctrl", > .data = (void *)&rk3188_pin_ctrl }, > + { .compatible = "rockchip,rk3228-pinctrl", > + .data = (void *)&rk3228_pin_ctrl }, > { .compatible = "rockchip,rk3288-pinctrl", > .data = (void *)&rk3288_pin_ctrl }, > { .compatible = "rockchip,rk3368-pinctrl", > -- > 2.1.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 @ 2015-12-09 20:09 ` Rob Herring 0 siblings, 0 replies; 58+ messages in thread From: Rob Herring @ 2015-12-09 20:09 UTC (permalink / raw) To: linux-arm-kernel On Wed, Dec 09, 2015 at 05:04:06PM +0800, Jeffy Chen wrote: > The pinctrl of rk3228 is much the same as rk3288's, but > without pmu. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > --- > > .../bindings/pinctrl/rockchip,pinctrl.txt | 3 +- For the binding: Acked-by: Rob Herring <robh@kernel.org> > drivers/pinctrl/pinctrl-rockchip.c | 53 ++++++++++++++++++++++ > 2 files changed, 55 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > index 391ef4b..0cd701b 100644 > --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. > Required properties for iomux controller: > - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" > "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" > - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" > + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" > + "rockchip,rk3368-pinctrl" > - rockchip,grf: phandle referencing a syscon providing the > "general register files" > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c > index a065112..faab36e 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, > } > } > > +#define RK3228_PULL_OFFSET 0x100 > + > +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_PULL_OFFSET; > + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; > + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); > + *bit *= RK3188_PULL_BITS_PER_PIN; > +} > + > +#define RK3228_DRV_GRF_OFFSET 0x200 > + > +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, > + int pin_num, struct regmap **regmap, > + int *reg, u8 *bit) > +{ > + struct rockchip_pinctrl *info = bank->drvdata; > + > + *regmap = info->regmap_base; > + *reg = RK3228_DRV_GRF_OFFSET; > + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; > + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); > + > + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); > + *bit *= RK3288_DRV_BITS_PER_PIN; > +} > + > #define RK3368_PULL_GRF_OFFSET 0x100 > #define RK3368_PULL_PMU_OFFSET 0x10 > > @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { > .pull_calc_reg = rk3188_calc_pull_reg_and_bit, > }; > > +static struct rockchip_pin_bank rk3228_pin_banks[] = { > + PIN_BANK(0, 32, "gpio0"), > + PIN_BANK(1, 32, "gpio1"), > + PIN_BANK(2, 32, "gpio2"), > + PIN_BANK(3, 32, "gpio3"), > +}; > + > +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { > + .pin_banks = rk3228_pin_banks, > + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), > + .label = "RK3228-GPIO", > + .type = RK3288, > + .grf_mux_offset = 0x0, > + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, > + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, > +}; > + > static struct rockchip_pin_bank rk3288_pin_banks[] = { > PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, > IOMUX_SOURCE_PMU, > @@ -2220,6 +2271,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { > .data = (void *)&rk3066b_pin_ctrl }, > { .compatible = "rockchip,rk3188-pinctrl", > .data = (void *)&rk3188_pin_ctrl }, > + { .compatible = "rockchip,rk3228-pinctrl", > + .data = (void *)&rk3228_pin_ctrl }, > { .compatible = "rockchip,rk3288-pinctrl", > .data = (void *)&rk3288_pin_ctrl }, > { .compatible = "rockchip,rk3368-pinctrl", > -- > 2.1.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-11 18:10 ` Linus Walleij -1 siblings, 0 replies; 58+ messages in thread From: Linus Walleij @ 2015-12-11 18:10 UTC (permalink / raw) To: Jeffy Chen Cc: Heiko Stübner, Russell King - ARM Linux, linux-arm-kernel, open list:ARM/Rockchip SoC..., linux-kernel, devicetree, linux-gpio, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland On Wed, Dec 9, 2015 at 10:04 AM, Jeffy Chen <jeffy.chen@rock-chips.com> wrote: > The pinctrl of rk3228 is much the same as rk3288's, but > without pmu. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Patch applied with Heiko's and Rob's Review/ACKs. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 @ 2015-12-11 18:10 ` Linus Walleij 0 siblings, 0 replies; 58+ messages in thread From: Linus Walleij @ 2015-12-11 18:10 UTC (permalink / raw) To: linux-arm-kernel On Wed, Dec 9, 2015 at 10:04 AM, Jeffy Chen <jeffy.chen@rock-chips.com> wrote: > The pinctrl of rk3228 is much the same as rk3288's, but > without pmu. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Patch applied with Heiko's and Rob's Review/ACKs. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 2/8] clk: rockchip: add dt-binding header for rk3228 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 9:04 ` Jeffy Chen -1 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Add the dt-bindings header for the rk3228, that gets shared between the clock controller and the clock references in the dts. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- include/dt-bindings/clock/rk3228-cru.h | 220 +++++++++++++++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 include/dt-bindings/clock/rk3228-cru.h diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h new file mode 100644 index 0000000..a78dd89 --- /dev/null +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_PERI 363 + +/* hclk gates */ +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 2/8] clk: rockchip: add dt-binding header for rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel Add the dt-bindings header for the rk3228, that gets shared between the clock controller and the clock references in the dts. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- include/dt-bindings/clock/rk3228-cru.h | 220 +++++++++++++++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 include/dt-bindings/clock/rk3228-cru.h diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h new file mode 100644 index 0000000..a78dd89 --- /dev/null +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_PERI 363 + +/* hclk gates */ +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 2/8] clk: rockchip: add dt-binding header for rk3228 @ 2015-12-09 23:17 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:17 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Am Mittwoch, 9. Dezember 2015, 17:04:07 schrieb Jeffy Chen: > Add the dt-bindings header for the rk3228, that gets shared between > the clock controller and the clock references in the dts. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my clk branch for 4.5 ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 2/8] clk: rockchip: add dt-binding header for rk3228 @ 2015-12-09 23:17 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:17 UTC (permalink / raw) To: linux-arm-kernel Am Mittwoch, 9. Dezember 2015, 17:04:07 schrieb Jeffy Chen: > Add the dt-bindings header for the rk3228, that gets shared between > the clock controller and the clock references in the dts. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my clk branch for 4.5 ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 2/8] clk: rockchip: add dt-binding header for rk3228 @ 2015-12-09 23:17 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:17 UTC (permalink / raw) To: Jeffy Chen Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ, Pawel Moll, Ian Campbell, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Kumar Gala, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Am Mittwoch, 9. Dezember 2015, 17:04:07 schrieb Jeffy Chen: > Add the dt-bindings header for the rk3228, that gets shared between > the clock controller and the clock references in the dts. > > Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> applied to my clk branch for 4.5 ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 3/8] rockchip: add clock controller for rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, Michael Turquette, Stephen Boyd, linux-clk Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 11 +- 3 files changed, 773 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/rockchip/clk-rk3228.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index d599829..80b9a37 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-y += clk-rk3036.o obj-y += clk-rk3188.o +obj-y += clk-rk3228.o obj-y += clk-rk3288.o obj-y += clk-rk3368.o diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c new file mode 100644 index 0000000..eb3701e --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -0,0 +1,762 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include "clk.h" + +#define RK3228_GRF_SOC_STATUS0 0x480 + +enum rk3228_plls { + apll, dpll, cpll, gpll, +}; + +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +#define RK3228_DIV_CPU_MASK 0x1f +#define RK3228_DIV_CPU_SHIFT 8 + +#define RK3228_DIV_PERI_MASK 0xf +#define RK3228_DIV_PERI_SHIFT 0 +#define RK3228_DIV_ACLK_MASK 0x7 +#define RK3228_DIV_ACLK_SHIFT 4 +#define RK3228_DIV_HCLK_MASK 0x3 +#define RK3228_DIV_HCLK_SHIFT 8 +#define RK3228_DIV_PCLK_MASK 0x7 +#define RK3228_DIV_PCLK_SHIFT 12 + +#define RK3228_CLKSEL1(_core_peri_div) \ + { \ + .reg = RK2928_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ + RK3228_DIV_PERI_SHIFT) \ + } + +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ + { \ + .prate = _prate, \ + .divs = { \ + RK3228_CLKSEL1(_core_peri_div), \ + }, \ + } + +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { + RK3228_CPUCLK_RATE(816000000, 4), + RK3228_CPUCLK_RATE(600000000, 4), + RK3228_CPUCLK_RATE(312000000, 4), +}; + +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { + .core_reg = RK2928_CLKSEL_CON(0), + .div_core_shift = 0, + .div_core_mask = 0x1f, + .mux_core_shift = 6, +}; + +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; + +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; + +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; + +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; + +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; + +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; + +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; + +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; + +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; + +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), + RK2928_MODE_CON, 4, 6, 0, NULL), + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), + RK2928_MODE_CON, 8, 8, 0, NULL), + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { + /* + * Clock-Architecture Diagram 1 + */ + + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), + + /* PD_DDR */ + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, + RK2928_CLKGATE_CON(7), 1, GFLAGS), + + /* PD_CORE */ + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK2928_CLKGATE_CON(4), 1, GFLAGS), + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK2928_CLKGATE_CON(4), 0, GFLAGS), + + /* PD_MISC */ + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 13, 1, MFLAGS), + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 14, 1, MFLAGS), + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 15, 1, MFLAGS), + + /* PD_BUS */ + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, + RK2928_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(6), 1, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, + RK2928_CLKGATE_CON(6), 2, GFLAGS), + GATE(0, "pclk_cpu", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 3, GFLAGS), + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 4, GFLAGS), + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 13, GFLAGS), + + /* PD_VIDEO */ + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(4), 4, GFLAGS), + + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(4), 5, GFLAGS), + + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), + + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), + + /* PD_VIO */ + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), + + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), + + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, + RK2928_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), + + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), + + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, + RK2928_CLKGATE_CON(3), 7, GFLAGS), + + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), + + /* PD_PERI */ + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, + RK2928_CLKGATE_CON(5), 2, GFLAGS), + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, + RK2928_CLKGATE_CON(5), 1, GFLAGS), + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, + RK2928_CLKGATE_CON(5), 0, GFLAGS), + + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, + RK2928_CLKGATE_CON(6), 5, GFLAGS), + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, + RK2928_CLKGATE_CON(6), 6, GFLAGS), + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, + RK2928_CLKGATE_CON(6), 7, GFLAGS), + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, + RK2928_CLKGATE_CON(6), 8, GFLAGS), + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, + RK2928_CLKGATE_CON(6), 9, GFLAGS), + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, + RK2928_CLKGATE_CON(6), 10, GFLAGS), + + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), + + GATE(0, "sclk_hsadc", "ext_hsadc", 0, + RK3288_CLKGATE_CON(10), 12, GFLAGS), + + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), + + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), + + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, + RK2928_CLKGATE_CON(2), 13, GFLAGS), + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), + + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, + RK2928_CLKGATE_CON(2), 14, GFLAGS), + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), + + /* + * Clock-Architecture Diagram 2 + */ + + GATE(0, "gpll_vop", "gpll", 0, + RK2928_CLKGATE_CON(3), 1, GFLAGS), + GATE(0, "cpll_vop", "cpll", 0, + RK2928_CLKGATE_CON(3), 1, GFLAGS), + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), + + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(8), 0, + RK3288_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(0), 5, GFLAGS), + + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(7), 0, + RK3288_CLKGATE_CON(0), 11, GFLAGS), + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, + RK2928_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, + RK2928_CLKGATE_CON(0), 13, GFLAGS), + + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(30), 0, + RK3288_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(0), 9, GFLAGS), + + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(20), 0, + RK3288_CLKGATE_CON(2), 12, GFLAGS), + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), + + GATE(0, "jtag", "ext_jtag", 0, + RK2928_CLKGATE_CON(1), 3, GFLAGS), + + GATE(0, "sclk_otgphy0", "xin24m", 0, + RK2928_CLKGATE_CON(1), 5, GFLAGS), + GATE(0, "sclk_otgphy1", "xin24m", 0, + RK2928_CLKGATE_CON(1), 6, GFLAGS), + + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, + RK2928_CLKGATE_CON(2), 8, GFLAGS), + + GATE(0, "cpll_gpu", "cpll", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "gpll_gpu", "gpll", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "usb480m_gpu", "usb480m", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), + + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), + + /* PD_UART */ + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, + 0, RK2928_CLKSEL_CON(15), 12, 2, + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(17), 0, + RK2928_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(18), 0, + RK2928_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(19), 0, + RK2928_CLKGATE_CON(1), 13, GFLAGS), + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), + + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), + + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 4, GFLAGS), + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 3, GFLAGS), + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 5, GFLAGS), + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 6, GFLAGS), + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), + + /* + * Clock-Architecture Diagram 3 + */ + + /* PD_VOP */ + GATE(0, "aclk_rga", "aclk_rga_pre", 0, + RK2928_CLKGATE_CON(13), 0, GFLAGS), + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, + RK2928_CLKGATE_CON(13), 11, GFLAGS), + GATE(0, "aclk_iep", "aclk_iep_pre", 0, + RK2928_CLKGATE_CON(13), 2, GFLAGS), + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, + RK2928_CLKGATE_CON(13), 9, GFLAGS), + + GATE(0, "aclk_vop", "aclk_vop_pre", 0, + RK2928_CLKGATE_CON(13), 5, GFLAGS), + GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, + RK2928_CLKGATE_CON(13), 12, GFLAGS), + + GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, + RK2928_CLKGATE_CON(14), 10, GFLAGS), + GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, + RK2928_CLKGATE_CON(13), 10, GFLAGS), + + GATE(0, "hclk_rga", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 1, GFLAGS), + GATE(0, "hclk_iep", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 3, GFLAGS), + GATE(0, "hclk_vop", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 6, GFLAGS), + GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 7, GFLAGS), + GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 8, GFLAGS), + GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 13, GFLAGS), + GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 7, GFLAGS), + GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 12, GFLAGS), + GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 6, GFLAGS), + GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 8, GFLAGS), + GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 11, GFLAGS), + + /* PD_PERI */ + GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 0, GFLAGS), + GATE(0, "aclk_gmac", "aclk_peri", 0, + RK2928_CLKGATE_CON(11), 4, GFLAGS), + + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 0, GFLAGS), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 1, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 2, GFLAGS), + GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 3, GFLAGS), + GATE(0, "hclk_host0", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 6, GFLAGS), + GATE(0, "hclk_host0_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 7, GFLAGS), + GATE(0, "hclk_host1", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 8, GFLAGS), + GATE(0, "hclk_host1_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 9, GFLAGS), + GATE(0, "hclk_host2", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 10, GFLAGS), + GATE(0, "hclk_otg", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 12, GFLAGS), + GATE(0, "hclk_otg_pmu", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 13, GFLAGS), + GATE(0, "hclk_host2_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 14, GFLAGS), + GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 1, GFLAGS), + + GATE(0, "pclk_gmac", "pclk_peri", 0, + RK2928_CLKGATE_CON(11), 5, GFLAGS), + GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 2, GFLAGS), + + /* PD_GPU */ + GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, + RK2928_CLKGATE_CON(13), 14, GFLAGS), + GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, + RK2928_CLKGATE_CON(13), 15, GFLAGS), + + /* PD_BUS */ + GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 1, GFLAGS), + GATE(0, "aclk_initmem", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 0, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 2, GFLAGS), + GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 1, GFLAGS), + + GATE(0, "hclk_rom", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 3, GFLAGS), + GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 7, GFLAGS), + GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 8, GFLAGS), + GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 9, GFLAGS), + GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 10, GFLAGS), + GATE(0, "hclk_tsp", "hclk_cpu", 0, + RK2928_CLKGATE_CON(10), 11, GFLAGS), + GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 11, GFLAGS), + GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 12, GFLAGS), + + GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(8), 4, GFLAGS), + GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(8), 6, GFLAGS), + GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(10), 2, GFLAGS), + + GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 13, GFLAGS), + GATE(0, "pclk_efuse_256", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 14, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 15, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 2, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 4, GFLAGS), + GATE(0, "pclk_stimer", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 5, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 6, GFLAGS), + GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 7, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 8, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 9, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 10, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 11, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 12, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 13, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 14, GFLAGS), + GATE(0, "pclk_tsadc", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 15, GFLAGS), + GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 0, GFLAGS), + GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 1, GFLAGS), + GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 2, GFLAGS), + GATE(0, "pclk_sim", "pclk_cpu", 0, + RK2928_CLKGATE_CON(10), 3, GFLAGS), + + GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 3, GFLAGS), + GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 5, GFLAGS), + GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 7, GFLAGS), + GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 8, GFLAGS), + GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 9, GFLAGS), + + GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 0, GFLAGS), + GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 4, GFLAGS), + GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 2, GFLAGS), + GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 6, GFLAGS), + GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 1, GFLAGS), + GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 5, GFLAGS), + GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 3, GFLAGS), + GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 7, GFLAGS), + + /* PD_MMC */ + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1), + + MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1), + + MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1), +}; + +static const char *const rk3228_critical_clocks[] __initconst = { + "aclk_cpu", + "aclk_peri", + "hclk_peri", + "pclk_peri", +}; + +static void __init rk3228_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + struct clk *clk; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + + /* xin12m is created by an cru-internal divider */ + clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock xin12m: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy4x", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock ddrphy: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre", + "hclk_vpu_src", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre", + "hclk_rkvdec_src", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n", + __func__, PTR_ERR(clk)); + + rockchip_clk_register_plls(rk3228_pll_clks, + ARRAY_SIZE(rk3228_pll_clks), + RK3228_GRF_SOC_STATUS0); + rockchip_clk_register_branches(rk3228_clk_branches, + ARRAY_SIZE(rk3228_clk_branches)); + rockchip_clk_protect_critical(rk3228_critical_clocks, + ARRAY_SIZE(rk3228_critical_clocks)); + + rockchip_clk_register_armclk(ARMCLK, "armclk", + mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + &rk3228_cpuclk_data, rk3228_cpuclk_rates, + ARRAY_SIZE(rk3228_cpuclk_rates)); + + rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(RK3228_GLB_SRST_FST); +} +CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 8d8f942..01bc372 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -33,7 +33,7 @@ struct clk; #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */ +/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */ #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) @@ -50,6 +50,15 @@ struct clk; #define RK3036_EMMC_CON0 0x154 #define RK3036_EMMC_CON1 0x158 +#define RK3228_GLB_SRST_FST 0x1f0 +#define RK3228_GLB_SRST_SND 0x1f4 +#define RK3228_SDMMC_CON0 0x1c0 +#define RK3228_SDMMC_CON1 0x1c4 +#define RK3228_SDIO_CON0 0x1c8 +#define RK3228_SDIO_CON1 0x1cc +#define RK3228_EMMC_CON0 0x1d8 +#define RK3228_EMMC_CON1 0x1dc + #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) #define RK3288_MODE_CON 0x50 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 3/8] rockchip: add clock controller for rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 11 +- 3 files changed, 773 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/rockchip/clk-rk3228.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index d599829..80b9a37 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-y += clk-rk3036.o obj-y += clk-rk3188.o +obj-y += clk-rk3228.o obj-y += clk-rk3288.o obj-y += clk-rk3368.o diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c new file mode 100644 index 0000000..eb3701e --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -0,0 +1,762 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include "clk.h" + +#define RK3228_GRF_SOC_STATUS0 0x480 + +enum rk3228_plls { + apll, dpll, cpll, gpll, +}; + +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +#define RK3228_DIV_CPU_MASK 0x1f +#define RK3228_DIV_CPU_SHIFT 8 + +#define RK3228_DIV_PERI_MASK 0xf +#define RK3228_DIV_PERI_SHIFT 0 +#define RK3228_DIV_ACLK_MASK 0x7 +#define RK3228_DIV_ACLK_SHIFT 4 +#define RK3228_DIV_HCLK_MASK 0x3 +#define RK3228_DIV_HCLK_SHIFT 8 +#define RK3228_DIV_PCLK_MASK 0x7 +#define RK3228_DIV_PCLK_SHIFT 12 + +#define RK3228_CLKSEL1(_core_peri_div) \ + { \ + .reg = RK2928_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ + RK3228_DIV_PERI_SHIFT) \ + } + +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ + { \ + .prate = _prate, \ + .divs = { \ + RK3228_CLKSEL1(_core_peri_div), \ + }, \ + } + +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { + RK3228_CPUCLK_RATE(816000000, 4), + RK3228_CPUCLK_RATE(600000000, 4), + RK3228_CPUCLK_RATE(312000000, 4), +}; + +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { + .core_reg = RK2928_CLKSEL_CON(0), + .div_core_shift = 0, + .div_core_mask = 0x1f, + .mux_core_shift = 6, +}; + +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; + +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; + +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; + +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; + +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; + +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; + +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; + +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; + +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; + +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), + RK2928_MODE_CON, 4, 6, 0, NULL), + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), + RK2928_MODE_CON, 8, 8, 0, NULL), + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { + /* + * Clock-Architecture Diagram 1 + */ + + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), + + /* PD_DDR */ + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, + RK2928_CLKGATE_CON(7), 1, GFLAGS), + + /* PD_CORE */ + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK2928_CLKGATE_CON(4), 1, GFLAGS), + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK2928_CLKGATE_CON(4), 0, GFLAGS), + + /* PD_MISC */ + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 13, 1, MFLAGS), + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 14, 1, MFLAGS), + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 15, 1, MFLAGS), + + /* PD_BUS */ + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, + RK2928_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(6), 1, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, + RK2928_CLKGATE_CON(6), 2, GFLAGS), + GATE(0, "pclk_cpu", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 3, GFLAGS), + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 4, GFLAGS), + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 13, GFLAGS), + + /* PD_VIDEO */ + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(4), 4, GFLAGS), + + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(4), 5, GFLAGS), + + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), + + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), + + /* PD_VIO */ + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), + + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), + + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, + RK2928_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), + + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), + + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, + RK2928_CLKGATE_CON(3), 7, GFLAGS), + + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), + + /* PD_PERI */ + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, + RK2928_CLKGATE_CON(5), 2, GFLAGS), + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, + RK2928_CLKGATE_CON(5), 1, GFLAGS), + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, + RK2928_CLKGATE_CON(5), 0, GFLAGS), + + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, + RK2928_CLKGATE_CON(6), 5, GFLAGS), + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, + RK2928_CLKGATE_CON(6), 6, GFLAGS), + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, + RK2928_CLKGATE_CON(6), 7, GFLAGS), + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, + RK2928_CLKGATE_CON(6), 8, GFLAGS), + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, + RK2928_CLKGATE_CON(6), 9, GFLAGS), + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, + RK2928_CLKGATE_CON(6), 10, GFLAGS), + + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), + + GATE(0, "sclk_hsadc", "ext_hsadc", 0, + RK3288_CLKGATE_CON(10), 12, GFLAGS), + + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), + + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), + + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, + RK2928_CLKGATE_CON(2), 13, GFLAGS), + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), + + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, + RK2928_CLKGATE_CON(2), 14, GFLAGS), + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), + + /* + * Clock-Architecture Diagram 2 + */ + + GATE(0, "gpll_vop", "gpll", 0, + RK2928_CLKGATE_CON(3), 1, GFLAGS), + GATE(0, "cpll_vop", "cpll", 0, + RK2928_CLKGATE_CON(3), 1, GFLAGS), + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), + + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(8), 0, + RK3288_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(0), 5, GFLAGS), + + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(7), 0, + RK3288_CLKGATE_CON(0), 11, GFLAGS), + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, + RK2928_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, + RK2928_CLKGATE_CON(0), 13, GFLAGS), + + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(30), 0, + RK3288_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(0), 9, GFLAGS), + + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(20), 0, + RK3288_CLKGATE_CON(2), 12, GFLAGS), + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), + + GATE(0, "jtag", "ext_jtag", 0, + RK2928_CLKGATE_CON(1), 3, GFLAGS), + + GATE(0, "sclk_otgphy0", "xin24m", 0, + RK2928_CLKGATE_CON(1), 5, GFLAGS), + GATE(0, "sclk_otgphy1", "xin24m", 0, + RK2928_CLKGATE_CON(1), 6, GFLAGS), + + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, + RK2928_CLKGATE_CON(2), 8, GFLAGS), + + GATE(0, "cpll_gpu", "cpll", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "gpll_gpu", "gpll", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "usb480m_gpu", "usb480m", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), + + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), + + /* PD_UART */ + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, + 0, RK2928_CLKSEL_CON(15), 12, 2, + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(17), 0, + RK2928_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(18), 0, + RK2928_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(19), 0, + RK2928_CLKGATE_CON(1), 13, GFLAGS), + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), + + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), + + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 4, GFLAGS), + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 3, GFLAGS), + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 5, GFLAGS), + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 6, GFLAGS), + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), + + /* + * Clock-Architecture Diagram 3 + */ + + /* PD_VOP */ + GATE(0, "aclk_rga", "aclk_rga_pre", 0, + RK2928_CLKGATE_CON(13), 0, GFLAGS), + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, + RK2928_CLKGATE_CON(13), 11, GFLAGS), + GATE(0, "aclk_iep", "aclk_iep_pre", 0, + RK2928_CLKGATE_CON(13), 2, GFLAGS), + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, + RK2928_CLKGATE_CON(13), 9, GFLAGS), + + GATE(0, "aclk_vop", "aclk_vop_pre", 0, + RK2928_CLKGATE_CON(13), 5, GFLAGS), + GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, + RK2928_CLKGATE_CON(13), 12, GFLAGS), + + GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, + RK2928_CLKGATE_CON(14), 10, GFLAGS), + GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, + RK2928_CLKGATE_CON(13), 10, GFLAGS), + + GATE(0, "hclk_rga", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 1, GFLAGS), + GATE(0, "hclk_iep", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 3, GFLAGS), + GATE(0, "hclk_vop", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 6, GFLAGS), + GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 7, GFLAGS), + GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 8, GFLAGS), + GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 13, GFLAGS), + GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 7, GFLAGS), + GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 12, GFLAGS), + GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 6, GFLAGS), + GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 8, GFLAGS), + GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 11, GFLAGS), + + /* PD_PERI */ + GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 0, GFLAGS), + GATE(0, "aclk_gmac", "aclk_peri", 0, + RK2928_CLKGATE_CON(11), 4, GFLAGS), + + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 0, GFLAGS), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 1, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 2, GFLAGS), + GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 3, GFLAGS), + GATE(0, "hclk_host0", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 6, GFLAGS), + GATE(0, "hclk_host0_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 7, GFLAGS), + GATE(0, "hclk_host1", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 8, GFLAGS), + GATE(0, "hclk_host1_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 9, GFLAGS), + GATE(0, "hclk_host2", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 10, GFLAGS), + GATE(0, "hclk_otg", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 12, GFLAGS), + GATE(0, "hclk_otg_pmu", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 13, GFLAGS), + GATE(0, "hclk_host2_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 14, GFLAGS), + GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 1, GFLAGS), + + GATE(0, "pclk_gmac", "pclk_peri", 0, + RK2928_CLKGATE_CON(11), 5, GFLAGS), + GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 2, GFLAGS), + + /* PD_GPU */ + GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, + RK2928_CLKGATE_CON(13), 14, GFLAGS), + GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, + RK2928_CLKGATE_CON(13), 15, GFLAGS), + + /* PD_BUS */ + GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 1, GFLAGS), + GATE(0, "aclk_initmem", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 0, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 2, GFLAGS), + GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 1, GFLAGS), + + GATE(0, "hclk_rom", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 3, GFLAGS), + GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 7, GFLAGS), + GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 8, GFLAGS), + GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 9, GFLAGS), + GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 10, GFLAGS), + GATE(0, "hclk_tsp", "hclk_cpu", 0, + RK2928_CLKGATE_CON(10), 11, GFLAGS), + GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 11, GFLAGS), + GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 12, GFLAGS), + + GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(8), 4, GFLAGS), + GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(8), 6, GFLAGS), + GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(10), 2, GFLAGS), + + GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 13, GFLAGS), + GATE(0, "pclk_efuse_256", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 14, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 15, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 2, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 4, GFLAGS), + GATE(0, "pclk_stimer", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 5, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 6, GFLAGS), + GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 7, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 8, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 9, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 10, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 11, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 12, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 13, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 14, GFLAGS), + GATE(0, "pclk_tsadc", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 15, GFLAGS), + GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 0, GFLAGS), + GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 1, GFLAGS), + GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 2, GFLAGS), + GATE(0, "pclk_sim", "pclk_cpu", 0, + RK2928_CLKGATE_CON(10), 3, GFLAGS), + + GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 3, GFLAGS), + GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 5, GFLAGS), + GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 7, GFLAGS), + GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 8, GFLAGS), + GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 9, GFLAGS), + + GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 0, GFLAGS), + GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 4, GFLAGS), + GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 2, GFLAGS), + GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 6, GFLAGS), + GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 1, GFLAGS), + GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 5, GFLAGS), + GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 3, GFLAGS), + GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 7, GFLAGS), + + /* PD_MMC */ + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1), + + MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1), + + MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1), +}; + +static const char *const rk3228_critical_clocks[] __initconst = { + "aclk_cpu", + "aclk_peri", + "hclk_peri", + "pclk_peri", +}; + +static void __init rk3228_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + struct clk *clk; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + + /* xin12m is created by an cru-internal divider */ + clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock xin12m: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy4x", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock ddrphy: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre", + "hclk_vpu_src", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre", + "hclk_rkvdec_src", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n", + __func__, PTR_ERR(clk)); + + rockchip_clk_register_plls(rk3228_pll_clks, + ARRAY_SIZE(rk3228_pll_clks), + RK3228_GRF_SOC_STATUS0); + rockchip_clk_register_branches(rk3228_clk_branches, + ARRAY_SIZE(rk3228_clk_branches)); + rockchip_clk_protect_critical(rk3228_critical_clocks, + ARRAY_SIZE(rk3228_critical_clocks)); + + rockchip_clk_register_armclk(ARMCLK, "armclk", + mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + &rk3228_cpuclk_data, rk3228_cpuclk_rates, + ARRAY_SIZE(rk3228_cpuclk_rates)); + + rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(RK3228_GLB_SRST_FST); +} +CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 8d8f942..01bc372 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -33,7 +33,7 @@ struct clk; #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */ +/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */ #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) @@ -50,6 +50,15 @@ struct clk; #define RK3036_EMMC_CON0 0x154 #define RK3036_EMMC_CON1 0x158 +#define RK3228_GLB_SRST_FST 0x1f0 +#define RK3228_GLB_SRST_SND 0x1f4 +#define RK3228_SDMMC_CON0 0x1c0 +#define RK3228_SDMMC_CON1 0x1c4 +#define RK3228_SDIO_CON0 0x1c8 +#define RK3228_SDIO_CON1 0x1cc +#define RK3228_EMMC_CON0 0x1d8 +#define RK3228_EMMC_CON1 0x1dc + #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) #define RK3288_MODE_CON 0x50 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 3/8] rockchip: add clock controller for rk3228 @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: Michael Turquette, Jeffy Chen, Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 11 +- 3 files changed, 773 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/rockchip/clk-rk3228.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index d599829..80b9a37 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-y += clk-rk3036.o obj-y += clk-rk3188.o +obj-y += clk-rk3228.o obj-y += clk-rk3288.o obj-y += clk-rk3368.o diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c new file mode 100644 index 0000000..eb3701e --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -0,0 +1,762 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include "clk.h" + +#define RK3228_GRF_SOC_STATUS0 0x480 + +enum rk3228_plls { + apll, dpll, cpll, gpll, +}; + +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +#define RK3228_DIV_CPU_MASK 0x1f +#define RK3228_DIV_CPU_SHIFT 8 + +#define RK3228_DIV_PERI_MASK 0xf +#define RK3228_DIV_PERI_SHIFT 0 +#define RK3228_DIV_ACLK_MASK 0x7 +#define RK3228_DIV_ACLK_SHIFT 4 +#define RK3228_DIV_HCLK_MASK 0x3 +#define RK3228_DIV_HCLK_SHIFT 8 +#define RK3228_DIV_PCLK_MASK 0x7 +#define RK3228_DIV_PCLK_SHIFT 12 + +#define RK3228_CLKSEL1(_core_peri_div) \ + { \ + .reg = RK2928_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ + RK3228_DIV_PERI_SHIFT) \ + } + +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ + { \ + .prate = _prate, \ + .divs = { \ + RK3228_CLKSEL1(_core_peri_div), \ + }, \ + } + +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { + RK3228_CPUCLK_RATE(816000000, 4), + RK3228_CPUCLK_RATE(600000000, 4), + RK3228_CPUCLK_RATE(312000000, 4), +}; + +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { + .core_reg = RK2928_CLKSEL_CON(0), + .div_core_shift = 0, + .div_core_mask = 0x1f, + .mux_core_shift = 6, +}; + +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; + +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; + +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; + +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; + +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; + +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; + +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; + +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; + +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; + +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), + RK2928_MODE_CON, 4, 6, 0, NULL), + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), + RK2928_MODE_CON, 8, 8, 0, NULL), + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { + /* + * Clock-Architecture Diagram 1 + */ + + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), + + /* PD_DDR */ + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, + RK2928_CLKGATE_CON(7), 1, GFLAGS), + + /* PD_CORE */ + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK2928_CLKGATE_CON(4), 1, GFLAGS), + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK2928_CLKGATE_CON(4), 0, GFLAGS), + + /* PD_MISC */ + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 13, 1, MFLAGS), + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 14, 1, MFLAGS), + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, + RK2928_MISC_CON, 15, 1, MFLAGS), + + /* PD_BUS */ + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, + RK2928_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(6), 1, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, + RK2928_CLKGATE_CON(6), 2, GFLAGS), + GATE(0, "pclk_cpu", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 3, GFLAGS), + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 4, GFLAGS), + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, + RK2928_CLKGATE_CON(6), 13, GFLAGS), + + /* PD_VIDEO */ + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(4), 4, GFLAGS), + + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(4), 5, GFLAGS), + + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), + + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), + + /* PD_VIO */ + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), + + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), + + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, + RK2928_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), + + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), + + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, + RK2928_CLKGATE_CON(3), 7, GFLAGS), + + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), + + /* PD_PERI */ + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, + RK2928_CLKGATE_CON(5), 2, GFLAGS), + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, + RK2928_CLKGATE_CON(5), 1, GFLAGS), + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, + RK2928_CLKGATE_CON(5), 0, GFLAGS), + + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, + RK2928_CLKGATE_CON(6), 5, GFLAGS), + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, + RK2928_CLKGATE_CON(6), 6, GFLAGS), + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, + RK2928_CLKGATE_CON(6), 7, GFLAGS), + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, + RK2928_CLKGATE_CON(6), 8, GFLAGS), + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, + RK2928_CLKGATE_CON(6), 9, GFLAGS), + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, + RK2928_CLKGATE_CON(6), 10, GFLAGS), + + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), + + GATE(0, "sclk_hsadc", "ext_hsadc", 0, + RK3288_CLKGATE_CON(10), 12, GFLAGS), + + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), + + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), + + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, + RK2928_CLKGATE_CON(2), 13, GFLAGS), + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), + + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, + RK2928_CLKGATE_CON(2), 14, GFLAGS), + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), + + /* + * Clock-Architecture Diagram 2 + */ + + GATE(0, "gpll_vop", "gpll", 0, + RK2928_CLKGATE_CON(3), 1, GFLAGS), + GATE(0, "cpll_vop", "cpll", 0, + RK2928_CLKGATE_CON(3), 1, GFLAGS), + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), + + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(8), 0, + RK3288_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(0), 5, GFLAGS), + + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(7), 0, + RK3288_CLKGATE_CON(0), 11, GFLAGS), + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, + RK2928_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, + RK2928_CLKGATE_CON(0), 13, GFLAGS), + + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(30), 0, + RK3288_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, + RK2928_CLKGATE_CON(0), 9, GFLAGS), + + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(20), 0, + RK3288_CLKGATE_CON(2), 12, GFLAGS), + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), + + GATE(0, "jtag", "ext_jtag", 0, + RK2928_CLKGATE_CON(1), 3, GFLAGS), + + GATE(0, "sclk_otgphy0", "xin24m", 0, + RK2928_CLKGATE_CON(1), 5, GFLAGS), + GATE(0, "sclk_otgphy1", "xin24m", 0, + RK2928_CLKGATE_CON(1), 6, GFLAGS), + + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, + RK2928_CLKGATE_CON(2), 8, GFLAGS), + + GATE(0, "cpll_gpu", "cpll", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "gpll_gpu", "gpll", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + GATE(0, "usb480m_gpu", "usb480m", 0, + RK2928_CLKGATE_CON(3), 13, GFLAGS), + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), + + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), + + /* PD_UART */ + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, + 0, RK2928_CLKSEL_CON(15), 12, 2, + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(17), 0, + RK2928_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(18), 0, + RK2928_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(19), 0, + RK2928_CLKGATE_CON(1), 13, GFLAGS), + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), + + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), + + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 4, GFLAGS), + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 3, GFLAGS), + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 5, GFLAGS), + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, + RK2928_CLKGATE_CON(5), 6, GFLAGS), + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), + + /* + * Clock-Architecture Diagram 3 + */ + + /* PD_VOP */ + GATE(0, "aclk_rga", "aclk_rga_pre", 0, + RK2928_CLKGATE_CON(13), 0, GFLAGS), + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, + RK2928_CLKGATE_CON(13), 11, GFLAGS), + GATE(0, "aclk_iep", "aclk_iep_pre", 0, + RK2928_CLKGATE_CON(13), 2, GFLAGS), + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, + RK2928_CLKGATE_CON(13), 9, GFLAGS), + + GATE(0, "aclk_vop", "aclk_vop_pre", 0, + RK2928_CLKGATE_CON(13), 5, GFLAGS), + GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, + RK2928_CLKGATE_CON(13), 12, GFLAGS), + + GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, + RK2928_CLKGATE_CON(14), 10, GFLAGS), + GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, + RK2928_CLKGATE_CON(13), 10, GFLAGS), + + GATE(0, "hclk_rga", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 1, GFLAGS), + GATE(0, "hclk_iep", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 3, GFLAGS), + GATE(0, "hclk_vop", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 6, GFLAGS), + GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 7, GFLAGS), + GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 8, GFLAGS), + GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(13), 13, GFLAGS), + GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 7, GFLAGS), + GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 12, GFLAGS), + GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 6, GFLAGS), + GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 8, GFLAGS), + GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, + RK2928_CLKGATE_CON(14), 11, GFLAGS), + + /* PD_PERI */ + GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 0, GFLAGS), + GATE(0, "aclk_gmac", "aclk_peri", 0, + RK2928_CLKGATE_CON(11), 4, GFLAGS), + + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 0, GFLAGS), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 1, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 2, GFLAGS), + GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 3, GFLAGS), + GATE(0, "hclk_host0", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 6, GFLAGS), + GATE(0, "hclk_host0_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 7, GFLAGS), + GATE(0, "hclk_host1", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 8, GFLAGS), + GATE(0, "hclk_host1_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 9, GFLAGS), + GATE(0, "hclk_host2", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 10, GFLAGS), + GATE(0, "hclk_otg", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 12, GFLAGS), + GATE(0, "hclk_otg_pmu", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 13, GFLAGS), + GATE(0, "hclk_host2_arb", "hclk_peri", 0, + RK2928_CLKGATE_CON(11), 14, GFLAGS), + GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 1, GFLAGS), + + GATE(0, "pclk_gmac", "pclk_peri", 0, + RK2928_CLKGATE_CON(11), 5, GFLAGS), + GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(12), 2, GFLAGS), + + /* PD_GPU */ + GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, + RK2928_CLKGATE_CON(13), 14, GFLAGS), + GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, + RK2928_CLKGATE_CON(13), 15, GFLAGS), + + /* PD_BUS */ + GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 1, GFLAGS), + GATE(0, "aclk_initmem", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 0, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, + RK2928_CLKGATE_CON(8), 2, GFLAGS), + GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 1, GFLAGS), + + GATE(0, "hclk_rom", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 3, GFLAGS), + GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 7, GFLAGS), + GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 8, GFLAGS), + GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 9, GFLAGS), + GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 10, GFLAGS), + GATE(0, "hclk_tsp", "hclk_cpu", 0, + RK2928_CLKGATE_CON(10), 11, GFLAGS), + GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 11, GFLAGS), + GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, + RK2928_CLKGATE_CON(8), 12, GFLAGS), + + GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(8), 4, GFLAGS), + GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(8), 6, GFLAGS), + GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, + RK2928_CLKGATE_CON(10), 2, GFLAGS), + + GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 13, GFLAGS), + GATE(0, "pclk_efuse_256", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 14, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(8), 15, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 2, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 4, GFLAGS), + GATE(0, "pclk_stimer", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 5, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 6, GFLAGS), + GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 7, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 8, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 9, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 10, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 11, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 12, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 13, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 14, GFLAGS), + GATE(0, "pclk_tsadc", "pclk_cpu", 0, + RK2928_CLKGATE_CON(9), 15, GFLAGS), + GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 0, GFLAGS), + GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 1, GFLAGS), + GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(10), 2, GFLAGS), + GATE(0, "pclk_sim", "pclk_cpu", 0, + RK2928_CLKGATE_CON(10), 3, GFLAGS), + + GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 3, GFLAGS), + GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 5, GFLAGS), + GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 7, GFLAGS), + GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 8, GFLAGS), + GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, + RK2928_CLKGATE_CON(10), 9, GFLAGS), + + GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 0, GFLAGS), + GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 4, GFLAGS), + GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 2, GFLAGS), + GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 6, GFLAGS), + GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 1, GFLAGS), + GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, + RK2928_CLKGATE_CON(15), 5, GFLAGS), + GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 3, GFLAGS), + GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, + RK2928_CLKGATE_CON(15), 7, GFLAGS), + + /* PD_MMC */ + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1), + + MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1), + + MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1), +}; + +static const char *const rk3228_critical_clocks[] __initconst = { + "aclk_cpu", + "aclk_peri", + "hclk_peri", + "pclk_peri", +}; + +static void __init rk3228_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + struct clk *clk; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + + /* xin12m is created by an cru-internal divider */ + clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock xin12m: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy4x", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock ddrphy: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre", + "hclk_vpu_src", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n", + __func__, PTR_ERR(clk)); + + clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre", + "hclk_rkvdec_src", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n", + __func__, PTR_ERR(clk)); + + rockchip_clk_register_plls(rk3228_pll_clks, + ARRAY_SIZE(rk3228_pll_clks), + RK3228_GRF_SOC_STATUS0); + rockchip_clk_register_branches(rk3228_clk_branches, + ARRAY_SIZE(rk3228_clk_branches)); + rockchip_clk_protect_critical(rk3228_critical_clocks, + ARRAY_SIZE(rk3228_critical_clocks)); + + rockchip_clk_register_armclk(ARMCLK, "armclk", + mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + &rk3228_cpuclk_data, rk3228_cpuclk_rates, + ARRAY_SIZE(rk3228_cpuclk_rates)); + + rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(RK3228_GLB_SRST_FST); +} +CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 8d8f942..01bc372 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -33,7 +33,7 @@ struct clk; #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */ +/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */ #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) @@ -50,6 +50,15 @@ struct clk; #define RK3036_EMMC_CON0 0x154 #define RK3036_EMMC_CON1 0x158 +#define RK3228_GLB_SRST_FST 0x1f0 +#define RK3228_GLB_SRST_SND 0x1f4 +#define RK3228_SDMMC_CON0 0x1c0 +#define RK3228_SDMMC_CON1 0x1c4 +#define RK3228_SDIO_CON0 0x1c8 +#define RK3228_SDIO_CON1 0x1cc +#define RK3228_EMMC_CON0 0x1d8 +#define RK3228_EMMC_CON1 0x1dc + #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) #define RK3288_MODE_CON 0x50 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 3/8] rockchip: add clock controller for rk3228 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-10 0:19 ` Heiko Stuebner -1 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-10 0:19 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, Michael Turquette, Stephen Boyd, linux-clk Hi Jeffy, Am Mittwoch, 9. Dezember 2015, 17:04:08 schrieb Jeffy Chen: > Add the clock tree definition for the new rk3228 SoC. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > --- > > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ > drivers/clk/rockchip/clk.h | 11 +- > 3 files changed, 773 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/rockchip/clk-rk3228.c > > diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile > index d599829..80b9a37 100644 > --- a/drivers/clk/rockchip/Makefile > +++ b/drivers/clk/rockchip/Makefile > @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o > > obj-y += clk-rk3036.o > obj-y += clk-rk3188.o > +obj-y += clk-rk3228.o > obj-y += clk-rk3288.o > obj-y += clk-rk3368.o > diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c > new file mode 100644 > index 0000000..eb3701e > --- /dev/null > +++ b/drivers/clk/rockchip/clk-rk3228.c > @@ -0,0 +1,762 @@ > +/* > + * Copyright (c) 2014 MundoReader S.L. > + * Author: Heiko Stuebner <heiko@sntech.de> > + * > + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. > + * Author: Xing Zheng <zhengxing@rock-chips.com> > + * > + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. > + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/syscore_ops.h> > +#include <dt-bindings/clock/rk3228-cru.h> > +#include "clk.h" > + > +#define RK3228_GRF_SOC_STATUS0 0x480 > + > +enum rk3228_plls { > + apll, dpll, cpll, gpll, > +}; > + > +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { > + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ > + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), > + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), > + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), > + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), > + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), > + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), > + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), > + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), > + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), > + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), > + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), > + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), > + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), > + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), > + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), > + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), > + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), > + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), > + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), > + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), > + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), > + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), > + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), > + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), > + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), > + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), > + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), > + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), > + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), > + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), > + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), > + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), > + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), > + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), > + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), > + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), > + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), > + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), > + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), > + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), > + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), > + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), > + { /* sentinel */ }, > +}; > + > +#define RK3228_DIV_CPU_MASK 0x1f > +#define RK3228_DIV_CPU_SHIFT 8 > + > +#define RK3228_DIV_PERI_MASK 0xf > +#define RK3228_DIV_PERI_SHIFT 0 > +#define RK3228_DIV_ACLK_MASK 0x7 > +#define RK3228_DIV_ACLK_SHIFT 4 > +#define RK3228_DIV_HCLK_MASK 0x3 > +#define RK3228_DIV_HCLK_SHIFT 8 > +#define RK3228_DIV_PCLK_MASK 0x7 > +#define RK3228_DIV_PCLK_SHIFT 12 > + > +#define RK3228_CLKSEL1(_core_peri_div) \ > + { \ > + .reg = RK2928_CLKSEL_CON(1), \ > + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ > + RK3228_DIV_PERI_SHIFT) \ > + } > + > +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ > + { \ > + .prate = _prate, \ > + .divs = { \ > + RK3228_CLKSEL1(_core_peri_div), \ > + }, \ > + } > + > +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { > + RK3228_CPUCLK_RATE(816000000, 4), > + RK3228_CPUCLK_RATE(600000000, 4), > + RK3228_CPUCLK_RATE(312000000, 4), > +}; > + > +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { > + .core_reg = RK2928_CLKSEL_CON(0), > + .div_core_shift = 0, > + .div_core_mask = 0x1f, > + .mux_core_shift = 6, > +}; > + > +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; > + > +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; > +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; > +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; > +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; > +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; > +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; > + > +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; > +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; > +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; > +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; > +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; isn't that the same as your mux_pll_src_3plls_p? > +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; > +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; > + > +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; > + > +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; > +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; > + > +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; > +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; > +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; > +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; > +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; > + > +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; > + > +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; > +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; > +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; > + > +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; > +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; > +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; > + > +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { > + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), > + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), > + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), > + RK2928_MODE_CON, 4, 6, 0, NULL), > + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), > + RK2928_MODE_CON, 8, 8, 0, NULL), > + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), > + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), > +}; > + > +#define MFLAGS CLK_MUX_HIWORD_MASK > +#define DFLAGS CLK_DIVIDER_HIWORD_MASK > +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) > + > +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { > + /* > + * Clock-Architecture Diagram 1 > + */ > + > + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), > + > + /* PD_DDR */ > + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 2, GFLAGS), > + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 2, GFLAGS), > + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 2, GFLAGS), > + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, > + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > + RK2928_CLKGATE_CON(7), 1, GFLAGS), please keep the formatting the same as in the other clock drivers, as it makes reading this later easier when everything is always in the same place: + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, + RK2928_CLKGATE_CON(7), 1, GFLAGS), We're "flexible" with the 80col limit for this ;-) > + > + /* PD_CORE */ > + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 6, GFLAGS), > + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 6, GFLAGS), > + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 6, GFLAGS), > + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, > + RK2928_CLKGATE_CON(4), 1, GFLAGS), > + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, > + RK2928_CLKGATE_CON(4), 0, GFLAGS), > + > + /* PD_MISC */ > + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, > + RK2928_MISC_CON, 13, 1, MFLAGS), > + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, > + RK2928_MISC_CON, 14, 1, MFLAGS), > + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, > + RK2928_MISC_CON, 15, 1, MFLAGS), > + > + /* PD_BUS */ > + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 1, GFLAGS), > + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), > + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), > + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, > + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), > + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, > + RK2928_CLKGATE_CON(6), 0, GFLAGS), > + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, > + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, > + RK2928_CLKGATE_CON(6), 1, GFLAGS), > + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, > + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, > + RK2928_CLKGATE_CON(6), 2, GFLAGS), > + GATE(0, "pclk_cpu", "pclk_bus_src", 0, > + RK2928_CLKGATE_CON(6), 3, GFLAGS), > + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, > + RK2928_CLKGATE_CON(6), 4, GFLAGS), > + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, > + RK2928_CLKGATE_CON(6), 13, GFLAGS), > + > + /* PD_VIDEO */ > + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), > + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, > + RK2928_CLKGATE_CON(4), 4, GFLAGS), > + > + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), > + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, > + RK2928_CLKGATE_CON(4), 5, GFLAGS), > + > + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), > + > + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), > + > + /* PD_VIO */ > + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), > + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, > + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), > + > + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), > + > + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), > + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, > + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, > + RK2928_CLKGATE_CON(1), 2, GFLAGS), > + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, > + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), > + > + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), > + > + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, > + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, > + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), > + > + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, > + RK2928_CLKGATE_CON(3), 7, GFLAGS), > + > + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, > + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, > + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), > + > + /* PD_PERI */ > + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(2), 0, GFLAGS), > + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(2), 0, GFLAGS), > + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(2), 0, GFLAGS), > + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, > + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), > + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, > + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, > + RK2928_CLKGATE_CON(5), 2, GFLAGS), > + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, > + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, > + RK2928_CLKGATE_CON(5), 1, GFLAGS), > + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, > + RK2928_CLKGATE_CON(5), 0, GFLAGS), > + > + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 5, GFLAGS), > + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 6, GFLAGS), > + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 7, GFLAGS), > + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 8, GFLAGS), > + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 9, GFLAGS), > + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 10, GFLAGS), > + > + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), > + > + GATE(0, "sclk_hsadc", "ext_hsadc", 0, > + RK3288_CLKGATE_CON(10), 12, GFLAGS), > + > + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, > + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, > + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), > + > + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, > + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, > + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), > + > + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, > + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, > + RK2928_CLKGATE_CON(2), 13, GFLAGS), > + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, > + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), > + > + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, > + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, > + RK2928_CLKGATE_CON(2), 14, GFLAGS), > + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, > + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), > + > + /* > + * Clock-Architecture Diagram 2 > + */ > + > + GATE(0, "gpll_vop", "gpll", 0, > + RK2928_CLKGATE_CON(3), 1, GFLAGS), > + GATE(0, "cpll_vop", "cpll", 0, > + RK2928_CLKGATE_CON(3), 1, GFLAGS), > + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, > + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), > + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, > + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), > + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, > + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), > + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, > + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), > + > + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), > + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(8), 0, > + RK3288_CLKGATE_CON(0), 4, GFLAGS), > + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, > + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, > + RK2928_CLKGATE_CON(0), 5, GFLAGS), > + > + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), > + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(7), 0, > + RK3288_CLKGATE_CON(0), 11, GFLAGS), > + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, > + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), > + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, > + RK2928_CLKGATE_CON(0), 14, GFLAGS), > + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, > + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, > + RK2928_CLKGATE_CON(0), 13, GFLAGS), > + > + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), > + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(30), 0, > + RK3288_CLKGATE_CON(0), 8, GFLAGS), > + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, > + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, > + RK2928_CLKGATE_CON(0), 9, GFLAGS), > + > + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), > + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(20), 0, > + RK3288_CLKGATE_CON(2), 12, GFLAGS), > + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, > + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), > + > + GATE(0, "jtag", "ext_jtag", 0, > + RK2928_CLKGATE_CON(1), 3, GFLAGS), > + > + GATE(0, "sclk_otgphy0", "xin24m", 0, > + RK2928_CLKGATE_CON(1), 5, GFLAGS), > + GATE(0, "sclk_otgphy1", "xin24m", 0, > + RK2928_CLKGATE_CON(1), 6, GFLAGS), > + > + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, > + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, > + RK2928_CLKGATE_CON(2), 8, GFLAGS), > + > + GATE(0, "cpll_gpu", "cpll", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + GATE(0, "gpll_gpu", "gpll", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + GATE(0, "usb480m_gpu", "usb480m", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, > + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), > + > + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), > + > + /* PD_UART */ > + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, > + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), > + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, > + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), > + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, > + 0, RK2928_CLKSEL_CON(15), 12, 2, > + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), > + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(17), 0, > + RK2928_CLKGATE_CON(1), 9, GFLAGS), > + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(18), 0, > + RK2928_CLKGATE_CON(1), 11, GFLAGS), > + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(19), 0, > + RK2928_CLKGATE_CON(1), 13, GFLAGS), > + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), > + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), > + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), > + > + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), > + > + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), > + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, > + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), > + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, > + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), > + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 4, GFLAGS), > + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 3, GFLAGS), > + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 5, GFLAGS), > + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 6, GFLAGS), > + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, > + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, > + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), > + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), > + > + /* > + * Clock-Architecture Diagram 3 > + */ > + > + /* PD_VOP */ > + GATE(0, "aclk_rga", "aclk_rga_pre", 0, > + RK2928_CLKGATE_CON(13), 0, GFLAGS), the simple gate clocks from this diagram 3 can be on one line, as they really are only a big number of simple gates. Again similar to how the other socs do it. > + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, > + RK2928_CLKGATE_CON(13), 11, GFLAGS), > + GATE(0, "aclk_iep", "aclk_iep_pre", 0, > + RK2928_CLKGATE_CON(13), 2, GFLAGS), > + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, > + RK2928_CLKGATE_CON(13), 9, GFLAGS), Otherwise this looks great Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 3/8] rockchip: add clock controller for rk3228 @ 2015-12-10 0:19 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-10 0:19 UTC (permalink / raw) To: linux-arm-kernel Hi Jeffy, Am Mittwoch, 9. Dezember 2015, 17:04:08 schrieb Jeffy Chen: > Add the clock tree definition for the new rk3228 SoC. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > --- > > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ > drivers/clk/rockchip/clk.h | 11 +- > 3 files changed, 773 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/rockchip/clk-rk3228.c > > diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile > index d599829..80b9a37 100644 > --- a/drivers/clk/rockchip/Makefile > +++ b/drivers/clk/rockchip/Makefile > @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o > > obj-y += clk-rk3036.o > obj-y += clk-rk3188.o > +obj-y += clk-rk3228.o > obj-y += clk-rk3288.o > obj-y += clk-rk3368.o > diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c > new file mode 100644 > index 0000000..eb3701e > --- /dev/null > +++ b/drivers/clk/rockchip/clk-rk3228.c > @@ -0,0 +1,762 @@ > +/* > + * Copyright (c) 2014 MundoReader S.L. > + * Author: Heiko Stuebner <heiko@sntech.de> > + * > + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. > + * Author: Xing Zheng <zhengxing@rock-chips.com> > + * > + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. > + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/syscore_ops.h> > +#include <dt-bindings/clock/rk3228-cru.h> > +#include "clk.h" > + > +#define RK3228_GRF_SOC_STATUS0 0x480 > + > +enum rk3228_plls { > + apll, dpll, cpll, gpll, > +}; > + > +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { > + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ > + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), > + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), > + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), > + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), > + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), > + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), > + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), > + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), > + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), > + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), > + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), > + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), > + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), > + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), > + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), > + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), > + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), > + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), > + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), > + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), > + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), > + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), > + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), > + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), > + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), > + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), > + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), > + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), > + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), > + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), > + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), > + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), > + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), > + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), > + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), > + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), > + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), > + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), > + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), > + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), > + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), > + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), > + { /* sentinel */ }, > +}; > + > +#define RK3228_DIV_CPU_MASK 0x1f > +#define RK3228_DIV_CPU_SHIFT 8 > + > +#define RK3228_DIV_PERI_MASK 0xf > +#define RK3228_DIV_PERI_SHIFT 0 > +#define RK3228_DIV_ACLK_MASK 0x7 > +#define RK3228_DIV_ACLK_SHIFT 4 > +#define RK3228_DIV_HCLK_MASK 0x3 > +#define RK3228_DIV_HCLK_SHIFT 8 > +#define RK3228_DIV_PCLK_MASK 0x7 > +#define RK3228_DIV_PCLK_SHIFT 12 > + > +#define RK3228_CLKSEL1(_core_peri_div) \ > + { \ > + .reg = RK2928_CLKSEL_CON(1), \ > + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ > + RK3228_DIV_PERI_SHIFT) \ > + } > + > +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ > + { \ > + .prate = _prate, \ > + .divs = { \ > + RK3228_CLKSEL1(_core_peri_div), \ > + }, \ > + } > + > +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { > + RK3228_CPUCLK_RATE(816000000, 4), > + RK3228_CPUCLK_RATE(600000000, 4), > + RK3228_CPUCLK_RATE(312000000, 4), > +}; > + > +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { > + .core_reg = RK2928_CLKSEL_CON(0), > + .div_core_shift = 0, > + .div_core_mask = 0x1f, > + .mux_core_shift = 6, > +}; > + > +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; > + > +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; > +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; > +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; > +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; > +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; > +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; > + > +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; > +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; > +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; > +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; > +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; isn't that the same as your mux_pll_src_3plls_p? > +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; > +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; > + > +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; > + > +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; > +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; > + > +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; > +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; > +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; > +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; > +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; > + > +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; > + > +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; > +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; > +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; > + > +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; > +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; > +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; > + > +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { > + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), > + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), > + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), > + RK2928_MODE_CON, 4, 6, 0, NULL), > + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), > + RK2928_MODE_CON, 8, 8, 0, NULL), > + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), > + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), > +}; > + > +#define MFLAGS CLK_MUX_HIWORD_MASK > +#define DFLAGS CLK_DIVIDER_HIWORD_MASK > +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) > + > +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { > + /* > + * Clock-Architecture Diagram 1 > + */ > + > + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), > + > + /* PD_DDR */ > + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 2, GFLAGS), > + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 2, GFLAGS), > + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 2, GFLAGS), > + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, > + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > + RK2928_CLKGATE_CON(7), 1, GFLAGS), please keep the formatting the same as in the other clock drivers, as it makes reading this later easier when everything is always in the same place: + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, + RK2928_CLKGATE_CON(7), 1, GFLAGS), We're "flexible" with the 80col limit for this ;-) > + > + /* PD_CORE */ > + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 6, GFLAGS), > + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 6, GFLAGS), > + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 6, GFLAGS), > + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, > + RK2928_CLKGATE_CON(4), 1, GFLAGS), > + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, > + RK2928_CLKGATE_CON(4), 0, GFLAGS), > + > + /* PD_MISC */ > + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, > + RK2928_MISC_CON, 13, 1, MFLAGS), > + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, > + RK2928_MISC_CON, 14, 1, MFLAGS), > + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, > + RK2928_MISC_CON, 15, 1, MFLAGS), > + > + /* PD_BUS */ > + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(0), 1, GFLAGS), > + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), > + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), > + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, > + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), > + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, > + RK2928_CLKGATE_CON(6), 0, GFLAGS), > + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, > + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, > + RK2928_CLKGATE_CON(6), 1, GFLAGS), > + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, > + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, > + RK2928_CLKGATE_CON(6), 2, GFLAGS), > + GATE(0, "pclk_cpu", "pclk_bus_src", 0, > + RK2928_CLKGATE_CON(6), 3, GFLAGS), > + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, > + RK2928_CLKGATE_CON(6), 4, GFLAGS), > + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, > + RK2928_CLKGATE_CON(6), 13, GFLAGS), > + > + /* PD_VIDEO */ > + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), > + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, > + RK2928_CLKGATE_CON(4), 4, GFLAGS), > + > + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), > + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, > + RK2928_CLKGATE_CON(4), 5, GFLAGS), > + > + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), > + > + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), > + > + /* PD_VIO */ > + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), > + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, > + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), > + > + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), > + > + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), > + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, > + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, > + RK2928_CLKGATE_CON(1), 2, GFLAGS), > + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, > + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), > + > + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, > + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), > + > + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, > + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, > + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), > + > + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, > + RK2928_CLKGATE_CON(3), 7, GFLAGS), > + > + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, > + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, > + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), > + > + /* PD_PERI */ > + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(2), 0, GFLAGS), > + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(2), 0, GFLAGS), > + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, > + RK2928_CLKGATE_CON(2), 0, GFLAGS), > + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, > + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), > + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, > + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, > + RK2928_CLKGATE_CON(5), 2, GFLAGS), > + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, > + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, > + RK2928_CLKGATE_CON(5), 1, GFLAGS), > + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, > + RK2928_CLKGATE_CON(5), 0, GFLAGS), > + > + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 5, GFLAGS), > + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 6, GFLAGS), > + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 7, GFLAGS), > + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 8, GFLAGS), > + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 9, GFLAGS), > + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, > + RK2928_CLKGATE_CON(6), 10, GFLAGS), > + > + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), > + > + GATE(0, "sclk_hsadc", "ext_hsadc", 0, > + RK3288_CLKGATE_CON(10), 12, GFLAGS), > + > + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, > + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, > + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), > + > + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, > + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, > + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), > + > + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, > + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, > + RK2928_CLKGATE_CON(2), 13, GFLAGS), > + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, > + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), > + > + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, > + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, > + RK2928_CLKGATE_CON(2), 14, GFLAGS), > + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, > + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), > + > + /* > + * Clock-Architecture Diagram 2 > + */ > + > + GATE(0, "gpll_vop", "gpll", 0, > + RK2928_CLKGATE_CON(3), 1, GFLAGS), > + GATE(0, "cpll_vop", "cpll", 0, > + RK2928_CLKGATE_CON(3), 1, GFLAGS), > + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, > + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), > + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, > + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), > + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, > + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), > + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, > + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), > + > + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), > + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(8), 0, > + RK3288_CLKGATE_CON(0), 4, GFLAGS), > + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, > + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, > + RK2928_CLKGATE_CON(0), 5, GFLAGS), > + > + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), > + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(7), 0, > + RK3288_CLKGATE_CON(0), 11, GFLAGS), > + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, > + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), > + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, > + RK2928_CLKGATE_CON(0), 14, GFLAGS), > + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, > + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, > + RK2928_CLKGATE_CON(0), 13, GFLAGS), > + > + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), > + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(30), 0, > + RK3288_CLKGATE_CON(0), 8, GFLAGS), > + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, > + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, > + RK2928_CLKGATE_CON(0), 9, GFLAGS), > + > + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), > + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, > + RK3288_CLKSEL_CON(20), 0, > + RK3288_CLKGATE_CON(2), 12, GFLAGS), > + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, > + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), > + > + GATE(0, "jtag", "ext_jtag", 0, > + RK2928_CLKGATE_CON(1), 3, GFLAGS), > + > + GATE(0, "sclk_otgphy0", "xin24m", 0, > + RK2928_CLKGATE_CON(1), 5, GFLAGS), > + GATE(0, "sclk_otgphy1", "xin24m", 0, > + RK2928_CLKGATE_CON(1), 6, GFLAGS), > + > + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, > + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, > + RK2928_CLKGATE_CON(2), 8, GFLAGS), > + > + GATE(0, "cpll_gpu", "cpll", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + GATE(0, "gpll_gpu", "gpll", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + GATE(0, "usb480m_gpu", "usb480m", 0, > + RK2928_CLKGATE_CON(3), 13, GFLAGS), > + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, > + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), > + > + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), > + > + /* PD_UART */ > + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, > + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), > + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, > + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, > + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), > + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, > + 0, RK2928_CLKSEL_CON(15), 12, 2, > + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), > + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(17), 0, > + RK2928_CLKGATE_CON(1), 9, GFLAGS), > + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(18), 0, > + RK2928_CLKGATE_CON(1), 11, GFLAGS), > + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(19), 0, > + RK2928_CLKGATE_CON(1), 13, GFLAGS), > + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), > + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), > + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, > + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), > + > + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), > + > + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, > + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), > + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, > + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), > + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, > + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), > + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 4, GFLAGS), > + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 3, GFLAGS), > + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 5, GFLAGS), > + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, > + RK2928_CLKGATE_CON(5), 6, GFLAGS), > + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, > + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, > + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), > + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, > + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, > + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), > + > + /* > + * Clock-Architecture Diagram 3 > + */ > + > + /* PD_VOP */ > + GATE(0, "aclk_rga", "aclk_rga_pre", 0, > + RK2928_CLKGATE_CON(13), 0, GFLAGS), the simple gate clocks from this diagram 3 can be on one line, as they really are only a big number of simple gates. Again similar to how the other socs do it. > + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, > + RK2928_CLKGATE_CON(13), 11, GFLAGS), > + GATE(0, "aclk_iep", "aclk_iep_pre", 0, > + RK2928_CLKGATE_CON(13), 2, GFLAGS), > + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, > + RK2928_CLKGATE_CON(13), 9, GFLAGS), Otherwise this looks great Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 3/8] rockchip: add clock controller for rk3228 2015-12-10 0:19 ` Heiko Stuebner @ 2015-12-11 1:46 ` Jeffy Chen -1 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-11 1:46 UTC (permalink / raw) To: Heiko Stuebner Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, Michael Turquette, Stephen Boyd, linux-clk Hi Heiko, Thank you for your comments :) On 2015-12-10 8:19, Heiko Stuebner wrote: > Hi Jeffy, > > Am Mittwoch, 9. Dezember 2015, 17:04:08 schrieb Jeffy Chen: >> Add the clock tree definition for the new rk3228 SoC. >> >> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> --- >> >> drivers/clk/rockchip/Makefile | 1 + >> drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ >> drivers/clk/rockchip/clk.h | 11 +- >> 3 files changed, 773 insertions(+), 1 deletion(-) >> create mode 100644 drivers/clk/rockchip/clk-rk3228.c >> >> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile >> index d599829..80b9a37 100644 >> --- a/drivers/clk/rockchip/Makefile >> +++ b/drivers/clk/rockchip/Makefile >> @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o >> >> obj-y += clk-rk3036.o >> obj-y += clk-rk3188.o >> +obj-y += clk-rk3228.o >> obj-y += clk-rk3288.o >> obj-y += clk-rk3368.o >> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c >> new file mode 100644 >> index 0000000..eb3701e >> --- /dev/null >> +++ b/drivers/clk/rockchip/clk-rk3228.c >> @@ -0,0 +1,762 @@ >> +/* >> + * Copyright (c) 2014 MundoReader S.L. >> + * Author: Heiko Stuebner <heiko@sntech.de> >> + * >> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. >> + * Author: Xing Zheng <zhengxing@rock-chips.com> >> + * >> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. >> + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/syscore_ops.h> >> +#include <dt-bindings/clock/rk3228-cru.h> >> +#include "clk.h" >> + >> +#define RK3228_GRF_SOC_STATUS0 0x480 >> + >> +enum rk3228_plls { >> + apll, dpll, cpll, gpll, >> +}; >> + >> +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { >> + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ >> + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), >> + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), >> + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), >> + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), >> + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), >> + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), >> + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), >> + { /* sentinel */ }, >> +}; >> + >> +#define RK3228_DIV_CPU_MASK 0x1f >> +#define RK3228_DIV_CPU_SHIFT 8 >> + >> +#define RK3228_DIV_PERI_MASK 0xf >> +#define RK3228_DIV_PERI_SHIFT 0 >> +#define RK3228_DIV_ACLK_MASK 0x7 >> +#define RK3228_DIV_ACLK_SHIFT 4 >> +#define RK3228_DIV_HCLK_MASK 0x3 >> +#define RK3228_DIV_HCLK_SHIFT 8 >> +#define RK3228_DIV_PCLK_MASK 0x7 >> +#define RK3228_DIV_PCLK_SHIFT 12 >> + >> +#define RK3228_CLKSEL1(_core_peri_div) \ >> + { \ >> + .reg = RK2928_CLKSEL_CON(1), \ >> + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ >> + RK3228_DIV_PERI_SHIFT) \ >> + } >> + >> +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ >> + { \ >> + .prate = _prate, \ >> + .divs = { \ >> + RK3228_CLKSEL1(_core_peri_div), \ >> + }, \ >> + } >> + >> +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { >> + RK3228_CPUCLK_RATE(816000000, 4), >> + RK3228_CPUCLK_RATE(600000000, 4), >> + RK3228_CPUCLK_RATE(312000000, 4), >> +}; >> + >> +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { >> + .core_reg = RK2928_CLKSEL_CON(0), >> + .div_core_shift = 0, >> + .div_core_mask = 0x1f, >> + .mux_core_shift = 6, >> +}; >> + >> +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; >> + >> +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; >> +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; >> +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; >> +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; >> +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; >> +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; >> + >> +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; >> +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; >> +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; >> +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; >> +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; > isn't that the same as your mux_pll_src_3plls_p? sorry, that is a mistake...i'll fix it in version 2. > > >> +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; >> +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; >> + >> +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; >> + >> +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; >> +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; >> + >> +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; >> +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; >> +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; >> +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; >> +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; >> + >> +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; >> + >> +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; >> +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; >> +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; >> + >> +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; >> +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; >> +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; >> + >> +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { >> + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), >> + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), >> + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), >> + RK2928_MODE_CON, 4, 6, 0, NULL), >> + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), >> + RK2928_MODE_CON, 8, 8, 0, NULL), >> + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), >> + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), >> +}; >> + >> +#define MFLAGS CLK_MUX_HIWORD_MASK >> +#define DFLAGS CLK_DIVIDER_HIWORD_MASK >> +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) >> + >> +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { >> + /* >> + * Clock-Architecture Diagram 1 >> + */ >> + >> + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), >> + >> + /* PD_DDR */ >> + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 2, GFLAGS), >> + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 2, GFLAGS), >> + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 2, GFLAGS), >> + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, >> + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, >> + RK2928_CLKGATE_CON(7), 1, GFLAGS), > please keep the formatting the same as in the other clock drivers, as it > makes reading this later easier when everything is always in the same place: > > + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > + RK2928_CLKGATE_CON(7), 1, GFLAGS), > > We're "flexible" with the 80col limit for this ;-) > done. >> + >> + /* PD_CORE */ >> + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 6, GFLAGS), >> + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 6, GFLAGS), >> + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 6, GFLAGS), >> + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, >> + RK2928_CLKGATE_CON(4), 1, GFLAGS), >> + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, >> + RK2928_CLKGATE_CON(4), 0, GFLAGS), >> + >> + /* PD_MISC */ >> + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, >> + RK2928_MISC_CON, 13, 1, MFLAGS), >> + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, >> + RK2928_MISC_CON, 14, 1, MFLAGS), >> + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, >> + RK2928_MISC_CON, 15, 1, MFLAGS), >> + >> + /* PD_BUS */ >> + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 1, GFLAGS), >> + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), >> + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), >> + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, >> + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), >> + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, >> + RK2928_CLKGATE_CON(6), 0, GFLAGS), >> + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, >> + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, >> + RK2928_CLKGATE_CON(6), 1, GFLAGS), >> + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, >> + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, >> + RK2928_CLKGATE_CON(6), 2, GFLAGS), >> + GATE(0, "pclk_cpu", "pclk_bus_src", 0, >> + RK2928_CLKGATE_CON(6), 3, GFLAGS), >> + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, >> + RK2928_CLKGATE_CON(6), 4, GFLAGS), >> + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, >> + RK2928_CLKGATE_CON(6), 13, GFLAGS), >> + >> + /* PD_VIDEO */ >> + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), >> + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, >> + RK2928_CLKGATE_CON(4), 4, GFLAGS), >> + >> + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), >> + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, >> + RK2928_CLKGATE_CON(4), 5, GFLAGS), >> + >> + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), >> + >> + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), >> + >> + /* PD_VIO */ >> + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), >> + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, >> + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), >> + >> + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), >> + >> + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), >> + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, >> + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, >> + RK2928_CLKGATE_CON(1), 2, GFLAGS), >> + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, >> + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), >> + >> + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), >> + >> + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, >> + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, >> + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), >> + >> + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, >> + RK2928_CLKGATE_CON(3), 7, GFLAGS), >> + >> + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, >> + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, >> + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), >> + >> + /* PD_PERI */ >> + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(2), 0, GFLAGS), >> + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(2), 0, GFLAGS), >> + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(2), 0, GFLAGS), >> + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, >> + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), >> + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, >> + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, >> + RK2928_CLKGATE_CON(5), 2, GFLAGS), >> + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, >> + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, >> + RK2928_CLKGATE_CON(5), 1, GFLAGS), >> + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, >> + RK2928_CLKGATE_CON(5), 0, GFLAGS), >> + >> + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 5, GFLAGS), >> + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 6, GFLAGS), >> + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 7, GFLAGS), >> + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 8, GFLAGS), >> + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 9, GFLAGS), >> + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 10, GFLAGS), >> + >> + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), >> + >> + GATE(0, "sclk_hsadc", "ext_hsadc", 0, >> + RK3288_CLKGATE_CON(10), 12, GFLAGS), >> + >> + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, >> + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, >> + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), >> + >> + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, >> + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, >> + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), >> + >> + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, >> + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, >> + RK2928_CLKGATE_CON(2), 13, GFLAGS), >> + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, >> + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), >> + >> + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, >> + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, >> + RK2928_CLKGATE_CON(2), 14, GFLAGS), >> + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, >> + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), >> + >> + /* >> + * Clock-Architecture Diagram 2 >> + */ >> + >> + GATE(0, "gpll_vop", "gpll", 0, >> + RK2928_CLKGATE_CON(3), 1, GFLAGS), >> + GATE(0, "cpll_vop", "cpll", 0, >> + RK2928_CLKGATE_CON(3), 1, GFLAGS), >> + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, >> + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), >> + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, >> + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), >> + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, >> + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), >> + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, >> + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), >> + >> + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), >> + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(8), 0, >> + RK3288_CLKGATE_CON(0), 4, GFLAGS), >> + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, >> + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, >> + RK2928_CLKGATE_CON(0), 5, GFLAGS), >> + >> + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), >> + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(7), 0, >> + RK3288_CLKGATE_CON(0), 11, GFLAGS), >> + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, >> + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), >> + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, >> + RK2928_CLKGATE_CON(0), 14, GFLAGS), >> + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, >> + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, >> + RK2928_CLKGATE_CON(0), 13, GFLAGS), >> + >> + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), >> + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(30), 0, >> + RK3288_CLKGATE_CON(0), 8, GFLAGS), >> + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, >> + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, >> + RK2928_CLKGATE_CON(0), 9, GFLAGS), >> + >> + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), >> + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(20), 0, >> + RK3288_CLKGATE_CON(2), 12, GFLAGS), >> + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, >> + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), >> + >> + GATE(0, "jtag", "ext_jtag", 0, >> + RK2928_CLKGATE_CON(1), 3, GFLAGS), >> + >> + GATE(0, "sclk_otgphy0", "xin24m", 0, >> + RK2928_CLKGATE_CON(1), 5, GFLAGS), >> + GATE(0, "sclk_otgphy1", "xin24m", 0, >> + RK2928_CLKGATE_CON(1), 6, GFLAGS), >> + >> + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, >> + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, >> + RK2928_CLKGATE_CON(2), 8, GFLAGS), >> + >> + GATE(0, "cpll_gpu", "cpll", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + GATE(0, "gpll_gpu", "gpll", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + GATE(0, "usb480m_gpu", "usb480m", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, >> + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), >> + >> + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), >> + >> + /* PD_UART */ >> + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, >> + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), >> + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, >> + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), >> + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, >> + 0, RK2928_CLKSEL_CON(15), 12, 2, >> + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), >> + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(17), 0, >> + RK2928_CLKGATE_CON(1), 9, GFLAGS), >> + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(18), 0, >> + RK2928_CLKGATE_CON(1), 11, GFLAGS), >> + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(19), 0, >> + RK2928_CLKGATE_CON(1), 13, GFLAGS), >> + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), >> + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), >> + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), >> + >> + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), >> + >> + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), >> + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, >> + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), >> + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, >> + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), >> + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 4, GFLAGS), >> + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 3, GFLAGS), >> + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 5, GFLAGS), >> + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 6, GFLAGS), >> + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, >> + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, >> + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), >> + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), >> + >> + /* >> + * Clock-Architecture Diagram 3 >> + */ >> + >> + /* PD_VOP */ >> + GATE(0, "aclk_rga", "aclk_rga_pre", 0, >> + RK2928_CLKGATE_CON(13), 0, GFLAGS), > the simple gate clocks from this diagram 3 can be on one line, as they > really are only a big number of simple gates. > > Again similar to how the other socs do it. done. > >> + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, >> + RK2928_CLKGATE_CON(13), 11, GFLAGS), >> + GATE(0, "aclk_iep", "aclk_iep_pre", 0, >> + RK2928_CLKGATE_CON(13), 2, GFLAGS), >> + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, >> + RK2928_CLKGATE_CON(13), 9, GFLAGS), > Otherwise this looks great > > Heiko > ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 3/8] rockchip: add clock controller for rk3228 @ 2015-12-11 1:46 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-11 1:46 UTC (permalink / raw) To: linux-arm-kernel Hi Heiko, Thank you for your comments :) On 2015-12-10 8:19, Heiko Stuebner wrote: > Hi Jeffy, > > Am Mittwoch, 9. Dezember 2015, 17:04:08 schrieb Jeffy Chen: >> Add the clock tree definition for the new rk3228 SoC. >> >> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> --- >> >> drivers/clk/rockchip/Makefile | 1 + >> drivers/clk/rockchip/clk-rk3228.c | 762 ++++++++++++++++++++++++++++++++++++++ >> drivers/clk/rockchip/clk.h | 11 +- >> 3 files changed, 773 insertions(+), 1 deletion(-) >> create mode 100644 drivers/clk/rockchip/clk-rk3228.c >> >> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile >> index d599829..80b9a37 100644 >> --- a/drivers/clk/rockchip/Makefile >> +++ b/drivers/clk/rockchip/Makefile >> @@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o >> >> obj-y += clk-rk3036.o >> obj-y += clk-rk3188.o >> +obj-y += clk-rk3228.o >> obj-y += clk-rk3288.o >> obj-y += clk-rk3368.o >> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c >> new file mode 100644 >> index 0000000..eb3701e >> --- /dev/null >> +++ b/drivers/clk/rockchip/clk-rk3228.c >> @@ -0,0 +1,762 @@ >> +/* >> + * Copyright (c) 2014 MundoReader S.L. >> + * Author: Heiko Stuebner <heiko@sntech.de> >> + * >> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. >> + * Author: Xing Zheng <zhengxing@rock-chips.com> >> + * >> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. >> + * Author: Jeffy Chen <jeffy.chen@rock-chips.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/syscore_ops.h> >> +#include <dt-bindings/clock/rk3228-cru.h> >> +#include "clk.h" >> + >> +#define RK3228_GRF_SOC_STATUS0 0x480 >> + >> +enum rk3228_plls { >> + apll, dpll, cpll, gpll, >> +}; >> + >> +static struct rockchip_pll_rate_table rk3228_pll_rates[] = { >> + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ >> + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), >> + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), >> + RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), >> + RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), >> + RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), >> + RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), >> + RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), >> + RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), >> + RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), >> + { /* sentinel */ }, >> +}; >> + >> +#define RK3228_DIV_CPU_MASK 0x1f >> +#define RK3228_DIV_CPU_SHIFT 8 >> + >> +#define RK3228_DIV_PERI_MASK 0xf >> +#define RK3228_DIV_PERI_SHIFT 0 >> +#define RK3228_DIV_ACLK_MASK 0x7 >> +#define RK3228_DIV_ACLK_SHIFT 4 >> +#define RK3228_DIV_HCLK_MASK 0x3 >> +#define RK3228_DIV_HCLK_SHIFT 8 >> +#define RK3228_DIV_PCLK_MASK 0x7 >> +#define RK3228_DIV_PCLK_SHIFT 12 >> + >> +#define RK3228_CLKSEL1(_core_peri_div) \ >> + { \ >> + .reg = RK2928_CLKSEL_CON(1), \ >> + .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ >> + RK3228_DIV_PERI_SHIFT) \ >> + } >> + >> +#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ >> + { \ >> + .prate = _prate, \ >> + .divs = { \ >> + RK3228_CLKSEL1(_core_peri_div), \ >> + }, \ >> + } >> + >> +static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { >> + RK3228_CPUCLK_RATE(816000000, 4), >> + RK3228_CPUCLK_RATE(600000000, 4), >> + RK3228_CPUCLK_RATE(312000000, 4), >> +}; >> + >> +static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { >> + .core_reg = RK2928_CLKSEL_CON(0), >> + .div_core_shift = 0, >> + .div_core_mask = 0x1f, >> + .mux_core_shift = 6, >> +}; >> + >> +PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; >> + >> +PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; >> +PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; >> +PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; >> +PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; >> +PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; >> +PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; >> + >> +PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; >> +PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; >> +PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; >> +PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; >> +PNAME(mux_aclk_peri_src_p) = { "cpll", "gpll", "hdmiphy" }; > isn't that the same as your mux_pll_src_3plls_p? sorry, that is a mistake...i'll fix it in version 2. > > >> +PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; >> +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; >> + >> +PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; >> + >> +PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; >> +PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; >> + >> +PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; >> +PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; >> +PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; >> +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; >> +PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; >> + >> +PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; >> + >> +PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; >> +PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; >> +PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; >> + >> +PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; >> +PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; >> +PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; >> + >> +static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { >> + [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), >> + RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), >> + [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), >> + RK2928_MODE_CON, 4, 6, 0, NULL), >> + [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), >> + RK2928_MODE_CON, 8, 8, 0, NULL), >> + [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), >> + RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), >> +}; >> + >> +#define MFLAGS CLK_MUX_HIWORD_MASK >> +#define DFLAGS CLK_DIVIDER_HIWORD_MASK >> +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) >> + >> +static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { >> + /* >> + * Clock-Architecture Diagram 1 >> + */ >> + >> + DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), >> + >> + /* PD_DDR */ >> + GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 2, GFLAGS), >> + GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 2, GFLAGS), >> + GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 2, GFLAGS), >> + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, >> + 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, >> + RK2928_CLKGATE_CON(7), 1, GFLAGS), > please keep the formatting the same as in the other clock drivers, as it > makes reading this later easier when everything is always in the same place: > > + COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, > + RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > + RK2928_CLKGATE_CON(7), 1, GFLAGS), > > We're "flexible" with the 80col limit for this ;-) > done. >> + >> + /* PD_CORE */ >> + GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 6, GFLAGS), >> + GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 6, GFLAGS), >> + GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 6, GFLAGS), >> + COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, >> + RK2928_CLKGATE_CON(4), 1, GFLAGS), >> + COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, >> + RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, >> + RK2928_CLKGATE_CON(4), 0, GFLAGS), >> + >> + /* PD_MISC */ >> + MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, >> + RK2928_MISC_CON, 13, 1, MFLAGS), >> + MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, >> + RK2928_MISC_CON, 14, 1, MFLAGS), >> + MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, >> + RK2928_MISC_CON, 15, 1, MFLAGS), >> + >> + /* PD_BUS */ >> + GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(0), 1, GFLAGS), >> + GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), >> + GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 1, GFLAGS), >> + COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, >> + RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), >> + GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, >> + RK2928_CLKGATE_CON(6), 0, GFLAGS), >> + COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, >> + RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, >> + RK2928_CLKGATE_CON(6), 1, GFLAGS), >> + COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, >> + RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, >> + RK2928_CLKGATE_CON(6), 2, GFLAGS), >> + GATE(0, "pclk_cpu", "pclk_bus_src", 0, >> + RK2928_CLKGATE_CON(6), 3, GFLAGS), >> + GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, >> + RK2928_CLKGATE_CON(6), 4, GFLAGS), >> + GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, >> + RK2928_CLKGATE_CON(6), 13, GFLAGS), >> + >> + /* PD_VIDEO */ >> + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), >> + GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, >> + RK2928_CLKGATE_CON(4), 4, GFLAGS), >> + >> + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), >> + GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, >> + RK2928_CLKGATE_CON(4), 5, GFLAGS), >> + >> + COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 3, GFLAGS), >> + >> + COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 4, GFLAGS), >> + >> + /* PD_VIO */ >> + COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), >> + DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, >> + RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), >> + >> + COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), >> + >> + MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), >> + COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, >> + RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, >> + RK2928_CLKGATE_CON(1), 2, GFLAGS), >> + COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, >> + RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), >> + >> + COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, >> + RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), >> + >> + COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, >> + RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, >> + 8, 6, DFLAGS, RK2928_CLKGATE_CON(3), 5, GFLAGS), >> + >> + GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, >> + RK2928_CLKGATE_CON(3), 7, GFLAGS), >> + >> + COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, >> + RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, >> + 0, 14, DFLAGS, RK2928_CLKGATE_CON(3), 8, GFLAGS), >> + >> + /* PD_PERI */ >> + GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(2), 0, GFLAGS), >> + GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(2), 0, GFLAGS), >> + GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, >> + RK2928_CLKGATE_CON(2), 0, GFLAGS), >> + COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, >> + RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), >> + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, >> + RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, >> + RK2928_CLKGATE_CON(5), 2, GFLAGS), >> + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, >> + RK2928_CLKSEL_CON(10), 8, 3, DFLAGS, >> + RK2928_CLKGATE_CON(5), 1, GFLAGS), >> + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, >> + RK2928_CLKGATE_CON(5), 0, GFLAGS), >> + >> + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 5, GFLAGS), >> + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 6, GFLAGS), >> + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 7, GFLAGS), >> + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 8, GFLAGS), >> + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 9, GFLAGS), >> + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, >> + RK2928_CLKGATE_CON(6), 10, GFLAGS), >> + >> + COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 7, GFLAGS), >> + >> + GATE(0, "sclk_hsadc", "ext_hsadc", 0, >> + RK3288_CLKGATE_CON(10), 12, GFLAGS), >> + >> + COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, >> + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, >> + 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), >> + >> + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, >> + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, >> + 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), >> + >> + COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, >> + RK2928_CLKSEL_CON(11), 10, 2, DFLAGS, >> + RK2928_CLKGATE_CON(2), 13, GFLAGS), >> + DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, >> + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), >> + >> + COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, >> + RK2928_CLKSEL_CON(11), 12, 2, DFLAGS, >> + RK2928_CLKGATE_CON(2), 14, GFLAGS), >> + DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, >> + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), >> + >> + /* >> + * Clock-Architecture Diagram 2 >> + */ >> + >> + GATE(0, "gpll_vop", "gpll", 0, >> + RK2928_CLKGATE_CON(3), 1, GFLAGS), >> + GATE(0, "cpll_vop", "cpll", 0, >> + RK2928_CLKGATE_CON(3), 1, GFLAGS), >> + MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, >> + RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), >> + DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0, >> + RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), >> + DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, >> + RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), >> + MUX(0, "dclk_vop", mux_dclk_vop_p, 0, >> + RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), >> + >> + COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 3, GFLAGS), >> + COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(8), 0, >> + RK3288_CLKGATE_CON(0), 4, GFLAGS), >> + COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, >> + RK2928_CLKSEL_CON(9), 8, 2, DFLAGS, >> + RK2928_CLKGATE_CON(0), 5, GFLAGS), >> + >> + COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 10, GFLAGS), >> + COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(7), 0, >> + RK3288_CLKGATE_CON(0), 11, GFLAGS), >> + MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, >> + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), >> + GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, >> + RK2928_CLKGATE_CON(0), 14, GFLAGS), >> + COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, >> + RK2928_CLKSEL_CON(3), 12, 1, DFLAGS, >> + RK2928_CLKGATE_CON(0), 13, GFLAGS), >> + >> + COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), >> + COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(30), 0, >> + RK3288_CLKGATE_CON(0), 8, GFLAGS), >> + COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, >> + RK2928_CLKSEL_CON(16), 8, 2, DFLAGS, >> + RK2928_CLKGATE_CON(0), 9, GFLAGS), >> + >> + COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 10, GFLAGS), >> + COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, >> + RK3288_CLKSEL_CON(20), 0, >> + RK3288_CLKGATE_CON(2), 12, GFLAGS), >> + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, >> + RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), >> + >> + GATE(0, "jtag", "ext_jtag", 0, >> + RK2928_CLKGATE_CON(1), 3, GFLAGS), >> + >> + GATE(0, "sclk_otgphy0", "xin24m", 0, >> + RK2928_CLKGATE_CON(1), 5, GFLAGS), >> + GATE(0, "sclk_otgphy1", "xin24m", 0, >> + RK2928_CLKGATE_CON(1), 6, GFLAGS), >> + >> + COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, >> + RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, >> + RK2928_CLKGATE_CON(2), 8, GFLAGS), >> + >> + GATE(0, "cpll_gpu", "cpll", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + GATE(0, "gpll_gpu", "gpll", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + GATE(0, "hdmiphy_gpu", "hdmiphy", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + GATE(0, "usb480m_gpu", "usb480m", 0, >> + RK2928_CLKGATE_CON(3), 13, GFLAGS), >> + COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, >> + RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), >> + >> + COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(2), 9, GFLAGS), >> + >> + /* PD_UART */ >> + COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, >> + RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), >> + COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, >> + RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, >> + 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), >> + COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, >> + 0, RK2928_CLKSEL_CON(15), 12, 2, >> + MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), >> + COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(17), 0, >> + RK2928_CLKGATE_CON(1), 9, GFLAGS), >> + COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(18), 0, >> + RK2928_CLKGATE_CON(1), 11, GFLAGS), >> + COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(19), 0, >> + RK2928_CLKGATE_CON(1), 13, GFLAGS), >> + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), >> + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), >> + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, >> + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), >> + >> + COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), >> + >> + COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, >> + 0, 5, DFLAGS, RK2928_CLKGATE_CON(1), 7, GFLAGS), >> + MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, >> + RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), >> + MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, >> + RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), >> + GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 4, GFLAGS), >> + GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 3, GFLAGS), >> + GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 5, GFLAGS), >> + GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, >> + RK2928_CLKGATE_CON(5), 6, GFLAGS), >> + COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, >> + RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, >> + 8, 2, DFLAGS, RK2928_CLKGATE_CON(5), 7, GFLAGS), >> + COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, >> + RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, >> + 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 2, GFLAGS), >> + >> + /* >> + * Clock-Architecture Diagram 3 >> + */ >> + >> + /* PD_VOP */ >> + GATE(0, "aclk_rga", "aclk_rga_pre", 0, >> + RK2928_CLKGATE_CON(13), 0, GFLAGS), > the simple gate clocks from this diagram 3 can be on one line, as they > really are only a big number of simple gates. > > Again similar to how the other socs do it. done. > >> + GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, >> + RK2928_CLKGATE_CON(13), 11, GFLAGS), >> + GATE(0, "aclk_iep", "aclk_iep_pre", 0, >> + RK2928_CLKGATE_CON(13), 2, GFLAGS), >> + GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, >> + RK2928_CLKGATE_CON(13), 9, GFLAGS), > Otherwise this looks great > > Heiko > ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, Xing Zheng Add the devicetree binding for the cru on the rk3228 which quite similar structured as previous clock controllers. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt new file mode 100644 index 0000000..f323048 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt @@ -0,0 +1,58 @@ +* Rockchip RK3228 Clock and Reset Unit + +The RK3228 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3228-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@10110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10110000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + }; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel Add the devicetree binding for the cru on the rk3228 which quite similar structured as previous clock controllers. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt new file mode 100644 index 0000000..f323048 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt @@ -0,0 +1,58 @@ +* Rockchip RK3228 Clock and Reset Unit + +The RK3228 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3228-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + +Example: Clock controller node: + + cru: cru at 20000000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial at 10110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10110000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + }; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: Jeffy Chen, devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, Xing Zheng Add the devicetree binding for the cru on the rk3228 which quite similar structured as previous clock controllers. Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt new file mode 100644 index 0000000..f323048 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt @@ -0,0 +1,58 @@ +* Rockchip RK3228 Clock and Reset Unit + +The RK3228 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3228-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@10110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10110000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + }; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 20:12 ` Rob Herring -1 siblings, 0 replies; 58+ messages in thread From: Rob Herring @ 2015-12-09 20:12 UTC (permalink / raw) To: Jeffy Chen Cc: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Pawel Moll, Mark Rutland, Xing Zheng On Wed, Dec 09, 2015 at 05:04:09PM +0800, Jeffy Chen wrote: > Add the devicetree binding for the cru on the rk3228 which quite similar > structured as previous clock controllers. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Seems like there is a lot of duplication across Rockchip cru bindings. Perhaps they should be combined? Otherwise: Acked-by: Rob Herring <robh@kernel.org> > --- > > .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt > new file mode 100644 > index 0000000..f323048 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt > @@ -0,0 +1,58 @@ > +* Rockchip RK3228 Clock and Reset Unit > + > +The RK3228 clock controller generates and supplies clock to various > +controllers within the SoC and also implements a reset controller for SoC > +peripherals. > + > +Required Properties: > + > +- compatible: should be "rockchip,rk3228-cru" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- #clock-cells: should be 1. > +- #reset-cells: should be 1. > + > +Optional Properties: > + > +- rockchip,grf: phandle to the syscon managing the "general register files" > + If missing pll rates are not changeable, due to the missing pll lock status. > + > +Each clock is assigned an identifier and client nodes can use this identifier > +to specify the clock which they consume. All available clocks are defined as > +preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be > +used in device tree sources. Similar macros exist for the reset sources in > +these files. > + > +External clocks: > + > +There are several clocks that are generated outside the SoC. It is expected > +that they are defined using standard clock bindings with following > +clock-output-names: > + - "xin24m" - crystal input - required, > + - "ext_i2s" - external I2S clock - optional, > + - "ext_gmac" - external GMAC clock - optional > + - "ext_hsadc" - external HSADC clock - optional > + - "phy_50m_out" - output clock of the pll in the mac phy > + > +Example: Clock controller node: > + > + cru: cru@20000000 { > + compatible = "rockchip,rk3228-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > +Example: UART controller node that consumes the clock generated by the clock > + controller: > + > + uart0: serial@10110000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x10110000 0x100>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&cru SCLK_UART0>; > + }; > -- > 2.1.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 20:12 ` Rob Herring 0 siblings, 0 replies; 58+ messages in thread From: Rob Herring @ 2015-12-09 20:12 UTC (permalink / raw) To: linux-arm-kernel On Wed, Dec 09, 2015 at 05:04:09PM +0800, Jeffy Chen wrote: > Add the devicetree binding for the cru on the rk3228 which quite similar > structured as previous clock controllers. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Seems like there is a lot of duplication across Rockchip cru bindings. Perhaps they should be combined? Otherwise: Acked-by: Rob Herring <robh@kernel.org> > --- > > .../bindings/clock/rockchip,rk3228-cru.txt | 58 ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt > new file mode 100644 > index 0000000..f323048 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt > @@ -0,0 +1,58 @@ > +* Rockchip RK3228 Clock and Reset Unit > + > +The RK3228 clock controller generates and supplies clock to various > +controllers within the SoC and also implements a reset controller for SoC > +peripherals. > + > +Required Properties: > + > +- compatible: should be "rockchip,rk3228-cru" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- #clock-cells: should be 1. > +- #reset-cells: should be 1. > + > +Optional Properties: > + > +- rockchip,grf: phandle to the syscon managing the "general register files" > + If missing pll rates are not changeable, due to the missing pll lock status. > + > +Each clock is assigned an identifier and client nodes can use this identifier > +to specify the clock which they consume. All available clocks are defined as > +preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be > +used in device tree sources. Similar macros exist for the reset sources in > +these files. > + > +External clocks: > + > +There are several clocks that are generated outside the SoC. It is expected > +that they are defined using standard clock bindings with following > +clock-output-names: > + - "xin24m" - crystal input - required, > + - "ext_i2s" - external I2S clock - optional, > + - "ext_gmac" - external GMAC clock - optional > + - "ext_hsadc" - external HSADC clock - optional > + - "phy_50m_out" - output clock of the pll in the mac phy > + > +Example: Clock controller node: > + > + cru: cru at 20000000 { > + compatible = "rockchip,rk3228-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > +Example: UART controller node that consumes the clock generated by the clock > + controller: > + > + uart0: serial at 10110000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x10110000 0x100>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&cru SCLK_UART0>; > + }; > -- > 2.1.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller 2015-12-09 20:12 ` Rob Herring @ 2015-12-09 23:11 ` Heiko Stuebner -1 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:11 UTC (permalink / raw) To: Rob Herring Cc: Jeffy Chen, linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Pawel Moll, Mark Rutland, Xing Zheng Hi Rob, Am Mittwoch, 9. Dezember 2015, 14:12:00 schrieb Rob Herring: > On Wed, Dec 09, 2015 at 05:04:09PM +0800, Jeffy Chen wrote: > > Add the devicetree binding for the cru on the rk3228 which quite similar > > structured as previous clock controllers. > > > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > Seems like there is a lot of duplication across Rockchip cru bindings. > Perhaps they should be combined? You're right and I've put that on my list for the near future. > Otherwise: > > Acked-by: Rob Herring <robh@kernel.org> Thanks Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 23:11 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:11 UTC (permalink / raw) To: linux-arm-kernel Hi Rob, Am Mittwoch, 9. Dezember 2015, 14:12:00 schrieb Rob Herring: > On Wed, Dec 09, 2015 at 05:04:09PM +0800, Jeffy Chen wrote: > > Add the devicetree binding for the cru on the rk3228 which quite similar > > structured as previous clock controllers. > > > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > Seems like there is a lot of duplication across Rockchip cru bindings. > Perhaps they should be combined? You're right and I've put that on my list for the near future. > Otherwise: > > Acked-by: Rob Herring <robh@kernel.org> Thanks Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 23:17 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:17 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, Xing Zheng Am Mittwoch, 9. Dezember 2015, 17:04:09 schrieb Jeffy Chen: > Add the devicetree binding for the cru on the rk3228 which quite similar > structured as previous clock controllers. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my clock branch with Rob's ack ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 23:17 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:17 UTC (permalink / raw) To: linux-arm-kernel Am Mittwoch, 9. Dezember 2015, 17:04:09 schrieb Jeffy Chen: > Add the devicetree binding for the cru on the rk3228 which quite similar > structured as previous clock controllers. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my clock branch with Rob's ack ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller @ 2015-12-09 23:17 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 23:17 UTC (permalink / raw) To: Jeffy Chen Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ, Xing Zheng, Pawel Moll, Ian Campbell, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Kumar Gala, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Am Mittwoch, 9. Dezember 2015, 17:04:09 schrieb Jeffy Chen: > Add the devicetree binding for the cru on the rk3228 which quite similar > structured as previous clock controllers. > > Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> applied to my clock branch with Rob's ack ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 5/8] clk: rockchip: allow more than 2 parents for cpuclk @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, Michael Turquette, Stephen Boyd, linux-clk RK3228's armclk has 3 parents, so allow cpuclk to have more than 2 parents. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- drivers/clk/rockchip/clk-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 330870a..d07374f 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -242,8 +242,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, struct clk *clk, *cclk; int ret; - if (num_parents != 2) { - pr_err("%s: needs two parent clocks\n", __func__); + if (num_parents < 2) { + pr_err("%s: needs at least two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 5/8] clk: rockchip: allow more than 2 parents for cpuclk @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel RK3228's armclk has 3 parents, so allow cpuclk to have more than 2 parents. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- drivers/clk/rockchip/clk-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 330870a..d07374f 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -242,8 +242,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, struct clk *clk, *cclk; int ret; - if (num_parents != 2) { - pr_err("%s: needs two parent clocks\n", __func__); + if (num_parents < 2) { + pr_err("%s: needs@least two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 5/8] clk: rockchip: allow more than 2 parents for cpuclk @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: Michael Turquette, Jeffy Chen, Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA RK3228's armclk has 3 parents, so allow cpuclk to have more than 2 parents. Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- drivers/clk/rockchip/clk-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 330870a..d07374f 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -242,8 +242,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, struct clk *clk, *cclk; int ret; - if (num_parents != 2) { - pr_err("%s: needs two parent clocks\n", __func__); + if (num_parents < 2) { + pr_err("%s: needs at least two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 5/8] clk: rockchip: allow more than 2 parents for cpuclk 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 21:35 ` Heiko Stuebner -1 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 21:35 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, Michael Turquette, Stephen Boyd, linux-clk Am Mittwoch, 9. Dezember 2015, 17:04:10 schrieb Jeffy Chen: > RK3228's armclk has 3 parents, so allow cpuclk to have > more than 2 parents. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my clk branch for 4.5 Thanks Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 5/8] clk: rockchip: allow more than 2 parents for cpuclk @ 2015-12-09 21:35 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 21:35 UTC (permalink / raw) To: linux-arm-kernel Am Mittwoch, 9. Dezember 2015, 17:04:10 schrieb Jeffy Chen: > RK3228's armclk has 3 parents, so allow cpuclk to have > more than 2 parents. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my clk branch for 4.5 Thanks Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 6/8] ARM: rockchip: enable support for RK3228 SoCs 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 9:04 ` Jeffy Chen -1 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel; +Cc: Jeffy Chen Add a rockchip,rk3228 compatible. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- arch/arm/mach-rockchip/rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 608b31c..0cd4313 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -92,6 +92,7 @@ static const char * const rockchip_board_dt_compat[] = { "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188", + "rockchip,rk3228", "rockchip,rk3288", NULL, }; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 6/8] ARM: rockchip: enable support for RK3228 SoCs @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel Add a rockchip,rk3228 compatible. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- arch/arm/mach-rockchip/rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 608b31c..0cd4313 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -92,6 +92,7 @@ static const char * const rockchip_board_dt_compat[] = { "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188", + "rockchip,rk3228", "rockchip,rk3288", NULL, }; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 6/8] ARM: rockchip: enable support for RK3228 SoCs 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-09 21:27 ` Heiko Stuebner -1 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 21:27 UTC (permalink / raw) To: Jeffy Chen; +Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel Am Mittwoch, 9. Dezember 2015, 17:04:11 schrieb Jeffy Chen: > Add a rockchip,rk3228 compatible. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my soc branch for 4.5 ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 6/8] ARM: rockchip: enable support for RK3228 SoCs @ 2015-12-09 21:27 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-09 21:27 UTC (permalink / raw) To: linux-arm-kernel Am Mittwoch, 9. Dezember 2015, 17:04:11 schrieb Jeffy Chen: > Add a rockchip,rk3228 compatible. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> applied to my soc branch for 4.5 ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Initial release for rk3228 shared dtsi. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228.dtsi diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi new file mode 100644 index 0000000..d6b3e40 --- /dev/null +++ b/arch/arm/boot/dts/rk3228.dtsi @@ -0,0 +1,478 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3228"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + hdmiphy_phy: hdmiphy_phy { + compatible = "fixed-clock"; + clock-frequency = <594000000>; + clock-output-names = "hdmiphy_phy"; + #clock-cells = <0>; + }; + + phy_50m_out: phy_50m_out { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "phy_50m_out"; + #clock-cells = <0>; + }; + + usb480m_phy0: usb480m_phy0 { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + }; + + usb480m_phy1: usb480m_phy1 { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + cru: clock-controller@110e0000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x110e0000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>; + }; + + grf: syscon@11000000 { + compatible = "syscon"; + reg = <0x11000000 0x1000>; + }; + + timer: timer@110c0000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x110c0000 0x20>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + + emmc: dwmmc@30020000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30020000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "disabled"; + }; + + pwm0: pwm@110b0000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm@110b0010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm@110b0020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm@110b0030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + uart0: serial@11010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11010000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial@11020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11020000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@11030000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11030000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@11110000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11110000 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@11120000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11120000 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@11130000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11130000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@11140000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11140000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>, + <1 28 RK_FUNC_2 &pcfg_pull_none>, + <1 29 RK_FUNC_2 &pcfg_pull_none>, + <1 30 RK_FUNC_2 &pcfg_pull_none>, + <1 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, + <2 27 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, + <1 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel Initial release for rk3228 shared dtsi. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228.dtsi diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi new file mode 100644 index 0000000..d6b3e40 --- /dev/null +++ b/arch/arm/boot/dts/rk3228.dtsi @@ -0,0 +1,478 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3228"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu at f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + + cpu2: cpu at f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + }; + + cpu3: cpu at f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma at 110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + hdmiphy_phy: hdmiphy_phy { + compatible = "fixed-clock"; + clock-frequency = <594000000>; + clock-output-names = "hdmiphy_phy"; + #clock-cells = <0>; + }; + + phy_50m_out: phy_50m_out { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "phy_50m_out"; + #clock-cells = <0>; + }; + + usb480m_phy0: usb480m_phy0 { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + }; + + usb480m_phy1: usb480m_phy1 { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + cru: clock-controller at 110e0000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x110e0000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + gic: interrupt-controller at 32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>; + }; + + grf: syscon at 11000000 { + compatible = "syscon"; + reg = <0x11000000 0x1000>; + }; + + timer: timer at 110c0000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x110c0000 0x20>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + + emmc: dwmmc at 30020000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30020000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "disabled"; + }; + + pwm0: pwm at 110b0000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm at 110b0010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm at 110b0020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm at 110b0030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + uart0: serial at 11010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11010000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial at 11020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11020000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial at 11030000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11030000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0 at 11110000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11110000 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1 at 11120000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11120000 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2 at 11130000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11130000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3 at 11140000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11140000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>, + <1 28 RK_FUNC_2 &pcfg_pull_none>, + <1 29 RK_FUNC_2 &pcfg_pull_none>, + <1 30 RK_FUNC_2 &pcfg_pull_none>, + <1 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, + <2 27 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, + <1 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: Jeffy Chen, devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Initial release for rk3228 shared dtsi. Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228.dtsi diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi new file mode 100644 index 0000000..d6b3e40 --- /dev/null +++ b/arch/arm/boot/dts/rk3228.dtsi @@ -0,0 +1,478 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3228"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + hdmiphy_phy: hdmiphy_phy { + compatible = "fixed-clock"; + clock-frequency = <594000000>; + clock-output-names = "hdmiphy_phy"; + #clock-cells = <0>; + }; + + phy_50m_out: phy_50m_out { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "phy_50m_out"; + #clock-cells = <0>; + }; + + usb480m_phy0: usb480m_phy0 { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + }; + + usb480m_phy1: usb480m_phy1 { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + cru: clock-controller@110e0000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x110e0000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>; + }; + + grf: syscon@11000000 { + compatible = "syscon"; + reg = <0x11000000 0x1000>; + }; + + timer: timer@110c0000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x110c0000 0x20>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + + emmc: dwmmc@30020000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30020000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "disabled"; + }; + + pwm0: pwm@110b0000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm@110b0010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm@110b0020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm@110b0030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + uart0: serial@11010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11010000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial@11020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11020000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@11030000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11030000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@11110000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11110000 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@11120000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11120000 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@11130000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11130000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@11140000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11140000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>, + <1 28 RK_FUNC_2 &pcfg_pull_none>, + <1 29 RK_FUNC_2 &pcfg_pull_none>, + <1 30 RK_FUNC_2 &pcfg_pull_none>, + <1 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, + <2 27 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, + <1 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi 2015-12-09 9:04 ` Jeffy Chen @ 2015-12-10 0:32 ` Heiko Stuebner -1 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-10 0:32 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Jeffy, Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: > Initial release for rk3228 shared dtsi. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > --- > > arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 478 insertions(+) > create mode 100644 arch/arm/boot/dts/rk3228.dtsi > > diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi > new file mode 100644 > index 0000000..d6b3e40 > --- /dev/null > +++ b/arch/arm/boot/dts/rk3228.dtsi > @@ -0,0 +1,478 @@ > +/* > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/rockchip.h> > +#include <dt-bindings/clock/rk3228-cru.h> > +#include "skeleton.dtsi" > + > +/ { > + compatible = "rockchip,rk3228"; > + > + interrupt-parent = <&gic>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x60000000 0x40000000>; > + }; The amount of memory is a property of the board > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; no enable-method? As the rk3228 also does not have a pmu, does the newly created "rockchip,rk3036-smp" work for you? > + > + cpu0: cpu@f00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf00>; > + resets = <&cru SRST_CORE0>; > + operating-points = < > + /* KHz uV */ > + 816000 1000000 > + >; > + clock-latency = <40000>; > + clocks = <&cru ARMCLK>; > + }; > + > + cpu1: cpu@f01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf01>; > + resets = <&cru SRST_CORE1>; > + }; > + > + cpu2: cpu@f02 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf02>; > + resets = <&cru SRST_CORE2>; > + }; > + > + cpu3: cpu@f03 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf03>; > + resets = <&cru SRST_CORE3>; > + }; > + }; > + > + amba { > + compatible = "arm,amba-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + pdma: pdma@110f0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x110f0000 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + clocks = <&cru ACLK_DMAC>; > + clock-names = "apb_pclk"; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + arm,cpu-registers-not-fw-configured; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > + clock-frequency = <24000000>; > + }; > + > + hdmiphy_phy: hdmiphy_phy { > + compatible = "fixed-clock"; > + clock-frequency = <594000000>; > + clock-output-names = "hdmiphy_phy"; > + #clock-cells = <0>; > + }; > + > + phy_50m_out: phy_50m_out { > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + clock-output-names = "phy_50m_out"; > + #clock-cells = <0>; > + }; > + > + usb480m_phy0: usb480m_phy0 { > + compatible = "fixed-clock"; > + clock-frequency = <480000000>; > + clock-output-names = "usb480m_phy0"; > + #clock-cells = <0>; > + }; > + > + usb480m_phy1: usb480m_phy1 { > + compatible = "fixed-clock"; > + clock-frequency = <480000000>; > + clock-output-names = "usb480m_phy1"; > + #clock-cells = <0>; > + }; these clocks starting with hdmiphy clock come from IPs in the soc, so the relevant drivers should provide them (see my patch series for the picophy, or how rk808 and hym8563 do it) - especially as these clocks might get turned off in the IP-block itself. The clock framework can handle orphans, so just leave these out for now please. > + > + xin24m: oscillator { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + #clock-cells = <0>; > + }; > + > + cru: clock-controller@110e0000 { > + compatible = "rockchip,rk3228-cru"; > + reg = <0x110e0000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + assigned-clocks = <&cru PLL_GPLL>; > + assigned-clock-rates = <594000000>; > + }; > + > + gic: interrupt-controller@32010000 { please order by register address, so gic should move quite a bit lower. > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + > + reg = <0x32011000 0x1000>, > + <0x32012000 0x1000>; please also provide the vgic registers and interrupt. > + }; > + > + grf: syscon@11000000 { > + compatible = "syscon"; > + reg = <0x11000000 0x1000>; > + }; > + > + timer: timer@110c0000 { > + compatible = "rockchip,rk3288-timer"; > + reg = <0x110c0000 0x20>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xin24m>, <&cru PCLK_TIMER>; > + clock-names = "timer", "pclk"; > + }; > + > + emmc: dwmmc@30020000 { > + compatible = "rockchip,rk3288-dw-mshc"; > + clock-frequency = <37500000>; > + clock-freq-min-max = <400000 37500000>; > + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, > + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; > + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x30020000 0x4000>; > + broken-cd; > + bus-width = <8>; > + cap-mmc-highspeed; > + mmc-ddr-1_8v; > + disable-wp; > + non-removable; > + num-slots = <1>; > + default-sample-phase = <158>; > + pinctrl-names = "default"; > + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; please separate board and core properties. broken-cd, cap-*, mmc-ddr-1_8v, disable-wp, non-removable are per-board properties as they depend on what is connected to the controller. > + status = "disabled"; > + }; > + > + pwm0: pwm@110b0000 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0000 0x10>; > + #pwm-cells = <3>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm0_pin>; > + status = "disabled"; > + }; > + > + pwm1: pwm@110b0010 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0010 0x10>; > + #pwm-cells = <3>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm1_pin>; > + status = "disabled"; > + }; > + > + pwm2: pwm@110b0020 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0020 0x10>; > + #pwm-cells = <3>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm2_pin>; > + status = "disabled"; > + }; > + > + pwm3: pwm@110b0030 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0030 0x10>; > + #pwm-cells = <2>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm3_pin>; > + status = "disabled"; > + }; > + > + uart0: serial@11010000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11010000 0x100>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > + clock-names = "baudclk", "apb_pclk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; > + status = "disabled"; > + }; > + > + uart1: serial@11020000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11020000 0x100>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; > + clock-names = "baudclk", "apb_pclk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart1_xfer>; > + status = "disabled"; > + }; > + > + uart2: serial@11030000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11030000 0x100>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; > + clock-names = "baudclk", "apb_pclk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart2_xfer>; > + status = "disabled"; > + }; > + > + > + pinctrl: pinctrl { > + compatible = "rockchip,rk3228-pinctrl"; > + rockchip,grf = <&grf>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + gpio0: gpio0@11110000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11110000 0x100>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO0>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio1: gpio1@11120000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11120000 0x100>; > + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO1>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio2@11130000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11130000 0x100>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO2>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio3@11140000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11140000 0x100>; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO3>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + pcfg_pull_up: pcfg-pull-up { > + bias-pull-up; > + }; > + > + pcfg_pull_down: pcfg-pull-down { > + bias-pull-down; > + }; > + > + pcfg_pull_none: pcfg-pull-none { > + bias-disable; > + }; > + > + emmc { > + emmc_clk: emmc-clk { > + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; > + }; > + > + emmc_cmd: emmc-cmd { > + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; > + }; > + > + emmc_bus8: emmc-bus8 { > + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, > + <1 25 RK_FUNC_2 &pcfg_pull_none>, > + <1 26 RK_FUNC_2 &pcfg_pull_none>, > + <1 27 RK_FUNC_2 &pcfg_pull_none>, > + <1 28 RK_FUNC_2 &pcfg_pull_none>, > + <1 29 RK_FUNC_2 &pcfg_pull_none>, > + <1 30 RK_FUNC_2 &pcfg_pull_none>, > + <1 31 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + pwm0 { > + pwm0_pin: pwm0-pin { > + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + > + pwm1 { > + pwm1_pin: pwm1-pin { > + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + pwm2 { > + pwm2_pin: pwm2-pin { > + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + pwm3 { > + pwm3_pin: pwm3-pin { > + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + uart0 { > + uart0_xfer: uart0-xfer { > + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, > + <2 27 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart0_cts: uart0-cts { > + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart0_rts: uart0-rts { > + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + > + uart1 { > + uart1_xfer: uart1-xfer { > + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, > + <1 10 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart1_cts: uart1-cts { > + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart1_rts: uart1-rts { > + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + > + uart2 { > + uart2_xfer: uart2-xfer { > + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, > + <1 19 RK_FUNC_2 &pcfg_pull_none>; > + }; > + > + uart2_cts: uart2-cts { > + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart2_rts: uart2-rts { > + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + }; > +}; > ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-10 0:32 ` Heiko Stuebner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stuebner @ 2015-12-10 0:32 UTC (permalink / raw) To: linux-arm-kernel Hi Jeffy, Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: > Initial release for rk3228 shared dtsi. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > --- > > arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 478 insertions(+) > create mode 100644 arch/arm/boot/dts/rk3228.dtsi > > diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi > new file mode 100644 > index 0000000..d6b3e40 > --- /dev/null > +++ b/arch/arm/boot/dts/rk3228.dtsi > @@ -0,0 +1,478 @@ > +/* > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/rockchip.h> > +#include <dt-bindings/clock/rk3228-cru.h> > +#include "skeleton.dtsi" > + > +/ { > + compatible = "rockchip,rk3228"; > + > + interrupt-parent = <&gic>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x60000000 0x40000000>; > + }; The amount of memory is a property of the board > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; no enable-method? As the rk3228 also does not have a pmu, does the newly created "rockchip,rk3036-smp" work for you? > + > + cpu0: cpu at f00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf00>; > + resets = <&cru SRST_CORE0>; > + operating-points = < > + /* KHz uV */ > + 816000 1000000 > + >; > + clock-latency = <40000>; > + clocks = <&cru ARMCLK>; > + }; > + > + cpu1: cpu at f01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf01>; > + resets = <&cru SRST_CORE1>; > + }; > + > + cpu2: cpu at f02 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf02>; > + resets = <&cru SRST_CORE2>; > + }; > + > + cpu3: cpu at f03 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf03>; > + resets = <&cru SRST_CORE3>; > + }; > + }; > + > + amba { > + compatible = "arm,amba-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + pdma: pdma at 110f0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x110f0000 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + clocks = <&cru ACLK_DMAC>; > + clock-names = "apb_pclk"; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + arm,cpu-registers-not-fw-configured; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > + clock-frequency = <24000000>; > + }; > + > + hdmiphy_phy: hdmiphy_phy { > + compatible = "fixed-clock"; > + clock-frequency = <594000000>; > + clock-output-names = "hdmiphy_phy"; > + #clock-cells = <0>; > + }; > + > + phy_50m_out: phy_50m_out { > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + clock-output-names = "phy_50m_out"; > + #clock-cells = <0>; > + }; > + > + usb480m_phy0: usb480m_phy0 { > + compatible = "fixed-clock"; > + clock-frequency = <480000000>; > + clock-output-names = "usb480m_phy0"; > + #clock-cells = <0>; > + }; > + > + usb480m_phy1: usb480m_phy1 { > + compatible = "fixed-clock"; > + clock-frequency = <480000000>; > + clock-output-names = "usb480m_phy1"; > + #clock-cells = <0>; > + }; these clocks starting with hdmiphy clock come from IPs in the soc, so the relevant drivers should provide them (see my patch series for the picophy, or how rk808 and hym8563 do it) - especially as these clocks might get turned off in the IP-block itself. The clock framework can handle orphans, so just leave these out for now please. > + > + xin24m: oscillator { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + #clock-cells = <0>; > + }; > + > + cru: clock-controller at 110e0000 { > + compatible = "rockchip,rk3228-cru"; > + reg = <0x110e0000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + assigned-clocks = <&cru PLL_GPLL>; > + assigned-clock-rates = <594000000>; > + }; > + > + gic: interrupt-controller at 32010000 { please order by register address, so gic should move quite a bit lower. > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + > + reg = <0x32011000 0x1000>, > + <0x32012000 0x1000>; please also provide the vgic registers and interrupt. > + }; > + > + grf: syscon at 11000000 { > + compatible = "syscon"; > + reg = <0x11000000 0x1000>; > + }; > + > + timer: timer at 110c0000 { > + compatible = "rockchip,rk3288-timer"; > + reg = <0x110c0000 0x20>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xin24m>, <&cru PCLK_TIMER>; > + clock-names = "timer", "pclk"; > + }; > + > + emmc: dwmmc at 30020000 { > + compatible = "rockchip,rk3288-dw-mshc"; > + clock-frequency = <37500000>; > + clock-freq-min-max = <400000 37500000>; > + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, > + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; > + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x30020000 0x4000>; > + broken-cd; > + bus-width = <8>; > + cap-mmc-highspeed; > + mmc-ddr-1_8v; > + disable-wp; > + non-removable; > + num-slots = <1>; > + default-sample-phase = <158>; > + pinctrl-names = "default"; > + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; please separate board and core properties. broken-cd, cap-*, mmc-ddr-1_8v, disable-wp, non-removable are per-board properties as they depend on what is connected to the controller. > + status = "disabled"; > + }; > + > + pwm0: pwm at 110b0000 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0000 0x10>; > + #pwm-cells = <3>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm0_pin>; > + status = "disabled"; > + }; > + > + pwm1: pwm at 110b0010 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0010 0x10>; > + #pwm-cells = <3>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm1_pin>; > + status = "disabled"; > + }; > + > + pwm2: pwm at 110b0020 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0020 0x10>; > + #pwm-cells = <3>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm2_pin>; > + status = "disabled"; > + }; > + > + pwm3: pwm at 110b0030 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0030 0x10>; > + #pwm-cells = <2>; > + clocks = <&cru PCLK_PWM>; > + clock-names = "pwm"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm3_pin>; > + status = "disabled"; > + }; > + > + uart0: serial at 11010000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11010000 0x100>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > + clock-names = "baudclk", "apb_pclk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; > + status = "disabled"; > + }; > + > + uart1: serial at 11020000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11020000 0x100>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; > + clock-names = "baudclk", "apb_pclk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart1_xfer>; > + status = "disabled"; > + }; > + > + uart2: serial at 11030000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11030000 0x100>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; > + clock-names = "baudclk", "apb_pclk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart2_xfer>; > + status = "disabled"; > + }; > + > + > + pinctrl: pinctrl { > + compatible = "rockchip,rk3228-pinctrl"; > + rockchip,grf = <&grf>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + gpio0: gpio0 at 11110000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11110000 0x100>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO0>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio1: gpio1 at 11120000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11120000 0x100>; > + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO1>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio2 at 11130000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11130000 0x100>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO2>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio3 at 11140000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11140000 0x100>; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru PCLK_GPIO3>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + pcfg_pull_up: pcfg-pull-up { > + bias-pull-up; > + }; > + > + pcfg_pull_down: pcfg-pull-down { > + bias-pull-down; > + }; > + > + pcfg_pull_none: pcfg-pull-none { > + bias-disable; > + }; > + > + emmc { > + emmc_clk: emmc-clk { > + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; > + }; > + > + emmc_cmd: emmc-cmd { > + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; > + }; > + > + emmc_bus8: emmc-bus8 { > + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, > + <1 25 RK_FUNC_2 &pcfg_pull_none>, > + <1 26 RK_FUNC_2 &pcfg_pull_none>, > + <1 27 RK_FUNC_2 &pcfg_pull_none>, > + <1 28 RK_FUNC_2 &pcfg_pull_none>, > + <1 29 RK_FUNC_2 &pcfg_pull_none>, > + <1 30 RK_FUNC_2 &pcfg_pull_none>, > + <1 31 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + pwm0 { > + pwm0_pin: pwm0-pin { > + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + > + pwm1 { > + pwm1_pin: pwm1-pin { > + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + pwm2 { > + pwm2_pin: pwm2-pin { > + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + pwm3 { > + pwm3_pin: pwm3-pin { > + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; > + }; > + }; > + > + uart0 { > + uart0_xfer: uart0-xfer { > + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, > + <2 27 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart0_cts: uart0-cts { > + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart0_rts: uart0-rts { > + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + > + uart1 { > + uart1_xfer: uart1-xfer { > + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, > + <1 10 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart1_cts: uart1-cts { > + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart1_rts: uart1-rts { > + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + > + uart2 { > + uart2_xfer: uart2-xfer { > + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, > + <1 19 RK_FUNC_2 &pcfg_pull_none>; > + }; > + > + uart2_cts: uart2-cts { > + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; > + }; > + > + uart2_rts: uart2-rts { > + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; > + }; > + }; > + }; > +}; > ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi 2015-12-10 0:32 ` Heiko Stuebner (?) @ 2015-12-11 1:53 ` Jeffy Chen -1 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-11 1:53 UTC (permalink / raw) To: Heiko Stuebner Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Heiko, On 2015-12-10 8:32, Heiko Stuebner wrote: > Hi Jeffy, > > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >> Initial release for rk3228 shared dtsi. >> >> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> --- >> >> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 478 insertions(+) >> create mode 100644 arch/arm/boot/dts/rk3228.dtsi >> >> diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi >> new file mode 100644 >> index 0000000..d6b3e40 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3228.dtsi >> @@ -0,0 +1,478 @@ >> +/* >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/pinctrl/rockchip.h> >> +#include <dt-bindings/clock/rk3228-cru.h> >> +#include "skeleton.dtsi" >> + >> +/ { >> + compatible = "rockchip,rk3228"; >> + >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + }; >> + >> + memory { >> + device_type = "memory"; >> + reg = <0x60000000 0x40000000>; >> + }; > The amount of memory is a property of the board done. >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; > no enable-method? > > As the rk3228 also does not have a pmu, does the newly created > "rockchip,rk3036-smp" work for you? unlucky, that doesn't work...and our 3.10 kernel is using psci for rk3228's smp ops, maybe i should check that too, but i know nothing about psci for now :( >> + >> + cpu0: cpu@f00 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf00>; >> + resets = <&cru SRST_CORE0>; >> + operating-points = < >> + /* KHz uV */ >> + 816000 1000000 >> + >; >> + clock-latency = <40000>; >> + clocks = <&cru ARMCLK>; >> + }; >> + >> + cpu1: cpu@f01 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf01>; >> + resets = <&cru SRST_CORE1>; >> + }; >> + >> + cpu2: cpu@f02 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf02>; >> + resets = <&cru SRST_CORE2>; >> + }; >> + >> + cpu3: cpu@f03 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf03>; >> + resets = <&cru SRST_CORE3>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + pdma: pdma@110f0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x110f0000 0x4000>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; >> + #dma-cells = <1>; >> + clocks = <&cru ACLK_DMAC>; >> + clock-names = "apb_pclk"; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a7-pmu"; >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; >> + arm,cpu-registers-not-fw-configured; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; >> + clock-frequency = <24000000>; >> + }; >> + >> + hdmiphy_phy: hdmiphy_phy { >> + compatible = "fixed-clock"; >> + clock-frequency = <594000000>; >> + clock-output-names = "hdmiphy_phy"; >> + #clock-cells = <0>; >> + }; >> + >> + phy_50m_out: phy_50m_out { >> + compatible = "fixed-clock"; >> + clock-frequency = <50000000>; >> + clock-output-names = "phy_50m_out"; >> + #clock-cells = <0>; >> + }; >> + >> + usb480m_phy0: usb480m_phy0 { >> + compatible = "fixed-clock"; >> + clock-frequency = <480000000>; >> + clock-output-names = "usb480m_phy0"; >> + #clock-cells = <0>; >> + }; >> + >> + usb480m_phy1: usb480m_phy1 { >> + compatible = "fixed-clock"; >> + clock-frequency = <480000000>; >> + clock-output-names = "usb480m_phy1"; >> + #clock-cells = <0>; >> + }; > these clocks starting with hdmiphy clock come from IPs in the soc, so the > relevant drivers should provide them (see my patch series for the picophy, > or how rk808 and hym8563 do it) - especially as these clocks might get > turned off in the IP-block itself. > > The clock framework can handle orphans, so just leave these out for now > please. you're right, done. > >> + >> + xin24m: oscillator { >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "xin24m"; >> + #clock-cells = <0>; >> + }; >> + >> + cru: clock-controller@110e0000 { >> + compatible = "rockchip,rk3228-cru"; >> + reg = <0x110e0000 0x1000>; >> + rockchip,grf = <&grf>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + assigned-clocks = <&cru PLL_GPLL>; >> + assigned-clock-rates = <594000000>; >> + }; >> + >> + gic: interrupt-controller@32010000 { > please order by register address, so gic should move quite > a bit lower. done. >> + compatible = "arm,gic-400"; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + >> + reg = <0x32011000 0x1000>, >> + <0x32012000 0x1000>; > please also provide the vgic registers and interrupt. done. > >> + }; >> + >> + grf: syscon@11000000 { >> + compatible = "syscon"; >> + reg = <0x11000000 0x1000>; >> + }; >> + >> + timer: timer@110c0000 { >> + compatible = "rockchip,rk3288-timer"; >> + reg = <0x110c0000 0x20>; >> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&xin24m>, <&cru PCLK_TIMER>; >> + clock-names = "timer", "pclk"; >> + }; >> + >> + emmc: dwmmc@30020000 { >> + compatible = "rockchip,rk3288-dw-mshc"; >> + clock-frequency = <37500000>; >> + clock-freq-min-max = <400000 37500000>; >> + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, >> + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; >> + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; >> + fifo-depth = <0x100>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x30020000 0x4000>; >> + broken-cd; >> + bus-width = <8>; >> + cap-mmc-highspeed; >> + mmc-ddr-1_8v; >> + disable-wp; >> + non-removable; >> + num-slots = <1>; >> + default-sample-phase = <158>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; > please separate board and core properties. > broken-cd, cap-*, mmc-ddr-1_8v, disable-wp, non-removable > are per-board properties as they depend on what is connected to > the controller. done. >> + status = "disabled"; >> + }; >> + >> + pwm0: pwm@110b0000 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0000 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm0_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm1: pwm@110b0010 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0010 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm1_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm2: pwm@110b0020 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0020 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm2_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm3: pwm@110b0030 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0030 0x10>; >> + #pwm-cells = <2>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm3_pin>; >> + status = "disabled"; >> + }; >> + >> + uart0: serial@11010000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11010000 0x100>; >> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; >> + status = "disabled"; >> + }; >> + >> + uart1: serial@11020000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11020000 0x100>; >> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart1_xfer>; >> + status = "disabled"; >> + }; >> + >> + uart2: serial@11030000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11030000 0x100>; >> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart2_xfer>; >> + status = "disabled"; >> + }; >> + >> + >> + pinctrl: pinctrl { >> + compatible = "rockchip,rk3228-pinctrl"; >> + rockchip,grf = <&grf>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + gpio0: gpio0@11110000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11110000 0x100>; >> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO0>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio1: gpio1@11120000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11120000 0x100>; >> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO1>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio2: gpio2@11130000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11130000 0x100>; >> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO2>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio3: gpio3@11140000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11140000 0x100>; >> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO3>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + pcfg_pull_up: pcfg-pull-up { >> + bias-pull-up; >> + }; >> + >> + pcfg_pull_down: pcfg-pull-down { >> + bias-pull-down; >> + }; >> + >> + pcfg_pull_none: pcfg-pull-none { >> + bias-disable; >> + }; >> + >> + emmc { >> + emmc_clk: emmc-clk { >> + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + emmc_cmd: emmc-cmd { >> + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + emmc_bus8: emmc-bus8 { >> + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, >> + <1 25 RK_FUNC_2 &pcfg_pull_none>, >> + <1 26 RK_FUNC_2 &pcfg_pull_none>, >> + <1 27 RK_FUNC_2 &pcfg_pull_none>, >> + <1 28 RK_FUNC_2 &pcfg_pull_none>, >> + <1 29 RK_FUNC_2 &pcfg_pull_none>, >> + <1 30 RK_FUNC_2 &pcfg_pull_none>, >> + <1 31 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm0 { >> + pwm0_pin: pwm0-pin { >> + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm1 { >> + pwm1_pin: pwm1-pin { >> + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm2 { >> + pwm2_pin: pwm2-pin { >> + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm3 { >> + pwm3_pin: pwm3-pin { >> + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart0 { >> + uart0_xfer: uart0-xfer { >> + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, >> + <2 27 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart0_cts: uart0-cts { >> + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart0_rts: uart0-rts { >> + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart1 { >> + uart1_xfer: uart1-xfer { >> + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, >> + <1 10 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart1_cts: uart1-cts { >> + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart1_rts: uart1-rts { >> + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart2 { >> + uart2_xfer: uart2-xfer { >> + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, >> + <1 19 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + uart2_cts: uart2-cts { >> + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart2_rts: uart2-rts { >> + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + }; >> +}; >> > ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-11 1:53 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-11 1:53 UTC (permalink / raw) To: linux-arm-kernel Hi Heiko, On 2015-12-10 8:32, Heiko Stuebner wrote: > Hi Jeffy, > > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >> Initial release for rk3228 shared dtsi. >> >> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> --- >> >> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 478 insertions(+) >> create mode 100644 arch/arm/boot/dts/rk3228.dtsi >> >> diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi >> new file mode 100644 >> index 0000000..d6b3e40 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3228.dtsi >> @@ -0,0 +1,478 @@ >> +/* >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/pinctrl/rockchip.h> >> +#include <dt-bindings/clock/rk3228-cru.h> >> +#include "skeleton.dtsi" >> + >> +/ { >> + compatible = "rockchip,rk3228"; >> + >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + }; >> + >> + memory { >> + device_type = "memory"; >> + reg = <0x60000000 0x40000000>; >> + }; > The amount of memory is a property of the board done. >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; > no enable-method? > > As the rk3228 also does not have a pmu, does the newly created > "rockchip,rk3036-smp" work for you? unlucky, that doesn't work...and our 3.10 kernel is using psci for rk3228's smp ops, maybe i should check that too, but i know nothing about psci for now :( >> + >> + cpu0: cpu at f00 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf00>; >> + resets = <&cru SRST_CORE0>; >> + operating-points = < >> + /* KHz uV */ >> + 816000 1000000 >> + >; >> + clock-latency = <40000>; >> + clocks = <&cru ARMCLK>; >> + }; >> + >> + cpu1: cpu at f01 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf01>; >> + resets = <&cru SRST_CORE1>; >> + }; >> + >> + cpu2: cpu at f02 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf02>; >> + resets = <&cru SRST_CORE2>; >> + }; >> + >> + cpu3: cpu at f03 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf03>; >> + resets = <&cru SRST_CORE3>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + pdma: pdma at 110f0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x110f0000 0x4000>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; >> + #dma-cells = <1>; >> + clocks = <&cru ACLK_DMAC>; >> + clock-names = "apb_pclk"; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a7-pmu"; >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; >> + arm,cpu-registers-not-fw-configured; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; >> + clock-frequency = <24000000>; >> + }; >> + >> + hdmiphy_phy: hdmiphy_phy { >> + compatible = "fixed-clock"; >> + clock-frequency = <594000000>; >> + clock-output-names = "hdmiphy_phy"; >> + #clock-cells = <0>; >> + }; >> + >> + phy_50m_out: phy_50m_out { >> + compatible = "fixed-clock"; >> + clock-frequency = <50000000>; >> + clock-output-names = "phy_50m_out"; >> + #clock-cells = <0>; >> + }; >> + >> + usb480m_phy0: usb480m_phy0 { >> + compatible = "fixed-clock"; >> + clock-frequency = <480000000>; >> + clock-output-names = "usb480m_phy0"; >> + #clock-cells = <0>; >> + }; >> + >> + usb480m_phy1: usb480m_phy1 { >> + compatible = "fixed-clock"; >> + clock-frequency = <480000000>; >> + clock-output-names = "usb480m_phy1"; >> + #clock-cells = <0>; >> + }; > these clocks starting with hdmiphy clock come from IPs in the soc, so the > relevant drivers should provide them (see my patch series for the picophy, > or how rk808 and hym8563 do it) - especially as these clocks might get > turned off in the IP-block itself. > > The clock framework can handle orphans, so just leave these out for now > please. you're right, done. > >> + >> + xin24m: oscillator { >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "xin24m"; >> + #clock-cells = <0>; >> + }; >> + >> + cru: clock-controller at 110e0000 { >> + compatible = "rockchip,rk3228-cru"; >> + reg = <0x110e0000 0x1000>; >> + rockchip,grf = <&grf>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + assigned-clocks = <&cru PLL_GPLL>; >> + assigned-clock-rates = <594000000>; >> + }; >> + >> + gic: interrupt-controller at 32010000 { > please order by register address, so gic should move quite > a bit lower. done. >> + compatible = "arm,gic-400"; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + >> + reg = <0x32011000 0x1000>, >> + <0x32012000 0x1000>; > please also provide the vgic registers and interrupt. done. > >> + }; >> + >> + grf: syscon at 11000000 { >> + compatible = "syscon"; >> + reg = <0x11000000 0x1000>; >> + }; >> + >> + timer: timer at 110c0000 { >> + compatible = "rockchip,rk3288-timer"; >> + reg = <0x110c0000 0x20>; >> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&xin24m>, <&cru PCLK_TIMER>; >> + clock-names = "timer", "pclk"; >> + }; >> + >> + emmc: dwmmc at 30020000 { >> + compatible = "rockchip,rk3288-dw-mshc"; >> + clock-frequency = <37500000>; >> + clock-freq-min-max = <400000 37500000>; >> + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, >> + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; >> + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; >> + fifo-depth = <0x100>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x30020000 0x4000>; >> + broken-cd; >> + bus-width = <8>; >> + cap-mmc-highspeed; >> + mmc-ddr-1_8v; >> + disable-wp; >> + non-removable; >> + num-slots = <1>; >> + default-sample-phase = <158>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; > please separate board and core properties. > broken-cd, cap-*, mmc-ddr-1_8v, disable-wp, non-removable > are per-board properties as they depend on what is connected to > the controller. done. >> + status = "disabled"; >> + }; >> + >> + pwm0: pwm at 110b0000 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0000 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm0_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm1: pwm at 110b0010 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0010 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm1_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm2: pwm at 110b0020 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0020 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm2_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm3: pwm at 110b0030 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0030 0x10>; >> + #pwm-cells = <2>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm3_pin>; >> + status = "disabled"; >> + }; >> + >> + uart0: serial at 11010000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11010000 0x100>; >> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; >> + status = "disabled"; >> + }; >> + >> + uart1: serial at 11020000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11020000 0x100>; >> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart1_xfer>; >> + status = "disabled"; >> + }; >> + >> + uart2: serial at 11030000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11030000 0x100>; >> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart2_xfer>; >> + status = "disabled"; >> + }; >> + >> + >> + pinctrl: pinctrl { >> + compatible = "rockchip,rk3228-pinctrl"; >> + rockchip,grf = <&grf>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + gpio0: gpio0 at 11110000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11110000 0x100>; >> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO0>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio1: gpio1 at 11120000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11120000 0x100>; >> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO1>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio2: gpio2 at 11130000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11130000 0x100>; >> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO2>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio3: gpio3 at 11140000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11140000 0x100>; >> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO3>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + pcfg_pull_up: pcfg-pull-up { >> + bias-pull-up; >> + }; >> + >> + pcfg_pull_down: pcfg-pull-down { >> + bias-pull-down; >> + }; >> + >> + pcfg_pull_none: pcfg-pull-none { >> + bias-disable; >> + }; >> + >> + emmc { >> + emmc_clk: emmc-clk { >> + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + emmc_cmd: emmc-cmd { >> + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + emmc_bus8: emmc-bus8 { >> + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, >> + <1 25 RK_FUNC_2 &pcfg_pull_none>, >> + <1 26 RK_FUNC_2 &pcfg_pull_none>, >> + <1 27 RK_FUNC_2 &pcfg_pull_none>, >> + <1 28 RK_FUNC_2 &pcfg_pull_none>, >> + <1 29 RK_FUNC_2 &pcfg_pull_none>, >> + <1 30 RK_FUNC_2 &pcfg_pull_none>, >> + <1 31 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm0 { >> + pwm0_pin: pwm0-pin { >> + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm1 { >> + pwm1_pin: pwm1-pin { >> + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm2 { >> + pwm2_pin: pwm2-pin { >> + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm3 { >> + pwm3_pin: pwm3-pin { >> + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart0 { >> + uart0_xfer: uart0-xfer { >> + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, >> + <2 27 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart0_cts: uart0-cts { >> + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart0_rts: uart0-rts { >> + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart1 { >> + uart1_xfer: uart1-xfer { >> + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, >> + <1 10 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart1_cts: uart1-cts { >> + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart1_rts: uart1-rts { >> + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart2 { >> + uart2_xfer: uart2-xfer { >> + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, >> + <1 19 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + uart2_cts: uart2-cts { >> + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart2_rts: uart2-rts { >> + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + }; >> +}; >> > ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-11 1:53 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-11 1:53 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Heiko, On 2015-12-10 8:32, Heiko Stuebner wrote: > Hi Jeffy, > > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >> Initial release for rk3228 shared dtsi. >> >> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> --- >> >> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 478 insertions(+) >> create mode 100644 arch/arm/boot/dts/rk3228.dtsi >> >> diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi >> new file mode 100644 >> index 0000000..d6b3e40 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3228.dtsi >> @@ -0,0 +1,478 @@ >> +/* >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/pinctrl/rockchip.h> >> +#include <dt-bindings/clock/rk3228-cru.h> >> +#include "skeleton.dtsi" >> + >> +/ { >> + compatible = "rockchip,rk3228"; >> + >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + }; >> + >> + memory { >> + device_type = "memory"; >> + reg = <0x60000000 0x40000000>; >> + }; > The amount of memory is a property of the board done. >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; > no enable-method? > > As the rk3228 also does not have a pmu, does the newly created > "rockchip,rk3036-smp" work for you? unlucky, that doesn't work...and our 3.10 kernel is using psci for rk3228's smp ops, maybe i should check that too, but i know nothing about psci for now :( >> + >> + cpu0: cpu@f00 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf00>; >> + resets = <&cru SRST_CORE0>; >> + operating-points = < >> + /* KHz uV */ >> + 816000 1000000 >> + >; >> + clock-latency = <40000>; >> + clocks = <&cru ARMCLK>; >> + }; >> + >> + cpu1: cpu@f01 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf01>; >> + resets = <&cru SRST_CORE1>; >> + }; >> + >> + cpu2: cpu@f02 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf02>; >> + resets = <&cru SRST_CORE2>; >> + }; >> + >> + cpu3: cpu@f03 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf03>; >> + resets = <&cru SRST_CORE3>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + pdma: pdma@110f0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x110f0000 0x4000>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; >> + #dma-cells = <1>; >> + clocks = <&cru ACLK_DMAC>; >> + clock-names = "apb_pclk"; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a7-pmu"; >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; >> + arm,cpu-registers-not-fw-configured; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; >> + clock-frequency = <24000000>; >> + }; >> + >> + hdmiphy_phy: hdmiphy_phy { >> + compatible = "fixed-clock"; >> + clock-frequency = <594000000>; >> + clock-output-names = "hdmiphy_phy"; >> + #clock-cells = <0>; >> + }; >> + >> + phy_50m_out: phy_50m_out { >> + compatible = "fixed-clock"; >> + clock-frequency = <50000000>; >> + clock-output-names = "phy_50m_out"; >> + #clock-cells = <0>; >> + }; >> + >> + usb480m_phy0: usb480m_phy0 { >> + compatible = "fixed-clock"; >> + clock-frequency = <480000000>; >> + clock-output-names = "usb480m_phy0"; >> + #clock-cells = <0>; >> + }; >> + >> + usb480m_phy1: usb480m_phy1 { >> + compatible = "fixed-clock"; >> + clock-frequency = <480000000>; >> + clock-output-names = "usb480m_phy1"; >> + #clock-cells = <0>; >> + }; > these clocks starting with hdmiphy clock come from IPs in the soc, so the > relevant drivers should provide them (see my patch series for the picophy, > or how rk808 and hym8563 do it) - especially as these clocks might get > turned off in the IP-block itself. > > The clock framework can handle orphans, so just leave these out for now > please. you're right, done. > >> + >> + xin24m: oscillator { >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "xin24m"; >> + #clock-cells = <0>; >> + }; >> + >> + cru: clock-controller@110e0000 { >> + compatible = "rockchip,rk3228-cru"; >> + reg = <0x110e0000 0x1000>; >> + rockchip,grf = <&grf>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + assigned-clocks = <&cru PLL_GPLL>; >> + assigned-clock-rates = <594000000>; >> + }; >> + >> + gic: interrupt-controller@32010000 { > please order by register address, so gic should move quite > a bit lower. done. >> + compatible = "arm,gic-400"; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + >> + reg = <0x32011000 0x1000>, >> + <0x32012000 0x1000>; > please also provide the vgic registers and interrupt. done. > >> + }; >> + >> + grf: syscon@11000000 { >> + compatible = "syscon"; >> + reg = <0x11000000 0x1000>; >> + }; >> + >> + timer: timer@110c0000 { >> + compatible = "rockchip,rk3288-timer"; >> + reg = <0x110c0000 0x20>; >> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&xin24m>, <&cru PCLK_TIMER>; >> + clock-names = "timer", "pclk"; >> + }; >> + >> + emmc: dwmmc@30020000 { >> + compatible = "rockchip,rk3288-dw-mshc"; >> + clock-frequency = <37500000>; >> + clock-freq-min-max = <400000 37500000>; >> + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, >> + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; >> + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; >> + fifo-depth = <0x100>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x30020000 0x4000>; >> + broken-cd; >> + bus-width = <8>; >> + cap-mmc-highspeed; >> + mmc-ddr-1_8v; >> + disable-wp; >> + non-removable; >> + num-slots = <1>; >> + default-sample-phase = <158>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; > please separate board and core properties. > broken-cd, cap-*, mmc-ddr-1_8v, disable-wp, non-removable > are per-board properties as they depend on what is connected to > the controller. done. >> + status = "disabled"; >> + }; >> + >> + pwm0: pwm@110b0000 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0000 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm0_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm1: pwm@110b0010 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0010 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm1_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm2: pwm@110b0020 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0020 0x10>; >> + #pwm-cells = <3>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm2_pin>; >> + status = "disabled"; >> + }; >> + >> + pwm3: pwm@110b0030 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0030 0x10>; >> + #pwm-cells = <2>; >> + clocks = <&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pwm3_pin>; >> + status = "disabled"; >> + }; >> + >> + uart0: serial@11010000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11010000 0x100>; >> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; >> + status = "disabled"; >> + }; >> + >> + uart1: serial@11020000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11020000 0x100>; >> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart1_xfer>; >> + status = "disabled"; >> + }; >> + >> + uart2: serial@11030000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11030000 0x100>; >> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + clock-frequency = <24000000>; >> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart2_xfer>; >> + status = "disabled"; >> + }; >> + >> + >> + pinctrl: pinctrl { >> + compatible = "rockchip,rk3228-pinctrl"; >> + rockchip,grf = <&grf>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + gpio0: gpio0@11110000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11110000 0x100>; >> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO0>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio1: gpio1@11120000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11120000 0x100>; >> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO1>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio2: gpio2@11130000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11130000 0x100>; >> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO2>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio3: gpio3@11140000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11140000 0x100>; >> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cru PCLK_GPIO3>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + pcfg_pull_up: pcfg-pull-up { >> + bias-pull-up; >> + }; >> + >> + pcfg_pull_down: pcfg-pull-down { >> + bias-pull-down; >> + }; >> + >> + pcfg_pull_none: pcfg-pull-none { >> + bias-disable; >> + }; >> + >> + emmc { >> + emmc_clk: emmc-clk { >> + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + emmc_cmd: emmc-cmd { >> + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + emmc_bus8: emmc-bus8 { >> + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, >> + <1 25 RK_FUNC_2 &pcfg_pull_none>, >> + <1 26 RK_FUNC_2 &pcfg_pull_none>, >> + <1 27 RK_FUNC_2 &pcfg_pull_none>, >> + <1 28 RK_FUNC_2 &pcfg_pull_none>, >> + <1 29 RK_FUNC_2 &pcfg_pull_none>, >> + <1 30 RK_FUNC_2 &pcfg_pull_none>, >> + <1 31 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm0 { >> + pwm0_pin: pwm0-pin { >> + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm1 { >> + pwm1_pin: pwm1-pin { >> + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm2 { >> + pwm2_pin: pwm2-pin { >> + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm3 { >> + pwm3_pin: pwm3-pin { >> + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart0 { >> + uart0_xfer: uart0-xfer { >> + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, >> + <2 27 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart0_cts: uart0-cts { >> + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart0_rts: uart0-rts { >> + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart1 { >> + uart1_xfer: uart1-xfer { >> + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, >> + <1 10 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart1_cts: uart1-cts { >> + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart1_rts: uart1-rts { >> + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + >> + uart2 { >> + uart2_xfer: uart2-xfer { >> + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, >> + <1 19 RK_FUNC_2 &pcfg_pull_none>; >> + }; >> + >> + uart2_cts: uart2-cts { >> + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + >> + uart2_rts: uart2-rts { >> + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; >> + }; >> + }; >> + }; >> +}; >> > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-11 10:12 ` Heiko Stübner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stübner @ 2015-12-11 10:12 UTC (permalink / raw) To: Jeffy Chen Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Jeffy, Am Freitag, 11. Dezember 2015, 09:53:59 schrieb Jeffy Chen: > On 2015-12-10 8:32, Heiko Stuebner wrote: > > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: > >> Initial release for rk3228 shared dtsi. > >> > >> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > >> --- > >> > >> arch/arm/boot/dts/rk3228.dtsi | 478 > >> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 > >> insertions(+) > >> create mode 100644 arch/arm/boot/dts/rk3228.dtsi > >> > >> diff --git a/arch/arm/boot/dts/rk3228.dtsi > >> b/arch/arm/boot/dts/rk3228.dtsi > >> new file mode 100644 > >> index 0000000..d6b3e40 > >> --- /dev/null > >> +++ b/arch/arm/boot/dts/rk3228.dtsi > >> @@ -0,0 +1,478 @@ > >> +/* > >> + * This file is dual-licensed: you can use it either under the terms > >> + * of the GPL or the X11 license, at your option. Note that this dual > >> + * licensing only applies to this file, and not this project as a > >> + * whole. > >> + * > >> + * a) This file is free software; you can redistribute it and/or > >> + * modify it under the terms of the GNU General Public License as > >> + * published by the Free Software Foundation; either version 2 of > >> the > >> + * License, or (at your option) any later version. > >> + * > >> + * This file is distributed in the hope that it will be useful, > >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> + * GNU General Public License for more details. > >> + * > >> + * Or, alternatively, > >> + * > >> + * b) Permission is hereby granted, free of charge, to any person > >> + * obtaining a copy of this software and associated documentation > >> + * files (the "Software"), to deal in the Software without > >> + * restriction, including without limitation the rights to use, > >> + * copy, modify, merge, publish, distribute, sublicense, and/or > >> + * sell copies of the Software, and to permit persons to whom the > >> + * Software is furnished to do so, subject to the following > >> + * conditions: > >> + * > >> + * The above copyright notice and this permission notice shall be > >> + * included in all copies or substantial portions of the Software. > >> + * > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > >> + * OTHER DEALINGS IN THE SOFTWARE. > >> + */ > >> + > >> +#include <dt-bindings/gpio/gpio.h> > >> +#include <dt-bindings/interrupt-controller/irq.h> > >> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >> +#include <dt-bindings/pinctrl/rockchip.h> > >> +#include <dt-bindings/clock/rk3228-cru.h> > >> +#include "skeleton.dtsi" > >> + > >> +/ { > >> + compatible = "rockchip,rk3228"; > >> + > >> + interrupt-parent = <&gic>; > >> + > >> + aliases { > >> + serial0 = &uart0; > >> + serial1 = &uart1; > >> + serial2 = &uart2; > >> + }; > >> + > >> + memory { > >> + device_type = "memory"; > >> + reg = <0x60000000 0x40000000>; > >> + }; > > > > The amount of memory is a property of the board > > done. > > >> + > >> + cpus { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > > > > no enable-method? > > > > As the rk3228 also does not have a pmu, does the newly created > > "rockchip,rk3036-smp" work for you? > > unlucky, that doesn't work...and our 3.10 kernel is using psci for > rk3228's smp ops, maybe i should check that too, but i know nothing > about psci for now :( Using PSCI on more rockchip socs will make the ARM people very happy ;-) . So definitly no argument from me against it. I guess you should only need the enable-method and psci node you should already have in your 3.10 dts, to actually enable it. cpu@xxx { enable-method = "psci"; }; psci { compatible = "arm,psci-0.2"; ... }; But we can of course add that in a later patch as well. Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-11 10:12 ` Heiko Stübner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stübner @ 2015-12-11 10:12 UTC (permalink / raw) To: linux-arm-kernel Hi Jeffy, Am Freitag, 11. Dezember 2015, 09:53:59 schrieb Jeffy Chen: > On 2015-12-10 8:32, Heiko Stuebner wrote: > > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: > >> Initial release for rk3228 shared dtsi. > >> > >> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > >> --- > >> > >> arch/arm/boot/dts/rk3228.dtsi | 478 > >> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 > >> insertions(+) > >> create mode 100644 arch/arm/boot/dts/rk3228.dtsi > >> > >> diff --git a/arch/arm/boot/dts/rk3228.dtsi > >> b/arch/arm/boot/dts/rk3228.dtsi > >> new file mode 100644 > >> index 0000000..d6b3e40 > >> --- /dev/null > >> +++ b/arch/arm/boot/dts/rk3228.dtsi > >> @@ -0,0 +1,478 @@ > >> +/* > >> + * This file is dual-licensed: you can use it either under the terms > >> + * of the GPL or the X11 license, at your option. Note that this dual > >> + * licensing only applies to this file, and not this project as a > >> + * whole. > >> + * > >> + * a) This file is free software; you can redistribute it and/or > >> + * modify it under the terms of the GNU General Public License as > >> + * published by the Free Software Foundation; either version 2 of > >> the > >> + * License, or (at your option) any later version. > >> + * > >> + * This file is distributed in the hope that it will be useful, > >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> + * GNU General Public License for more details. > >> + * > >> + * Or, alternatively, > >> + * > >> + * b) Permission is hereby granted, free of charge, to any person > >> + * obtaining a copy of this software and associated documentation > >> + * files (the "Software"), to deal in the Software without > >> + * restriction, including without limitation the rights to use, > >> + * copy, modify, merge, publish, distribute, sublicense, and/or > >> + * sell copies of the Software, and to permit persons to whom the > >> + * Software is furnished to do so, subject to the following > >> + * conditions: > >> + * > >> + * The above copyright notice and this permission notice shall be > >> + * included in all copies or substantial portions of the Software. > >> + * > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > >> + * OTHER DEALINGS IN THE SOFTWARE. > >> + */ > >> + > >> +#include <dt-bindings/gpio/gpio.h> > >> +#include <dt-bindings/interrupt-controller/irq.h> > >> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >> +#include <dt-bindings/pinctrl/rockchip.h> > >> +#include <dt-bindings/clock/rk3228-cru.h> > >> +#include "skeleton.dtsi" > >> + > >> +/ { > >> + compatible = "rockchip,rk3228"; > >> + > >> + interrupt-parent = <&gic>; > >> + > >> + aliases { > >> + serial0 = &uart0; > >> + serial1 = &uart1; > >> + serial2 = &uart2; > >> + }; > >> + > >> + memory { > >> + device_type = "memory"; > >> + reg = <0x60000000 0x40000000>; > >> + }; > > > > The amount of memory is a property of the board > > done. > > >> + > >> + cpus { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > > > > no enable-method? > > > > As the rk3228 also does not have a pmu, does the newly created > > "rockchip,rk3036-smp" work for you? > > unlucky, that doesn't work...and our 3.10 kernel is using psci for > rk3228's smp ops, maybe i should check that too, but i know nothing > about psci for now :( Using PSCI on more rockchip socs will make the ARM people very happy ;-) . So definitly no argument from me against it. I guess you should only need the enable-method and psci node you should already have in your 3.10 dts, to actually enable it. cpu at xxx { enable-method = "psci"; }; psci { compatible = "arm,psci-0.2"; ... }; But we can of course add that in a later patch as well. Heiko ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-11 10:12 ` Heiko Stübner 0 siblings, 0 replies; 58+ messages in thread From: Heiko Stübner @ 2015-12-11 10:12 UTC (permalink / raw) To: Jeffy Chen Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Jeffy, Am Freitag, 11. Dezember 2015, 09:53:59 schrieb Jeffy Chen: > On 2015-12-10 8:32, Heiko Stuebner wrote: > > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: > >> Initial release for rk3228 shared dtsi. > >> > >> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > >> --- > >> > >> arch/arm/boot/dts/rk3228.dtsi | 478 > >> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 > >> insertions(+) > >> create mode 100644 arch/arm/boot/dts/rk3228.dtsi > >> > >> diff --git a/arch/arm/boot/dts/rk3228.dtsi > >> b/arch/arm/boot/dts/rk3228.dtsi > >> new file mode 100644 > >> index 0000000..d6b3e40 > >> --- /dev/null > >> +++ b/arch/arm/boot/dts/rk3228.dtsi > >> @@ -0,0 +1,478 @@ > >> +/* > >> + * This file is dual-licensed: you can use it either under the terms > >> + * of the GPL or the X11 license, at your option. Note that this dual > >> + * licensing only applies to this file, and not this project as a > >> + * whole. > >> + * > >> + * a) This file is free software; you can redistribute it and/or > >> + * modify it under the terms of the GNU General Public License as > >> + * published by the Free Software Foundation; either version 2 of > >> the > >> + * License, or (at your option) any later version. > >> + * > >> + * This file is distributed in the hope that it will be useful, > >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> + * GNU General Public License for more details. > >> + * > >> + * Or, alternatively, > >> + * > >> + * b) Permission is hereby granted, free of charge, to any person > >> + * obtaining a copy of this software and associated documentation > >> + * files (the "Software"), to deal in the Software without > >> + * restriction, including without limitation the rights to use, > >> + * copy, modify, merge, publish, distribute, sublicense, and/or > >> + * sell copies of the Software, and to permit persons to whom the > >> + * Software is furnished to do so, subject to the following > >> + * conditions: > >> + * > >> + * The above copyright notice and this permission notice shall be > >> + * included in all copies or substantial portions of the Software. > >> + * > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > >> + * OTHER DEALINGS IN THE SOFTWARE. > >> + */ > >> + > >> +#include <dt-bindings/gpio/gpio.h> > >> +#include <dt-bindings/interrupt-controller/irq.h> > >> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >> +#include <dt-bindings/pinctrl/rockchip.h> > >> +#include <dt-bindings/clock/rk3228-cru.h> > >> +#include "skeleton.dtsi" > >> + > >> +/ { > >> + compatible = "rockchip,rk3228"; > >> + > >> + interrupt-parent = <&gic>; > >> + > >> + aliases { > >> + serial0 = &uart0; > >> + serial1 = &uart1; > >> + serial2 = &uart2; > >> + }; > >> + > >> + memory { > >> + device_type = "memory"; > >> + reg = <0x60000000 0x40000000>; > >> + }; > > > > The amount of memory is a property of the board > > done. > > >> + > >> + cpus { > >> + #address-cells = <1>; > >> + #size-cells = <0>; > > > > no enable-method? > > > > As the rk3228 also does not have a pmu, does the newly created > > "rockchip,rk3036-smp" work for you? > > unlucky, that doesn't work...and our 3.10 kernel is using psci for > rk3228's smp ops, maybe i should check that too, but i know nothing > about psci for now :( Using PSCI on more rockchip socs will make the ARM people very happy ;-) . So definitly no argument from me against it. I guess you should only need the enable-method and psci node you should already have in your 3.10 dts, to actually enable it. cpu@xxx { enable-method = "psci"; }; psci { compatible = "arm,psci-0.2"; ... }; But we can of course add that in a later patch as well. Heiko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi 2015-12-11 10:12 ` Heiko Stübner (?) @ 2015-12-12 2:34 ` Jeffy Chen -1 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-12 2:34 UTC (permalink / raw) To: Heiko Stübner Cc: linux, linux-arm-kernel, linux-rockchip, linux-kernel, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Heiko, On 2015-12-11 18:12, Heiko Stübner wrote: > Hi Jeffy, > > Am Freitag, 11. Dezember 2015, 09:53:59 schrieb Jeffy Chen: >> On 2015-12-10 8:32, Heiko Stuebner wrote: >>> Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >>>> Initial release for rk3228 shared dtsi. >>>> >>>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >>>> --- >>>> >>>> arch/arm/boot/dts/rk3228.dtsi | 478 >>>> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 >>>> insertions(+) >>>> create mode 100644 arch/arm/boot/dts/rk3228.dtsi >>>> >>>> diff --git a/arch/arm/boot/dts/rk3228.dtsi >>>> b/arch/arm/boot/dts/rk3228.dtsi >>>> new file mode 100644 >>>> index 0000000..d6b3e40 >>>> --- /dev/null >>>> +++ b/arch/arm/boot/dts/rk3228.dtsi >>>> @@ -0,0 +1,478 @@ >>>> +/* >>>> + * This file is dual-licensed: you can use it either under the terms >>>> + * of the GPL or the X11 license, at your option. Note that this dual >>>> + * licensing only applies to this file, and not this project as a >>>> + * whole. >>>> + * >>>> + * a) This file is free software; you can redistribute it and/or >>>> + * modify it under the terms of the GNU General Public License as >>>> + * published by the Free Software Foundation; either version 2 of >>>> the >>>> + * License, or (at your option) any later version. >>>> + * >>>> + * This file is distributed in the hope that it will be useful, >>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>>> + * GNU General Public License for more details. >>>> + * >>>> + * Or, alternatively, >>>> + * >>>> + * b) Permission is hereby granted, free of charge, to any person >>>> + * obtaining a copy of this software and associated documentation >>>> + * files (the "Software"), to deal in the Software without >>>> + * restriction, including without limitation the rights to use, >>>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>>> + * sell copies of the Software, and to permit persons to whom the >>>> + * Software is furnished to do so, subject to the following >>>> + * conditions: >>>> + * >>>> + * The above copyright notice and this permission notice shall be >>>> + * included in all copies or substantial portions of the Software. >>>> + * >>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>>> + * OTHER DEALINGS IN THE SOFTWARE. >>>> + */ >>>> + >>>> +#include <dt-bindings/gpio/gpio.h> >>>> +#include <dt-bindings/interrupt-controller/irq.h> >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> +#include <dt-bindings/pinctrl/rockchip.h> >>>> +#include <dt-bindings/clock/rk3228-cru.h> >>>> +#include "skeleton.dtsi" >>>> + >>>> +/ { >>>> + compatible = "rockchip,rk3228"; >>>> + >>>> + interrupt-parent = <&gic>; >>>> + >>>> + aliases { >>>> + serial0 = &uart0; >>>> + serial1 = &uart1; >>>> + serial2 = &uart2; >>>> + }; >>>> + >>>> + memory { >>>> + device_type = "memory"; >>>> + reg = <0x60000000 0x40000000>; >>>> + }; >>> The amount of memory is a property of the board >> done. >> >>>> + >>>> + cpus { >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>> no enable-method? >>> >>> As the rk3228 also does not have a pmu, does the newly created >>> "rockchip,rk3036-smp" work for you? >> unlucky, that doesn't work...and our 3.10 kernel is using psci for >> rk3228's smp ops, maybe i should check that too, but i know nothing >> about psci for now :( > Using PSCI on more rockchip socs will make the ARM people very happy ;-) . > > So definitly no argument from me against it. I guess you should only need the > enable-method and psci node you should already have in your 3.10 dts, to > actually enable it. > > cpu@xxx { > enable-method = "psci"; > }; > > psci { > compatible = "arm,psci-0.2"; > ... > }; > > > But we can of course add that in a later patch as well. > > > Heiko > yes, you're right~ after added psci node and enabled CONFIG_ARM_PSCI, it could bring up all cpus : [ 0.090371] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.091018] Setting up static identity map for 0x60100000 - 0x60100058 [ 0.095260] CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 [ 0.096648] CPU2: thread -1, cpu 2, socket 15, mpidr 80000f02 [ 0.098070] CPU3: thread -1, cpu 3, socket 15, mpidr 80000f03 [ 0.098228] Brought up 4 CPUs [ 0.100145] SMP: Total of 4 processors activated (192.00 BogoMIPS). [ 0.100732] CPU: All CPU(s) started in SVC mode. patch coming :) ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-12 2:34 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-12 2:34 UTC (permalink / raw) To: linux-arm-kernel Hi Heiko, On 2015-12-11 18:12, Heiko St?bner wrote: > Hi Jeffy, > > Am Freitag, 11. Dezember 2015, 09:53:59 schrieb Jeffy Chen: >> On 2015-12-10 8:32, Heiko Stuebner wrote: >>> Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >>>> Initial release for rk3228 shared dtsi. >>>> >>>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >>>> --- >>>> >>>> arch/arm/boot/dts/rk3228.dtsi | 478 >>>> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 >>>> insertions(+) >>>> create mode 100644 arch/arm/boot/dts/rk3228.dtsi >>>> >>>> diff --git a/arch/arm/boot/dts/rk3228.dtsi >>>> b/arch/arm/boot/dts/rk3228.dtsi >>>> new file mode 100644 >>>> index 0000000..d6b3e40 >>>> --- /dev/null >>>> +++ b/arch/arm/boot/dts/rk3228.dtsi >>>> @@ -0,0 +1,478 @@ >>>> +/* >>>> + * This file is dual-licensed: you can use it either under the terms >>>> + * of the GPL or the X11 license, at your option. Note that this dual >>>> + * licensing only applies to this file, and not this project as a >>>> + * whole. >>>> + * >>>> + * a) This file is free software; you can redistribute it and/or >>>> + * modify it under the terms of the GNU General Public License as >>>> + * published by the Free Software Foundation; either version 2 of >>>> the >>>> + * License, or (at your option) any later version. >>>> + * >>>> + * This file is distributed in the hope that it will be useful, >>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>>> + * GNU General Public License for more details. >>>> + * >>>> + * Or, alternatively, >>>> + * >>>> + * b) Permission is hereby granted, free of charge, to any person >>>> + * obtaining a copy of this software and associated documentation >>>> + * files (the "Software"), to deal in the Software without >>>> + * restriction, including without limitation the rights to use, >>>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>>> + * sell copies of the Software, and to permit persons to whom the >>>> + * Software is furnished to do so, subject to the following >>>> + * conditions: >>>> + * >>>> + * The above copyright notice and this permission notice shall be >>>> + * included in all copies or substantial portions of the Software. >>>> + * >>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>>> + * OTHER DEALINGS IN THE SOFTWARE. >>>> + */ >>>> + >>>> +#include <dt-bindings/gpio/gpio.h> >>>> +#include <dt-bindings/interrupt-controller/irq.h> >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> +#include <dt-bindings/pinctrl/rockchip.h> >>>> +#include <dt-bindings/clock/rk3228-cru.h> >>>> +#include "skeleton.dtsi" >>>> + >>>> +/ { >>>> + compatible = "rockchip,rk3228"; >>>> + >>>> + interrupt-parent = <&gic>; >>>> + >>>> + aliases { >>>> + serial0 = &uart0; >>>> + serial1 = &uart1; >>>> + serial2 = &uart2; >>>> + }; >>>> + >>>> + memory { >>>> + device_type = "memory"; >>>> + reg = <0x60000000 0x40000000>; >>>> + }; >>> The amount of memory is a property of the board >> done. >> >>>> + >>>> + cpus { >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>> no enable-method? >>> >>> As the rk3228 also does not have a pmu, does the newly created >>> "rockchip,rk3036-smp" work for you? >> unlucky, that doesn't work...and our 3.10 kernel is using psci for >> rk3228's smp ops, maybe i should check that too, but i know nothing >> about psci for now :( > Using PSCI on more rockchip socs will make the ARM people very happy ;-) . > > So definitly no argument from me against it. I guess you should only need the > enable-method and psci node you should already have in your 3.10 dts, to > actually enable it. > > cpu at xxx { > enable-method = "psci"; > }; > > psci { > compatible = "arm,psci-0.2"; > ... > }; > > > But we can of course add that in a later patch as well. > > > Heiko > yes, you're right~ after added psci node and enabled CONFIG_ARM_PSCI, it could bring up all cpus : [ 0.090371] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.091018] Setting up static identity map for 0x60100000 - 0x60100058 [ 0.095260] CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 [ 0.096648] CPU2: thread -1, cpu 2, socket 15, mpidr 80000f02 [ 0.098070] CPU3: thread -1, cpu 3, socket 15, mpidr 80000f03 [ 0.098228] Brought up 4 CPUs [ 0.100145] SMP: Total of 4 processors activated (192.00 BogoMIPS). [ 0.100732] CPU: All CPU(s) started in SVC mode. patch coming :) ^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi @ 2015-12-12 2:34 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-12 2:34 UTC (permalink / raw) To: Heiko Stübner Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Hi Heiko, On 2015-12-11 18:12, Heiko Stübner wrote: > Hi Jeffy, > > Am Freitag, 11. Dezember 2015, 09:53:59 schrieb Jeffy Chen: >> On 2015-12-10 8:32, Heiko Stuebner wrote: >>> Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >>>> Initial release for rk3228 shared dtsi. >>>> >>>> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >>>> --- >>>> >>>> arch/arm/boot/dts/rk3228.dtsi | 478 >>>> ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 >>>> insertions(+) >>>> create mode 100644 arch/arm/boot/dts/rk3228.dtsi >>>> >>>> diff --git a/arch/arm/boot/dts/rk3228.dtsi >>>> b/arch/arm/boot/dts/rk3228.dtsi >>>> new file mode 100644 >>>> index 0000000..d6b3e40 >>>> --- /dev/null >>>> +++ b/arch/arm/boot/dts/rk3228.dtsi >>>> @@ -0,0 +1,478 @@ >>>> +/* >>>> + * This file is dual-licensed: you can use it either under the terms >>>> + * of the GPL or the X11 license, at your option. Note that this dual >>>> + * licensing only applies to this file, and not this project as a >>>> + * whole. >>>> + * >>>> + * a) This file is free software; you can redistribute it and/or >>>> + * modify it under the terms of the GNU General Public License as >>>> + * published by the Free Software Foundation; either version 2 of >>>> the >>>> + * License, or (at your option) any later version. >>>> + * >>>> + * This file is distributed in the hope that it will be useful, >>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>>> + * GNU General Public License for more details. >>>> + * >>>> + * Or, alternatively, >>>> + * >>>> + * b) Permission is hereby granted, free of charge, to any person >>>> + * obtaining a copy of this software and associated documentation >>>> + * files (the "Software"), to deal in the Software without >>>> + * restriction, including without limitation the rights to use, >>>> + * copy, modify, merge, publish, distribute, sublicense, and/or >>>> + * sell copies of the Software, and to permit persons to whom the >>>> + * Software is furnished to do so, subject to the following >>>> + * conditions: >>>> + * >>>> + * The above copyright notice and this permission notice shall be >>>> + * included in all copies or substantial portions of the Software. >>>> + * >>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>>> + * OTHER DEALINGS IN THE SOFTWARE. >>>> + */ >>>> + >>>> +#include <dt-bindings/gpio/gpio.h> >>>> +#include <dt-bindings/interrupt-controller/irq.h> >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> +#include <dt-bindings/pinctrl/rockchip.h> >>>> +#include <dt-bindings/clock/rk3228-cru.h> >>>> +#include "skeleton.dtsi" >>>> + >>>> +/ { >>>> + compatible = "rockchip,rk3228"; >>>> + >>>> + interrupt-parent = <&gic>; >>>> + >>>> + aliases { >>>> + serial0 = &uart0; >>>> + serial1 = &uart1; >>>> + serial2 = &uart2; >>>> + }; >>>> + >>>> + memory { >>>> + device_type = "memory"; >>>> + reg = <0x60000000 0x40000000>; >>>> + }; >>> The amount of memory is a property of the board >> done. >> >>>> + >>>> + cpus { >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>> no enable-method? >>> >>> As the rk3228 also does not have a pmu, does the newly created >>> "rockchip,rk3036-smp" work for you? >> unlucky, that doesn't work...and our 3.10 kernel is using psci for >> rk3228's smp ops, maybe i should check that too, but i know nothing >> about psci for now :( > Using PSCI on more rockchip socs will make the ARM people very happy ;-) . > > So definitly no argument from me against it. I guess you should only need the > enable-method and psci node you should already have in your 3.10 dts, to > actually enable it. > > cpu@xxx { > enable-method = "psci"; > }; > > psci { > compatible = "arm,psci-0.2"; > ... > }; > > > But we can of course add that in a later patch as well. > > > Heiko > yes, you're right~ after added psci node and enabled CONFIG_ARM_PSCI, it could bring up all cpus : [ 0.090371] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 [ 0.091018] Setting up static identity map for 0x60100000 - 0x60100058 [ 0.095260] CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 [ 0.096648] CPU2: thread -1, cpu 2, socket 15, mpidr 80000f02 [ 0.098070] CPU3: thread -1, cpu 3, socket 15, mpidr 80000f03 [ 0.098228] Brought up 4 CPUs [ 0.100145] SMP: Total of 4 processors activated (192.00 BogoMIPS). [ 0.100732] CPU: All CPU(s) started in SVC mode. patch coming :) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v1 8/8] ARM: dts: rockchip: add rk3228-evb board @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko, linux, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Jeffy Chen, devicetree, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Initial release for rk3228 sdk board. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3228-evb.dts | 56 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228-evb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2d8b9e0..0223846 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -521,6 +521,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-marsboard.dtb \ rk3066a-rayeager.dtb \ rk3188-radxarock.dtb \ + rk3228-evb.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts new file mode 100644 index 0000000..eb4621a --- /dev/null +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -0,0 +1,56 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3228.dtsi" + +/ { + model = "Rockchip RK3228 Evaluation board"; + compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +}; + +&emmc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 8/8] ARM: dts: rockchip: add rk3228-evb board @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: linux-arm-kernel Initial release for rk3228 sdk board. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3228-evb.dts | 56 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228-evb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2d8b9e0..0223846 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -521,6 +521,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-marsboard.dtb \ rk3066a-rayeager.dtb \ rk3188-radxarock.dtb \ + rk3228-evb.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts new file mode 100644 index 0000000..eb4621a --- /dev/null +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -0,0 +1,56 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3228.dtsi" + +/ { + model = "Rockchip RK3228 Evaluation board"; + compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +}; + +&emmc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- 2.1.4 ^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v1 8/8] ARM: dts: rockchip: add rk3228-evb board @ 2015-12-09 9:04 ` Jeffy Chen 0 siblings, 0 replies; 58+ messages in thread From: Jeffy Chen @ 2015-12-09 9:04 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: Jeffy Chen, devicetree-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland Initial release for rk3228 sdk board. Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3228-evb.dts | 56 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228-evb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2d8b9e0..0223846 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -521,6 +521,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-marsboard.dtb \ rk3066a-rayeager.dtb \ rk3188-radxarock.dtb \ + rk3228-evb.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts new file mode 100644 index 0000000..eb4621a --- /dev/null +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -0,0 +1,56 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3228.dtsi" + +/ { + model = "Rockchip RK3228 Evaluation board"; + compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +}; + +&emmc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 58+ messages in thread
end of thread, other threads:[~2015-12-12 2:34 UTC | newest] Thread overview: 58+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-12-09 9:04 [PATCH v1 0/8] This serial of patches add dts/pinctrl/clock-tree/doc for rk3228 Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 9:04 ` [PATCH v1 1/8] pinctrl: rockchip: add support for the rk3228 Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 11:30 ` Heiko Stübner 2015-12-09 11:30 ` Heiko Stübner 2015-12-09 20:09 ` Rob Herring 2015-12-09 20:09 ` Rob Herring 2015-12-11 18:10 ` Linus Walleij 2015-12-11 18:10 ` Linus Walleij 2015-12-09 9:04 ` [PATCH v1 2/8] clk: rockchip: add dt-binding header for rk3228 Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 23:17 ` Heiko Stuebner 2015-12-09 23:17 ` Heiko Stuebner 2015-12-09 23:17 ` Heiko Stuebner 2015-12-09 9:04 ` [PATCH v1 3/8] rockchip: add clock controller " Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-10 0:19 ` Heiko Stuebner 2015-12-10 0:19 ` Heiko Stuebner 2015-12-11 1:46 ` Jeffy Chen 2015-12-11 1:46 ` Jeffy Chen 2015-12-09 9:04 ` [PATCH v1 4/8] dt-bindings: add documentation of rk3228 clock controller Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 20:12 ` Rob Herring 2015-12-09 20:12 ` Rob Herring 2015-12-09 23:11 ` Heiko Stuebner 2015-12-09 23:11 ` Heiko Stuebner 2015-12-09 23:17 ` Heiko Stuebner 2015-12-09 23:17 ` Heiko Stuebner 2015-12-09 23:17 ` Heiko Stuebner 2015-12-09 9:04 ` [PATCH v1 5/8] clk: rockchip: allow more than 2 parents for cpuclk Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 21:35 ` Heiko Stuebner 2015-12-09 21:35 ` Heiko Stuebner 2015-12-09 9:04 ` [PATCH v1 6/8] ARM: rockchip: enable support for RK3228 SoCs Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 21:27 ` Heiko Stuebner 2015-12-09 21:27 ` Heiko Stuebner 2015-12-09 9:04 ` [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-10 0:32 ` Heiko Stuebner 2015-12-10 0:32 ` Heiko Stuebner 2015-12-11 1:53 ` Jeffy Chen 2015-12-11 1:53 ` Jeffy Chen 2015-12-11 1:53 ` Jeffy Chen 2015-12-11 10:12 ` Heiko Stübner 2015-12-11 10:12 ` Heiko Stübner 2015-12-11 10:12 ` Heiko Stübner 2015-12-12 2:34 ` Jeffy Chen 2015-12-12 2:34 ` Jeffy Chen 2015-12-12 2:34 ` Jeffy Chen 2015-12-09 9:04 ` [PATCH v1 8/8] ARM: dts: rockchip: add rk3228-evb board Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen 2015-12-09 9:04 ` Jeffy Chen
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