[PATCH v3 0/7] ARM: hisi: Add initial support including clock driver for Hi3519 soc.

[PATCH v3 0/7] ARM: hisi: Add initial support including clock driver for Hi3519 soc.

[Jiancheng Xue]

Hello,

Hi3519 soc is mainly used for ip camera and sport DV solutions. This patchset adds initial support
for Hi3519 soc. It includes clock driver, arch configuration, debug uart configuration and device tree.
It has been tested on hi3519 reference board.

Spi-nor flash driver and other peripheral drivers will be submitted later.

Any comments will be appreciated!

Thanks!

Change Log
----------
v3:
-Rebase to v4.4-rc4
-Adjust according to Arnd's comments
-Remove ARCH_HI3519, using ARCH_HISI directly

v2:
-Rebase to v4.4-rc3
-Put dt-binding doc and header file in a separate patch.
-Delete unused clocks definitions.
-Adjust the ARCH_xxx order in Kconfig file
-Rename ARCH_HI3xxx to ARCH_36xx

Jiancheng Xue (7):
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: add dt-binding document for Hi3519 CRG
  ARM: hisi: add dt_machine definition for Hi3519
  ARM: config: hisi: enable CONFIG_RESET_CONTROLLER
  ARM: debug: add hi3519 debug uart
  mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl
  ARM: dts: add dts files for Hi3519

 .../devicetree/bindings/clock/hi3519-crg.txt       |  46 +++++++
 Documentation/devicetree/bindings/mfd/hi3519.txt   |  14 ++
 arch/arm/Kconfig.debug                             |  10 ++
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/hi3519-demb.dts                  |  42 ++++++
 arch/arm/boot/dts/hi3519.dtsi                      | 142 ++++++++++++++++++++
 arch/arm/configs/hisi_defconfig                    |   1 +
 arch/arm/mach-hisi/hisilicon.c                     |   9 ++
 drivers/clk/hisilicon/Kconfig                      |   7 +
 drivers/clk/hisilicon/Makefile                     |   2 +
 drivers/clk/hisilicon/clk-hi3519.c                 |  95 +++++++++++++
 drivers/clk/hisilicon/reset.c                      | 149 +++++++++++++++++++++
 drivers/clk/hisilicon/reset.h                      |  32 +++++
 include/dt-bindings/clock/hi3519-clock.h           |  43 ++++++
 14 files changed, 594 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
 create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt
 create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
 create mode 100644 arch/arm/boot/dts/hi3519.dtsi
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

-- 
1.9.1

[PATCH v3 0/7] ARM: hisi: Add initial support including clock driver for Hi3519 soc.

[Jiancheng Xue]

Hello,

Hi3519 soc is mainly used for ip camera and sport DV solutions. This patchset adds initial support
for Hi3519 soc. It includes clock driver, arch configuration, debug uart configuration and device tree.
It has been tested on hi3519 reference board.

Spi-nor flash driver and other peripheral drivers will be submitted later.

Any comments will be appreciated!

Thanks!

Change Log
----------
v3:
-Rebase to v4.4-rc4
-Adjust according to Arnd's comments
-Remove ARCH_HI3519, using ARCH_HISI directly

v2:
-Rebase to v4.4-rc3
-Put dt-binding doc and header file in a separate patch.
-Delete unused clocks definitions.
-Adjust the ARCH_xxx order in Kconfig file
-Rename ARCH_HI3xxx to ARCH_36xx

Jiancheng Xue (7):
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: add dt-binding document for Hi3519 CRG
  ARM: hisi: add dt_machine definition for Hi3519
  ARM: config: hisi: enable CONFIG_RESET_CONTROLLER
  ARM: debug: add hi3519 debug uart
  mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl
  ARM: dts: add dts files for Hi3519

 .../devicetree/bindings/clock/hi3519-crg.txt       |  46 +++++++
 Documentation/devicetree/bindings/mfd/hi3519.txt   |  14 ++
 arch/arm/Kconfig.debug                             |  10 ++
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/hi3519-demb.dts                  |  42 ++++++
 arch/arm/boot/dts/hi3519.dtsi                      | 142 ++++++++++++++++++++
 arch/arm/configs/hisi_defconfig                    |   1 +
 arch/arm/mach-hisi/hisilicon.c                     |   9 ++
 drivers/clk/hisilicon/Kconfig                      |   7 +
 drivers/clk/hisilicon/Makefile                     |   2 +
 drivers/clk/hisilicon/clk-hi3519.c                 |  95 +++++++++++++
 drivers/clk/hisilicon/reset.c                      | 149 +++++++++++++++++++++
 drivers/clk/hisilicon/reset.h                      |  32 +++++
 include/dt-bindings/clock/hi3519-clock.h           |  43 ++++++
 14 files changed, 594 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
 create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt
 create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
 create mode 100644 arch/arm/boot/dts/hi3519.dtsi
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

-- 
1.9.1

[PATCH v3 0/7] ARM: hisi: Add initial support including clock driver for Hi3519 soc.

[Jiancheng Xue]

Hello,

Hi3519 soc is mainly used for ip camera and sport DV solutions. This patchset adds initial support
for Hi3519 soc. It includes clock driver, arch configuration, debug uart configuration and device tree.
It has been tested on hi3519 reference board.

Spi-nor flash driver and other peripheral drivers will be submitted later.

Any comments will be appreciated!

Thanks!

Change Log
----------
v3:
-Rebase to v4.4-rc4
-Adjust according to Arnd's comments
-Remove ARCH_HI3519, using ARCH_HISI directly

v2:
-Rebase to v4.4-rc3
-Put dt-binding doc and header file in a separate patch.
-Delete unused clocks definitions.
-Adjust the ARCH_xxx order in Kconfig file
-Rename ARCH_HI3xxx to ARCH_36xx

Jiancheng Xue (7):
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: add dt-binding document for Hi3519 CRG
  ARM: hisi: add dt_machine definition for Hi3519
  ARM: config: hisi: enable CONFIG_RESET_CONTROLLER
  ARM: debug: add hi3519 debug uart
  mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl
  ARM: dts: add dts files for Hi3519

 .../devicetree/bindings/clock/hi3519-crg.txt       |  46 +++++++
 Documentation/devicetree/bindings/mfd/hi3519.txt   |  14 ++
 arch/arm/Kconfig.debug                             |  10 ++
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/hi3519-demb.dts                  |  42 ++++++
 arch/arm/boot/dts/hi3519.dtsi                      | 142 ++++++++++++++++++++
 arch/arm/configs/hisi_defconfig                    |   1 +
 arch/arm/mach-hisi/hisilicon.c                     |   9 ++
 drivers/clk/hisilicon/Kconfig                      |   7 +
 drivers/clk/hisilicon/Makefile                     |   2 +
 drivers/clk/hisilicon/clk-hi3519.c                 |  95 +++++++++++++
 drivers/clk/hisilicon/reset.c                      | 149 +++++++++++++++++++++
 drivers/clk/hisilicon/reset.h                      |  32 +++++
 include/dt-bindings/clock/hi3519-clock.h           |  43 ++++++
 14 files changed, 594 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
 create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt
 create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
 create mode 100644 arch/arm/boot/dts/hi3519.dtsi
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

-- 
1.9.1

[PATCH v3 1/7] clk: hisilicon: add CRG driver for hi3519 soc

[Jiancheng Xue]

The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 drivers/clk/hisilicon/Kconfig            |   7 ++
 drivers/clk/hisilicon/Makefile           |   2 +
 drivers/clk/hisilicon/clk-hi3519.c       |  95 ++++++++++++++++++++
 drivers/clk/hisilicon/reset.c            | 149 +++++++++++++++++++++++++++++++
 drivers/clk/hisilicon/reset.h            |  32 +++++++
 include/dt-bindings/clock/hi3519-clock.h |  43 +++++++++
 6 files changed, 328 insertions(+)
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index e434854..b6baebf 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_CLK_HI3519
+	tristate "Clock Driver for Hi3519"
+	depends on ARCH_HISI
+	default y
+	help
+	  Build the clock driver for hi3519.
+
 config COMMON_CLK_HI6220
 	bool "Hi6220 Clock Driver"
 	depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 74dba31..3f57b09 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -4,8 +4,10 @@
 
 obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o
 
+obj-$(CONFIG_RESET_CONTROLLER)	+= reset.o
 obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2)	+= clk-hix5hd2.o
 obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o
 obj-$(CONFIG_STUB_CLK_HI6220)	+= clk-hi6220-stub.o
+obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
new file mode 100644
index 0000000..928e848
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/of_address.h>
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "clk.h"
+#include "reset.h"
+
+#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
+#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 2)
+#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 3)
+#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 4)
+#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 5)
+#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 6)
+#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
+#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
+#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
+
+#define HI3519_NR_CLKS	128
+#define HI3519_NR_RSTS	128
+
+static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
+	{ HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
+	{ HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
+	{ HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
+	{ HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
+	{ HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
+	{ HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
+	{ HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
+	{ HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
+	{ HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
+};
+
+static const char *fmc_mux_p[] __initconst = {
+		"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
+	{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+		CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+};
+
+static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
+	/* fmc */
+	{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
+		CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
+	/* uart */
+	{ HI3519_UART0_CLK, "clk_uart0", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
+	{ HI3519_UART1_CLK, "clk_uart1", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
+	{ HI3519_UART2_CLK, "clk_uart2", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
+	{ HI3519_UART3_CLK, "clk_uart3", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
+	{ HI3519_UART4_CLK, "clk_uart4", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
+};
+
+static void __init hi3519_clk_init(struct device_node *np)
+{
+	struct hisi_clock_data *clk_data;
+
+	clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
+	if (!clk_data)
+		return;
+
+	hisi_reset_init(np, HI3519_NR_RSTS);
+
+	hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
+				     ARRAY_SIZE(hi3519_fixed_rate_clks),
+				     clk_data);
+	hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
+					clk_data);
+	hisi_clk_register_gate(hi3519_gate_clks,
+			ARRAY_SIZE(hi3519_gate_clks), clk_data);
+}
+
+CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
new file mode 100644
index 0000000..cf5c32a
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.c
@@ -0,0 +1,149 @@
+/*
+ * Hisilicon Reset Controller driver
+ *
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define	HISI_RESET_BIT_SHIFT	0
+#define	HISI_RESET_BIT_WIDTH	16
+#define	HISI_RESET_OFFSET_SHIFT	16
+#define	HISI_RESET_OFFSET_WIDTH	16
+
+struct hisi_reset_controller {
+	spinlock_t	lock;
+	void __iomem	*membase;
+	struct reset_controller_dev	rcdev;
+};
+
+
+#define to_hisi_reset_controller(rcdev)  \
+	container_of(rcdev, struct hisi_reset_controller, rcdev)
+
+/*31                        16                         0
+ * |---reset_spec->args[0]---|---reset_spec->args[1]---|
+ * |-------reg_offset--------|--------reg_bit----------|
+ */
+static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
+			const struct of_phandle_args *reset_spec)
+{
+	unsigned int offset, bit, id;
+	const __be32 *addr;
+	u64 size;
+
+	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+		return -EINVAL;
+
+	addr = of_get_address(rcdev->of_node, 0, &size, NULL);
+	if (!addr)
+		return -EINVAL;
+
+	if (reset_spec->args[1] >= 32
+		|| reset_spec->args[0] + reset_spec->args[1] / 8 > size)
+		return -EINVAL;
+
+	offset = reset_spec->args[0] & (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = (reset_spec->args[1] & (BIT(HISI_RESET_BIT_WIDTH) - 1));
+	id = offset << HISI_RESET_OFFSET_SHIFT | bit;
+
+	return id;
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned int offset, bit;
+	unsigned long flags;
+	u32 reg;
+
+	offset = id >> HISI_RESET_OFFSET_SHIFT;
+	offset &= (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = id & (BIT(HISI_RESET_BIT_WIDTH) - 1);
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg | BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned int offset, bit;
+	unsigned long flags;
+	u32 reg;
+
+	offset = id >> HISI_RESET_OFFSET_SHIFT;
+	offset &= (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = id & (BIT(HISI_RESET_BIT_WIDTH) - 1);
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg & ~BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+	.assert		= hisi_reset_assert,
+	.deassert	= hisi_reset_deassert,
+};
+
+int __init hisi_reset_init(struct device_node *np,
+					     int nr_rsts)
+{
+	struct hisi_reset_controller *rstc;
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	rstc->membase = of_iomap(np, 0);
+	if (!rstc->membase)
+		return -EINVAL;
+
+	spin_lock_init(&rstc->lock);
+
+	rstc->rcdev.owner = THIS_MODULE;
+	rstc->rcdev.nr_resets = nr_rsts;
+	rstc->rcdev.ops = &hisi_reset_ops;
+	rstc->rcdev.of_node = np;
+	rstc->rcdev.of_reset_n_cells = 2;
+	rstc->rcdev.of_xlate = hisi_reset_of_xlate;
+
+	return reset_controller_register(&rstc->rcdev);
+}
+
diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
new file mode 100644
index 0000000..b04796f
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	__HISI_RESET_H
+#define	__HISI_RESET_H
+
+#include <linux/of.h>
+
+#ifdef CONFIG_RESET_CONTROLLER
+int __init hisi_reset_init(struct device_node *np, int nr_rsts);
+#else
+static inline int __init hisi_reset_init(struct device_node *np, int nr_rsts)
+{
+	return 0;
+}
+#endif
+
+#endif	/* __HISI_RESET_H */
diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 0000000..66a37b1
--- /dev/null
+++ b/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FIXED_3M			1
+#define HI3519_FMC_CLK			2
+#define HI3519_USB2_BUS_CLK		3
+#define HI3519_USB2_PORT_CLK		4
+#define HI3519_USB3_CLK			5
+#define HI3519_ETH_PHY_CLK		6
+#define HI3519_ETH_MAC_CLK		7
+#define HI3519_ETH_MACIF_CLK		8
+#define HI3519_PWM_CLK			9
+#define HI3519_DMA_CLK			10
+#define HI3519_SSP0_CLK			11
+#define HI3519_SSP1_CLK			12
+#define HI3519_SSP2_CLK			13
+#define HI3519_IR_CLK			14
+#define HI3519_UART0_CLK		15
+#define HI3519_UART1_CLK		16
+#define HI3519_UART2_CLK		17
+#define HI3519_UART3_CLK		18
+#define HI3519_UART4_CLK		19
+
+#define HI3519_EXT_CLKS			19
+
+#endif	/* __DTS_HI3519_CLOCK_H */
-- 
1.9.1

[PATCH v3 1/7] clk: hisilicon: add CRG driver for hi3519 soc

[Jiancheng Xue]

The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.

Signed-off-by: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/hisilicon/Kconfig            |   7 ++
 drivers/clk/hisilicon/Makefile           |   2 +
 drivers/clk/hisilicon/clk-hi3519.c       |  95 ++++++++++++++++++++
 drivers/clk/hisilicon/reset.c            | 149 +++++++++++++++++++++++++++++++
 drivers/clk/hisilicon/reset.h            |  32 +++++++
 include/dt-bindings/clock/hi3519-clock.h |  43 +++++++++
 6 files changed, 328 insertions(+)
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index e434854..b6baebf 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_CLK_HI3519
+	tristate "Clock Driver for Hi3519"
+	depends on ARCH_HISI
+	default y
+	help
+	  Build the clock driver for hi3519.
+
 config COMMON_CLK_HI6220
 	bool "Hi6220 Clock Driver"
 	depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 74dba31..3f57b09 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -4,8 +4,10 @@
 
 obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o
 
+obj-$(CONFIG_RESET_CONTROLLER)	+= reset.o
 obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2)	+= clk-hix5hd2.o
 obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o
 obj-$(CONFIG_STUB_CLK_HI6220)	+= clk-hi6220-stub.o
+obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
new file mode 100644
index 0000000..928e848
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/of_address.h>
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "clk.h"
+#include "reset.h"
+
+#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
+#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 2)
+#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 3)
+#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 4)
+#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 5)
+#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 6)
+#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
+#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
+#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
+
+#define HI3519_NR_CLKS	128
+#define HI3519_NR_RSTS	128
+
+static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
+	{ HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
+	{ HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
+	{ HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
+	{ HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
+	{ HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
+	{ HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
+	{ HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
+	{ HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
+	{ HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
+};
+
+static const char *fmc_mux_p[] __initconst = {
+		"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
+	{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+		CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+};
+
+static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
+	/* fmc */
+	{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
+		CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
+	/* uart */
+	{ HI3519_UART0_CLK, "clk_uart0", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
+	{ HI3519_UART1_CLK, "clk_uart1", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
+	{ HI3519_UART2_CLK, "clk_uart2", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
+	{ HI3519_UART3_CLK, "clk_uart3", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
+	{ HI3519_UART4_CLK, "clk_uart4", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
+};
+
+static void __init hi3519_clk_init(struct device_node *np)
+{
+	struct hisi_clock_data *clk_data;
+
+	clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
+	if (!clk_data)
+		return;
+
+	hisi_reset_init(np, HI3519_NR_RSTS);
+
+	hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
+				     ARRAY_SIZE(hi3519_fixed_rate_clks),
+				     clk_data);
+	hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
+					clk_data);
+	hisi_clk_register_gate(hi3519_gate_clks,
+			ARRAY_SIZE(hi3519_gate_clks), clk_data);
+}
+
+CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
new file mode 100644
index 0000000..cf5c32a
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.c
@@ -0,0 +1,149 @@
+/*
+ * Hisilicon Reset Controller driver
+ *
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define	HISI_RESET_BIT_SHIFT	0
+#define	HISI_RESET_BIT_WIDTH	16
+#define	HISI_RESET_OFFSET_SHIFT	16
+#define	HISI_RESET_OFFSET_WIDTH	16
+
+struct hisi_reset_controller {
+	spinlock_t	lock;
+	void __iomem	*membase;
+	struct reset_controller_dev	rcdev;
+};
+
+
+#define to_hisi_reset_controller(rcdev)  \
+	container_of(rcdev, struct hisi_reset_controller, rcdev)
+
+/*31                        16                         0
+ * |---reset_spec->args[0]---|---reset_spec->args[1]---|
+ * |-------reg_offset--------|--------reg_bit----------|
+ */
+static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
+			const struct of_phandle_args *reset_spec)
+{
+	unsigned int offset, bit, id;
+	const __be32 *addr;
+	u64 size;
+
+	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+		return -EINVAL;
+
+	addr = of_get_address(rcdev->of_node, 0, &size, NULL);
+	if (!addr)
+		return -EINVAL;
+
+	if (reset_spec->args[1] >= 32
+		|| reset_spec->args[0] + reset_spec->args[1] / 8 > size)
+		return -EINVAL;
+
+	offset = reset_spec->args[0] & (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = (reset_spec->args[1] & (BIT(HISI_RESET_BIT_WIDTH) - 1));
+	id = offset << HISI_RESET_OFFSET_SHIFT | bit;
+
+	return id;
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned int offset, bit;
+	unsigned long flags;
+	u32 reg;
+
+	offset = id >> HISI_RESET_OFFSET_SHIFT;
+	offset &= (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = id & (BIT(HISI_RESET_BIT_WIDTH) - 1);
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg | BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned int offset, bit;
+	unsigned long flags;
+	u32 reg;
+
+	offset = id >> HISI_RESET_OFFSET_SHIFT;
+	offset &= (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = id & (BIT(HISI_RESET_BIT_WIDTH) - 1);
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg & ~BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+	.assert		= hisi_reset_assert,
+	.deassert	= hisi_reset_deassert,
+};
+
+int __init hisi_reset_init(struct device_node *np,
+					     int nr_rsts)
+{
+	struct hisi_reset_controller *rstc;
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	rstc->membase = of_iomap(np, 0);
+	if (!rstc->membase)
+		return -EINVAL;
+
+	spin_lock_init(&rstc->lock);
+
+	rstc->rcdev.owner = THIS_MODULE;
+	rstc->rcdev.nr_resets = nr_rsts;
+	rstc->rcdev.ops = &hisi_reset_ops;
+	rstc->rcdev.of_node = np;
+	rstc->rcdev.of_reset_n_cells = 2;
+	rstc->rcdev.of_xlate = hisi_reset_of_xlate;
+
+	return reset_controller_register(&rstc->rcdev);
+}
+
diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
new file mode 100644
index 0000000..b04796f
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	__HISI_RESET_H
+#define	__HISI_RESET_H
+
+#include <linux/of.h>
+
+#ifdef CONFIG_RESET_CONTROLLER
+int __init hisi_reset_init(struct device_node *np, int nr_rsts);
+#else
+static inline int __init hisi_reset_init(struct device_node *np, int nr_rsts)
+{
+	return 0;
+}
+#endif
+
+#endif	/* __HISI_RESET_H */
diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 0000000..66a37b1
--- /dev/null
+++ b/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FIXED_3M			1
+#define HI3519_FMC_CLK			2
+#define HI3519_USB2_BUS_CLK		3
+#define HI3519_USB2_PORT_CLK		4
+#define HI3519_USB3_CLK			5
+#define HI3519_ETH_PHY_CLK		6
+#define HI3519_ETH_MAC_CLK		7
+#define HI3519_ETH_MACIF_CLK		8
+#define HI3519_PWM_CLK			9
+#define HI3519_DMA_CLK			10
+#define HI3519_SSP0_CLK			11
+#define HI3519_SSP1_CLK			12
+#define HI3519_SSP2_CLK			13
+#define HI3519_IR_CLK			14
+#define HI3519_UART0_CLK		15
+#define HI3519_UART1_CLK		16
+#define HI3519_UART2_CLK		17
+#define HI3519_UART3_CLK		18
+#define HI3519_UART4_CLK		19
+
+#define HI3519_EXT_CLKS			19
+
+#endif	/* __DTS_HI3519_CLOCK_H */
-- 
1.9.1

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[PATCH v3 1/7] clk: hisilicon: add CRG driver for hi3519 soc

[Jiancheng Xue]

The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 drivers/clk/hisilicon/Kconfig            |   7 ++
 drivers/clk/hisilicon/Makefile           |   2 +
 drivers/clk/hisilicon/clk-hi3519.c       |  95 ++++++++++++++++++++
 drivers/clk/hisilicon/reset.c            | 149 +++++++++++++++++++++++++++++++
 drivers/clk/hisilicon/reset.h            |  32 +++++++
 include/dt-bindings/clock/hi3519-clock.h |  43 +++++++++
 6 files changed, 328 insertions(+)
 create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
 create mode 100644 drivers/clk/hisilicon/reset.c
 create mode 100644 drivers/clk/hisilicon/reset.h
 create mode 100644 include/dt-bindings/clock/hi3519-clock.h

diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index e434854..b6baebf 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_CLK_HI3519
+	tristate "Clock Driver for Hi3519"
+	depends on ARCH_HISI
+	default y
+	help
+	  Build the clock driver for hi3519.
+
 config COMMON_CLK_HI6220
 	bool "Hi6220 Clock Driver"
 	depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 74dba31..3f57b09 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -4,8 +4,10 @@
 
 obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o
 
+obj-$(CONFIG_RESET_CONTROLLER)	+= reset.o
 obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2)	+= clk-hix5hd2.o
 obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o
 obj-$(CONFIG_STUB_CLK_HI6220)	+= clk-hi6220-stub.o
+obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
new file mode 100644
index 0000000..928e848
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/of_address.h>
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "clk.h"
+#include "reset.h"
+
+#define HI3519_FIXED_24M	(HI3519_EXT_CLKS + 1)
+#define HI3519_FIXED_75M	(HI3519_EXT_CLKS + 2)
+#define HI3519_FIXED_125M	(HI3519_EXT_CLKS + 3)
+#define HI3519_FIXED_150M	(HI3519_EXT_CLKS + 4)
+#define HI3519_FIXED_200M	(HI3519_EXT_CLKS + 5)
+#define HI3519_FIXED_250M	(HI3519_EXT_CLKS + 6)
+#define HI3519_FIXED_300M	(HI3519_EXT_CLKS + 8)
+#define HI3519_FIXED_400M	(HI3519_EXT_CLKS + 9)
+#define HI3519_FMC_MUX		(HI3519_EXT_CLKS + 10)
+
+#define HI3519_NR_CLKS	128
+#define HI3519_NR_RSTS	128
+
+static struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] __initdata = {
+	{ HI3519_FIXED_3M, "3m", NULL, CLK_IS_ROOT, 3000000, },
+	{ HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
+	{ HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
+	{ HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
+	{ HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
+	{ HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
+	{ HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
+	{ HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
+	{ HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
+};
+
+static const char *fmc_mux_p[] __initconst = {
+		"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static struct hisi_mux_clock hi3519_mux_clks[] __initdata = {
+	{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+		CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+};
+
+static struct hisi_gate_clock hi3519_gate_clks[] __initdata = {
+	/* fmc */
+	{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
+		CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
+	/* uart */
+	{ HI3519_UART0_CLK, "clk_uart0", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
+	{ HI3519_UART1_CLK, "clk_uart1", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
+	{ HI3519_UART2_CLK, "clk_uart2", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
+	{ HI3519_UART3_CLK, "clk_uart3", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
+	{ HI3519_UART4_CLK, "clk_uart4", "24m",
+		CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
+};
+
+static void __init hi3519_clk_init(struct device_node *np)
+{
+	struct hisi_clock_data *clk_data;
+
+	clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
+	if (!clk_data)
+		return;
+
+	hisi_reset_init(np, HI3519_NR_RSTS);
+
+	hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
+				     ARRAY_SIZE(hi3519_fixed_rate_clks),
+				     clk_data);
+	hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
+					clk_data);
+	hisi_clk_register_gate(hi3519_gate_clks,
+			ARRAY_SIZE(hi3519_gate_clks), clk_data);
+}
+
+CLK_OF_DECLARE(hi3519_clk, "hisilicon,hi3519-crg", hi3519_clk_init);
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
new file mode 100644
index 0000000..cf5c32a
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.c
@@ -0,0 +1,149 @@
+/*
+ * Hisilicon Reset Controller driver
+ *
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define	HISI_RESET_BIT_SHIFT	0
+#define	HISI_RESET_BIT_WIDTH	16
+#define	HISI_RESET_OFFSET_SHIFT	16
+#define	HISI_RESET_OFFSET_WIDTH	16
+
+struct hisi_reset_controller {
+	spinlock_t	lock;
+	void __iomem	*membase;
+	struct reset_controller_dev	rcdev;
+};
+
+
+#define to_hisi_reset_controller(rcdev)  \
+	container_of(rcdev, struct hisi_reset_controller, rcdev)
+
+/*31                        16                         0
+ * |---reset_spec->args[0]---|---reset_spec->args[1]---|
+ * |-------reg_offset--------|--------reg_bit----------|
+ */
+static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
+			const struct of_phandle_args *reset_spec)
+{
+	unsigned int offset, bit, id;
+	const __be32 *addr;
+	u64 size;
+
+	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+		return -EINVAL;
+
+	addr = of_get_address(rcdev->of_node, 0, &size, NULL);
+	if (!addr)
+		return -EINVAL;
+
+	if (reset_spec->args[1] >= 32
+		|| reset_spec->args[0] + reset_spec->args[1] / 8 > size)
+		return -EINVAL;
+
+	offset = reset_spec->args[0] & (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = (reset_spec->args[1] & (BIT(HISI_RESET_BIT_WIDTH) - 1));
+	id = offset << HISI_RESET_OFFSET_SHIFT | bit;
+
+	return id;
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned int offset, bit;
+	unsigned long flags;
+	u32 reg;
+
+	offset = id >> HISI_RESET_OFFSET_SHIFT;
+	offset &= (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = id & (BIT(HISI_RESET_BIT_WIDTH) - 1);
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg | BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+	unsigned int offset, bit;
+	unsigned long flags;
+	u32 reg;
+
+	offset = id >> HISI_RESET_OFFSET_SHIFT;
+	offset &= (BIT(HISI_RESET_OFFSET_WIDTH) - 1);
+	bit = id & (BIT(HISI_RESET_BIT_WIDTH) - 1);
+
+	spin_lock_irqsave(&rstc->lock, flags);
+
+	reg = readl(rstc->membase + offset);
+	writel(reg & ~BIT(bit), rstc->membase + offset);
+
+	spin_unlock_irqrestore(&rstc->lock, flags);
+
+	return 0;
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+	.assert		= hisi_reset_assert,
+	.deassert	= hisi_reset_deassert,
+};
+
+int __init hisi_reset_init(struct device_node *np,
+					     int nr_rsts)
+{
+	struct hisi_reset_controller *rstc;
+
+	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	rstc->membase = of_iomap(np, 0);
+	if (!rstc->membase)
+		return -EINVAL;
+
+	spin_lock_init(&rstc->lock);
+
+	rstc->rcdev.owner = THIS_MODULE;
+	rstc->rcdev.nr_resets = nr_rsts;
+	rstc->rcdev.ops = &hisi_reset_ops;
+	rstc->rcdev.of_node = np;
+	rstc->rcdev.of_reset_n_cells = 2;
+	rstc->rcdev.of_xlate = hisi_reset_of_xlate;
+
+	return reset_controller_register(&rstc->rcdev);
+}
+
diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
new file mode 100644
index 0000000..b04796f
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	__HISI_RESET_H
+#define	__HISI_RESET_H
+
+#include <linux/of.h>
+
+#ifdef CONFIG_RESET_CONTROLLER
+int __init hisi_reset_init(struct device_node *np, int nr_rsts);
+#else
+static inline int __init hisi_reset_init(struct device_node *np, int nr_rsts)
+{
+	return 0;
+}
+#endif
+
+#endif	/* __HISI_RESET_H */
diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 0000000..66a37b1
--- /dev/null
+++ b/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FIXED_3M			1
+#define HI3519_FMC_CLK			2
+#define HI3519_USB2_BUS_CLK		3
+#define HI3519_USB2_PORT_CLK		4
+#define HI3519_USB3_CLK			5
+#define HI3519_ETH_PHY_CLK		6
+#define HI3519_ETH_MAC_CLK		7
+#define HI3519_ETH_MACIF_CLK		8
+#define HI3519_PWM_CLK			9
+#define HI3519_DMA_CLK			10
+#define HI3519_SSP0_CLK			11
+#define HI3519_SSP1_CLK			12
+#define HI3519_SSP2_CLK			13
+#define HI3519_IR_CLK			14
+#define HI3519_UART0_CLK		15
+#define HI3519_UART1_CLK		16
+#define HI3519_UART2_CLK		17
+#define HI3519_UART3_CLK		18
+#define HI3519_UART4_CLK		19
+
+#define HI3519_EXT_CLKS			19
+
+#endif	/* __DTS_HI3519_CLOCK_H */
-- 
1.9.1

[PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[Jiancheng Xue]

add dt-binding document for Hi3519 CRG block

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt

diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..e0d30a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+    Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller {
+	compatible = "hisilicon,hi3519-crg";
+        reg = <0x12010000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@0x12110000 {
+	compatible = "hisilicon,hi3519-i2c";
+        reg = <0x12110000 0x1000>;
+        clocks = <&CRG HI3519_I2C0_RST>;*/
+        resets = <&CRG 0xE4 0>;
+};
-- 
1.9.1

[PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[Jiancheng Xue]

add dt-binding document for Hi3519 CRG block

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt

diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..e0d30a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+    Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller {
+	compatible = "hisilicon,hi3519-crg";
+        reg = <0x12010000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@0x12110000 {
+	compatible = "hisilicon,hi3519-i2c";
+        reg = <0x12110000 0x1000>;
+        clocks = <&CRG HI3519_I2C0_RST>;*/
+        resets = <&CRG 0xE4 0>;
+};
-- 
1.9.1

[PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[Jiancheng Xue]

add dt-binding document for Hi3519 CRG block

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt

diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..e0d30a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+    Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller {
+	compatible = "hisilicon,hi3519-crg";
+        reg = <0x12010000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@0x12110000 {
+	compatible = "hisilicon,hi3519-i2c";
+        reg = <0x12110000 0x1000>;
+        clocks = <&CRG HI3519_I2C0_RST>;*/
+        resets = <&CRG 0xE4 0>;
+};
-- 
1.9.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[Jiancheng Xue]

add dt-binding document for Hi3519 CRG block

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt

diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..e0d30a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+    Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller {
+	compatible = "hisilicon,hi3519-crg";
+        reg = <0x12010000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c at 0x12110000 {
+	compatible = "hisilicon,hi3519-i2c";
+        reg = <0x12110000 0x1000>;
+        clocks = <&CRG HI3519_I2C0_RST>;*/
+        resets = <&CRG 0xE4 0>;
+};
-- 
1.9.1

[PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[Jiancheng Xue]

add dt_machine definition for hi3519.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 8cc6215..010d8a2 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
 DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
 	.dt_compat      = hip01_compat,
 MACHINE_END
+
+static const char *const hi3519_compat[] __initconst = {
+	"hisilicon,hi3519",
+	NULL,
+};
+
+DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
+	.dt_compat	= hi3519_compat,
+MACHINE_END
-- 
1.9.1

[PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[Jiancheng Xue]

add dt_machine definition for hi3519.

Signed-off-by: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 8cc6215..010d8a2 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
 DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
 	.dt_compat      = hip01_compat,
 MACHINE_END
+
+static const char *const hi3519_compat[] __initconst = {
+	"hisilicon,hi3519",
+	NULL,
+};
+
+DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
+	.dt_compat	= hi3519_compat,
+MACHINE_END
-- 
1.9.1

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[PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[Jiancheng Xue]

add dt_machine definition for hi3519.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 8cc6215..010d8a2 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
 DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
 	.dt_compat      = hip01_compat,
 MACHINE_END
+
+static const char *const hi3519_compat[] __initconst = {
+	"hisilicon,hi3519",
+	NULL,
+};
+
+DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
+	.dt_compat	= hi3519_compat,
+MACHINE_END
-- 
1.9.1

[PATCH v3 4/7] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER

[Jiancheng Xue]

enable CONFIG_RESET_CONTROLLER in hisi_defconfig

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/configs/hisi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index b2e340b..ba62c07 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -75,6 +75,7 @@ CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_PL330_DMA=y
 CONFIG_PWM=y
+CONFIG_RESET_CONTROLLER=y
 CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_EXT4_FS=y
 CONFIG_TMPFS=y
-- 
1.9.1

[PATCH v3 4/7] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER

[Jiancheng Xue]

enable CONFIG_RESET_CONTROLLER in hisi_defconfig

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/configs/hisi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index b2e340b..ba62c07 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -75,6 +75,7 @@ CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_PL330_DMA=y
 CONFIG_PWM=y
+CONFIG_RESET_CONTROLLER=y
 CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_EXT4_FS=y
 CONFIG_TMPFS=y
-- 
1.9.1

[PATCH v3 4/7] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER

[Jiancheng Xue]

enable CONFIG_RESET_CONTROLLER in hisi_defconfig

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/configs/hisi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index b2e340b..ba62c07 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -75,6 +75,7 @@ CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_PL330_DMA=y
 CONFIG_PWM=y
+CONFIG_RESET_CONTROLLER=y
 CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_EXT4_FS=y
 CONFIG_TMPFS=y
-- 
1.9.1

[PATCH v3 5/7] ARM: debug: add hi3519 debug uart

[Jiancheng Xue]

add hi3519 debug uart.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/Kconfig.debug | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 259c0ca..29af057 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -270,6 +270,14 @@ choice
 		  Say Y here if you want the debug print routines to direct
 		  their output to the 8250 at PCI COM1.
 
+	config DEBUG_HI3519_UART
+		bool "Hisilicon Hi3519 Debug UART"
+		depends on ARCH_HISI
+		select DEBUG_UART_PL01X
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on HI3519 UART.
+
 	config DEBUG_HI3620_UART
 		bool "Hisilicon HI3620 Debug UART"
 		depends on ARCH_HI3xxx
@@ -1449,6 +1457,7 @@ config DEBUG_UART_PHYS
 	default 0xf7fc9000 if DEBUG_BERLIN_UART
 	default 0xf8b00000 if DEBUG_HIX5HD2_UART
 	default 0xf991e000 if DEBUG_QCOM_UARTDM
+	default 0x12100000 if DEBUG_HI3519_UART
 	default 0xfcb00000 if DEBUG_HI3620_UART
 	default 0xfd883000 if DEBUG_ALPINE_UART0
 	default 0xfe800000 if ARCH_IOP32X
@@ -1529,6 +1538,7 @@ config DEBUG_UART_VIRT
 	default 0xfe230000 if DEBUG_PICOXCELL_UART
 	default 0xfe300000 if DEBUG_BCM_KONA_UART
 	default 0xfe800000 if ARCH_IOP32X
+	default 0xfef00000 if DEBUG_HI3519_UART
 	default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
 	default 0xfeb24000 if DEBUG_RK3X_UART0
 	default 0xfeb26000 if DEBUG_RK3X_UART1
-- 
1.9.1

[PATCH v3 5/7] ARM: debug: add hi3519 debug uart

[Jiancheng Xue]

add hi3519 debug uart.

Signed-off-by: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 arch/arm/Kconfig.debug | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 259c0ca..29af057 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -270,6 +270,14 @@ choice
 		  Say Y here if you want the debug print routines to direct
 		  their output to the 8250 at PCI COM1.
 
+	config DEBUG_HI3519_UART
+		bool "Hisilicon Hi3519 Debug UART"
+		depends on ARCH_HISI
+		select DEBUG_UART_PL01X
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on HI3519 UART.
+
 	config DEBUG_HI3620_UART
 		bool "Hisilicon HI3620 Debug UART"
 		depends on ARCH_HI3xxx
@@ -1449,6 +1457,7 @@ config DEBUG_UART_PHYS
 	default 0xf7fc9000 if DEBUG_BERLIN_UART
 	default 0xf8b00000 if DEBUG_HIX5HD2_UART
 	default 0xf991e000 if DEBUG_QCOM_UARTDM
+	default 0x12100000 if DEBUG_HI3519_UART
 	default 0xfcb00000 if DEBUG_HI3620_UART
 	default 0xfd883000 if DEBUG_ALPINE_UART0
 	default 0xfe800000 if ARCH_IOP32X
@@ -1529,6 +1538,7 @@ config DEBUG_UART_VIRT
 	default 0xfe230000 if DEBUG_PICOXCELL_UART
 	default 0xfe300000 if DEBUG_BCM_KONA_UART
 	default 0xfe800000 if ARCH_IOP32X
+	default 0xfef00000 if DEBUG_HI3519_UART
 	default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
 	default 0xfeb24000 if DEBUG_RK3X_UART0
 	default 0xfeb26000 if DEBUG_RK3X_UART1
-- 
1.9.1

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[PATCH v3 5/7] ARM: debug: add hi3519 debug uart

[Jiancheng Xue]

add hi3519 debug uart.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/Kconfig.debug | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 259c0ca..29af057 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -270,6 +270,14 @@ choice
 		  Say Y here if you want the debug print routines to direct
 		  their output to the 8250 at PCI COM1.
 
+	config DEBUG_HI3519_UART
+		bool "Hisilicon Hi3519 Debug UART"
+		depends on ARCH_HISI
+		select DEBUG_UART_PL01X
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on HI3519 UART.
+
 	config DEBUG_HI3620_UART
 		bool "Hisilicon HI3620 Debug UART"
 		depends on ARCH_HI3xxx
@@ -1449,6 +1457,7 @@ config DEBUG_UART_PHYS
 	default 0xf7fc9000 if DEBUG_BERLIN_UART
 	default 0xf8b00000 if DEBUG_HIX5HD2_UART
 	default 0xf991e000 if DEBUG_QCOM_UARTDM
+	default 0x12100000 if DEBUG_HI3519_UART
 	default 0xfcb00000 if DEBUG_HI3620_UART
 	default 0xfd883000 if DEBUG_ALPINE_UART0
 	default 0xfe800000 if ARCH_IOP32X
@@ -1529,6 +1538,7 @@ config DEBUG_UART_VIRT
 	default 0xfe230000 if DEBUG_PICOXCELL_UART
 	default 0xfe300000 if DEBUG_BCM_KONA_UART
 	default 0xfe800000 if ARCH_IOP32X
+	default 0xfef00000 if DEBUG_HI3519_UART
 	default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
 	default 0xfeb24000 if DEBUG_RK3X_UART0
 	default 0xfeb26000 if DEBUG_RK3X_UART1
-- 
1.9.1

[PATCH v3 6/7] mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl

[Jiancheng Xue]

Add device tree bindings for Hi3519 system controller.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt

diff --git a/Documentation/devicetree/bindings/mfd/hi3519.txt b/Documentation/devicetree/bindings/mfd/hi3519.txt
new file mode 100644
index 0000000..4b1c294
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hi3519.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Dcumentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: "hislicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller@12010000 {
+	compatible = "hisilicon,hi3519-sysctrl", "syscon";
+	reg = <0x12010000 0x1000>;
+};
-- 
1.9.1

[PATCH v3 6/7] mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl

[Jiancheng Xue]

Add device tree bindings for Hi3519 system controller.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt

diff --git a/Documentation/devicetree/bindings/mfd/hi3519.txt b/Documentation/devicetree/bindings/mfd/hi3519.txt
new file mode 100644
index 0000000..4b1c294
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hi3519.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Dcumentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: "hislicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller@12010000 {
+	compatible = "hisilicon,hi3519-sysctrl", "syscon";
+	reg = <0x12010000 0x1000>;
+};
-- 
1.9.1

[PATCH v3 6/7] mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl

[Jiancheng Xue]

Add device tree bindings for Hi3519 system controller.

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt

diff --git a/Documentation/devicetree/bindings/mfd/hi3519.txt b/Documentation/devicetree/bindings/mfd/hi3519.txt
new file mode 100644
index 0000000..4b1c294
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hi3519.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Dcumentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: "hislicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller at 12010000 {
+	compatible = "hisilicon,hi3519-sysctrl", "syscon";
+	reg = <0x12010000 0x1000>;
+};
-- 
1.9.1

[PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[Jiancheng Xue]

add dts files for Hi3519

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
 arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 186 insertions(+)
 create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
 create mode 100644 arch/arm/boot/dts/hi3519.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..1ff3ed9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
 	exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += \
 	hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HISI) += \
+	hi3519-demb.dtb
 dtb-$(CONFIG_ARCH_HIX5HD2) += \
 	hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
new file mode 100644
index 0000000..6991ab6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519-demb.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/dts-v1/;
+#include "hi3519.dtsi"
+
+/ {
+	model = "HiSilicon HI3519 DEMO Board";
+	compatible = "hisilicon,hi3519";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&dual_timer0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
new file mode 100644
index 0000000..50b736e
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hi3519-clock.h>
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+	};
+
+	gic: interrupt-controller@10300000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		amba {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "arm,amba-bus";
+			ranges;
+
+			uart0: serial@12100000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12100000 0x1000>;
+				interrupts = <0 4 4>;
+				clocks = <&crg HI3519_UART0_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart1: serial@12101000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12101000 0x1000>;
+				interrupts = <0 5 4>;
+				clocks = <&crg HI3519_UART1_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart2: serial@12102000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12102000 0x1000>;
+				interrupts = <0 6 4>;
+				clocks = <&crg HI3519_UART2_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart3: serial@12103000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12103000 0x1000>;
+				interrupts = <0 7 4>;
+				clocks = <&crg HI3519_UART3_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart4: serial@12104000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12104000 0x1000>;
+				interrupts = <0 8 4>;
+				clocks = <&crg HI3519_UART4_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			dual_timer0: timer@12000000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 64 4>, <0 65 4>;
+				reg = <0x12000000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+
+			dual_timer1: timer@12001000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 66 4>, <0 67 4>;
+				reg = <0x12001000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+
+			dual_timer2: timer@12002000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 68 4>, <0 69 4>;
+				reg = <0x12002000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+		};
+
+		sysctrl: system-controller@12020000 {
+			compatible = "hisilicon,hi3519-sysctrl", "syscon";
+			reg = <0x12020000 0x1000>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&sysctrl>;
+			offset = <0x4>;
+			mask = <0xdeadbeef>;
+		};
+
+		crg: clock-reset-controller@12010000 {
+			compatible = "hisilicon,hi3519-crg";
+			#clock-cells = <1>;
+			#reset-cells = <2>;
+			reg = <0x12010000 0x10000>;
+		};
+	};
+};
-- 
1.9.1

[PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[Jiancheng Xue]

add dts files for Hi3519

Signed-off-by: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
 arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 186 insertions(+)
 create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
 create mode 100644 arch/arm/boot/dts/hi3519.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..1ff3ed9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
 	exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += \
 	hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HISI) += \
+	hi3519-demb.dtb
 dtb-$(CONFIG_ARCH_HIX5HD2) += \
 	hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
new file mode 100644
index 0000000..6991ab6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519-demb.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/dts-v1/;
+#include "hi3519.dtsi"
+
+/ {
+	model = "HiSilicon HI3519 DEMO Board";
+	compatible = "hisilicon,hi3519";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&dual_timer0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
new file mode 100644
index 0000000..50b736e
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hi3519-clock.h>
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+	};
+
+	gic: interrupt-controller@10300000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		amba {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "arm,amba-bus";
+			ranges;
+
+			uart0: serial@12100000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12100000 0x1000>;
+				interrupts = <0 4 4>;
+				clocks = <&crg HI3519_UART0_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart1: serial@12101000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12101000 0x1000>;
+				interrupts = <0 5 4>;
+				clocks = <&crg HI3519_UART1_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart2: serial@12102000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12102000 0x1000>;
+				interrupts = <0 6 4>;
+				clocks = <&crg HI3519_UART2_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart3: serial@12103000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12103000 0x1000>;
+				interrupts = <0 7 4>;
+				clocks = <&crg HI3519_UART3_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart4: serial@12104000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12104000 0x1000>;
+				interrupts = <0 8 4>;
+				clocks = <&crg HI3519_UART4_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			dual_timer0: timer@12000000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 64 4>, <0 65 4>;
+				reg = <0x12000000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+
+			dual_timer1: timer@12001000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 66 4>, <0 67 4>;
+				reg = <0x12001000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+
+			dual_timer2: timer@12002000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 68 4>, <0 69 4>;
+				reg = <0x12002000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+		};
+
+		sysctrl: system-controller@12020000 {
+			compatible = "hisilicon,hi3519-sysctrl", "syscon";
+			reg = <0x12020000 0x1000>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&sysctrl>;
+			offset = <0x4>;
+			mask = <0xdeadbeef>;
+		};
+
+		crg: clock-reset-controller@12010000 {
+			compatible = "hisilicon,hi3519-crg";
+			#clock-cells = <1>;
+			#reset-cells = <2>;
+			reg = <0x12010000 0x10000>;
+		};
+	};
+};
-- 
1.9.1

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[PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[Jiancheng Xue]

add dts files for Hi3519

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
 arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 186 insertions(+)
 create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
 create mode 100644 arch/arm/boot/dts/hi3519.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..1ff3ed9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
 	exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += \
 	hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HISI) += \
+	hi3519-demb.dtb
 dtb-$(CONFIG_ARCH_HIX5HD2) += \
 	hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
new file mode 100644
index 0000000..6991ab6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519-demb.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/dts-v1/;
+#include "hi3519.dtsi"
+
+/ {
+	model = "HiSilicon HI3519 DEMO Board";
+	compatible = "hisilicon,hi3519";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&dual_timer0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
new file mode 100644
index 0000000..50b736e
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hi3519-clock.h>
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+	};
+
+	gic: interrupt-controller at 10300000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		amba {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "arm,amba-bus";
+			ranges;
+
+			uart0: serial at 12100000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12100000 0x1000>;
+				interrupts = <0 4 4>;
+				clocks = <&crg HI3519_UART0_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart1: serial at 12101000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12101000 0x1000>;
+				interrupts = <0 5 4>;
+				clocks = <&crg HI3519_UART1_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart2: serial at 12102000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12102000 0x1000>;
+				interrupts = <0 6 4>;
+				clocks = <&crg HI3519_UART2_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart3: serial at 12103000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12103000 0x1000>;
+				interrupts = <0 7 4>;
+				clocks = <&crg HI3519_UART3_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			uart4: serial at 12104000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x12104000 0x1000>;
+				interrupts = <0 8 4>;
+				clocks = <&crg HI3519_UART4_CLK>;
+				clock-names = "apb_pclk";
+				status = "disable";
+			};
+
+			dual_timer0: timer at 12000000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 64 4>, <0 65 4>;
+				reg = <0x12000000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+
+			dual_timer1: timer at 12001000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 66 4>, <0 67 4>;
+				reg = <0x12001000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+
+			dual_timer2: timer at 12002000 {
+				compatible = "arm,sp804", "arm,primecell";
+				interrupts = <0 68 4>, <0 69 4>;
+				reg = <0x12002000 0x1000>;
+				clocks = <&crg HI3519_FIXED_3M>;
+				status = "disable";
+			};
+		};
+
+		sysctrl: system-controller at 12020000 {
+			compatible = "hisilicon,hi3519-sysctrl", "syscon";
+			reg = <0x12020000 0x1000>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&sysctrl>;
+			offset = <0x4>;
+			mask = <0xdeadbeef>;
+		};
+
+		crg: clock-reset-controller at 12010000 {
+			compatible = "hisilicon,hi3519-crg";
+			#clock-cells = <1>;
+			#reset-cells = <2>;
+			reg = <0x12010000 0x10000>;
+		};
+	};
+};
-- 
1.9.1

Re: [PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:16PM +0800, Jiancheng Xue wrote:
> add dt-binding document for Hi3519 CRG block
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> ---
>  .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> new file mode 100644
> index 0000000..e0d30a4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> @@ -0,0 +1,46 @@
> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
> +
> +The Hi3519 CRG module provides clock and reset signals to various
> +controllers within the SoC.
> +
> +This binding uses the following bindings:
> +    Documentation/devicetree/bindings/clock/clock-bindings.txt
> +    Documentation/devicetree/bindings/reset/reset.txt
> +
> +Required Properties:
> +
> +- compatible: should be one of the following.
> +  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #clock-cells: should be 1.
> +
> +Each clock is assigned an identifier and client nodes use this identifier
> +to specify the clock which they consume.
> +
> +All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.

This header should be part of this patch.

> +
> +- #reset-cells: should be 2.
> +
> +A reset signal can be controlled by writing a bit register in the CRG module.
> +The reset specifier consists of two cells. The first cell represents the
> +register offset relative to the base address. The second cell represents the
> +bit index in the register.
> +
> +Example: CRG nodes
> +CRG: clock-reset-controller {

clock-reset-controller@12010000

> +	compatible = "hisilicon,hi3519-crg";
> +        reg = <0x12010000 0x10000>;
> +        #clock-cells = <1>;
> +        #reset-cells = <2>;
> +};
> +
> +Example: consumer nodes
> +i2c0: i2c@0x12110000 {

Drop '0x'

> +	compatible = "hisilicon,hi3519-i2c";
> +        reg = <0x12110000 0x1000>;
> +        clocks = <&CRG HI3519_I2C0_RST>;*/
> +        resets = <&CRG 0xE4 0>;

lowercase hex please

> +};
> -- 
> 1.9.1
> 

[PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:16PM +0800, Jiancheng Xue wrote:
> add dt-binding document for Hi3519 CRG block
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> ---
>  .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> new file mode 100644
> index 0000000..e0d30a4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
> @@ -0,0 +1,46 @@
> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
> +
> +The Hi3519 CRG module provides clock and reset signals to various
> +controllers within the SoC.
> +
> +This binding uses the following bindings:
> +    Documentation/devicetree/bindings/clock/clock-bindings.txt
> +    Documentation/devicetree/bindings/reset/reset.txt
> +
> +Required Properties:
> +
> +- compatible: should be one of the following.
> +  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #clock-cells: should be 1.
> +
> +Each clock is assigned an identifier and client nodes use this identifier
> +to specify the clock which they consume.
> +
> +All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.

This header should be part of this patch.

> +
> +- #reset-cells: should be 2.
> +
> +A reset signal can be controlled by writing a bit register in the CRG module.
> +The reset specifier consists of two cells. The first cell represents the
> +register offset relative to the base address. The second cell represents the
> +bit index in the register.
> +
> +Example: CRG nodes
> +CRG: clock-reset-controller {

clock-reset-controller at 12010000

> +	compatible = "hisilicon,hi3519-crg";
> +        reg = <0x12010000 0x10000>;
> +        #clock-cells = <1>;
> +        #reset-cells = <2>;
> +};
> +
> +Example: consumer nodes
> +i2c0: i2c at 0x12110000 {

Drop '0x'

> +	compatible = "hisilicon,hi3519-i2c";
> +        reg = <0x12110000 0x1000>;
> +        clocks = <&CRG HI3519_I2C0_RST>;*/
> +        resets = <&CRG 0xE4 0>;

lowercase hex please

> +};
> -- 
> 1.9.1
> 

Re: [PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:17PM +0800, Jiancheng Xue wrote:
> add dt_machine definition for hi3519.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> ---
>  arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
> index 8cc6215..010d8a2 100644
> --- a/arch/arm/mach-hisi/hisilicon.c
> +++ b/arch/arm/mach-hisi/hisilicon.c
> @@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
>  DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
>  	.dt_compat      = hip01_compat,
>  MACHINE_END
> +
> +static const char *const hi3519_compat[] __initconst = {
> +	"hisilicon,hi3519",
> +	NULL,
> +};

You should just have 1 mach desc with multiple compatible strings to 
match against, not 1 mach desc per compatible string.

Rob

> +
> +DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
> +	.dt_compat	= hi3519_compat,
> +MACHINE_END
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:17PM +0800, Jiancheng Xue wrote:
> add dt_machine definition for hi3519.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> ---
>  arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
> index 8cc6215..010d8a2 100644
> --- a/arch/arm/mach-hisi/hisilicon.c
> +++ b/arch/arm/mach-hisi/hisilicon.c
> @@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
>  DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
>  	.dt_compat      = hip01_compat,
>  MACHINE_END
> +
> +static const char *const hi3519_compat[] __initconst = {
> +	"hisilicon,hi3519",
> +	NULL,
> +};

You should just have 1 mach desc with multiple compatible strings to 
match against, not 1 mach desc per compatible string.

Rob

> +
> +DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
> +	.dt_compat	= hi3519_compat,
> +MACHINE_END
> -- 
> 1.9.1
> 
> --
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> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:21PM +0800, Jiancheng Xue wrote:
> add dts files for Hi3519
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> ---
>  arch/arm/boot/dts/Makefile        |   2 +
>  arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
>  arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 186 insertions(+)
>  create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
>  create mode 100644 arch/arm/boot/dts/hi3519.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 30bbc37..1ff3ed9 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
>  	exynos5800-peach-pi.dtb
>  dtb-$(CONFIG_ARCH_HI3xxx) += \
>  	hi3620-hi4511.dtb
> +dtb-$(CONFIG_ARCH_HISI) += \
> +	hi3519-demb.dtb
>  dtb-$(CONFIG_ARCH_HIX5HD2) += \
>  	hisi-x5hd2-dkb.dtb
>  dtb-$(CONFIG_ARCH_HIGHBANK) += \
> diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
> new file mode 100644
> index 0000000..6991ab6
> --- /dev/null
> +++ b/arch/arm/boot/dts/hi3519-demb.dts
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +/dts-v1/;
> +#include "hi3519.dtsi"
> +
> +/ {
> +	model = "HiSilicon HI3519 DEMO Board";
> +	compatible = "hisilicon,hi3519";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x80000000 0x40000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&dual_timer0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
> new file mode 100644
> index 0000000..50b736e
> --- /dev/null
> +++ b/arch/arm/boot/dts/hi3519.dtsi
> @@ -0,0 +1,142 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#include "skeleton.dtsi"

Don't include skeleton.dtsi. We've decided it was a bad idea.

> +#include <dt-bindings/clock/hi3519-clock.h>
> +/ {
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {

Single core system? Add the other cpu nodes if not. Adding them doesn't 
have to be in sync with SMP kernel support.

> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0>;
> +		};
> +	};
> +
> +	gic: interrupt-controller@10300000 {
> +		compatible = "arm,cortex-a7-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;

Looks like everything is in 0x12xxxxxx range, so you should add actual 
translation here if that's the case.

> +
> +		amba {

Is this actually a separate bus in the physical design of the chip?

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "arm,amba-bus";

Just simple-bus. "arm,amba-bus" is not any type of bus, nor is it 
documented.

> +			ranges;
> +
> +			uart0: serial@12100000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12100000 0x1000>;
> +				interrupts = <0 4 4>;
> +				clocks = <&crg HI3519_UART0_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart1: serial@12101000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12101000 0x1000>;
> +				interrupts = <0 5 4>;
> +				clocks = <&crg HI3519_UART1_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart2: serial@12102000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12102000 0x1000>;
> +				interrupts = <0 6 4>;
> +				clocks = <&crg HI3519_UART2_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart3: serial@12103000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12103000 0x1000>;
> +				interrupts = <0 7 4>;
> +				clocks = <&crg HI3519_UART3_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart4: serial@12104000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12104000 0x1000>;
> +				interrupts = <0 8 4>;
> +				clocks = <&crg HI3519_UART4_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			dual_timer0: timer@12000000 {
> +				compatible = "arm,sp804", "arm,primecell";
> +				interrupts = <0 64 4>, <0 65 4>;
> +				reg = <0x12000000 0x1000>;
> +				clocks = <&crg HI3519_FIXED_3M>;
> +				status = "disable";
> +			};
> +
> +			dual_timer1: timer@12001000 {
> +				compatible = "arm,sp804", "arm,primecell";
> +				interrupts = <0 66 4>, <0 67 4>;
> +				reg = <0x12001000 0x1000>;
> +				clocks = <&crg HI3519_FIXED_3M>;
> +				status = "disable";
> +			};
> +
> +			dual_timer2: timer@12002000 {
> +				compatible = "arm,sp804", "arm,primecell";
> +				interrupts = <0 68 4>, <0 69 4>;
> +				reg = <0x12002000 0x1000>;
> +				clocks = <&crg HI3519_FIXED_3M>;
> +				status = "disable";
> +			};
> +		};
> +
> +		sysctrl: system-controller@12020000 {
> +			compatible = "hisilicon,hi3519-sysctrl", "syscon";
> +			reg = <0x12020000 0x1000>;
> +		};
> +
> +		reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&sysctrl>;
> +			offset = <0x4>;
> +			mask = <0xdeadbeef>;
> +		};
> +
> +		crg: clock-reset-controller@12010000 {
> +			compatible = "hisilicon,hi3519-crg";
> +			#clock-cells = <1>;
> +			#reset-cells = <2>;
> +			reg = <0x12010000 0x10000>;
> +		};
> +	};
> +};
> -- 
> 1.9.1
> 
> --
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[PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:21PM +0800, Jiancheng Xue wrote:
> add dts files for Hi3519
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> ---
>  arch/arm/boot/dts/Makefile        |   2 +
>  arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
>  arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 186 insertions(+)
>  create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
>  create mode 100644 arch/arm/boot/dts/hi3519.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 30bbc37..1ff3ed9 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
>  	exynos5800-peach-pi.dtb
>  dtb-$(CONFIG_ARCH_HI3xxx) += \
>  	hi3620-hi4511.dtb
> +dtb-$(CONFIG_ARCH_HISI) += \
> +	hi3519-demb.dtb
>  dtb-$(CONFIG_ARCH_HIX5HD2) += \
>  	hisi-x5hd2-dkb.dtb
>  dtb-$(CONFIG_ARCH_HIGHBANK) += \
> diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
> new file mode 100644
> index 0000000..6991ab6
> --- /dev/null
> +++ b/arch/arm/boot/dts/hi3519-demb.dts
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +/dts-v1/;
> +#include "hi3519.dtsi"
> +
> +/ {
> +	model = "HiSilicon HI3519 DEMO Board";
> +	compatible = "hisilicon,hi3519";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x80000000 0x40000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&dual_timer0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
> new file mode 100644
> index 0000000..50b736e
> --- /dev/null
> +++ b/arch/arm/boot/dts/hi3519.dtsi
> @@ -0,0 +1,142 @@
> +/*
> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#include "skeleton.dtsi"

Don't include skeleton.dtsi. We've decided it was a bad idea.

> +#include <dt-bindings/clock/hi3519-clock.h>
> +/ {
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at 0 {

Single core system? Add the other cpu nodes if not. Adding them doesn't 
have to be in sync with SMP kernel support.

> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0>;
> +		};
> +	};
> +
> +	gic: interrupt-controller at 10300000 {
> +		compatible = "arm,cortex-a7-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;

Looks like everything is in 0x12xxxxxx range, so you should add actual 
translation here if that's the case.

> +
> +		amba {

Is this actually a separate bus in the physical design of the chip?

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "arm,amba-bus";

Just simple-bus. "arm,amba-bus" is not any type of bus, nor is it 
documented.

> +			ranges;
> +
> +			uart0: serial at 12100000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12100000 0x1000>;
> +				interrupts = <0 4 4>;
> +				clocks = <&crg HI3519_UART0_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart1: serial at 12101000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12101000 0x1000>;
> +				interrupts = <0 5 4>;
> +				clocks = <&crg HI3519_UART1_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart2: serial at 12102000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12102000 0x1000>;
> +				interrupts = <0 6 4>;
> +				clocks = <&crg HI3519_UART2_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart3: serial at 12103000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12103000 0x1000>;
> +				interrupts = <0 7 4>;
> +				clocks = <&crg HI3519_UART3_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			uart4: serial at 12104000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x12104000 0x1000>;
> +				interrupts = <0 8 4>;
> +				clocks = <&crg HI3519_UART4_CLK>;
> +				clock-names = "apb_pclk";
> +				status = "disable";
> +			};
> +
> +			dual_timer0: timer at 12000000 {
> +				compatible = "arm,sp804", "arm,primecell";
> +				interrupts = <0 64 4>, <0 65 4>;
> +				reg = <0x12000000 0x1000>;
> +				clocks = <&crg HI3519_FIXED_3M>;
> +				status = "disable";
> +			};
> +
> +			dual_timer1: timer at 12001000 {
> +				compatible = "arm,sp804", "arm,primecell";
> +				interrupts = <0 66 4>, <0 67 4>;
> +				reg = <0x12001000 0x1000>;
> +				clocks = <&crg HI3519_FIXED_3M>;
> +				status = "disable";
> +			};
> +
> +			dual_timer2: timer at 12002000 {
> +				compatible = "arm,sp804", "arm,primecell";
> +				interrupts = <0 68 4>, <0 69 4>;
> +				reg = <0x12002000 0x1000>;
> +				clocks = <&crg HI3519_FIXED_3M>;
> +				status = "disable";
> +			};
> +		};
> +
> +		sysctrl: system-controller at 12020000 {
> +			compatible = "hisilicon,hi3519-sysctrl", "syscon";
> +			reg = <0x12020000 0x1000>;
> +		};
> +
> +		reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&sysctrl>;
> +			offset = <0x4>;
> +			mask = <0xdeadbeef>;
> +		};
> +
> +		crg: clock-reset-controller at 12010000 {
> +			compatible = "hisilicon,hi3519-crg";
> +			#clock-cells = <1>;
> +			#reset-cells = <2>;
> +			reg = <0x12010000 0x10000>;
> +		};
> +	};
> +};
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 6/7] mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:20PM +0800, Jiancheng Xue wrote:
> Add device tree bindings for Hi3519 system controller.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>

Acked-by: Rob Herring <robh@kernel.org>

> ---
>  Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt
> 
> diff --git a/Documentation/devicetree/bindings/mfd/hi3519.txt b/Documentation/devicetree/bindings/mfd/hi3519.txt
> new file mode 100644
> index 0000000..4b1c294
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/hi3519.txt
> @@ -0,0 +1,14 @@
> +* Hisilicon Hi3519 System Controller Block
> +
> +This bindings use the following binding:
> +Dcumentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible: "hislicon,hi3519-sysctrl".
> +- reg: the register region of this block
> +
> +Examples:
> +sysctrl: system-controller@12010000 {
> +	compatible = "hisilicon,hi3519-sysctrl", "syscon";
> +	reg = <0x12010000 0x1000>;
> +};
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
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[PATCH v3 6/7] mfd: dt-bindings: add device tree bindings for Hi3519 sysctrl

[Rob Herring]

On Fri, Dec 11, 2015 at 03:45:20PM +0800, Jiancheng Xue wrote:
> Add device tree bindings for Hi3519 system controller.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>

Acked-by: Rob Herring <robh@kernel.org>

> ---
>  Documentation/devicetree/bindings/mfd/hi3519.txt | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/hi3519.txt
> 
> diff --git a/Documentation/devicetree/bindings/mfd/hi3519.txt b/Documentation/devicetree/bindings/mfd/hi3519.txt
> new file mode 100644
> index 0000000..4b1c294
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/hi3519.txt
> @@ -0,0 +1,14 @@
> +* Hisilicon Hi3519 System Controller Block
> +
> +This bindings use the following binding:
> +Dcumentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible: "hislicon,hi3519-sysctrl".
> +- reg: the register region of this block
> +
> +Examples:
> +sysctrl: system-controller at 12010000 {
> +	compatible = "hisilicon,hi3519-sysctrl", "syscon";
> +	reg = <0x12010000 0x1000>;
> +};
> -- 
> 1.9.1
> 
> --
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> the body of a message to majordomo at vger.kernel.org
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Re: [PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[xuejiancheng]

On 2015/12/11 23:19, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:16PM +0800, Jiancheng Xue wrote:
>> add dt-binding document for Hi3519 CRG block
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> new file mode 100644
>> index 0000000..e0d30a4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> @@ -0,0 +1,46 @@
>> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
>> +
>> +The Hi3519 CRG module provides clock and reset signals to various
>> +controllers within the SoC.
>> +
>> +This binding uses the following bindings:
>> +    Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +    Documentation/devicetree/bindings/reset/reset.txt
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following.
>> +  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +Each clock is assigned an identifier and client nodes use this identifier
>> +to specify the clock which they consume.
>> +
>> +All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
> 
> This header should be part of this patch.

Because the header is also depended on by the clock driver. It's also a problem
if I separate it from the clock driver patch.

Is it OK if I put this binding file into the clock driver patch?
> 
>> +
>> +- #reset-cells: should be 2.
>> +
>> +A reset signal can be controlled by writing a bit register in the CRG module.
>> +The reset specifier consists of two cells. The first cell represents the
>> +register offset relative to the base address. The second cell represents the
>> +bit index in the register.
>> +
>> +Example: CRG nodes
>> +CRG: clock-reset-controller {
> 
> clock-reset-controller@12010000

OK.

> 
>> +	compatible = "hisilicon,hi3519-crg";
>> +        reg = <0x12010000 0x10000>;
>> +        #clock-cells = <1>;
>> +        #reset-cells = <2>;
>> +};
>> +
>> +Example: consumer nodes
>> +i2c0: i2c@0x12110000 {
> 
> Drop '0x'

OK.

> 
>> +	compatible = "hisilicon,hi3519-i2c";
>> +        reg = <0x12110000 0x1000>;
>> +        clocks = <&CRG HI3519_I2C0_RST>;*/
>> +        resets = <&CRG 0xE4 0>;
> 
> lowercase hex please

OK.

> 
>> +};
>> -- 
>> 1.9.1
>>
> 
> .
> 

Re: [PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[xuejiancheng]

On 2015/12/11 23:19, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:16PM +0800, Jiancheng Xue wrote:
>> add dt-binding document for Hi3519 CRG block
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> new file mode 100644
>> index 0000000..e0d30a4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> @@ -0,0 +1,46 @@
>> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
>> +
>> +The Hi3519 CRG module provides clock and reset signals to various
>> +controllers within the SoC.
>> +
>> +This binding uses the following bindings:
>> +    Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +    Documentation/devicetree/bindings/reset/reset.txt
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following.
>> +  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +Each clock is assigned an identifier and client nodes use this identifier
>> +to specify the clock which they consume.
>> +
>> +All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
> 
> This header should be part of this patch.

Because the header is also depended on by the clock driver. It's also a problem
if I separate it from the clock driver patch.

Is it OK if I put this binding file into the clock driver patch?
> 
>> +
>> +- #reset-cells: should be 2.
>> +
>> +A reset signal can be controlled by writing a bit register in the CRG module.
>> +The reset specifier consists of two cells. The first cell represents the
>> +register offset relative to the base address. The second cell represents the
>> +bit index in the register.
>> +
>> +Example: CRG nodes
>> +CRG: clock-reset-controller {
> 
> clock-reset-controller@12010000

OK.

> 
>> +	compatible = "hisilicon,hi3519-crg";
>> +        reg = <0x12010000 0x10000>;
>> +        #clock-cells = <1>;
>> +        #reset-cells = <2>;
>> +};
>> +
>> +Example: consumer nodes
>> +i2c0: i2c@0x12110000 {
> 
> Drop '0x'

OK.

> 
>> +	compatible = "hisilicon,hi3519-i2c";
>> +        reg = <0x12110000 0x1000>;
>> +        clocks = <&CRG HI3519_I2C0_RST>;*/
>> +        resets = <&CRG 0xE4 0>;
> 
> lowercase hex please

OK.

> 
>> +};
>> -- 
>> 1.9.1
>>
> 
> .
> 

[PATCH v3 2/7] clk: hisilicon: add dt-binding document for Hi3519 CRG

[xuejiancheng]

On 2015/12/11 23:19, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:16PM +0800, Jiancheng Xue wrote:
>> add dt-binding document for Hi3519 CRG block
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  .../devicetree/bindings/clock/hi3519-crg.txt       | 46 ++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> new file mode 100644
>> index 0000000..e0d30a4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
>> @@ -0,0 +1,46 @@
>> +* Hisilicon Hi3519 Clock and Reset Generator(CRG)
>> +
>> +The Hi3519 CRG module provides clock and reset signals to various
>> +controllers within the SoC.
>> +
>> +This binding uses the following bindings:
>> +    Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +    Documentation/devicetree/bindings/reset/reset.txt
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following.
>> +  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +Each clock is assigned an identifier and client nodes use this identifier
>> +to specify the clock which they consume.
>> +
>> +All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
> 
> This header should be part of this patch.

Because the header is also depended on by the clock driver. It's also a problem
if I separate it from the clock driver patch.

Is it OK if I put this binding file into the clock driver patch?
> 
>> +
>> +- #reset-cells: should be 2.
>> +
>> +A reset signal can be controlled by writing a bit register in the CRG module.
>> +The reset specifier consists of two cells. The first cell represents the
>> +register offset relative to the base address. The second cell represents the
>> +bit index in the register.
>> +
>> +Example: CRG nodes
>> +CRG: clock-reset-controller {
> 
> clock-reset-controller at 12010000

OK.

> 
>> +	compatible = "hisilicon,hi3519-crg";
>> +        reg = <0x12010000 0x10000>;
>> +        #clock-cells = <1>;
>> +        #reset-cells = <2>;
>> +};
>> +
>> +Example: consumer nodes
>> +i2c0: i2c at 0x12110000 {
> 
> Drop '0x'

OK.

> 
>> +	compatible = "hisilicon,hi3519-i2c";
>> +        reg = <0x12110000 0x1000>;
>> +        clocks = <&CRG HI3519_I2C0_RST>;*/
>> +        resets = <&CRG 0xE4 0>;
> 
> lowercase hex please

OK.

> 
>> +};
>> -- 
>> 1.9.1
>>
> 
> .
> 

Re: [PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[xuejiancheng]

On 2015/12/11 23:21, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:17PM +0800, Jiancheng Xue wrote:
>> add dt_machine definition for hi3519.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
>> index 8cc6215..010d8a2 100644
>> --- a/arch/arm/mach-hisi/hisilicon.c
>> +++ b/arch/arm/mach-hisi/hisilicon.c
>> @@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
>>  DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
>>  	.dt_compat      = hip01_compat,
>>  MACHINE_END
>> +
>> +static const char *const hi3519_compat[] __initconst = {
>> +	"hisilicon,hi3519",
>> +	NULL,
>> +};
> 
> You should just have 1 mach desc with multiple compatible strings to 
> match against, not 1 mach desc per compatible string.

Yes, you're right. But Hi3519 is a soc in a new family. It doesn't belong to
any other existing mach descs. And more hi3519 compatible boards will be added
in this mach desc afterwards.
Can I do it like this now, and combine them at a proper time?

Or just add a more generic mach desc, then other socs like hix5hd2/hip01/hip04 can use this?
static const char *const hisilicon_compat[] __initconst = {
        "hisilicon,hi3519",
        NULL,
};

DT_MACHINE_START(HISILICON_DT, "Hisilicon")
        .dt_compat      = hisilicon_compat,
MACHINE_END



> Rob
> 
>> +
>> +DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
>> +	.dt_compat	= hi3519_compat,
>> +MACHINE_END
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 

Re: [PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[xuejiancheng]

On 2015/12/11 23:21, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:17PM +0800, Jiancheng Xue wrote:
>> add dt_machine definition for hi3519.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
>> index 8cc6215..010d8a2 100644
>> --- a/arch/arm/mach-hisi/hisilicon.c
>> +++ b/arch/arm/mach-hisi/hisilicon.c
>> @@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
>>  DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
>>  	.dt_compat      = hip01_compat,
>>  MACHINE_END
>> +
>> +static const char *const hi3519_compat[] __initconst = {
>> +	"hisilicon,hi3519",
>> +	NULL,
>> +};
> 
> You should just have 1 mach desc with multiple compatible strings to 
> match against, not 1 mach desc per compatible string.

Yes, you're right. But Hi3519 is a soc in a new family. It doesn't belong to
any other existing mach descs. And more hi3519 compatible boards will be added
in this mach desc afterwards.
Can I do it like this now, and combine them at a proper time?

Or just add a more generic mach desc, then other socs like hix5hd2/hip01/hip04 can use this?
static const char *const hisilicon_compat[] __initconst = {
        "hisilicon,hi3519",
        NULL,
};

DT_MACHINE_START(HISILICON_DT, "Hisilicon")
        .dt_compat      = hisilicon_compat,
MACHINE_END



> Rob
> 
>> +
>> +DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
>> +	.dt_compat	= hi3519_compat,
>> +MACHINE_END
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 

[PATCH v3 3/7] ARM: hisi: add dt_machine definition for Hi3519

[xuejiancheng]

On 2015/12/11 23:21, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:17PM +0800, Jiancheng Xue wrote:
>> add dt_machine definition for hi3519.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  arch/arm/mach-hisi/hisilicon.c | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
>> index 8cc6215..010d8a2 100644
>> --- a/arch/arm/mach-hisi/hisilicon.c
>> +++ b/arch/arm/mach-hisi/hisilicon.c
>> @@ -81,3 +81,12 @@ static const char *const hip01_compat[] __initconst = {
>>  DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
>>  	.dt_compat      = hip01_compat,
>>  MACHINE_END
>> +
>> +static const char *const hi3519_compat[] __initconst = {
>> +	"hisilicon,hi3519",
>> +	NULL,
>> +};
> 
> You should just have 1 mach desc with multiple compatible strings to 
> match against, not 1 mach desc per compatible string.

Yes, you're right. But Hi3519 is a soc in a new family. It doesn't belong to
any other existing mach descs. And more hi3519 compatible boards will be added
in this mach desc afterwards.
Can I do it like this now, and combine them at a proper time?

Or just add a more generic mach desc, then other socs like hix5hd2/hip01/hip04 can use this?
static const char *const hisilicon_compat[] __initconst = {
        "hisilicon,hi3519",
        NULL,
};

DT_MACHINE_START(HISILICON_DT, "Hisilicon")
        .dt_compat      = hisilicon_compat,
MACHINE_END



> Rob
> 
>> +
>> +DT_MACHINE_START(HI3519_DT, "Hisilicon Hi3519")
>> +	.dt_compat	= hi3519_compat,
>> +MACHINE_END
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 

Re: [PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[xuejiancheng]

Hi Rob,

On 2015/12/12 0:28, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:21PM +0800, Jiancheng Xue wrote:
>> add dts files for Hi3519
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  arch/arm/boot/dts/Makefile        |   2 +
>>  arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
>>  arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 186 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
>>  create mode 100644 arch/arm/boot/dts/hi3519.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 30bbc37..1ff3ed9 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
>>  	exynos5800-peach-pi.dtb
>>  dtb-$(CONFIG_ARCH_HI3xxx) += \
>>  	hi3620-hi4511.dtb
>> +dtb-$(CONFIG_ARCH_HISI) += \
>> +	hi3519-demb.dtb
>>  dtb-$(CONFIG_ARCH_HIX5HD2) += \
>>  	hisi-x5hd2-dkb.dtb
>>  dtb-$(CONFIG_ARCH_HIGHBANK) += \
>> diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
>> new file mode 100644
>> index 0000000..6991ab6
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/hi3519-demb.dts
>> @@ -0,0 +1,42 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +#include "hi3519.dtsi"
>> +
>> +/ {
>> +	model = "HiSilicon HI3519 DEMO Board";
>> +	compatible = "hisilicon,hi3519";
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +	};
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x80000000 0x40000000>;
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	status = "okay";
>> +};
>> +
>> +&dual_timer0 {
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
>> new file mode 100644
>> index 0000000..50b736e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/hi3519.dtsi
>> @@ -0,0 +1,142 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#include "skeleton.dtsi"
> 
> Don't include skeleton.dtsi. We've decided it was a bad idea.

OK.

> 
>> +#include <dt-bindings/clock/hi3519-clock.h>
>> +/ {
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
> 
> Single core system? Add the other cpu nodes if not. Adding them doesn't 
> have to be in sync with SMP kernel support.

Hi3519 includes an A7 core and an A17 core. But it will run in AMP mode.
The A17 core is reserved for customers for special use. We can treat the
system as a single core system here.

> 
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a7";
>> +			reg = <0>;
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller@10300000 {
>> +		compatible = "arm,cortex-a7-gic";
>> +		#interrupt-cells = <3>;
>> +		interrupt-controller;
>> +		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
>> +	};
>> +
>> +	soc {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		compatible = "simple-bus";
>> +		interrupt-parent = <&gic>;
>> +		ranges;
> 
> Looks like everything is in 0x12xxxxxx range, so you should add actual 
> translation here if that's the case.

Other device nodes will be added later which are not in 0x12xxxxxx range.

> 
>> +
>> +		amba {
> 
> Is this actually a separate bus in the physical design of the chip?
> 
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			compatible = "arm,amba-bus";
> 
> Just simple-bus. "arm,amba-bus" is not any type of bus, nor is it 
> documented.

OK. I will modify this. Thank you!

> 
>> +			ranges;
>> +
>> +			uart0: serial@12100000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12100000 0x1000>;
>> +				interrupts = <0 4 4>;
>> +				clocks = <&crg HI3519_UART0_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart1: serial@12101000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12101000 0x1000>;
>> +				interrupts = <0 5 4>;
>> +				clocks = <&crg HI3519_UART1_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart2: serial@12102000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12102000 0x1000>;
>> +				interrupts = <0 6 4>;
>> +				clocks = <&crg HI3519_UART2_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart3: serial@12103000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12103000 0x1000>;
>> +				interrupts = <0 7 4>;
>> +				clocks = <&crg HI3519_UART3_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart4: serial@12104000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12104000 0x1000>;
>> +				interrupts = <0 8 4>;
>> +				clocks = <&crg HI3519_UART4_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer0: timer@12000000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 64 4>, <0 65 4>;
>> +				reg = <0x12000000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer1: timer@12001000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 66 4>, <0 67 4>;
>> +				reg = <0x12001000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer2: timer@12002000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 68 4>, <0 69 4>;
>> +				reg = <0x12002000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +		};
>> +
>> +		sysctrl: system-controller@12020000 {
>> +			compatible = "hisilicon,hi3519-sysctrl", "syscon";
>> +			reg = <0x12020000 0x1000>;
>> +		};
>> +
>> +		reboot {
>> +			compatible = "syscon-reboot";
>> +			regmap = <&sysctrl>;
>> +			offset = <0x4>;
>> +			mask = <0xdeadbeef>;
>> +		};
>> +
>> +		crg: clock-reset-controller@12010000 {
>> +			compatible = "hisilicon,hi3519-crg";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <2>;
>> +			reg = <0x12010000 0x10000>;
>> +		};
>> +	};
>> +};
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 
Many Thanks.

Jiancheng.

Re: [PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[xuejiancheng]

Hi Rob,

On 2015/12/12 0:28, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:21PM +0800, Jiancheng Xue wrote:
>> add dts files for Hi3519
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>> ---
>>  arch/arm/boot/dts/Makefile        |   2 +
>>  arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
>>  arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 186 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
>>  create mode 100644 arch/arm/boot/dts/hi3519.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 30bbc37..1ff3ed9 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
>>  	exynos5800-peach-pi.dtb
>>  dtb-$(CONFIG_ARCH_HI3xxx) += \
>>  	hi3620-hi4511.dtb
>> +dtb-$(CONFIG_ARCH_HISI) += \
>> +	hi3519-demb.dtb
>>  dtb-$(CONFIG_ARCH_HIX5HD2) += \
>>  	hisi-x5hd2-dkb.dtb
>>  dtb-$(CONFIG_ARCH_HIGHBANK) += \
>> diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
>> new file mode 100644
>> index 0000000..6991ab6
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/hi3519-demb.dts
>> @@ -0,0 +1,42 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +#include "hi3519.dtsi"
>> +
>> +/ {
>> +	model = "HiSilicon HI3519 DEMO Board";
>> +	compatible = "hisilicon,hi3519";
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +	};
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x80000000 0x40000000>;
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	status = "okay";
>> +};
>> +
>> +&dual_timer0 {
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
>> new file mode 100644
>> index 0000000..50b736e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/hi3519.dtsi
>> @@ -0,0 +1,142 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#include "skeleton.dtsi"
> 
> Don't include skeleton.dtsi. We've decided it was a bad idea.

OK.

> 
>> +#include <dt-bindings/clock/hi3519-clock.h>
>> +/ {
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
> 
> Single core system? Add the other cpu nodes if not. Adding them doesn't 
> have to be in sync with SMP kernel support.

Hi3519 includes an A7 core and an A17 core. But it will run in AMP mode.
The A17 core is reserved for customers for special use. We can treat the
system as a single core system here.

> 
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a7";
>> +			reg = <0>;
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller@10300000 {
>> +		compatible = "arm,cortex-a7-gic";
>> +		#interrupt-cells = <3>;
>> +		interrupt-controller;
>> +		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
>> +	};
>> +
>> +	soc {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		compatible = "simple-bus";
>> +		interrupt-parent = <&gic>;
>> +		ranges;
> 
> Looks like everything is in 0x12xxxxxx range, so you should add actual 
> translation here if that's the case.

Other device nodes will be added later which are not in 0x12xxxxxx range.

> 
>> +
>> +		amba {
> 
> Is this actually a separate bus in the physical design of the chip?
> 
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			compatible = "arm,amba-bus";
> 
> Just simple-bus. "arm,amba-bus" is not any type of bus, nor is it 
> documented.

OK. I will modify this. Thank you!

> 
>> +			ranges;
>> +
>> +			uart0: serial@12100000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12100000 0x1000>;
>> +				interrupts = <0 4 4>;
>> +				clocks = <&crg HI3519_UART0_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart1: serial@12101000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12101000 0x1000>;
>> +				interrupts = <0 5 4>;
>> +				clocks = <&crg HI3519_UART1_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart2: serial@12102000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12102000 0x1000>;
>> +				interrupts = <0 6 4>;
>> +				clocks = <&crg HI3519_UART2_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart3: serial@12103000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12103000 0x1000>;
>> +				interrupts = <0 7 4>;
>> +				clocks = <&crg HI3519_UART3_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart4: serial@12104000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12104000 0x1000>;
>> +				interrupts = <0 8 4>;
>> +				clocks = <&crg HI3519_UART4_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer0: timer@12000000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 64 4>, <0 65 4>;
>> +				reg = <0x12000000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer1: timer@12001000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 66 4>, <0 67 4>;
>> +				reg = <0x12001000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer2: timer@12002000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 68 4>, <0 69 4>;
>> +				reg = <0x12002000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +		};
>> +
>> +		sysctrl: system-controller@12020000 {
>> +			compatible = "hisilicon,hi3519-sysctrl", "syscon";
>> +			reg = <0x12020000 0x1000>;
>> +		};
>> +
>> +		reboot {
>> +			compatible = "syscon-reboot";
>> +			regmap = <&sysctrl>;
>> +			offset = <0x4>;
>> +			mask = <0xdeadbeef>;
>> +		};
>> +
>> +		crg: clock-reset-controller@12010000 {
>> +			compatible = "hisilicon,hi3519-crg";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <2>;
>> +			reg = <0x12010000 0x10000>;
>> +		};
>> +	};
>> +};
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 
Many Thanks.

Jiancheng.

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[PATCH v3 7/7] ARM: dts: add dts files for Hi3519

[xuejiancheng]

Hi Rob,

On 2015/12/12 0:28, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 03:45:21PM +0800, Jiancheng Xue wrote:
>> add dts files for Hi3519
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  arch/arm/boot/dts/Makefile        |   2 +
>>  arch/arm/boot/dts/hi3519-demb.dts |  42 +++++++++++
>>  arch/arm/boot/dts/hi3519.dtsi     | 142 ++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 186 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
>>  create mode 100644 arch/arm/boot/dts/hi3519.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 30bbc37..1ff3ed9 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
>>  	exynos5800-peach-pi.dtb
>>  dtb-$(CONFIG_ARCH_HI3xxx) += \
>>  	hi3620-hi4511.dtb
>> +dtb-$(CONFIG_ARCH_HISI) += \
>> +	hi3519-demb.dtb
>>  dtb-$(CONFIG_ARCH_HIX5HD2) += \
>>  	hisi-x5hd2-dkb.dtb
>>  dtb-$(CONFIG_ARCH_HIGHBANK) += \
>> diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
>> new file mode 100644
>> index 0000000..6991ab6
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/hi3519-demb.dts
>> @@ -0,0 +1,42 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +#include "hi3519.dtsi"
>> +
>> +/ {
>> +	model = "HiSilicon HI3519 DEMO Board";
>> +	compatible = "hisilicon,hi3519";
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +	};
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x80000000 0x40000000>;
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	status = "okay";
>> +};
>> +
>> +&dual_timer0 {
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
>> new file mode 100644
>> index 0000000..50b736e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/hi3519.dtsi
>> @@ -0,0 +1,142 @@
>> +/*
>> + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#include "skeleton.dtsi"
> 
> Don't include skeleton.dtsi. We've decided it was a bad idea.

OK.

> 
>> +#include <dt-bindings/clock/hi3519-clock.h>
>> +/ {
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu at 0 {
> 
> Single core system? Add the other cpu nodes if not. Adding them doesn't 
> have to be in sync with SMP kernel support.

Hi3519 includes an A7 core and an A17 core. But it will run in AMP mode.
The A17 core is reserved for customers for special use. We can treat the
system as a single core system here.

> 
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a7";
>> +			reg = <0>;
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller at 10300000 {
>> +		compatible = "arm,cortex-a7-gic";
>> +		#interrupt-cells = <3>;
>> +		interrupt-controller;
>> +		reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
>> +	};
>> +
>> +	soc {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		compatible = "simple-bus";
>> +		interrupt-parent = <&gic>;
>> +		ranges;
> 
> Looks like everything is in 0x12xxxxxx range, so you should add actual 
> translation here if that's the case.

Other device nodes will be added later which are not in 0x12xxxxxx range.

> 
>> +
>> +		amba {
> 
> Is this actually a separate bus in the physical design of the chip?
> 
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			compatible = "arm,amba-bus";
> 
> Just simple-bus. "arm,amba-bus" is not any type of bus, nor is it 
> documented.

OK. I will modify this. Thank you!

> 
>> +			ranges;
>> +
>> +			uart0: serial at 12100000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12100000 0x1000>;
>> +				interrupts = <0 4 4>;
>> +				clocks = <&crg HI3519_UART0_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart1: serial at 12101000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12101000 0x1000>;
>> +				interrupts = <0 5 4>;
>> +				clocks = <&crg HI3519_UART1_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart2: serial at 12102000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12102000 0x1000>;
>> +				interrupts = <0 6 4>;
>> +				clocks = <&crg HI3519_UART2_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart3: serial at 12103000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12103000 0x1000>;
>> +				interrupts = <0 7 4>;
>> +				clocks = <&crg HI3519_UART3_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			uart4: serial at 12104000 {
>> +				compatible = "arm,pl011", "arm,primecell";
>> +				reg = <0x12104000 0x1000>;
>> +				interrupts = <0 8 4>;
>> +				clocks = <&crg HI3519_UART4_CLK>;
>> +				clock-names = "apb_pclk";
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer0: timer at 12000000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 64 4>, <0 65 4>;
>> +				reg = <0x12000000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer1: timer at 12001000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 66 4>, <0 67 4>;
>> +				reg = <0x12001000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +
>> +			dual_timer2: timer at 12002000 {
>> +				compatible = "arm,sp804", "arm,primecell";
>> +				interrupts = <0 68 4>, <0 69 4>;
>> +				reg = <0x12002000 0x1000>;
>> +				clocks = <&crg HI3519_FIXED_3M>;
>> +				status = "disable";
>> +			};
>> +		};
>> +
>> +		sysctrl: system-controller at 12020000 {
>> +			compatible = "hisilicon,hi3519-sysctrl", "syscon";
>> +			reg = <0x12020000 0x1000>;
>> +		};
>> +
>> +		reboot {
>> +			compatible = "syscon-reboot";
>> +			regmap = <&sysctrl>;
>> +			offset = <0x4>;
>> +			mask = <0xdeadbeef>;
>> +		};
>> +
>> +		crg: clock-reset-controller at 12010000 {
>> +			compatible = "hisilicon,hi3519-crg";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <2>;
>> +			reg = <0x12010000 0x10000>;
>> +		};
>> +	};
>> +};
>> -- 
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 
Many Thanks.

Jiancheng.