* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
@ 2015-12-18 7:21 shengjiangwu
2015-12-18 7:44 ` Chin Liang See
0 siblings, 1 reply; 26+ messages in thread
From: shengjiangwu @ 2015-12-18 7:21 UTC (permalink / raw)
To: u-boot
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
2, /* MIXED1IO12 */
2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 42905f4..eccc705 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -32,7 +32,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
--
1.7.9.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-18 7:21 [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board shengjiangwu
@ 2015-12-18 7:44 ` Chin Liang See
0 siblings, 0 replies; 26+ messages in thread
From: Chin Liang See @ 2015-12-18 7:44 UTC (permalink / raw)
To: u-boot
Hi Shengjiang,
On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> ---
> board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------
> board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> index 442b1e0..06783dc 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
> 2, /* MIXED1IO12 */
> 2, /* MIXED1IO13 */
> 0, /* MIXED1IO14 */
> - 1, /* MIXED1IO15 */
> - 1, /* MIXED1IO16 */
> - 1, /* MIXED1IO17 */
> - 1, /* MIXED1IO18 */
> - 0, /* MIXED1IO19 */
> - 0, /* MIXED1IO20 */
> + 3, /* MIXED1IO15 */
> + 3, /* MIXED1IO16 */
> + 3, /* MIXED1IO17 */
> + 3, /* MIXED1IO18 */
> + 3, /* MIXED1IO19 */
> + 3, /* MIXED1IO20 */
> 0, /* MIXED1IO21 */
> 0, /* MIXED2IO0 */
> 0, /* MIXED2IO1 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h
> index 42905f4..eccc705 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -14,7 +14,7 @@
> #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
> #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
> #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
> -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
> +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
> #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
> #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
> #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
> @@ -32,7 +32,7 @@
> #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
> #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
Let's not change this as we are using mainpll for QSPI clock. Besides
that, the QSPI perpll will yield 500MHz which exceed the 400MHz max
clock.
Thanks
Chin Liang
> #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
> #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 2:38 ` Chin Liang See
@ 2015-12-23 3:04 ` Marek Vasut
0 siblings, 0 replies; 26+ messages in thread
From: Marek Vasut @ 2015-12-23 3:04 UTC (permalink / raw)
To: u-boot
On Wednesday, December 23, 2015 at 03:38:25 AM, Chin Liang See wrote:
> On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
> > On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> > > On Wednesday, December 23, 2015 at 03:26:07 AM, ?? ? wrote:
> [..]
>
> > > > Hi Marek,
> > > >
> > > > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > > > then usb
> > > > works,
> > > >
> > > > => usb start
> > > > starting USB...
> > > > USB0: Core Release: 2.93a
> > > > scanning bus 0 for devices... 2 USB Device(s) found
> > > > => usb tree
> > > > USB device tree:
> > > > 1 Hub (480 Mb/s, 0mA)
> > > >
> > > > > U-Boot Root Hub
> > > >
> > > > +-2 Mass Storage (480 Mb/s, 98mA)
> > > > Generic USB Storage 000000000272
> > >
> > > Cool, thanks! Patch please ;-)
> >
> > Nice, guess Altera email is very slow
>
> Yup, it work for me too with the pinmux change and dcache on.
>
> U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> spl: mmc boot mode: raw
>
>
> U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
>
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0 at ff704000: 0
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet at ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot: 0
> => dcache
> Data (writethrough) Cache is ON
> => usb reset
> resetting USB...
> USB0: Core Release: 2.93a
> scanning bus 0 for devices... 2 USB Device(s) found
> => usb info
> 1: Hub, USB Revision 1.10
> - U-Boot Root Hub
> - Class: Hub
> - PacketSize: 8 Configurations: 1
> - Vendor: 0x0000 Product 0x0000 Version 0.0
> Configuration: 1
> - Interfaces: 1 Self Powered 0mA
> Interface: 0
> - Alternate Setting 0, Endpoints: 1
> - Class Hub
> - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
>
> 2: Mass Storage, USB Revision 2.0
> - USB DISK 2.0 0781076602A6
> - Class: (from Interface) Mass Storage
> - PacketSize: 64 Configurations: 1
> - Vendor: 0x13fe Product 0x1e00 Version 1.16
> Configuration: 1
> - Interfaces: 1 Bus Powered 200mA
> Interface: 0
> - Alternate Setting 0, Endpoints: 2
> - Class Mass Storage, Transp. SCSI, Bulk only
> - Endpoint 1 In Bulk MaxPacket 512
> - Endpoint 2 Out Bulk MaxPacket 512
Cool, I will pick the patch shortly.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 2:29 ` Chin Liang See
@ 2015-12-23 2:38 ` Chin Liang See
2015-12-23 3:04 ` Marek Vasut
0 siblings, 1 reply; 26+ messages in thread
From: Chin Liang See @ 2015-12-23 2:38 UTC (permalink / raw)
To: u-boot
On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
> On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> > On Wednesday, December 23, 2015 at 03:26:07 AM, ?? ? wrote:
[..]
> > >
> > > Hi Marek,
> > >
> > > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > > then usb
> > > works,
> > >
> > > => usb start
> > > starting USB...
> > > USB0: Core Release: 2.93a
> > > scanning bus 0 for devices... 2 USB Device(s) found
> > > => usb tree
> > > USB device tree:
> > > 1 Hub (480 Mb/s, 0mA)
> > >
> > > > U-Boot Root Hub
> > >
> > > +-2 Mass Storage (480 Mb/s, 98mA)
> > > Generic USB Storage 000000000272
> >
> > Cool, thanks! Patch please ;-)
>
> Nice, guess Altera email is very slow
>
Yup, it work for me too with the pinmux change and dcache on.
U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC
spl: mmc boot mode: raw
U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC External Transceiver (1.8V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0 at ff704000: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet at ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
=> dcache
Data (writethrough) Cache is ON
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found
=> usb info
1: Hub, USB Revision 1.10
- U-Boot Root Hub
- Class: Hub
- PacketSize: 8 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 0.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
2: Mass Storage, USB Revision 2.0
- USB DISK 2.0 0781076602A6
- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x13fe Product 0x1e00 Version 1.16
Configuration: 1
- Interfaces: 1 Bus Powered 200mA
Interface: 0
- Alternate Setting 0, Endpoints: 2
- Class Mass Storage, Transp. SCSI, Bulk only
- Endpoint 1 In Bulk MaxPacket 512
- Endpoint 2 Out Bulk MaxPacket 512
Thanks
Chin Liang
> Thanks
> Chin Liang
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 2:27 ` Marek Vasut
@ 2015-12-23 2:29 ` Chin Liang See
2015-12-23 2:38 ` Chin Liang See
0 siblings, 1 reply; 26+ messages in thread
From: Chin Liang See @ 2015-12-23 2:29 UTC (permalink / raw)
To: u-boot
On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 03:26:07 AM, ?? ? wrote:
> > > From: Marek Vasut
> > > Date: 2015-12-23 10:07
> > > To: ShengjiangWu
> > > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> > > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk
> > > board
> > >
> > > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu
> > > wrote:
> > > > > -----Original Message-----
> > > > > From: Marek Vasut [mailto:marex at denx.de]
> > > > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > > > To: ?? ?
> > > > > Cc: u-boot at lists.denx.de; clsee at altera.com;
> > > > > dinguyen at opensource.altera.com; dinh.linux at gmail.com;
> > > > > pavel at denx.de;
> > > > > sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI
> > > > > doesn't work
> > > > > on socdk board
> > > > >
> > > > > On Wednesday, December 23, 2015 at 02:22:49 AM, ?? ? wrote:
> > > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de>
> > > > > > wrote:
> > > > > >
> > > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut
> > > > > > wrote:
> > > > > >
> > > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu
> > > > > > wrote:
> > > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > > > Updated QSPI clock.
> > > > > > >
> > > > > > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > > > > > Cc: Chin Liang See <clsee@altera.com>
> > > > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > > > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > > > > > Cc: Pavel Machek <pavel@denx.de>
> > > > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > > > Cc: Stefan Roese <sr@denx.de>
> > > > > >
> > > > > > Applied, thanks.
> > > > > >
> > > > > > I will push your patches to [1] in a few hours, can you try
> > > > > > and see
> > > > > > if the CV SOCDK works fine for you? Thanks
> > > > > >
> > > > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > > > >
> > > > > > Pushed. Please let me know how SoCDK works for you now and
> > > > > > if there
> > > > > > are still some problems.
> > > > > >
> > > > > >
> > > > > > Best regards,
> > > > > > Marek Vasut
> > > > > >
> > > > > >
> > > > > > Hi Marek,
> > > > > >
> > > > > > Thank you for your help, I tested the master branch, emac1
> > > > > > and QSPI
> > > > > > works. Below is log.
> > > > >
> > > > > Good! so we're happy ? Can you give USB a spin too? I think
> > > > > it might
> > > > > have some issues and I don't have the necessary cable here.
> > > > >
> > > > > [...]
> > > > >
> > > > > Best regards,
> > > > > Marek Vasut
> > > >
> > > > Hi Marek,
> > > >
> > > > Yes, emac1 and qspi are working now. I'm afraid USB is not
> > > > working,
> > > >
> > > > => usb reset
> > > > resetting USB...
> > > > USB0: Core Release: 2.93a
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > scanning bus 0 for devices... 1 USB Device(s) found
> > > > => usb tree
> > > > USB device tree:
> > > > 1 Hub (480 Mb/s, 0mA)
> > > > U-Boot Root Hub
> > >
> > > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong
> > > USB node
> > > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
> >
> > Hi Marek,
> >
> > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > then usb
> > works,
> >
> > => usb start
> > starting USB...
> > USB0: Core Release: 2.93a
> > scanning bus 0 for devices... 2 USB Device(s) found
> > => usb tree
> > USB device tree:
> > 1 Hub (480 Mb/s, 0mA)
> >
> > > U-Boot Root Hub
> >
> > +-2 Mass Storage (480 Mb/s, 98mA)
> > Generic USB Storage 000000000272
>
> Cool, thanks! Patch please ;-)
Nice, guess Altera email is very slow
Thanks
Chin Liang
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 2:07 ` Marek Vasut
@ 2015-12-23 2:27 ` Chin Liang See
0 siblings, 0 replies; 26+ messages in thread
From: Chin Liang See @ 2015-12-23 2:27 UTC (permalink / raw)
To: u-boot
On Wed, 2015-12-23 at 03:07 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
[..]
> > Hi Marek,
> >
> > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> >
> > => usb reset
> > resetting USB...
> > USB0: Core Release: 2.93a
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > scanning bus 0 for devices... 1 USB Device(s) found
> > => usb tree
> > USB device tree:
> > 1 Hub (480 Mb/s, 0mA)
> > U-Boot Root Hub
>
> Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB
> node
> in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
I am still setting up the SPL into SD card. In the mean time, I believe
the error come from pinmux. Shengjiang, can you try out below change?
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 06783dc..fb8648b 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -8,20 +8,20 @@
#define __SOCFPGA_PINMUX_CONFIG_H__
const u8 sys_mgr_init_table[] = {
- 3, /* EMACIO0 */
- 3, /* EMACIO1 */
- 3, /* EMACIO2 */
- 3, /* EMACIO3 */
- 3, /* EMACIO4 */
- 3, /* EMACIO5 */
- 3, /* EMACIO6 */
- 3, /* EMACIO7 */
- 3, /* EMACIO8 */
- 3, /* EMACIO9 */
- 3, /* EMACIO10 */
- 3, /* EMACIO11 */
- 3, /* EMACIO12 */
- 3, /* EMACIO13 */
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */
Thanks
Chin Liang
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 2:26 圣江 吴
@ 2015-12-23 2:27 ` Marek Vasut
2015-12-23 2:29 ` Chin Liang See
0 siblings, 1 reply; 26+ messages in thread
From: Marek Vasut @ 2015-12-23 2:27 UTC (permalink / raw)
To: u-boot
On Wednesday, December 23, 2015 at 03:26:07 AM, ?? ? wrote:
> > From: Marek Vasut
> > Date: 2015-12-23 10:07
> > To: ShengjiangWu
> > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
> >
> > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > > > -----Original Message-----
> > > > From: Marek Vasut [mailto:marex at denx.de]
> > > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > > To: ?? ?
> > > > Cc: u-boot at lists.denx.de; clsee at altera.com;
> > > > dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de;
> > > > sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work
> > > > on socdk board
> > > >
> > > > On Wednesday, December 23, 2015 at 02:22:49 AM, ?? ? wrote:
> > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
> > > > >
> > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > > > >
> > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > > Updated QSPI clock.
> > > > > >
> > > > > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > > > > Cc: Chin Liang See <clsee@altera.com>
> > > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > > > > Cc: Pavel Machek <pavel@denx.de>
> > > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > > Cc: Stefan Roese <sr@denx.de>
> > > > >
> > > > > Applied, thanks.
> > > > >
> > > > > I will push your patches to [1] in a few hours, can you try and see
> > > > > if the CV SOCDK works fine for you? Thanks
> > > > >
> > > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > > >
> > > > > Pushed. Please let me know how SoCDK works for you now and if there
> > > > > are still some problems.
> > > > >
> > > > >
> > > > > Best regards,
> > > > > Marek Vasut
> > > > >
> > > > >
> > > > > Hi Marek,
> > > > >
> > > > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > > > works. Below is log.
> > > >
> > > > Good! so we're happy ? Can you give USB a spin too? I think it might
> > > > have some issues and I don't have the necessary cable here.
> > > >
> > > > [...]
> > > >
> > > > Best regards,
> > > > Marek Vasut
> > >
> > > Hi Marek,
> > >
> > > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> > >
> > > => usb reset
> > > resetting USB...
> > > USB0: Core Release: 2.93a
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > scanning bus 0 for devices... 1 USB Device(s) found
> > > => usb tree
> > > USB device tree:
> > > 1 Hub (480 Mb/s, 0mA)
> > > U-Boot Root Hub
> >
> > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
> > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
>
> Hi Marek,
>
> Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb
> works,
>
> => usb start
> starting USB...
> USB0: Core Release: 2.93a
> scanning bus 0 for devices... 2 USB Device(s) found
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA)
>
> | U-Boot Root Hub
>
> +-2 Mass Storage (480 Mb/s, 98mA)
> Generic USB Storage 000000000272
Cool, thanks! Patch please ;-)
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
@ 2015-12-23 2:26 圣江 吴
2015-12-23 2:27 ` Marek Vasut
0 siblings, 1 reply; 26+ messages in thread
From: 圣江 吴 @ 2015-12-23 2:26 UTC (permalink / raw)
To: u-boot
> From: Marek Vasut
> Date: 2015-12-23 10:07
> To: ShengjiangWu
> CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
> On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > > -----Original Message-----
> > > From: Marek Vasut [mailto:marex at denx.de]
> > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > To: ?? ?
> > > Cc: u-boot at lists.denx.de; clsee at altera.com;
> > > dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de;
> > > sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on
> > > socdk board
> > >
> > > On Wednesday, December 23, 2015 at 02:22:49 AM, ?? ? wrote:
> > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
> > > >
> > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > > >
> > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > Updated QSPI clock.
> > > > >
> > > > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > > > Cc: Chin Liang See <clsee@altera.com>
> > > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > > > Cc: Pavel Machek <pavel@denx.de>
> > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > Cc: Stefan Roese <sr@denx.de>
> > > >
> > > > Applied, thanks.
> > > >
> > > > I will push your patches to [1] in a few hours, can you try and see if
> > > > the CV SOCDK works fine for you? Thanks
> > > >
> > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > >
> > > > Pushed. Please let me know how SoCDK works for you now and if there
> > > > are still some problems.
> > > >
> > > >
> > > > Best regards,
> > > > Marek Vasut
> > > >
> > > >
> > > > Hi Marek,
> > > >
> > > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > > works. Below is log.
> > >
> > > Good! so we're happy ? Can you give USB a spin too? I think it might have
> > > some issues and I don't have the necessary cable here.
> > >
> > > [...]
> > >
> > > Best regards,
> > > Marek Vasut
> >
> > Hi Marek,
> >
> > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> >
> > => usb reset
> > resetting USB...
> > USB0: Core Release: 2.93a
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > scanning bus 0 for devices... 1 USB Device(s) found
> > => usb tree
> > USB device tree:
> > 1 Hub (480 Mb/s, 0mA)
> > U-Boot Root Hub
>
> Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
> in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
Hi Marek,
Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works,
=> usb start
starting USB...
USB0: Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Mass Storage (480 Mb/s, 98mA)
Generic USB Storage 000000000272
=>
Best Regards,
ShengjiangWu
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 2:02 ` ShengjiangWu
@ 2015-12-23 2:07 ` Marek Vasut
2015-12-23 2:27 ` Chin Liang See
0 siblings, 1 reply; 26+ messages in thread
From: Marek Vasut @ 2015-12-23 2:07 UTC (permalink / raw)
To: u-boot
On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > -----Original Message-----
> > From: Marek Vasut [mailto:marex at denx.de]
> > Sent: Wednesday, December 23, 2015 9:25 AM
> > To: ?? ?
> > Cc: u-boot at lists.denx.de; clsee at altera.com;
> > dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de;
> > sr at denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on
> > socdk board
> >
> > On Wednesday, December 23, 2015 at 02:22:49 AM, ?? ? wrote:
> > > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
> > >
> > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > >
> > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > Updated QSPI clock.
> > > >
> > > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > > Cc: Chin Liang See <clsee@altera.com>
> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > > Cc: Pavel Machek <pavel@denx.de>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Stefan Roese <sr@denx.de>
> > >
> > > Applied, thanks.
> > >
> > > I will push your patches to [1] in a few hours, can you try and see if
> > > the CV SOCDK works fine for you? Thanks
> > >
> > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > socfpga.git;a=shortlog;h=refs/heads/master
> > >
> > > Pushed. Please let me know how SoCDK works for you now and if there
> > > are still some problems.
> > >
> > >
> > > Best regards,
> > > Marek Vasut
> > >
> > >
> > > Hi Marek,
> > >
> > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > works. Below is log.
> >
> > Good! so we're happy ? Can you give USB a spin too? I think it might have
> > some issues and I don't have the necessary cable here.
> >
> > [...]
> >
> > Best regards,
> > Marek Vasut
>
> Hi Marek,
>
> Yes, emac1 and qspi are working now. I'm afraid USB is not working,
>
> => usb reset
> resetting USB...
> USB0: Core Release: 2.93a
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> scanning bus 0 for devices... 1 USB Device(s) found
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA)
> U-Boot Root Hub
Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 1:24 ` Marek Vasut
@ 2015-12-23 2:02 ` ShengjiangWu
2015-12-23 2:07 ` Marek Vasut
0 siblings, 1 reply; 26+ messages in thread
From: ShengjiangWu @ 2015-12-23 2:02 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Wednesday, December 23, 2015 9:25 AM
> To: ?? ?
> Cc: u-boot at lists.denx.de; clsee at altera.com; dinguyen at opensource.altera.com; dinh.linux at gmail.com; pavel at denx.de; sr at denx.de
> Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
>
> On Wednesday, December 23, 2015 at 02:22:49 AM, ?? ? wrote:
> > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
> >
> > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> >
> > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > Updated QSPI clock.
> > >
> > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > Cc: Chin Liang See <clsee@altera.com>
> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > Cc: Pavel Machek <pavel@denx.de>
> > > Cc: Marek Vasut <marex@denx.de>
> > > Cc: Stefan Roese <sr@denx.de>
> >
> > Applied, thanks.
> >
> > I will push your patches to [1] in a few hours, can you try and see if
> > the CV SOCDK works fine for you? Thanks
> >
> > [1] http://git.denx.de/?p=u-boot/u-boot-
> > socfpga.git;a=shortlog;h=refs/heads/master
> >
> > Pushed. Please let me know how SoCDK works for you now and if there
> > are still some problems.
> >
> >
> > Best regards,
> > Marek Vasut
> >
> >
> > Hi Marek,
> >
> > Thank you for your help, I tested the master branch, emac1 and QSPI
> > works. Below is log.
>
> Good! so we're happy ? Can you give USB a spin too? I think it might have some issues and I don't have the necessary cable here.
>
> [...]
>
> Best regards,
> Marek Vasut
Hi Marek,
Yes, emac1 and qspi are working now. I'm afraid USB is not working,
=> usb reset
resetting USB...
USB0: Core Release: 2.93a
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
dwc_otg_core_host_init: Timeout!
scanning bus 0 for devices... 1 USB Device(s) found
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
U-Boot Root Hub
=>
Best Regards,
ShengjiangWu
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
[not found] <18c117d0-3bdb-4cf8-972a-35711ec3eacf@me.com>
@ 2015-12-23 1:26 ` Marek Vasut
0 siblings, 0 replies; 26+ messages in thread
From: Marek Vasut @ 2015-12-23 1:26 UTC (permalink / raw)
To: u-boot
On Wednesday, December 23, 2015 at 02:25:29 AM, ?? ? wrote:
> On Dec 22, 2015, at 05:22 PM, ?? ? <shengjiangwu@icloud.com> wrote:
>
>
>
> On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
>
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
>
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> >
> > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > Cc: Chin Liang See <clsee@altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Stefan Roese <sr@denx.de>
>
> Applied, thanks.
>
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
>
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
>
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
>
>
> Best regards,
> Marek Vasut
>
>
> Hi Marek,
>
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.
>
> Best Regards,
> ShengjiangWu
>
> => reset
> resetting ...
>
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
>
>
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
>
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0 at ff704000: 0
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet at ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot: 0
> => env default -a
> ## Resetting to default environment
> => setenv netmask 255.255.254.0
> => setenv gatewayip 128.224.98.1
> => setenv ipaddr 128.224.98.85
> => setenv serverip 128.224.99.137
> => setenv ethaddr 00:04:9f:13:57:b4
> => saveenv
> Saving Environment to MMC...
> Writing to MMC(0)... done
> => reset
> resetting ...
>
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
>
>
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
>
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0 at ff704000: 0
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net: eth0: ethernet at ff702000
> Hit any key to stop autoboot: 0
> => tftp 0x8000000 /tftpboot/altera/uVxWorks
> Speed: 100, full duplex
> Using ethernet at ff702000 device
> TFTP from server 128.224.99.137; our IP address is 128.224.98.85
> Filename '/tftpboot/altera/uVxWorks'.
> Load address: 0x8000000
> Loading: #################################################################
> #################################################################
> #################################################################
> #################################################################
> #################################################################
> #################################################################
> ################################################
> 3.3 MiB/s
> done
> Bytes transferred = 6418496 (61f040 hex)
> => sf probe
> SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total
> 128 MiB => sf read 0x7000000 0 0x60000
> device 0 offset 0x0, size 0x60000
> SF: 393216 bytes @ 0x0 Read: OK
> => md 0x7000000
> 07000000: ea00001a e59ff014 e59ff014 e59ff014 ................
> 07000010: e59ff014 e59ff014 e59ff014 e59ff014 ................
> 07000020: ffff0020 ffff0024 ffff0028 ffff002c ...$...(...,...
> 07000030: ffff0030 ffff0100 ffff0038 12345678 0.......8...xV4.
> 07000040: 31305341 2e160000 01390000 ea000007 AS01......9.....
> 07000050: 01000040 0000b854 0000b854 0000b900 @...T...T.......
> 07000060: 0000b854 0badc0de 0badc0de 0badc0de T...............
> 07000070: eb000040 e10f0000 e3c0001f e38000d3 @...............
> 07000080: e129f000 ee110f10 e3c00a02 ee010f10 ..).............
> 07000090: e59f00a8 ee0c0f10 eb000008 eb000015 ................
> 070000a0: eb000690 ee070f15 ee070f9a ee070f95 ................
> 070000b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ........../.../.
> 070000c0: e3a00000 ee080f17 ee070f15 ee070fd5 ................
> 070000d0: ee070f9a ee070f95 ee110f10 e3c00a02 ................
> 070000e0: e3c00007 e3800002 e3800b02 e3800a01 ................
> 070000f0: ee010f10 e1a0f00e ea000018 e320f000 .............. .
> =>
>
> BTW, I tested on master branch of u-boot-socfpga, not SoCDK.
Oh yeah, CV socdk is the abbreviation for "cyclone v soc development kit".
btw can you please fix your mailer so it adds ">" before the quoted text?
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-23 1:22 圣江 吴
@ 2015-12-23 1:24 ` Marek Vasut
2015-12-23 2:02 ` ShengjiangWu
0 siblings, 1 reply; 26+ messages in thread
From: Marek Vasut @ 2015-12-23 1:24 UTC (permalink / raw)
To: u-boot
On Wednesday, December 23, 2015 at 02:22:49 AM, ?? ? wrote:
> On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
>
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
>
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> >
> > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > Cc: Chin Liang See <clsee@altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Stefan Roese <sr@denx.de>
>
> Applied, thanks.
>
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
>
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
>
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
>
>
> Best regards,
> Marek Vasut
>
>
> Hi Marek,
>
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.
Good! so we're happy ? Can you give USB a spin too? I think it might have
some issues and I don't have the necessary cable here.
[...]
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
@ 2015-12-23 1:22 圣江 吴
2015-12-23 1:24 ` Marek Vasut
0 siblings, 1 reply; 26+ messages in thread
From: 圣江 吴 @ 2015-12-23 1:22 UTC (permalink / raw)
To: u-boot
On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex@denx.de> wrote:
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the
CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still
some problems.
Best regards,
Marek Vasut
Hi Marek,
Thank you for your help, I tested the master branch, emac1 and QSPI works.?Below is log.
Best Regards,
ShengjiangWu
=> reset
resetting ...
U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC
U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC External Transceiver (1.8V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0 at ff704000: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet at ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
=> env default -a
## Resetting to default environment
=> setenv netmask 255.255.254.0
=> setenv gatewayip 128.224.98.1
=> setenv ipaddr 128.224.98.85
=> setenv serverip 128.224.99.137
=> setenv ethaddr 00:04:9f:13:57:b4
=> saveenv
Saving Environment to MMC...
Writing to MMC(0)... done
=> reset
resetting ...
U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC
U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC External Transceiver (1.8V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0 at ff704000: 0
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net: eth0: ethernet at ff702000
Hit any key to stop autoboot: 0
=> tftp 0x8000000 /tftpboot/altera/uVxWorks
Speed: 100, full duplex
Using ethernet at ff702000 device
TFTP from server 128.224.99.137; our IP address is 128.224.98.85
Filename '/tftpboot/altera/uVxWorks'.
Load address: 0x8000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
################################################
3.3 MiB/s
done
Bytes transferred = 6418496 (61f040 hex)
=> sf probe
SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total 128 MiB
=> sf read 0x7000000 0 0x60000
device 0 offset 0x0, size 0x60000
SF: 393216 bytes @ 0x0 Read: OK
=> md 0x7000000
07000000: ea00001a e59ff014 e59ff014 e59ff014 ................
07000010: e59ff014 e59ff014 e59ff014 e59ff014 ................
07000020: ffff0020 ffff0024 ffff0028 ffff002c ...$...(...,...
07000030: ffff0030 ffff0100 ffff0038 12345678 0.......8...xV4.
07000040: 31305341 2e160000 01390000 ea000007 AS01......9.....
07000050: 01000040 0000b854 0000b854 0000b900 @...T...T.......
07000060: 0000b854 0badc0de 0badc0de 0badc0de T...............
07000070: eb000040 e10f0000 e3c0001f e38000d3 @...............
07000080: e129f000 ee110f10 e3c00a02 ee010f10 ..).............
07000090: e59f00a8 ee0c0f10 eb000008 eb000015 ................
070000a0: eb000690 ee070f15 ee070f9a ee070f95 ................
070000b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ........../.../.
070000c0: e3a00000 ee080f17 ee070f15 ee070fd5 ................
070000d0: ee070f9a ee070f95 ee110f10 e3c00a02 ................
070000e0: e3c00007 e3800002 e3800b02 e3800a01 ................
070000f0: ee010f10 e1a0f00e ea000018 e320f000 .............. .
=>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-22 20:19 ` Marek Vasut
@ 2015-12-22 20:33 ` Marek Vasut
0 siblings, 0 replies; 26+ messages in thread
From: Marek Vasut @ 2015-12-22 20:33 UTC (permalink / raw)
To: u-boot
On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> >
> > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > Cc: Chin Liang See <clsee@altera.com>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Stefan Roese <sr@denx.de>
>
> Applied, thanks.
>
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
>
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
Pushed. Please let me know how SoCDK works for you now and if there are still
some problems.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-22 9:18 shengjiangwu
2015-12-22 9:36 ` Chin Liang See
@ 2015-12-22 20:19 ` Marek Vasut
2015-12-22 20:33 ` Marek Vasut
1 sibling, 1 reply; 26+ messages in thread
From: Marek Vasut @ 2015-12-22 20:19 UTC (permalink / raw)
To: u-boot
On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
Applied, thanks.
I will push your patches to [1] in a few hours, can you try and see if the
CV SOCDK works fine for you? Thanks
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-22 9:18 shengjiangwu
@ 2015-12-22 9:36 ` Chin Liang See
2015-12-22 20:19 ` Marek Vasut
1 sibling, 0 replies; 26+ messages in thread
From: Chin Liang See @ 2015-12-22 9:36 UTC (permalink / raw)
To: u-boot
On Tue, 2015-12-22 at 17:18 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> ---
> board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------
> board/altera/cyclone5-socdk/qts/pll_config.h | 2 +-
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
Acked-by: Chin Liang See <clsee@altera.com>
Thanks
Chin Liang
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
@ 2015-12-22 9:18 shengjiangwu
2015-12-22 9:36 ` Chin Liang See
2015-12-22 20:19 ` Marek Vasut
0 siblings, 2 replies; 26+ messages in thread
From: shengjiangwu @ 2015-12-22 9:18 UTC (permalink / raw)
To: u-boot
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------
board/altera/cyclone5-socdk/qts/pll_config.h | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
2, /* MIXED1IO12 */
2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 9e336e3..4abd2e0 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
--
1.7.9.5
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-21 10:41 ` Pavel Machek
@ 2015-12-21 14:49 ` Marek Vasut
0 siblings, 0 replies; 26+ messages in thread
From: Marek Vasut @ 2015-12-21 14:49 UTC (permalink / raw)
To: u-boot
On Monday, December 21, 2015 at 11:41:24 AM, Pavel Machek wrote:
> On Mon 2015-12-21 11:12:29, Marek Vasut wrote:
> > On Monday, December 21, 2015 at 10:37:23 AM, Pavel Machek wrote:
> > > On Mon 2015-12-21 07:33:34, ?? ? wrote:
> > > > Hi Marek Vasut,
> > > >
> > > >
> > > > On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
> > > >
> > > > On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> > > > Hi Chin,
> > > >
> > > > The PLL settings are copied from previous version
> > > > http://git.rocketboards.org/u-boot-socfpga.git,
> > > >
> > > > This stuff should be generated by quartus, so why are you copying it
> > > > from some random version of u-boot somewhere ?
> > > >
> > > > Thank you for your comment, if this configuration
> > > > is automatically generated by Quartus without manually modification,
> > > > then I would like to withdraw this patch.
> > >
> > > No, please don't. socdk should work out of the box.
> >
> > SoCDK works out of the box last time I checked (2016.01rc1), did you test
> > it recently and do you observe problems ?
>
> Did you test QSPI? Because that is what subject claims does not work.
I'd have to retest that one, I only recall it booted and the basic functionality
was OK. Feel free to test QSPI again, that'd be actually helpful.
> > > I should not need
> > > quartus to build a working u-boot spl for the board.
> >
> > You DO need quartus to generate the header files (that go into
> > board/nnn/qts) to build working U-Boot SPL for any board. I fail to
> > understand your comment, sorry.
>
> Ok, lets talk about this personally or over phone.
Please stick to the ML.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-21 10:12 ` Marek Vasut
@ 2015-12-21 10:41 ` Pavel Machek
2015-12-21 14:49 ` Marek Vasut
0 siblings, 1 reply; 26+ messages in thread
From: Pavel Machek @ 2015-12-21 10:41 UTC (permalink / raw)
To: u-boot
On Mon 2015-12-21 11:12:29, Marek Vasut wrote:
> On Monday, December 21, 2015 at 10:37:23 AM, Pavel Machek wrote:
> > On Mon 2015-12-21 07:33:34, ?? ? wrote:
> > > Hi Marek Vasut,
> > >
> > >
> > > On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
> > >
> > > On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> > > Hi Chin,
> > >
> > > The PLL settings are copied from previous version
> > > http://git.rocketboards.org/u-boot-socfpga.git,
> > >
> > > This stuff should be generated by quartus, so why are you copying it from
> > > some random version of u-boot somewhere ?
> > >
> > > Thank you for your comment, if this configuration
> > > is automatically generated by Quartus without manually modification,
> > > then I would like to withdraw this patch.
> >
> > No, please don't. socdk should work out of the box.
>
> SoCDK works out of the box last time I checked (2016.01rc1), did you test it
> recently and do you observe problems ?
Did you test QSPI? Because that is what subject claims does not work.
> > I should not need
> > quartus to build a working u-boot spl for the board.
>
> You DO need quartus to generate the header files (that go into board/nnn/qts)
> to build working U-Boot SPL for any board. I fail to understand your comment,
> sorry.
Ok, lets talk about this personally or over phone.
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-21 9:56 ` Chin Liang See
@ 2015-12-21 10:12 ` Marek Vasut
0 siblings, 0 replies; 26+ messages in thread
From: Marek Vasut @ 2015-12-21 10:12 UTC (permalink / raw)
To: u-boot
On Monday, December 21, 2015 at 10:56:14 AM, Chin Liang See wrote:
> On Mon, 2015-12-21 at 10:37 +0100, Pavel Machek wrote:
> > On Mon 2015-12-21 07:33:34, ?? ? wrote:
> > > Hi Marek Vasut,
> > >
> > >
> > > On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
> > >
> > > On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> > > Hi Chin,
> > >
> > > The PLL settings are copied from previous version
> > > http://git.rocketboards.org/u-boot-socfpga.git,
> > >
> > > This stuff should be generated by quartus, so why are you copying
> > > it from
> > > some random version of u-boot somewhere ?
> > >
> > > Thank you for your comment, if this configuration is automatically
> > >
> > > generated by Quartus without manually modification, then I would
> > >
> > > like to withdraw this patch.
> >
> > No, please don't. socdk should work out of the box. I should not need
> > quartus to build a working u-boot spl for the board.
>
> Yah, let's upstream this. I believe the advise here is that we use the
> handoff file from quartus as a golden reference.
The ones in mainline are from GHRD I believe.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-21 9:37 ` Pavel Machek
2015-12-21 9:56 ` Chin Liang See
@ 2015-12-21 10:12 ` Marek Vasut
2015-12-21 10:41 ` Pavel Machek
1 sibling, 1 reply; 26+ messages in thread
From: Marek Vasut @ 2015-12-21 10:12 UTC (permalink / raw)
To: u-boot
On Monday, December 21, 2015 at 10:37:23 AM, Pavel Machek wrote:
> On Mon 2015-12-21 07:33:34, ?? ? wrote:
> > Hi Marek Vasut,
> >
> >
> > On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
> >
> > On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> > Hi Chin,
> >
> > The PLL settings are copied from previous version
> > http://git.rocketboards.org/u-boot-socfpga.git,
> >
> > This stuff should be generated by quartus, so why are you copying it from
> > some random version of u-boot somewhere ?
> >
> > Thank you for your comment, if this configuration
> > is automatically generated by Quartus without manually modification,
> > then I would like to withdraw this patch.
>
> No, please don't. socdk should work out of the box.
SoCDK works out of the box last time I checked (2016.01rc1), did you test it
recently and do you observe problems ?
> I should not need
> quartus to build a working u-boot spl for the board.
You DO need quartus to generate the header files (that go into board/nnn/qts)
to build working U-Boot SPL for any board. I fail to understand your comment,
sorry.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-21 9:37 ` Pavel Machek
@ 2015-12-21 9:56 ` Chin Liang See
2015-12-21 10:12 ` Marek Vasut
2015-12-21 10:12 ` Marek Vasut
1 sibling, 1 reply; 26+ messages in thread
From: Chin Liang See @ 2015-12-21 9:56 UTC (permalink / raw)
To: u-boot
On Mon, 2015-12-21 at 10:37 +0100, Pavel Machek wrote:
> On Mon 2015-12-21 07:33:34, ?? ? wrote:
> > Hi Marek Vasut,
> >
> >
> > On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
> >
> > On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> > Hi Chin,
> >
> > The PLL settings are copied from previous version
> > http://git.rocketboards.org/u-boot-socfpga.git,
> >
> > This stuff should be generated by quartus, so why are you copying
> > it from
> > some random version of u-boot somewhere ?
>
> > Thank you for your comment, if this configuration is automatically
> > generated by Quartus without manually modification, then I would
> > like to withdraw this patch.
> >
>
> No, please don't. socdk should work out of the box. I should not need
> quartus to build a working u-boot spl for the board.
>
Yah, let's upstream this. I believe the advise here is that we use the
handoff file from quartus as a golden reference.
Thanks
Chin Liang
>
> Pavel
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-21 7:33 圣江 吴
@ 2015-12-21 9:37 ` Pavel Machek
2015-12-21 9:56 ` Chin Liang See
2015-12-21 10:12 ` Marek Vasut
0 siblings, 2 replies; 26+ messages in thread
From: Pavel Machek @ 2015-12-21 9:37 UTC (permalink / raw)
To: u-boot
On Mon 2015-12-21 07:33:34, ?? ? wrote:
> Hi Marek Vasut,
>
>
> On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
>
> On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> Hi Chin,
>
> The PLL settings are copied from previous version
> http://git.rocketboards.org/u-boot-socfpga.git,
>
> This stuff should be generated by quartus, so why are you copying it from
> some random version of u-boot somewhere ?
> Thank you for your comment, if this configuration is?automatically?generated by Quartus without manually modification, then I would like to withdraw this patch.
>
No, please don't. socdk should work out of the box. I should not need
quartus to build a working u-boot spl for the board.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
@ 2015-12-21 7:33 圣江 吴
2015-12-21 9:37 ` Pavel Machek
0 siblings, 1 reply; 26+ messages in thread
From: 圣江 吴 @ 2015-12-21 7:33 UTC (permalink / raw)
To: u-boot
Hi Marek Vasut,
On Dec 18, 2015, at 04:50 AM, Marek Vasut <marex@denx.de> wrote:
On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
Hi Chin,
The PLL settings are copied from previous version
http://git.rocketboards.org/u-boot-socfpga.git,
This stuff should be generated by quartus, so why are you copying it from
some random version of u-boot somewhere ?
Thank you for your comment, if this configuration is?automatically?generated by Quartus without manually modification, then I would like to withdraw this patch.
Best Regards,
Shengjiang Wu
?
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
2015-12-18 7:57 圣江 吴
@ 2015-12-18 12:37 ` Marek Vasut
0 siblings, 0 replies; 26+ messages in thread
From: Marek Vasut @ 2015-12-18 12:37 UTC (permalink / raw)
To: u-boot
On Friday, December 18, 2015 at 08:57:22 AM, ?? ? wrote:
> Hi Chin,
>
> The PLL settings are copied from previous version
> http://git.rocketboards.org/u-boot-socfpga.git,
This stuff should be generated by quartus, so why are you copying it from
some random version of u-boot somewhere ?
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
@ 2015-12-18 7:57 圣江 吴
2015-12-18 12:37 ` Marek Vasut
0 siblings, 1 reply; 26+ messages in thread
From: 圣江 吴 @ 2015-12-18 7:57 UTC (permalink / raw)
To: u-boot
Hi Chin,
The PLL settings are copied from?previous version http://git.rocketboards.org/u-boot-socfpga.git,?
On Dec 17, 2015, at 11:45 PM, Chin Liang See <clsee@altera.com> wrote:
Hi Shengjiang,
On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
? ? ? ?2, /* MIXED1IO12 */
? ? ? ?2, /* MIXED1IO13 */
? ? ? ?0, /* MIXED1IO14 */
- ? ? ? ?1, /* MIXED1IO15 */
- ? ? ? ?1, /* MIXED1IO16 */
- ? ? ? ?1, /* MIXED1IO17 */
- ? ? ? ?1, /* MIXED1IO18 */
- ? ? ? ?0, /* MIXED1IO19 */
- ? ? ? ?0, /* MIXED1IO20 */
+ ? ? ? ?3, /* MIXED1IO15 */
+ ? ? ? ?3, /* MIXED1IO16 */
+ ? ? ? ?3, /* MIXED1IO17 */
+ ? ? ? ?3, /* MIXED1IO18 */
+ ? ? ? ?3, /* MIXED1IO19 */
+ ? ? ? ?3, /* MIXED1IO20 */
? ? ? ?0, /* MIXED1IO21 */
? ? ? ?0, /* MIXED2IO0 */
?0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 42905f4..eccc705 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -32,7 +32,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
Let's not change this as we are using mainpll for QSPI clock. Besides
that, the QSPI perpll will yield 500MHz which exceed the 400MHz max
clock.
Thanks
Chin Liang
OK, I will restore CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT as 511
Thanks ShengjiangWu
?
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
^ permalink raw reply related [flat|nested] 26+ messages in thread
end of thread, other threads:[~2015-12-23 3:04 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-18 7:21 [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board shengjiangwu
2015-12-18 7:44 ` Chin Liang See
2015-12-18 7:57 圣江 吴
2015-12-18 12:37 ` Marek Vasut
2015-12-21 7:33 圣江 吴
2015-12-21 9:37 ` Pavel Machek
2015-12-21 9:56 ` Chin Liang See
2015-12-21 10:12 ` Marek Vasut
2015-12-21 10:12 ` Marek Vasut
2015-12-21 10:41 ` Pavel Machek
2015-12-21 14:49 ` Marek Vasut
2015-12-22 9:18 shengjiangwu
2015-12-22 9:36 ` Chin Liang See
2015-12-22 20:19 ` Marek Vasut
2015-12-22 20:33 ` Marek Vasut
2015-12-23 1:22 圣江 吴
2015-12-23 1:24 ` Marek Vasut
2015-12-23 2:02 ` ShengjiangWu
2015-12-23 2:07 ` Marek Vasut
2015-12-23 2:27 ` Chin Liang See
[not found] <18c117d0-3bdb-4cf8-972a-35711ec3eacf@me.com>
2015-12-23 1:26 ` Marek Vasut
2015-12-23 2:26 圣江 吴
2015-12-23 2:27 ` Marek Vasut
2015-12-23 2:29 ` Chin Liang See
2015-12-23 2:38 ` Chin Liang See
2015-12-23 3:04 ` Marek Vasut
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