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* [PATCH] drm/i915/skl: Default to noncoherent access up to F0
@ 2015-12-18 14:14 Mika Kuoppala
  2015-12-18 14:40 ` Francisco Jerez
  2015-12-18 14:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 2 replies; 3+ messages in thread
From: Mika Kuoppala @ 2015-12-18 14:14 UTC (permalink / raw)
  To: intel-gfx; +Cc: Ben Widawsky

The workarounds for disabling hdc invalidation and also forcing
context to be non coherent, are advised to be used up until rev D0.

However as it was found that rev F0, without the
WaForceEnableNonCoherent might system hang if the mesa
tried to use coherent mode.

As these two workarounds are about non coherent access, are
grouped in scope and they point the same HSD, increase the
scope of both to set default behaviour to non coherent access.

References: HSD: gen9lp/2131413
References: http://lists.freedesktop.org/archives/mesa-dev/2015-November/101515.html
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eefce9a3e9c8..339701d7a9a5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1018,10 +1018,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		return ret;
 
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
-		/* WaDisableHDCInvalidation:skl */
-		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-			   BDW_DISABLE_HDC_INVALIDATION);
-
 		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
 		I915_WRITE(FF_SLICE_CS_CHICKEN2,
 			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
@@ -1046,7 +1042,7 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(HIZ_CHICKEN,
 				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
-	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
+	if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
 		/*
 		 *Use Force Non-Coherent whenever executing a 3D context. This
 		 * is a workaround for a possible hang in the unlikely event
@@ -1055,6 +1051,10 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		/* WaForceEnableNonCoherent:skl */
 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
 				  HDC_FORCE_NON_COHERENT);
+
+		/* WaDisableHDCInvalidation:skl */
+		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+			   BDW_DISABLE_HDC_INVALIDATION);
 	}
 
 	/* WaBarrierPerformanceFixDisable:skl */
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915/skl: Default to noncoherent access up to F0
  2015-12-18 14:14 [PATCH] drm/i915/skl: Default to noncoherent access up to F0 Mika Kuoppala
@ 2015-12-18 14:40 ` Francisco Jerez
  2015-12-18 14:49 ` ✗ warning: Fi.CI.BAT Patchwork
  1 sibling, 0 replies; 3+ messages in thread
From: Francisco Jerez @ 2015-12-18 14:40 UTC (permalink / raw)
  To: Mika Kuoppala, intel-gfx; +Cc: Ben Widawsky


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Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> The workarounds for disabling hdc invalidation and also forcing
> context to be non coherent, are advised to be used up until rev D0.
>
> However as it was found that rev F0, without the
> WaForceEnableNonCoherent might system hang if the mesa
> tried to use coherent mode.
>
> As these two workarounds are about non coherent access, are
> grouped in scope and they point the same HSD, increase the
> scope of both to set default behaviour to non coherent access.
>
> References: HSD: gen9lp/2131413
> References: http://lists.freedesktop.org/archives/mesa-dev/2015-November/101515.html
> Cc: Ben Widawsky <benjamin.widawsky@intel.com>
> Cc: Francisco Jerez <currojerez@riseup.net>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index eefce9a3e9c8..339701d7a9a5 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1018,10 +1018,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>  		return ret;
>  
>  	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
> -		/* WaDisableHDCInvalidation:skl */
> -		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> -			   BDW_DISABLE_HDC_INVALIDATION);
> -
>  		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
>  		I915_WRITE(FF_SLICE_CS_CHICKEN2,
>  			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
> @@ -1046,7 +1042,7 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>  		WA_SET_BIT_MASKED(HIZ_CHICKEN,
>  				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>  
> -	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
> +	if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
>  		/*
>  		 *Use Force Non-Coherent whenever executing a 3D context. This
>  		 * is a workaround for a possible hang in the unlikely event
> @@ -1055,6 +1051,10 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>  		/* WaForceEnableNonCoherent:skl */
>  		WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  				  HDC_FORCE_NON_COHERENT);
> +
> +		/* WaDisableHDCInvalidation:skl */
> +		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> +			   BDW_DISABLE_HDC_INVALIDATION);

Looks good to me,

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

>  	}
>  
>  	/* WaBarrierPerformanceFixDisable:skl */
> -- 
> 2.5.0

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 3+ messages in thread
* ✗ warning: Fi.CI.BAT
  2015-12-18 14:14 [PATCH] drm/i915/skl: Default to noncoherent access up to F0 Mika Kuoppala
  2015-12-18 14:40 ` Francisco Jerez
@ 2015-12-18 14:49 ` Patchwork
  1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2015-12-18 14:49 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

== Summary ==

Built on da33ddbb03875d7e1e5f06ac445368f97dcc3488 drm-intel-nightly: 2015y-12m-18d-13h-53m-06s UTC integration manifest

Test gem_mmap_gtt:
        Subgroup basic-write-no-prefault:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                dmesg-warn -> PASS       (skl-i5k-2)
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> DMESG-WARN (bsw-nuc-2)
                fail       -> PASS       (ilk-hp8440p)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a:
                dmesg-warn -> PASS       (snb-x220t)
                pass       -> DMESG-WARN (snb-dellxps)
        Subgroup read-crc-pipe-b-frame-sequence:
                dmesg-warn -> PASS       (byt-nuc)
        Subgroup read-crc-pipe-c:
                pass       -> DMESG-WARN (bdw-ultra)
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (snb-x220t)
                pass       -> DMESG-WARN (bdw-nuci7)
                dmesg-warn -> PASS       (skl-i7k-2)
                skip       -> PASS       (byt-nuc)
Test kms_setmode:
        Subgroup basic-clone-single-crtc:
                dmesg-warn -> PASS       (snb-dellxps)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                dmesg-warn -> PASS       (bdw-ultra)

bdw-nuci7        total:135  pass:124  dwarn:2   dfail:0   fail:0   skip:9  
bdw-ultra        total:132  pass:124  dwarn:2   dfail:0   fail:0   skip:6  
bsw-nuc-2        total:135  pass:113  dwarn:2   dfail:0   fail:0   skip:20 
byt-nuc          total:135  pass:121  dwarn:1   dfail:0   fail:0   skip:13 
hsw-brixbox      total:135  pass:127  dwarn:1   dfail:0   fail:0   skip:7  
hsw-gt2          total:135  pass:130  dwarn:1   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:135  pass:100  dwarn:0   dfail:0   fail:0   skip:35 
ivb-t430s        total:135  pass:127  dwarn:2   dfail:0   fail:0   skip:6  
skl-i5k-2        total:135  pass:123  dwarn:4   dfail:0   fail:0   skip:8  
skl-i7k-2        total:135  pass:124  dwarn:3   dfail:0   fail:0   skip:8  
snb-dellxps      total:135  pass:121  dwarn:2   dfail:0   fail:0   skip:12 
snb-x220t        total:135  pass:121  dwarn:2   dfail:0   fail:1   skip:11 

Results at /archive/results/CI_IGT_test/Patchwork_719/

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 3+ messages in thread
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2015-12-18 14:14 [PATCH] drm/i915/skl: Default to noncoherent access up to F0 Mika Kuoppala
2015-12-18 14:40 ` Francisco Jerez
2015-12-18 14:49 ` ✗ warning: Fi.CI.BAT Patchwork

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