* [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size()
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
@ 2015-12-18 20:00 ` yu.dai
2016-01-05 10:27 ` Daniel Vetter
2016-01-05 18:33 ` [PATCH v3] " yu.dai
2015-12-18 20:00 ` [PATCH v2 2/5] drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation yu.dai
` (7 subsequent siblings)
8 siblings, 2 replies; 17+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
To: intel-gfx
From: Dave Gordon <david.s.gordon@intel.com>
The GuC code needs to know the size of a logical context, so we
expose get_lr_context_size(), renaming it intel_lr_context__size()
to fit the naming conventions for nonstatic functions.
For: VIZ-2021
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e5fb8ea..7a6b896 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2399,7 +2399,7 @@ void intel_lr_context_free(struct intel_context *ctx)
}
}
-static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
+uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
{
int ret = 0;
@@ -2467,7 +2467,7 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
WARN_ON(ctx->engine[ring->id].state);
- context_size = round_up(get_lr_context_size(ring), 4096);
+ context_size = round_up(intel_lr_context_size(ring), 4096);
/* One extra page as the sharing data between driver and GuC */
context_size += PAGE_SIZE * LRC_PPHWSP_PN;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 0b821b9..ae90f86 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -84,6 +84,7 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
void intel_lr_context_free(struct intel_context *ctx);
+uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
int intel_lr_context_deferred_alloc(struct intel_context *ctx,
struct intel_engine_cs *ring);
void intel_lr_context_unpin(struct drm_i915_gem_request *req);
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size()
2015-12-18 20:00 ` [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size() yu.dai
@ 2016-01-05 10:27 ` Daniel Vetter
2016-01-05 12:21 ` [PATCH] drm/i915: add kerneldoc for intel_lr_context_size() Dave Gordon
2016-01-05 18:35 ` [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size() Yu Dai
2016-01-05 18:33 ` [PATCH v3] " yu.dai
1 sibling, 2 replies; 17+ messages in thread
From: Daniel Vetter @ 2016-01-05 10:27 UTC (permalink / raw)
To: yu.dai; +Cc: intel-gfx
On Fri, Dec 18, 2015 at 12:00:08PM -0800, yu.dai@intel.com wrote:
> From: Dave Gordon <david.s.gordon@intel.com>
>
> The GuC code needs to know the size of a logical context, so we
> expose get_lr_context_size(), renaming it intel_lr_context__size()
> to fit the naming conventions for nonstatic functions.
>
> For: VIZ-2021
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index e5fb8ea..7a6b896 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2399,7 +2399,7 @@ void intel_lr_context_free(struct intel_context *ctx)
> }
> }
>
> -static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
> +uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
As a rule of thumb, non-static functions should have kerneldoc within
drm/i915. At least in the files where we bothered with kerneldoc already.
Please do a follow-up patch to remedy this.
Thanks, Daniel
> {
> int ret = 0;
>
> @@ -2467,7 +2467,7 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
> WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
> WARN_ON(ctx->engine[ring->id].state);
>
> - context_size = round_up(get_lr_context_size(ring), 4096);
> + context_size = round_up(intel_lr_context_size(ring), 4096);
>
> /* One extra page as the sharing data between driver and GuC */
> context_size += PAGE_SIZE * LRC_PPHWSP_PN;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 0b821b9..ae90f86 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -84,6 +84,7 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
> #define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
>
> void intel_lr_context_free(struct intel_context *ctx);
> +uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
> int intel_lr_context_deferred_alloc(struct intel_context *ctx,
> struct intel_engine_cs *ring);
> void intel_lr_context_unpin(struct drm_i915_gem_request *req);
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH] drm/i915: add kerneldoc for intel_lr_context_size()
2016-01-05 10:27 ` Daniel Vetter
@ 2016-01-05 12:21 ` Dave Gordon
2016-01-05 13:57 ` Daniel Vetter
2016-01-05 18:35 ` [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size() Yu Dai
1 sibling, 1 reply; 17+ messages in thread
From: Dave Gordon @ 2016-01-05 12:21 UTC (permalink / raw)
To: intel-gfx
This function was recently renamed & exposed, so now it gets documented
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8da67b3..3662d14 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2386,6 +2386,20 @@ void intel_lr_context_free(struct intel_context *ctx)
}
}
+/**
+ * intel_lr_context_size() - return the size of the context for an engine
+ * @ring: which engine to find the context size for
+ *
+ * Each engine may require a different amount of space for a context image,
+ * so when allocating (or copying) an image, this function can be used to
+ * find the right size for the specific engine.
+ *
+ * Return: size (in bytes) of an engine-specific context image
+ *
+ * Note: this size includes the HWSP, which is part of the context image
+ * in LRC mode, but does not include the "shared data page" used with
+ * GuC submission. The caller should account for this if using the GuC.
+ */
uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
{
int ret = 0;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: add kerneldoc for intel_lr_context_size()
2016-01-05 12:21 ` [PATCH] drm/i915: add kerneldoc for intel_lr_context_size() Dave Gordon
@ 2016-01-05 13:57 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2016-01-05 13:57 UTC (permalink / raw)
To: Dave Gordon; +Cc: intel-gfx
On Tue, Jan 05, 2016 at 12:21:33PM +0000, Dave Gordon wrote:
> This function was recently renamed & exposed, so now it gets documented
>
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 8da67b3..3662d14 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2386,6 +2386,20 @@ void intel_lr_context_free(struct intel_context *ctx)
> }
> }
>
> +/**
> + * intel_lr_context_size() - return the size of the context for an engine
> + * @ring: which engine to find the context size for
> + *
> + * Each engine may require a different amount of space for a context image,
> + * so when allocating (or copying) an image, this function can be used to
> + * find the right size for the specific engine.
> + *
> + * Return: size (in bytes) of an engine-specific context image
> + *
> + * Note: this size includes the HWSP, which is part of the context image
> + * in LRC mode, but does not include the "shared data page" used with
> + * GuC submission. The caller should account for this if using the GuC.
> + */
> uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
> {
> int ret = 0;
> --
> 1.9.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size()
2016-01-05 10:27 ` Daniel Vetter
2016-01-05 12:21 ` [PATCH] drm/i915: add kerneldoc for intel_lr_context_size() Dave Gordon
@ 2016-01-05 18:35 ` Yu Dai
1 sibling, 0 replies; 17+ messages in thread
From: Yu Dai @ 2016-01-05 18:35 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On 01/05/2016 02:27 AM, Daniel Vetter wrote:
> On Fri, Dec 18, 2015 at 12:00:08PM -0800, yu.dai@intel.com wrote:
> > From: Dave Gordon <david.s.gordon@intel.com>
> >
> > The GuC code needs to know the size of a logical context, so we
> > expose get_lr_context_size(), renaming it intel_lr_context__size()
> > to fit the naming conventions for nonstatic functions.
> >
> > For: VIZ-2021
> > Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index e5fb8ea..7a6b896 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -2399,7 +2399,7 @@ void intel_lr_context_free(struct intel_context *ctx)
> > }
> > }
> >
> > -static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
> > +uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
>
> As a rule of thumb, non-static functions should have kerneldoc within
> drm/i915. At least in the files where we bothered with kerneldoc already.
> Please do a follow-up patch to remedy this.
Thanks for the review. I submitted v3 to add some comments for
kerneldoc. The other patches of this series are not touched.
Thanks,
Alex
> > {
> > int ret = 0;
> >
> > @@ -2467,7 +2467,7 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
> > WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
> > WARN_ON(ctx->engine[ring->id].state);
> >
> > - context_size = round_up(get_lr_context_size(ring), 4096);
> > + context_size = round_up(intel_lr_context_size(ring), 4096);
> >
> > /* One extra page as the sharing data between driver and GuC */
> > context_size += PAGE_SIZE * LRC_PPHWSP_PN;
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> > index 0b821b9..ae90f86 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.h
> > +++ b/drivers/gpu/drm/i915/intel_lrc.h
> > @@ -84,6 +84,7 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
> > #define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
> >
> > void intel_lr_context_free(struct intel_context *ctx);
> > +uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
> > int intel_lr_context_deferred_alloc(struct intel_context *ctx,
> > struct intel_engine_cs *ring);
> > void intel_lr_context_unpin(struct drm_i915_gem_request *req);
> > --
> > 2.5.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3] drm/i915/guc: Expose (intel)_lr_context_size()
2015-12-18 20:00 ` [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size() yu.dai
2016-01-05 10:27 ` Daniel Vetter
@ 2016-01-05 18:33 ` yu.dai
2016-01-06 7:38 ` Daniel Vetter
1 sibling, 1 reply; 17+ messages in thread
From: yu.dai @ 2016-01-05 18:33 UTC (permalink / raw)
To: intel-gfx
From: Dave Gordon <david.s.gordon@intel.com>
The GuC code needs to know the size of a logical context, so we
expose get_lr_context_size(), renaming it intel_lr_context__size()
to fit the naming conventions for nonstatic functions.
Add comments or kerneldoc (Daniel Vetter)
For: VIZ-2021
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 13 +++++++++++--
drivers/gpu/drm/i915/intel_lrc.h | 1 +
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e095058..9be9835 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2399,7 +2399,16 @@ void intel_lr_context_free(struct intel_context *ctx)
}
}
-static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
+/**
+ * intel_lr_context_size() - get the LRC state pages size
+ * @ring: engine to be used to get ring id
+ *
+ * The LRC state pages size varies for different engines. This function is used
+ * in ExecList / GuC mode to get LRC state pages size.
+ *
+ * Return: size of the LRC state pages. zero on unknown engine.
+ */
+uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
{
int ret = 0;
@@ -2467,7 +2476,7 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
WARN_ON(ctx->engine[ring->id].state);
- context_size = round_up(get_lr_context_size(ring), 4096);
+ context_size = round_up(intel_lr_context_size(ring), 4096);
/* One extra page as the sharing data between driver and GuC */
context_size += PAGE_SIZE * LRC_PPHWSP_PN;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 0b821b9..ae90f86 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -84,6 +84,7 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
void intel_lr_context_free(struct intel_context *ctx);
+uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
int intel_lr_context_deferred_alloc(struct intel_context *ctx,
struct intel_engine_cs *ring);
void intel_lr_context_unpin(struct drm_i915_gem_request *req);
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v3] drm/i915/guc: Expose (intel)_lr_context_size()
2016-01-05 18:33 ` [PATCH v3] " yu.dai
@ 2016-01-06 7:38 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2016-01-06 7:38 UTC (permalink / raw)
To: yu.dai; +Cc: intel-gfx
On Tue, Jan 05, 2016 at 10:33:02AM -0800, yu.dai@intel.com wrote:
> From: Dave Gordon <david.s.gordon@intel.com>
>
> The GuC code needs to know the size of a logical context, so we
> expose get_lr_context_size(), renaming it intel_lr_context__size()
> to fit the naming conventions for nonstatic functions.
>
> Add comments or kerneldoc (Daniel Vetter)
>
> For: VIZ-2021
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
Dave Gordon was faster, I already pulled in his follow-up. Note that with
commit rights dinq became non-rebasing, so as soon as a patch landed it's
frozen. Only follow-up patches are possible with this new process.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 13 +++++++++++--
> drivers/gpu/drm/i915/intel_lrc.h | 1 +
> 2 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index e095058..9be9835 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2399,7 +2399,16 @@ void intel_lr_context_free(struct intel_context *ctx)
> }
> }
>
> -static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
> +/**
> + * intel_lr_context_size() - get the LRC state pages size
> + * @ring: engine to be used to get ring id
> + *
> + * The LRC state pages size varies for different engines. This function is used
> + * in ExecList / GuC mode to get LRC state pages size.
> + *
> + * Return: size of the LRC state pages. zero on unknown engine.
> + */
> +uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
> {
> int ret = 0;
>
> @@ -2467,7 +2476,7 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
> WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
> WARN_ON(ctx->engine[ring->id].state);
>
> - context_size = round_up(get_lr_context_size(ring), 4096);
> + context_size = round_up(intel_lr_context_size(ring), 4096);
>
> /* One extra page as the sharing data between driver and GuC */
> context_size += PAGE_SIZE * LRC_PPHWSP_PN;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 0b821b9..ae90f86 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -84,6 +84,7 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
> #define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
>
> void intel_lr_context_free(struct intel_context *ctx);
> +uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
> int intel_lr_context_deferred_alloc(struct intel_context *ctx,
> struct intel_engine_cs *ring);
> void intel_lr_context_unpin(struct drm_i915_gem_request *req);
> --
> 2.5.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 2/5] drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
2015-12-18 20:00 ` [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size() yu.dai
@ 2015-12-18 20:00 ` yu.dai
2015-12-18 20:00 ` [PATCH v2 3/5] drm/i915/guc: Add GuC ADS - scheduler policies yu.dai
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
To: intel-gfx
From: Alex Dai <yu.dai@intel.com>
The GuC firmware uses this for various purposes. The ADS itself is
a chunk of memory created by driver to share with GuC. Its members
are usually addresses telling where GuC to access them, including
things like scheduler policies, register list that will be saved
and restored during reset etc.
This is the first patch of a series to enable GuC ADS. For now, we
only create the ADS obj whilst keep it disabled.
v1: remove dead code checking return of kmap_atomic (Chris Wilson)
v2: use kmap instead of the atomic version of it.
Signed-off-by: Alex Dai <yu.dai@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 90a84b4..8d27c09 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -40,6 +40,7 @@
#define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT)
#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
+#define SOFT_SCRATCH_COUNT 16
#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_MAX_COUNT 64
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 7554d16..d9b9390 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -842,6 +842,46 @@ static void guc_create_log(struct intel_guc *guc)
guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
}
+static void guc_create_ads(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_gem_object *obj;
+ struct guc_ads *ads;
+ struct intel_engine_cs *ring;
+ struct page *page;
+ u32 size, i;
+
+ /* The ads obj includes the struct itself and buffers passed to GuC */
+ size = sizeof(struct guc_ads);
+
+ obj = guc->ads_obj;
+ if (!obj) {
+ obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size));
+ if (!obj)
+ return;
+
+ guc->ads_obj = obj;
+ }
+
+ page = i915_gem_object_get_page(obj, 0);
+ ads = kmap(page);
+
+ /*
+ * The GuC requires a "Golden Context" when it reinitialises
+ * engines after a reset. Here we use the Render ring default
+ * context, which must already exist and be pinned in the GGTT,
+ * so its address won't change after we've told the GuC where
+ * to find it.
+ */
+ ring = &dev_priv->ring[RCS];
+ ads->golden_context_lrca = ring->status_page.gfx_addr;
+
+ for_each_ring(ring, dev_priv, i)
+ ads->eng_state_size[i] = intel_lr_context_size(ring);
+
+ kunmap(page);
+}
+
/*
* Set up the memory resources to be shared with the GuC. At this point,
* we require just one object that can be mapped through the GGTT.
@@ -868,6 +908,8 @@ int i915_guc_submission_init(struct drm_device *dev)
guc_create_log(guc);
+ guc_create_ads(guc);
+
return 0;
}
@@ -906,6 +948,9 @@ void i915_guc_submission_fini(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_guc *guc = &dev_priv->guc;
+ gem_release_guc_obj(dev_priv->guc.ads_obj);
+ guc->ads_obj = NULL;
+
gem_release_guc_obj(dev_priv->guc.log_obj);
guc->log_obj = NULL;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 5cf555d..5c9f894 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -89,6 +89,8 @@ struct intel_guc {
uint32_t log_flags;
struct drm_i915_gem_object *log_obj;
+ struct drm_i915_gem_object *ads_obj;
+
struct drm_i915_gem_object *ctx_pool_obj;
struct ida ctx_ids;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index eaa50a4..76ecc85 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -81,11 +81,14 @@
#define GUC_CTL_CTXINFO 0
#define GUC_CTL_CTXNUM_IN16_SHIFT 0
#define GUC_CTL_BASE_ADDR_SHIFT 12
+
#define GUC_CTL_ARAT_HIGH 1
#define GUC_CTL_ARAT_LOW 2
+
#define GUC_CTL_DEVICE_INFO 3
#define GUC_CTL_GTTYPE_SHIFT 0
#define GUC_CTL_COREFAMILY_SHIFT 7
+
#define GUC_CTL_LOG_PARAMS 4
#define GUC_LOG_VALID (1 << 0)
#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
@@ -97,9 +100,12 @@
#define GUC_LOG_ISR_PAGES 3
#define GUC_LOG_ISR_SHIFT 9
#define GUC_LOG_BUF_ADDR_SHIFT 12
+
#define GUC_CTL_PAGE_FAULT_CONTROL 5
+
#define GUC_CTL_WA 6
#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
+
#define GUC_CTL_FEATURE 7
#define GUC_CTL_VCS2_ENABLED (1 << 0)
#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
@@ -109,6 +115,7 @@
#define GUC_CTL_PREEMPTION_LOG (1 << 5)
#define GUC_CTL_ENABLE_SLPC (1 << 7)
#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
+
#define GUC_CTL_DEBUG 8
#define GUC_LOG_VERBOSITY_SHIFT 0
#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
@@ -118,9 +125,19 @@
/* Verbosity range-check limits, without the shift */
#define GUC_LOG_VERBOSITY_MIN 0
#define GUC_LOG_VERBOSITY_MAX 3
+#define GUC_LOG_VERBOSITY_MASK 0x0000000f
+#define GUC_LOG_DESTINATION_MASK (3 << 4)
+#define GUC_LOG_DISABLED (1 << 6)
+#define GUC_PROFILE_ENABLED (1 << 7)
+#define GUC_WQ_TRACK_ENABLED (1 << 8)
+#define GUC_ADS_ENABLED (1 << 9)
+#define GUC_DEBUG_RESERVED (1 << 10)
+#define GUC_ADS_ADDR_SHIFT 11
+#define GUC_ADS_ADDR_MASK 0xfffff800
+
#define GUC_CTL_RSRVD 9
-#define GUC_CTL_MAX_DWORDS (GUC_CTL_RSRVD + 1)
+#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
/**
* DOC: GuC Firmware Layout
@@ -299,6 +316,18 @@ struct guc_context_desc {
#define GUC_POWER_D2 3
#define GUC_POWER_D3 4
+/* GuC Additional Data Struct */
+
+struct guc_ads {
+ u32 reg_state_addr;
+ u32 reg_state_buffer;
+ u32 golden_context_lrca;
+ u32 scheduler_policies;
+ u32 reserved0[3];
+ u32 eng_state_size[I915_NUM_RINGS];
+ u32 reserved2[4];
+} __packed;
+
/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
enum host2guc_action {
HOST2GUC_ACTION_DEFAULT = 0x0,
--
2.5.0
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 3/5] drm/i915/guc: Add GuC ADS - scheduler policies
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
2015-12-18 20:00 ` [PATCH v2 1/5] drm/i915/guc: Expose (intel)_lr_context_size() yu.dai
2015-12-18 20:00 ` [PATCH v2 2/5] drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation yu.dai
@ 2015-12-18 20:00 ` yu.dai
2015-12-18 20:00 ` [PATCH v2 4/5] drm/i915/guc: Add GuC ADS - MMIO reg state yu.dai
` (5 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
To: intel-gfx
From: Alex Dai <yu.dai@intel.com>
GuC supports different scheduling policies for its four internal
queues. Currently these have been set to the same default values
as KMD_NORMAL queue.
Particularly POLICY_MAX_NUM_WI is set to 15 to match GuC internal
maximum submit queue numbers to avoid an out-of-space problem.
This value indicates max number of work items allowed to be queued
for one DPC process. A smaller value will let GuC schedule more
frequently while a larger number may increase chances to optimize
cmds (such as collapse cmds from same lrc) with risks that keeps
CS idle.
v1: tidy up code
Signed-off-by: Alex Dai <yu.dai@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index d9b9390..31a407b 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -842,17 +842,40 @@ static void guc_create_log(struct intel_guc *guc)
guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
}
+static void init_guc_policies(struct guc_policies *policies)
+{
+ struct guc_policy *policy;
+ u32 p, i;
+
+ policies->dpc_promote_time = 500000;
+ policies->max_num_work_items = POLICY_MAX_NUM_WI;
+
+ for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
+ for (i = 0; i < I915_NUM_RINGS; i++) {
+ policy = &policies->policy[p][i];
+
+ policy->execution_quantum = 1000000;
+ policy->preemption_time = 500000;
+ policy->fault_time = 250000;
+ policy->policy_flags = 0;
+ }
+ }
+
+ policies->is_valid = 1;
+}
+
static void guc_create_ads(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct drm_i915_gem_object *obj;
struct guc_ads *ads;
+ struct guc_policies *policies;
struct intel_engine_cs *ring;
struct page *page;
u32 size, i;
/* The ads obj includes the struct itself and buffers passed to GuC */
- size = sizeof(struct guc_ads);
+ size = sizeof(struct guc_ads) + sizeof(struct guc_policies);
obj = guc->ads_obj;
if (!obj) {
@@ -879,6 +902,13 @@ static void guc_create_ads(struct intel_guc *guc)
for_each_ring(ring, dev_priv, i)
ads->eng_state_size[i] = intel_lr_context_size(ring);
+ /* GuC scheduling policies */
+ policies = (void *)ads + sizeof(struct guc_ads);
+ init_guc_policies(policies);
+
+ ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) +
+ sizeof(struct guc_ads);
+
kunmap(page);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 76ecc85..0cc17c7 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,7 @@
#define GUC_CTX_PRIORITY_HIGH 1
#define GUC_CTX_PRIORITY_KMD_NORMAL 2
#define GUC_CTX_PRIORITY_NORMAL 3
+#define GUC_CTX_PRIORITY_NUM 4
#define GUC_MAX_GPU_CONTEXTS 1024
#define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS
@@ -316,6 +317,50 @@ struct guc_context_desc {
#define GUC_POWER_D2 3
#define GUC_POWER_D3 4
+/* Scheduling policy settings */
+
+/* Reset engine upon preempt failure */
+#define POLICY_RESET_ENGINE (1<<0)
+/* Preempt to idle on quantum expiry */
+#define POLICY_PREEMPT_TO_IDLE (1<<1)
+
+#define POLICY_MAX_NUM_WI 15
+
+struct guc_policy {
+ /* Time for one workload to execute. (in micro seconds) */
+ u32 execution_quantum;
+ u32 reserved1;
+
+ /* Time to wait for a preemption request to completed before issuing a
+ * reset. (in micro seconds). */
+ u32 preemption_time;
+
+ /* How much time to allow to run after the first fault is observed.
+ * Then preempt afterwards. (in micro seconds) */
+ u32 fault_time;
+
+ u32 policy_flags;
+ u32 reserved[2];
+} __packed;
+
+struct guc_policies {
+ struct guc_policy policy[GUC_CTX_PRIORITY_NUM][I915_NUM_RINGS];
+
+ /* In micro seconds. How much time to allow before DPC processing is
+ * called back via interrupt (to prevent DPC queue drain starving).
+ * Typically 1000s of micro seconds (example only, not granularity). */
+ u32 dpc_promote_time;
+
+ /* Must be set to take these new values. */
+ u32 is_valid;
+
+ /* Max number of WIs to process per call. A large value may keep CS
+ * idle. */
+ u32 max_num_work_items;
+
+ u32 reserved[19];
+} __packed;
+
/* GuC Additional Data Struct */
struct guc_ads {
--
2.5.0
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 4/5] drm/i915/guc: Add GuC ADS - MMIO reg state
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
` (2 preceding siblings ...)
2015-12-18 20:00 ` [PATCH v2 3/5] drm/i915/guc: Add GuC ADS - scheduler policies yu.dai
@ 2015-12-18 20:00 ` yu.dai
2015-12-18 20:00 ` [PATCH v2 5/5] drm/i915/guc: Add GuC ADS - enabling ADS yu.dai
` (4 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
To: intel-gfx
From: Alex Dai <yu.dai@intel.com>
GuC needs to know which registers and how they will be saved and
restored during event such as engine reset or power state changes.
For now only the base address of reg state is initialized. The
detail register table probably will be setup in future GuC TDR or
Preemption patch series.
Signed-off-by: Alex Dai <yu.dai@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 31a407b..40cb4ba 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -870,12 +870,15 @@ static void guc_create_ads(struct intel_guc *guc)
struct drm_i915_gem_object *obj;
struct guc_ads *ads;
struct guc_policies *policies;
+ struct guc_mmio_reg_state *reg_state;
struct intel_engine_cs *ring;
struct page *page;
u32 size, i;
/* The ads obj includes the struct itself and buffers passed to GuC */
- size = sizeof(struct guc_ads) + sizeof(struct guc_policies);
+ size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
+ sizeof(struct guc_mmio_reg_state) +
+ GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
obj = guc->ads_obj;
if (!obj) {
@@ -909,6 +912,23 @@ static void guc_create_ads(struct intel_guc *guc)
ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) +
sizeof(struct guc_ads);
+ /* MMIO reg state */
+ reg_state = (void *)policies + sizeof(struct guc_policies);
+
+ for (i = 0; i < I915_NUM_RINGS; i++) {
+ reg_state->mmio_white_list[i].mmio_start =
+ dev_priv->ring[i].mmio_base + GUC_MMIO_WHITE_LIST_START;
+
+ /* Nothing to be saved or restored for now. */
+ reg_state->mmio_white_list[i].count = 0;
+ }
+
+ ads->reg_state_addr = ads->scheduler_policies +
+ sizeof(struct guc_policies);
+
+ ads->reg_state_buffer = ads->reg_state_addr +
+ sizeof(struct guc_mmio_reg_state);
+
kunmap(page);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 0cc17c7..1bb6410 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -361,6 +361,43 @@ struct guc_policies {
u32 reserved[19];
} __packed;
+/* GuC MMIO reg state struct */
+
+#define GUC_REGSET_FLAGS_NONE 0x0
+#define GUC_REGSET_POWERCYCLE 0x1
+#define GUC_REGSET_MASKED 0x2
+#define GUC_REGSET_ENGINERESET 0x4
+#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
+#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
+
+#define GUC_REGSET_MAX_REGISTERS 20
+#define GUC_MMIO_WHITE_LIST_START 0x24d0
+#define GUC_MMIO_WHITE_LIST_MAX 12
+#define GUC_S3_SAVE_SPACE_PAGES 10
+
+struct guc_mmio_regset {
+ struct __packed {
+ u32 offset;
+ u32 value;
+ u32 flags;
+ } registers[GUC_REGSET_MAX_REGISTERS];
+
+ u32 values_valid;
+ u32 number_of_registers;
+} __packed;
+
+struct guc_mmio_reg_state {
+ struct guc_mmio_regset global_reg;
+ struct guc_mmio_regset engine_reg[I915_NUM_RINGS];
+
+ /* MMIO registers that are set as non privileged */
+ struct __packed {
+ u32 mmio_start;
+ u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
+ u32 count;
+ } mmio_white_list[I915_NUM_RINGS];
+} __packed;
+
/* GuC Additional Data Struct */
struct guc_ads {
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 5/5] drm/i915/guc: Add GuC ADS - enabling ADS
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
` (3 preceding siblings ...)
2015-12-18 20:00 ` [PATCH v2 4/5] drm/i915/guc: Add GuC ADS - MMIO reg state yu.dai
@ 2015-12-18 20:00 ` yu.dai
2015-12-19 8:49 ` ✗ warning: Fi.CI.BAT Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
To: intel-gfx
From: Alex Dai <yu.dai@intel.com>
Set ADS enabling flag during GuC init.
Signed-off-by: Alex Dai <yu.dai@intel.com>
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 4740949..625272f4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -165,6 +165,13 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
}
+ if (guc->ads_obj) {
+ u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj)
+ >> PAGE_SHIFT;
+ params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
+ params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
+ }
+
/* If GuC submission is enabled, set up additional parameters here */
if (i915.enable_guc_submission) {
u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
--
2.5.0
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* ✗ warning: Fi.CI.BAT
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
` (4 preceding siblings ...)
2015-12-18 20:00 ` [PATCH v2 5/5] drm/i915/guc: Add GuC ADS - enabling ADS yu.dai
@ 2015-12-19 8:49 ` Patchwork
2016-01-04 19:11 ` [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) Dave Gordon
` (2 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2015-12-19 8:49 UTC (permalink / raw)
To: yu.dai; +Cc: intel-gfx
== Summary ==
Built on 7cdc548e77f503593b83a1c5d58f4dcc862c17e2 drm-intel-nightly: 2015y-12m-18d-19h-26m-21s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (hsw-brixbox)
Subgroup basic-flip-vs-wf_vblank:
pass -> DMESG-WARN (byt-nuc)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a:
dmesg-warn -> PASS (snb-x220t)
Subgroup read-crc-pipe-a-frame-sequence:
dmesg-warn -> PASS (byt-nuc)
Subgroup read-crc-pipe-c:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (snb-x220t)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (bdw-nuci7)
Test kms_setmode:
Subgroup basic-clone-single-crtc:
dmesg-warn -> PASS (snb-dellxps)
bdw-nuci7 total:135 pass:124 dwarn:2 dfail:0 fail:0 skip:9
bdw-ultra total:132 pass:124 dwarn:2 dfail:0 fail:0 skip:6
byt-nuc total:135 pass:119 dwarn:3 dfail:0 fail:0 skip:13
hsw-brixbox total:135 pass:127 dwarn:1 dfail:0 fail:0 skip:7
hsw-gt2 total:135 pass:130 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:135 pass:100 dwarn:0 dfail:0 fail:0 skip:35
ivb-t430s total:135 pass:127 dwarn:2 dfail:0 fail:0 skip:6
skl-i5k-2 total:135 pass:122 dwarn:5 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:123 dwarn:4 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:122 dwarn:1 dfail:0 fail:0 skip:12
snb-x220t total:135 pass:121 dwarn:2 dfail:0 fail:1 skip:11
Results at /archive/results/CI_IGT_test/Patchwork_726/
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 0/5] Add GuC ADS (Addition Data Structure)
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
` (5 preceding siblings ...)
2015-12-19 8:49 ` ✗ warning: Fi.CI.BAT Patchwork
@ 2016-01-04 19:11 ` Dave Gordon
2016-01-05 10:35 ` Daniel Vetter
2016-01-05 12:30 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-06 9:01 ` Patchwork
8 siblings, 1 reply; 17+ messages in thread
From: Dave Gordon @ 2016-01-04 19:11 UTC (permalink / raw)
To: intel-gfx
On 18/12/15 20:00, yu.dai@intel.com wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> The GuC firmware uses this for various purposes. The ADS itself is a chunk of
> memory created by driver to share with GuC. This series creates the GuC ADS
> object and setup some basic settings for it.
>
> This version addresses some comments from Chris W. Tidy up some code; replace
> kmap_atomic by kmap etc.
>
> Alex Dai (4):
> drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
> drm/i915/guc: Add GuC ADS - scheduler policies
> drm/i915/guc: Add GuC ADS - MMIO reg state
> drm/i915/guc: Add GuC ADS - enabling ADS
>
> Dave Gordon (1):
> drm/i915/guc: Expose (intel)_lr_context_size()
>
> drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
> drivers/gpu/drm/i915/i915_guc_submission.c | 95 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc.h | 2 +
> drivers/gpu/drm/i915/intel_guc_fwif.h | 113 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_guc_loader.c | 7 ++
> drivers/gpu/drm/i915/intel_lrc.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.h | 1 +
> 7 files changed, 220 insertions(+), 3 deletions(-)
>
For the whole series,
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 0/5] Add GuC ADS (Addition Data Structure)
2016-01-04 19:11 ` [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) Dave Gordon
@ 2016-01-05 10:35 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2016-01-05 10:35 UTC (permalink / raw)
To: Dave Gordon; +Cc: intel-gfx
On Mon, Jan 04, 2016 at 07:11:29PM +0000, Dave Gordon wrote:
> On 18/12/15 20:00, yu.dai@intel.com wrote:
> >From: Alex Dai <yu.dai@intel.com>
> >
> >The GuC firmware uses this for various purposes. The ADS itself is a chunk of
> >memory created by driver to share with GuC. This series creates the GuC ADS
> >object and setup some basic settings for it.
> >
> >This version addresses some comments from Chris W. Tidy up some code; replace
> >kmap_atomic by kmap etc.
> >
> >Alex Dai (4):
> > drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
> > drm/i915/guc: Add GuC ADS - scheduler policies
> > drm/i915/guc: Add GuC ADS - MMIO reg state
> > drm/i915/guc: Add GuC ADS - enabling ADS
> >
> >Dave Gordon (1):
> > drm/i915/guc: Expose (intel)_lr_context_size()
> >
> > drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
> > drivers/gpu/drm/i915/i915_guc_submission.c | 95 ++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_guc.h | 2 +
> > drivers/gpu/drm/i915/intel_guc_fwif.h | 113 ++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_guc_loader.c | 7 ++
> > drivers/gpu/drm/i915/intel_lrc.c | 4 +-
> > drivers/gpu/drm/i915/intel_lrc.h | 1 +
> > 7 files changed, 220 insertions(+), 3 deletions(-)
> >
>
> For the whole series,
>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
All 5 merged to dinq, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ failure: Fi.CI.BAT
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
` (6 preceding siblings ...)
2016-01-04 19:11 ` [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) Dave Gordon
@ 2016-01-05 12:30 ` Patchwork
2016-01-06 9:01 ` Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2016-01-05 12:30 UTC (permalink / raw)
To: Dave Gordon; +Cc: intel-gfx
== Summary ==
HEAD is now at c837c0f drm-intel-nightly: 2016y-01m-05d-10h-35m-52s UTC integration manifest
Applying: drm/i915: add kerneldoc for intel_lr_context_size()
Applying: drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.
Patch failed at 0002 drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
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^ permalink raw reply [flat|nested] 17+ messages in thread* ✗ failure: Fi.CI.BAT
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
` (7 preceding siblings ...)
2016-01-05 12:30 ` ✗ failure: Fi.CI.BAT Patchwork
@ 2016-01-06 9:01 ` Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2016-01-06 9:01 UTC (permalink / raw)
To: yu.dai; +Cc: intel-gfx
== Summary ==
HEAD is now at 24b053a drm-intel-nightly: 2016y-01m-06d-08h-16m-11s UTC integration manifest
Applying: drm/i915/guc: Expose (intel)_lr_context_size()
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/intel_lrc.c
M drivers/gpu/drm/i915/intel_lrc.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_lrc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_lrc.c
Patch failed at 0001 drm/i915/guc: Expose (intel)_lr_context_size()
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^ permalink raw reply [flat|nested] 17+ messages in thread