* ✗ warning: Fi.CI.BAT
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
@ 2015-12-21 13:13 ` Patchwork
2015-12-21 13:14 ` Patchwork
` (7 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2015-12-21 13:13 UTC (permalink / raw)
To: Feceoru, Gabriel; +Cc: intel-gfx
== Summary ==
Built on e858593f63757a993fa56f282cb1493c57810a20 drm-intel-nightly: 2015y-12m-21d-12h-06m-20s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (skl-i5k-2)
pass -> DMESG-WARN (hsw-brixbox)
Subgroup basic-flip-vs-wf_vblank:
dmesg-warn -> PASS (snb-x220t)
dmesg-warn -> PASS (byt-nuc)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-WARN (snb-x220t)
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (skl-i5k-2)
dmesg-warn -> PASS (snb-dellxps)
Subgroup read-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (hsw-xps12)
pass -> DMESG-WARN (bdw-ultra)
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (bdw-ultra)
bdw-nuci7 total:132 pass:122 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:132 pass:124 dwarn:2 dfail:0 fail:0 skip:6
bsw-nuc-2 total:135 pass:113 dwarn:2 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:121 dwarn:1 dfail:0 fail:0 skip:13
hsw-brixbox total:135 pass:126 dwarn:2 dfail:0 fail:0 skip:7
hsw-gt2 total:135 pass:130 dwarn:1 dfail:0 fail:0 skip:4
hsw-xps12 total:132 pass:126 dwarn:2 dfail:0 fail:0 skip:4
ilk-hp8440p total:135 pass:99 dwarn:1 dfail:0 fail:0 skip:35
ivb-t430s total:135 pass:127 dwarn:2 dfail:0 fail:0 skip:6
skl-i5k-2 total:135 pass:122 dwarn:5 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:122 dwarn:5 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:122 dwarn:1 dfail:0 fail:0 skip:12
snb-x220t total:135 pass:122 dwarn:1 dfail:0 fail:1 skip:11
Results at /archive/results/CI_IGT_test/Patchwork_775/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* ✗ warning: Fi.CI.BAT
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
2015-12-21 13:13 ` ✗ warning: Fi.CI.BAT Patchwork
@ 2015-12-21 13:14 ` Patchwork
2016-01-11 17:56 ` [PATCH] drm/i915: Handle PipeC fused off on HSW Ville Syrjälä
` (6 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2015-12-21 13:14 UTC (permalink / raw)
To: Feceoru, Gabriel; +Cc: intel-gfx
== Summary ==
Built on e858593f63757a993fa56f282cb1493c57810a20 drm-intel-nightly: 2015y-12m-21d-12h-06m-20s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (skl-i5k-2)
pass -> DMESG-WARN (hsw-brixbox)
Subgroup basic-flip-vs-wf_vblank:
dmesg-warn -> PASS (snb-x220t)
dmesg-warn -> PASS (byt-nuc)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-WARN (snb-x220t)
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (skl-i5k-2)
dmesg-warn -> PASS (snb-dellxps)
Subgroup read-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (hsw-xps12)
pass -> DMESG-WARN (bdw-ultra)
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (bdw-ultra)
bdw-nuci7 total:132 pass:122 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:132 pass:124 dwarn:2 dfail:0 fail:0 skip:6
bsw-nuc-2 total:135 pass:113 dwarn:2 dfail:0 fail:0 skip:20
byt-nuc total:135 pass:121 dwarn:1 dfail:0 fail:0 skip:13
hsw-brixbox total:135 pass:126 dwarn:2 dfail:0 fail:0 skip:7
hsw-gt2 total:135 pass:130 dwarn:1 dfail:0 fail:0 skip:4
hsw-xps12 total:132 pass:126 dwarn:2 dfail:0 fail:0 skip:4
ilk-hp8440p total:135 pass:99 dwarn:1 dfail:0 fail:0 skip:35
ivb-t430s total:135 pass:127 dwarn:2 dfail:0 fail:0 skip:6
skl-i5k-2 total:135 pass:122 dwarn:5 dfail:0 fail:0 skip:8
skl-i7k-2 total:135 pass:122 dwarn:5 dfail:0 fail:0 skip:8
snb-dellxps total:135 pass:122 dwarn:1 dfail:0 fail:0 skip:12
snb-x220t total:135 pass:122 dwarn:1 dfail:0 fail:1 skip:11
Results at /archive/results/CI_IGT_test/Patchwork_775/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH] drm/i915: Handle PipeC fused off on HSW
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
2015-12-21 13:13 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 13:14 ` Patchwork
@ 2016-01-11 17:56 ` Ville Syrjälä
2016-01-12 15:00 ` Gabriel Feceoru
2016-01-13 14:46 ` [PATCH v2] drm/i915: Handle PipeC fused off on GEN7+ Gabriel Feceoru
` (5 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjälä @ 2016-01-11 17:56 UTC (permalink / raw)
To: Gabriel Feceoru; +Cc: intel-gfx
On Mon, Dec 21, 2015 at 01:57:22PM +0200, Gabriel Feceoru wrote:
> On some HSW boards all pipeC tests fail with various dmesg errors.
> This seems to be caused by Pipe C beeing disabled in FUSE_STRAP and
> thus reading back the PIPECONF register is always zero.
>
> Fixed by adjusting pipe_count to 2 and thus the pipeC igt tests will
> be skipped.
>
> Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 988a380..130a496 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> + } else if (I915_READ(FUSE_STRAP) & HSW_PIPE_C_DISABLE) {
> + DRM_INFO("PipeC fused off\n");
> + info->num_pipes = 2;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 007ae83..0432a5f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> +#define HSW_PIPE_C_DISABLE (1 << 28)
According to Bspec the bit is already present on IVB.
> #define ILK_HDCP_DISABLE (1 << 25)
> #define ILK_eDP_A_DISABLE (1 << 24)
> #define HSW_CDCLK_LIMIT (1 << 24)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH] drm/i915: Handle PipeC fused off on HSW
2016-01-11 17:56 ` [PATCH] drm/i915: Handle PipeC fused off on HSW Ville Syrjälä
@ 2016-01-12 15:00 ` Gabriel Feceoru
2016-01-12 15:08 ` Ville Syrjälä
0 siblings, 1 reply; 16+ messages in thread
From: Gabriel Feceoru @ 2016-01-12 15:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On 11.01.2016 19:56, Ville Syrjälä wrote:
> On Mon, Dec 21, 2015 at 01:57:22PM +0200, Gabriel Feceoru wrote:
>> On some HSW boards all pipeC tests fail with various dmesg errors.
>> This seems to be caused by Pipe C beeing disabled in FUSE_STRAP and
>> thus reading back the PIPECONF register is always zero.
>>
>> Fixed by adjusting pipe_count to 2 and thus the pipeC igt tests will
>> be skipped.
>>
>> Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_dma.c | 3 +++
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> 2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>> index 988a380..130a496 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
>> DRM_INFO("Display fused off, disabling\n");
>> info->num_pipes = 0;
>> + } else if (I915_READ(FUSE_STRAP) & HSW_PIPE_C_DISABLE) {
>> + DRM_INFO("PipeC fused off\n");
>> + info->num_pipes = 2;
>> }
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 007ae83..0432a5f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
>> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
>> #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
>> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
>> +#define HSW_PIPE_C_DISABLE (1 << 28)
>
> According to Bspec the bit is already present on IVB.
IVB and HSW are both Gen7. Are you suggesting it should be named
IVB_PIPE_C_DISABLE instead?
>
>> #define ILK_HDCP_DISABLE (1 << 25)
>> #define ILK_eDP_A_DISABLE (1 << 24)
>> #define HSW_CDCLK_LIMIT (1 << 24)
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH] drm/i915: Handle PipeC fused off on HSW
2016-01-12 15:00 ` Gabriel Feceoru
@ 2016-01-12 15:08 ` Ville Syrjälä
0 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjälä @ 2016-01-12 15:08 UTC (permalink / raw)
To: Gabriel Feceoru; +Cc: intel-gfx
On Tue, Jan 12, 2016 at 05:00:16PM +0200, Gabriel Feceoru wrote:
>
>
> On 11.01.2016 19:56, Ville Syrjälä wrote:
> > On Mon, Dec 21, 2015 at 01:57:22PM +0200, Gabriel Feceoru wrote:
> >> On some HSW boards all pipeC tests fail with various dmesg errors.
> >> This seems to be caused by Pipe C beeing disabled in FUSE_STRAP and
> >> thus reading back the PIPECONF register is always zero.
> >>
> >> Fixed by adjusting pipe_count to 2 and thus the pipeC igt tests will
> >> be skipped.
> >>
> >> Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> >> drivers/gpu/drm/i915/i915_reg.h | 1 +
> >> 2 files changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> >> index 988a380..130a496 100644
> >> --- a/drivers/gpu/drm/i915/i915_dma.c
> >> +++ b/drivers/gpu/drm/i915/i915_dma.c
> >> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> >> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> >> DRM_INFO("Display fused off, disabling\n");
> >> info->num_pipes = 0;
> >> + } else if (I915_READ(FUSE_STRAP) & HSW_PIPE_C_DISABLE) {
> >> + DRM_INFO("PipeC fused off\n");
> >> + info->num_pipes = 2;
> >> }
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 007ae83..0432a5f 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> >> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> >> #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> >> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> >> +#define HSW_PIPE_C_DISABLE (1 << 28)
> >
> > According to Bspec the bit is already present on IVB.
> IVB and HSW are both Gen7. Are you suggesting it should be named
> IVB_PIPE_C_DISABLE instead?
Yes.
> >
> >> #define ILK_HDCP_DISABLE (1 << 25)
> >> #define ILK_eDP_A_DISABLE (1 << 24)
> >> #define HSW_CDCLK_LIMIT (1 << 24)
> >> --
> >> 1.9.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2] drm/i915: Handle PipeC fused off on GEN7+
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
` (2 preceding siblings ...)
2016-01-11 17:56 ` [PATCH] drm/i915: Handle PipeC fused off on HSW Ville Syrjälä
@ 2016-01-13 14:46 ` Gabriel Feceoru
2016-01-13 14:50 ` Damien Lespiau
2016-01-13 15:41 ` ✓ success: Fi.CI.BAT Patchwork
` (4 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Gabriel Feceoru @ 2016-01-13 14:46 UTC (permalink / raw)
To: intel-gfx
Starting with Gen7 (IVB) Display PipeC can be fused off on some production
parts. When disabled, display hardware will prevent the pipe C register bit
from being set to 1.
Fixed by adjusting pipe_count to reflect this.
Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44a896c..c3b93e7 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
+ } else if (I915_READ(FUSE_STRAP) & IVB_PIPE_C_DISABLE) {
+ DRM_INFO("PipeC fused off\n");
+ info->num_pipes -= 1;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..a182739 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define IVB_PIPE_C_DISABLE (1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2] drm/i915: Handle PipeC fused off on GEN7+
2016-01-13 14:46 ` [PATCH v2] drm/i915: Handle PipeC fused off on GEN7+ Gabriel Feceoru
@ 2016-01-13 14:50 ` Damien Lespiau
0 siblings, 0 replies; 16+ messages in thread
From: Damien Lespiau @ 2016-01-13 14:50 UTC (permalink / raw)
To: Gabriel Feceoru; +Cc: intel-gfx
On Wed, Jan 13, 2016 at 04:46:43PM +0200, Gabriel Feceoru wrote:
> Starting with Gen7 (IVB) Display PipeC can be fused off on some production
> parts. When disabled, display hardware will prevent the pipe C register bit
> from being set to 1.
>
> Fixed by adjusting pipe_count to reflect this.
The title is misleading, it's really just IVB/HSW/BDW not gen7+
You want to add the changelog of the patch in the commit message as
well, eg.
v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
on ivybridge (Ville)
also, we can get rid of the MMIO access (see below)
--
Damien
> Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 44a896c..c3b93e7 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> + } else if (I915_READ(FUSE_STRAP) & IVB_PIPE_C_DISABLE) {
> + DRM_INFO("PipeC fused off\n");
> + info->num_pipes -= 1;
FUSE_STRAP is alreay read above, it's in the fuse_trap variable.
HTH,
--
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ success: Fi.CI.BAT
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
` (3 preceding siblings ...)
2016-01-13 14:46 ` [PATCH v2] drm/i915: Handle PipeC fused off on GEN7+ Gabriel Feceoru
@ 2016-01-13 15:41 ` Patchwork
2016-01-13 16:02 ` [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW Gabriel Feceoru
` (3 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2016-01-13 15:41 UTC (permalink / raw)
To: Feceoru, Gabriel; +Cc: intel-gfx
== Summary ==
Built on aa7ddea990dfc10c7e90ad10820e0121a9667453 drm-intel-nightly: 2016y-01m-13d-15h-05m-13s UTC integration manifest
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b:
skip -> PASS (bdw-nuci7)
Subgroup nonblocking-crc-pipe-c:
pass -> SKIP (bdw-nuci7)
bdw-nuci7 total:138 pass:128 dwarn:0 dfail:0 fail:0 skip:10
bdw-ultra total:138 pass:131 dwarn:1 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
Results at /archive/results/CI_IGT_test/Patchwork_1171/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
` (4 preceding siblings ...)
2016-01-13 15:41 ` ✓ success: Fi.CI.BAT Patchwork
@ 2016-01-13 16:02 ` Gabriel Feceoru
2016-01-19 16:09 ` Patrik Jakobsson
2016-01-13 16:49 ` ✗ warning: Fi.CI.BAT Patchwork
` (2 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Gabriel Feceoru @ 2016-01-13 16:02 UTC (permalink / raw)
To: intel-gfx
Some Gen7/8 production parts may have the Display Pipe C fused off.
In this case, the display hardware will prevent the Pipe C register bit
from being set to 1.
Fixed by adjusting pipe_count to reflect this.
v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
on ivybridge (Ville)
v3: Remove unnecessary MMIO read, correct the description (Damien)
Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44a896c..dd0d100 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
+ } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
+ DRM_INFO("PipeC fused off\n");
+ info->num_pipes -= 1;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..a182739 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define IVB_PIPE_C_DISABLE (1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
2016-01-13 16:02 ` [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW Gabriel Feceoru
@ 2016-01-19 16:09 ` Patrik Jakobsson
0 siblings, 0 replies; 16+ messages in thread
From: Patrik Jakobsson @ 2016-01-19 16:09 UTC (permalink / raw)
To: Gabriel Feceoru; +Cc: intel-gfx
On Wed, Jan 13, 2016 at 06:02:52PM +0200, Gabriel Feceoru wrote:
> Some Gen7/8 production parts may have the Display Pipe C fused off.
> In this case, the display hardware will prevent the Pipe C register bit
> from being set to 1.
Please elaborate on what pipe c register bit is prevented from being set.
Thanks
Patrik
>
> Fixed by adjusting pipe_count to reflect this.
>
> v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> on ivybridge (Ville)
> v3: Remove unnecessary MMIO read, correct the description (Damien)
>
> Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 44a896c..dd0d100 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> + } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> + DRM_INFO("PipeC fused off\n");
> + info->num_pipes -= 1;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a98889..a182739 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> +#define IVB_PIPE_C_DISABLE (1 << 28)
> #define ILK_HDCP_DISABLE (1 << 25)
> #define ILK_eDP_A_DISABLE (1 << 24)
> #define HSW_CDCLK_LIMIT (1 << 24)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
---
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ warning: Fi.CI.BAT
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
` (5 preceding siblings ...)
2016-01-13 16:02 ` [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW Gabriel Feceoru
@ 2016-01-13 16:49 ` Patchwork
2016-01-22 11:28 ` [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW Gabriel Feceoru
2016-01-22 11:46 ` ✗ Fi.CI.BAT: warning for drm/i915: Handle PipeC fused off on HSW (rev4) Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2016-01-13 16:49 UTC (permalink / raw)
To: Feceoru, Gabriel; +Cc: intel-gfx
== Summary ==
Built on 0f3950521e4fd6b37f9d48d8484e2e0ce926ecca drm-intel-nightly: 2016y-01m-13d-15h-43m-52s UTC integration manifest
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS (skl-i7k-2)
Test gem_cpu_reloc:
Subgroup basic:
dmesg-fail -> PASS (skl-i7k-2)
Test gem_ctx_param_basic:
Subgroup basic:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup invalid-param-set:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup non-root-set-no-zeromap:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup root-set-no-zeromap-disabled:
dmesg-warn -> PASS (skl-i7k-2)
Test gem_mmap:
Subgroup basic:
dmesg-warn -> PASS (skl-i7k-2)
Test gem_mmap_gtt:
Subgroup basic-read:
dmesg-warn -> PASS (skl-i7k-2)
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (bdw-nuci7)
Test kms_addfb_basic:
Subgroup addfb25-modifier-no-flag:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup addfb25-x-tiled-mismatch:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup addfb25-yf-tiled:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup bad-pitch-1024:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup bad-pitch-63:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup bad-pitch-999:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup clobberred-modifier:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup too-high:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup too-wide:
dmesg-warn -> PASS (skl-i7k-2)
Subgroup unused-offsets:
dmesg-warn -> PASS (skl-i7k-2)
Test kms_flip:
Subgroup basic-plain-flip:
dmesg-fail -> PASS (skl-i7k-2)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a-frame-sequence:
dmesg-fail -> PASS (skl-i7k-2)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (bdw-ultra)
Subgroup read-crc-pipe-a-frame-sequence:
pass -> SKIP (bdw-nuci7)
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (bdw-ultra)
Subgroup read-crc-pipe-b-frame-sequence:
dmesg-fail -> PASS (skl-i7k-2)
Test prime_self_import:
Subgroup basic-with_two_bos:
dmesg-warn -> PASS (skl-i7k-2)
bdw-nuci7 total:138 pass:127 dwarn:1 dfail:0 fail:0 skip:10
bdw-ultra total:138 pass:130 dwarn:2 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6
skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1172/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
` (6 preceding siblings ...)
2016-01-13 16:49 ` ✗ warning: Fi.CI.BAT Patchwork
@ 2016-01-22 11:28 ` Gabriel Feceoru
2016-02-01 14:20 ` Patrik Jakobsson
2016-01-22 11:46 ` ✗ Fi.CI.BAT: warning for drm/i915: Handle PipeC fused off on HSW (rev4) Patchwork
8 siblings, 1 reply; 16+ messages in thread
From: Gabriel Feceoru @ 2016-01-22 11:28 UTC (permalink / raw)
To: intel-gfx
Some Gen7/8 production parts may have the Display Pipe C fused off.
In this case, the display hardware will prevent the enable bit in
PIPE_CONF register (for Pipe C) from being set to 1.
Fixed by adjusting pipe_count to reflect this.
v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
on ivybridge (Ville)
v3: Remove unnecessary MMIO read, correct the description (Damien)
v4: Be more specific in description (Patrick)
Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d70d96f..91404aa 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -816,6 +816,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
+ } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
+ DRM_INFO("PipeC fused off\n");
+ info->num_pipes -= 1;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..a182739 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define IVB_PIPE_C_DISABLE (1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
2016-01-22 11:28 ` [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW Gabriel Feceoru
@ 2016-02-01 14:20 ` Patrik Jakobsson
2016-02-10 7:29 ` Daniel Vetter
0 siblings, 1 reply; 16+ messages in thread
From: Patrik Jakobsson @ 2016-02-01 14:20 UTC (permalink / raw)
To: Gabriel Feceoru; +Cc: intel-gfx
On Fri, Jan 22, 2016 at 01:28:45PM +0200, Gabriel Feceoru wrote:
> Some Gen7/8 production parts may have the Display Pipe C fused off.
> In this case, the display hardware will prevent the enable bit in
> PIPE_CONF register (for Pipe C) from being set to 1.
>
> Fixed by adjusting pipe_count to reflect this.
>
> v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> on ivybridge (Ville)
> v3: Remove unnecessary MMIO read, correct the description (Damien)
> v4: Be more specific in description (Patrick)
>
> Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index d70d96f..91404aa 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -816,6 +816,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> + } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> + DRM_INFO("PipeC fused off\n");
> + info->num_pipes -= 1;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a98889..a182739 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> +#define IVB_PIPE_C_DISABLE (1 << 28)
> #define ILK_HDCP_DISABLE (1 << 25)
> #define ILK_eDP_A_DISABLE (1 << 24)
> #define HSW_CDCLK_LIMIT (1 << 24)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
---
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
2016-02-01 14:20 ` Patrik Jakobsson
@ 2016-02-10 7:29 ` Daniel Vetter
0 siblings, 0 replies; 16+ messages in thread
From: Daniel Vetter @ 2016-02-10 7:29 UTC (permalink / raw)
To: Gabriel Feceoru, intel-gfx
On Mon, Feb 01, 2016 at 03:20:19PM +0100, Patrik Jakobsson wrote:
> On Fri, Jan 22, 2016 at 01:28:45PM +0200, Gabriel Feceoru wrote:
> > Some Gen7/8 production parts may have the Display Pipe C fused off.
> > In this case, the display hardware will prevent the enable bit in
> > PIPE_CONF register (for Pipe C) from being set to 1.
> >
> > Fixed by adjusting pipe_count to reflect this.
> >
> > v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> > on ivybridge (Ville)
> > v3: Remove unnecessary MMIO read, correct the description (Damien)
> > v4: Be more specific in description (Patrick)
> >
> > Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
>
> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 3 +++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index d70d96f..91404aa 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -816,6 +816,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> > !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> > DRM_INFO("Display fused off, disabling\n");
> > info->num_pipes = 0;
> > + } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> > + DRM_INFO("PipeC fused off\n");
> > + info->num_pipes -= 1;
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0a98889..a182739 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
> > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> > +#define IVB_PIPE_C_DISABLE (1 << 28)
> > #define ILK_HDCP_DISABLE (1 << 25)
> > #define ILK_eDP_A_DISABLE (1 << 24)
> > #define HSW_CDCLK_LIMIT (1 << 24)
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> ---
> Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Handle PipeC fused off on HSW (rev4)
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
` (7 preceding siblings ...)
2016-01-22 11:28 ` [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW Gabriel Feceoru
@ 2016-01-22 11:46 ` Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2016-01-22 11:46 UTC (permalink / raw)
To: Feceoru, Gabriel; +Cc: intel-gfx
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly: 2016y-01m-21d-11h-02m-42s UTC integration manifest
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p)
bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:143 pass:137 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:143 pass:119 dwarn:0 dfail:0 fail:0 skip:24
byt-nuc total:143 pass:128 dwarn:0 dfail:0 fail:0 skip:15
hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7
ilk-hp8440p total:143 pass:103 dwarn:2 dfail:0 fail:0 skip:38
ivb-t430s total:143 pass:137 dwarn:0 dfail:0 fail:0 skip:6
skl-i5k-2 total:143 pass:134 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:143 pass:129 dwarn:0 dfail:0 fail:0 skip:14
snb-x220t total:143 pass:129 dwarn:0 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1247/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread