From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> To: <joro@8bytes.org>, <bp@alien8.de>, <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org> Cc: <linux-kernel@vger.kernel.org>, <iommu@lists.linux-foundation.org>, Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Subject: [PATCH v2 5/6] perf/amd/iommu: Introduce get_iommu_bnk_cnt_evt_idx Date: Fri, 1 Jan 2016 12:13:39 -0600 [thread overview] Message-ID: <1451672020-2150-6-git-send-email-Suravee.Suthikulpanit@amd.com> (raw) In-Reply-To: <1451672020-2150-1-git-send-email-Suravee.Suthikulpanit@amd.com> Introduce a helper function to calculate bit-index for assigning performance counter assignment. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> --- arch/x86/kernel/cpu/perf_event_amd_iommu.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_amd_iommu.c b/arch/x86/kernel/cpu/perf_event_amd_iommu.c index 99fcd10..8af7149 100644 --- a/arch/x86/kernel/cpu/perf_event_amd_iommu.c +++ b/arch/x86/kernel/cpu/perf_event_amd_iommu.c @@ -153,18 +153,28 @@ static struct attribute_group amd_iommu_cpumask_group = { /*---------------------------------------------*/ +static inline +int get_iommu_bnk_cnt_evt_idx(struct perf_amd_iommu *perf_iommu, + int iommu_index, int bank_index, + int cntr_index) +{ + int cntrs_per_iommu = perf_iommu->max_banks * perf_iommu->max_counters; + int index = (perf_iommu->max_counters * bank_index) + cntr_index; + + return (cntrs_per_iommu * iommu_index) + index; +} + static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu) { unsigned long flags; int shift, bank, cntr, retval; - int max_banks = perf_iommu->max_banks; - int max_cntrs = perf_iommu->max_counters; raw_spin_lock_irqsave(&perf_iommu->lock, flags); - for (bank = 0, shift = 0; bank < max_banks; bank++) { - for (cntr = 0; cntr < max_cntrs; cntr++) { - shift = bank + (bank*3) + cntr; + for (bank = 0, shift = 0; bank < perf_iommu->max_banks; bank++) { + for (cntr = 0; cntr < perf_iommu->max_counters; cntr++) { + shift = get_iommu_bnk_cnt_evt_idx(perf_iommu, + 0, bank, cntr); if (perf_iommu->cntr_assign_mask & (1ULL<<shift)) { continue; } else { -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Suravee Suthikulpanit <Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> To: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, bp-Gina5bIWoIWzQB+pC5nmwQ@public.gmane.org, peterz-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, acme-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH v2 5/6] perf/amd/iommu: Introduce get_iommu_bnk_cnt_evt_idx Date: Fri, 1 Jan 2016 12:13:39 -0600 [thread overview] Message-ID: <1451672020-2150-6-git-send-email-Suravee.Suthikulpanit@amd.com> (raw) In-Reply-To: <1451672020-2150-1-git-send-email-Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> Introduce a helper function to calculate bit-index for assigning performance counter assignment. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> --- arch/x86/kernel/cpu/perf_event_amd_iommu.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_amd_iommu.c b/arch/x86/kernel/cpu/perf_event_amd_iommu.c index 99fcd10..8af7149 100644 --- a/arch/x86/kernel/cpu/perf_event_amd_iommu.c +++ b/arch/x86/kernel/cpu/perf_event_amd_iommu.c @@ -153,18 +153,28 @@ static struct attribute_group amd_iommu_cpumask_group = { /*---------------------------------------------*/ +static inline +int get_iommu_bnk_cnt_evt_idx(struct perf_amd_iommu *perf_iommu, + int iommu_index, int bank_index, + int cntr_index) +{ + int cntrs_per_iommu = perf_iommu->max_banks * perf_iommu->max_counters; + int index = (perf_iommu->max_counters * bank_index) + cntr_index; + + return (cntrs_per_iommu * iommu_index) + index; +} + static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu) { unsigned long flags; int shift, bank, cntr, retval; - int max_banks = perf_iommu->max_banks; - int max_cntrs = perf_iommu->max_counters; raw_spin_lock_irqsave(&perf_iommu->lock, flags); - for (bank = 0, shift = 0; bank < max_banks; bank++) { - for (cntr = 0; cntr < max_cntrs; cntr++) { - shift = bank + (bank*3) + cntr; + for (bank = 0, shift = 0; bank < perf_iommu->max_banks; bank++) { + for (cntr = 0; cntr < perf_iommu->max_counters; cntr++) { + shift = get_iommu_bnk_cnt_evt_idx(perf_iommu, + 0, bank, cntr); if (perf_iommu->cntr_assign_mask & (1ULL<<shift)) { continue; } else { -- 1.9.1
next prev parent reply other threads:[~2016-01-01 18:24 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-01 18:13 [PATCH v2 0/6] perf/amd/iommu: Enable multi-IOMMU support Suravee Suthikulpanit 2016-01-01 18:13 ` Suravee Suthikulpanit 2016-01-01 18:13 ` [PATCH v2 1/6] perf/amd/iommu: Consolidate and move perf_event_amd_iommu header Suravee Suthikulpanit 2016-01-01 18:13 ` Suravee Suthikulpanit 2016-01-07 12:32 ` Joerg Roedel 2016-01-07 12:32 ` Joerg Roedel 2016-01-01 18:13 ` [PATCH v2 2/6] perf/amd/iommu: Modify functions to query max banks and counters Suravee Suthikulpanit 2016-01-01 18:13 ` Suravee Suthikulpanit 2016-01-07 12:34 ` Joerg Roedel 2016-01-07 12:34 ` Joerg Roedel 2016-01-07 15:28 ` Suravee Suthikulpanit 2016-01-07 15:28 ` Suravee Suthikulpanit 2016-01-01 18:13 ` [PATCH v2 3/6] iommu/amd: Introduce amd_iommu_get_num_iommus() Suravee Suthikulpanit 2016-01-01 18:13 ` Suravee Suthikulpanit 2016-01-07 12:15 ` Joerg Roedel 2016-02-09 22:09 ` Suravee Suthikulpanit 2016-02-09 22:09 ` Suravee Suthikulpanit 2016-01-01 18:13 ` [PATCH v2 4/6] perf/amd/iommu: Introduce data structure for tracking prev count Suravee Suthikulpanit 2016-01-01 18:13 ` Suravee Suthikulpanit 2016-01-07 12:27 ` Joerg Roedel 2016-01-07 12:27 ` Joerg Roedel 2016-01-01 18:13 ` Suravee Suthikulpanit [this message] 2016-01-01 18:13 ` [PATCH v2 5/6] perf/amd/iommu: Introduce get_iommu_bnk_cnt_evt_idx Suravee Suthikulpanit 2016-01-01 18:13 ` [PATCH v2 6/6] perf/amd/iommu: Enable support for multiple IOMMUs Suravee Suthikulpanit 2016-01-01 18:13 ` Suravee Suthikulpanit
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1451672020-2150-6-git-send-email-Suravee.Suthikulpanit@amd.com \ --to=suravee.suthikulpanit@amd.com \ --cc=acme@kernel.org \ --cc=bp@alien8.de \ --cc=iommu@lists.linux-foundation.org \ --cc=joro@8bytes.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mingo@redhat.com \ --cc=peterz@infradead.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.