[PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed

[PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed

[Mika Kahola]

These three patches are fixes for DP link trainging failures and flickering issues
reported by 

Mika Kahola (3):
  drm/i915: Disable fast link training if DP config changes
  drm/i915: Check DP no aux transaction bit on link training
  drm/i915: DP channel EQ check for use of DP link training optimization

 drivers/gpu/drm/i915/intel_dp.c               |  8 +++++++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 1/3] drm/i915: Disable fast link training if DP config changes

[Mika Kahola]

Disable DP link training optimization if DP link configuration
changes. If one of the DP link parameters i.e. link rate or
lane count changes the link training does no longer apply the
previously computed drive current and pre-emphasis level.
Instead, the link training is started with zero values.

v5: Commit message update. Split the original patch in two.
    This part considers only changes on link configuration.
    Removed unnecessary debug messages. (Ville)

v4: Parameter and debug message naming improvements.
    Fix for link parameter check (Ville)

v3: Remove cached old link parameters. Instead, disable
    fast link training feature when link parameters are
    set (Ville)

v2: Readout DPCD register to check if no aux handshaking is
    required in link training (Ander)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               | 5 +++++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..6b36d82 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1676,6 +1676,11 @@ found:
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
 			      const struct intel_crtc_state *pipe_config)
 {
+	if (intel_dp->link_rate != pipe_config->port_clock ||
+	    intel_dp->lane_count != pipe_config->lane_count) {
+		intel_dp->train_set_valid = false;
+	}
+
 	intel_dp->link_rate = pipe_config->port_clock;
 	intel_dp->lane_count = pipe_config->lane_count;
 }
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 8888793..59d59be 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -85,6 +85,9 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 			uint8_t dp_train_pat)
 {
+	DRM_DEBUG_KMS("link training optimization: %s\n",
+		      intel_dp->train_set_valid ? "true" : "false");
+
 	if (!intel_dp->train_set_valid)
 		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 	intel_dp_set_signal_levels(intel_dp);
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 2/3] drm/i915: Check DP no aux transaction bit on link training

[Mika Kahola]

Check if no AUX transactions are required on DP link training.
If this bit is set, we can reuse the known good drive current
and pre-emphasis level from the last "full" link training.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               |  2 +-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |  1 +
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b36d82..3137187 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3852,7 +3852,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 	intel_dp->DP = DP;
 }
 
-static bool
+bool
 intel_dp_get_dpcd(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 59d59be..5fb3f97 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -85,6 +85,25 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 			uint8_t dp_train_pat)
 {
+	bool has_dpcd;
+	bool no_aux_handshake = false;
+
+	has_dpcd = intel_dp_get_dpcd(intel_dp);
+
+	/*
+	 * Source device can try to use drive current and pre-emphasis
+	 * parameters computed by the last "full" link training if the
+	 * DP_NO_AUX_HANDSHAKE_LINK_TRAINING bit is set to 1.
+	 */
+	if (has_dpcd) {
+		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+			no_aux_handshake = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+					    DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
+		}
+	}
+
+	intel_dp->train_set_valid &= no_aux_handshake;
+
 	DRM_DEBUG_KMS("link training optimization: %s\n",
 		      intel_dp->train_set_valid ? "true" : "false");
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0438b57..918bdf1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1250,6 +1250,7 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 bool intel_dp_compute_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config);
 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
+bool intel_dp_get_dpcd(struct intel_dp *intel_dp);
 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
 				  bool long_hpd);
 void intel_edp_backlight_on(struct intel_dp *intel_dp);
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

[Mika Kahola]

Don't use DP link training optimization if channel EQ is not ok. It has
been reported that in case of failure in channel EQ check the link training
optimization can be enabled and therefore may not be able to reuse the
previously computed drive current and pre-emphasis levels.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3137187..0cd1ccb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4354,6 +4354,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
 		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
 		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
 			      intel_encoder->base.name);
+		intel_dp->train_set_valid = false;
 		intel_dp_start_link_train(intel_dp);
 		intel_dp_stop_link_train(intel_dp);
 	}
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ warning: Fi.CI.BAT

[Patchwork]

== Summary ==

Built on c1e9dc2dcb577438a6350c7f1cb36ba8ad0e1dfd drm-intel-nightly: 2016y-01m-04d-09h-35m-16s UTC integration manifest

Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                dmesg-warn -> PASS       (ilk-hp8440p)
        Subgroup basic-flip-vs-modeset:
                dmesg-warn -> PASS       (skl-i5k-2)
        Subgroup basic-plain-flip:
                dmesg-warn -> PASS       (bdw-ultra)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a:
                dmesg-warn -> PASS       (snb-x220t)
                pass       -> DMESG-WARN (snb-dellxps)
        Subgroup read-crc-pipe-b:
                dmesg-warn -> PASS       (snb-dellxps)
        Subgroup read-crc-pipe-c:
                pass       -> DMESG-WARN (skl-i5k-2)
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                pass       -> DMESG-WARN (bdw-ultra)

bdw-nuci7        total:132  pass:122  dwarn:1   dfail:0   fail:0   skip:9  
bdw-ultra        total:132  pass:124  dwarn:2   dfail:0   fail:0   skip:6  
byt-nuc          total:135  pass:120  dwarn:2   dfail:0   fail:0   skip:13 
hsw-brixbox      total:135  pass:126  dwarn:2   dfail:0   fail:0   skip:7  
hsw-gt2          total:135  pass:130  dwarn:1   dfail:0   fail:0   skip:4  
hsw-xps12        total:132  pass:125  dwarn:3   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:135  pass:100  dwarn:0   dfail:0   fail:0   skip:35 
ivb-t430s        total:135  pass:127  dwarn:2   dfail:0   fail:0   skip:6  
skl-i5k-2        total:135  pass:124  dwarn:3   dfail:0   fail:0   skip:8  
skl-i7k-2        total:135  pass:124  dwarn:3   dfail:0   fail:0   skip:8  
snb-dellxps      total:135  pass:121  dwarn:2   dfail:0   fail:0   skip:12 
snb-x220t        total:135  pass:122  dwarn:1   dfail:0   fail:1   skip:11 

Results at /archive/results/CI_IGT_test/Patchwork_1065/

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed

[Maarten Lankhorst]

Op 04-01-16 om 12:21 schreef Mika Kahola:
> These three patches are fixes for DP link trainging failures and flickering issues
> reported by 
Did your message get accidentally truncated here?
> Mika Kahola (3):
>   drm/i915: Disable fast link training if DP config changes
>   drm/i915: Check DP no aux transaction bit on link training
>   drm/i915: DP channel EQ check for use of DP link training optimization
>
>  drivers/gpu/drm/i915/intel_dp.c               |  8 +++++++-
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 22 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h              |  1 +
>  3 files changed, 30 insertions(+), 1 deletion(-)
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed

[Mika Kahola]

On Mon, 2016-01-04 at 13:11 +0100, Maarten Lankhorst wrote:
> Op 04-01-16 om 12:21 schreef Mika Kahola:
> > These three patches are fixes for DP link trainging failures and flickering issues
> > reported by 
> Did your message get accidentally truncated here?
It seems. The story should continue with 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393

> > Mika Kahola (3):
> >   drm/i915: Disable fast link training if DP config changes
> >   drm/i915: Check DP no aux transaction bit on link training
> >   drm/i915: DP channel EQ check for use of DP link training optimization
> >
> >  drivers/gpu/drm/i915/intel_dp.c               |  8 +++++++-
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 22 ++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h              |  1 +
> >  3 files changed, 30 insertions(+), 1 deletion(-)
> >
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 1/3] drm/i915: Disable fast link training if DP config changes

[Ville Syrjälä]

On Mon, Jan 04, 2016 at 01:21:22PM +0200, Mika Kahola wrote:
> Disable DP link training optimization if DP link configuration
> changes. If one of the DP link parameters i.e. link rate or
> lane count changes the link training does no longer apply the
> previously computed drive current and pre-emphasis level.
> Instead, the link training is started with zero values.
> 
> v5: Commit message update. Split the original patch in two.
>     This part considers only changes on link configuration.
>     Removed unnecessary debug messages. (Ville)
> 
> v4: Parameter and debug message naming improvements.
>     Fix for link parameter check (Ville)
> 
> v3: Remove cached old link parameters. Instead, disable
>     fast link training feature when link parameters are
>     set (Ville)
> 
> v2: Readout DPCD register to check if no aux handshaking is
>     required in link training (Ander)
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c               | 5 +++++
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 796e3d3..6b36d82 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1676,6 +1676,11 @@ found:
>  void intel_dp_set_link_params(struct intel_dp *intel_dp,
>  			      const struct intel_crtc_state *pipe_config)
>  {
> +	if (intel_dp->link_rate != pipe_config->port_clock ||
> +	    intel_dp->lane_count != pipe_config->lane_count) {
> +		intel_dp->train_set_valid = false;
> +	}
> +
>  	intel_dp->link_rate = pipe_config->port_clock;
>  	intel_dp->lane_count = pipe_config->lane_count;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 8888793..59d59be 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -85,6 +85,9 @@ static bool
>  intel_dp_reset_link_train(struct intel_dp *intel_dp,
>  			uint8_t dp_train_pat)
>  {
> +	DRM_DEBUG_KMS("link training optimization: %s\n",
> +		      intel_dp->train_set_valid ? "true" : "false");

yesno(intel_dp->train_set_valid)

With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  	if (!intel_dp->train_set_valid)
>  		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
>  	intel_dp_set_signal_levels(intel_dp);
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

[Ville Syrjälä]

On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote:
> Don't use DP link training optimization if channel EQ is not ok. It has
> been reported that in case of failure in channel EQ check the link training
> optimization can be enabled and therefore may not be able to reuse the
> previously computed drive current and pre-emphasis levels.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3137187..0cd1ccb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4354,6 +4354,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
>  		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
>  		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
>  			      intel_encoder->base.name);
> +		intel_dp->train_set_valid = false;
>  		intel_dp_start_link_train(intel_dp);
>  		intel_dp_stop_link_train(intel_dp);
>  	}

Should do the same for the MST case I suppose?

> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

[Ville Syrjälä]

On Mon, Jan 04, 2016 at 06:44:09PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote:
> > Don't use DP link training optimization if channel EQ is not ok. It has
> > been reported that in case of failure in channel EQ check the link training
> > optimization can be enabled and therefore may not be able to reuse the
> > previously computed drive current and pre-emphasis levels.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 3137187..0cd1ccb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4354,6 +4354,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
> >  		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
> >  		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> >  			      intel_encoder->base.name);
> > +		intel_dp->train_set_valid = false;
> >  		intel_dp_start_link_train(intel_dp);
> >  		intel_dp_stop_link_train(intel_dp);
> >  	}
> 
> Should do the same for the MST case I suppose?

Also I wonder if we shold maintain some sort of blacklist of unstable
vswing/preemph settings so that we wouldn't even try to retrain with
values we know to be of questionable quality...

> 
> > -- 
> > 1.9.1
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

[Mika Kahola]

On Mon, 2016-01-04 at 18:44 +0200, Ville Syrjälä wrote:
> On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote:
> > Don't use DP link training optimization if channel EQ is not ok. It has
> > been reported that in case of failure in channel EQ check the link training
> > optimization can be enabled and therefore may not be able to reuse the
> > previously computed drive current and pre-emphasis levels.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 3137187..0cd1ccb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4354,6 +4354,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
> >  		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
> >  		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> >  			      intel_encoder->base.name);
> > +		intel_dp->train_set_valid = false;
> >  		intel_dp_start_link_train(intel_dp);
> >  		intel_dp_stop_link_train(intel_dp);
> >  	}
> 
> Should do the same for the MST case I suppose?
Yes, we should do the same for MST case.

Cheers,
Mika
> 
> > -- 
> > 1.9.1
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

[Mika Kahola]

On Mon, 2016-01-04 at 18:53 +0200, Ville Syrjälä wrote:
> On Mon, Jan 04, 2016 at 06:44:09PM +0200, Ville Syrjälä wrote:
> > On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote:
> > > Don't use DP link training optimization if channel EQ is not ok. It has
> > > been reported that in case of failure in channel EQ check the link training
> > > optimization can be enabled and therefore may not be able to reuse the
> > > previously computed drive current and pre-emphasis levels.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 3137187..0cd1ccb 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4354,6 +4354,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
> > >  		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
> > >  		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> > >  			      intel_encoder->base.name);
> > > +		intel_dp->train_set_valid = false;
> > >  		intel_dp_start_link_train(intel_dp);
> > >  		intel_dp_stop_link_train(intel_dp);
> > >  	}
> > 
> > Should do the same for the MST case I suppose?
> 
> Also I wonder if we shold maintain some sort of blacklist of unstable
> vswing/preemph settings so that we wouldn't even try to retrain with
> values we know to be of questionable quality...
I think it would be quite tricky to maintain such a list. There is quite
a bunch of source/sink combinations out there. For eDP this would be
easier if we could first learn which vsing/preemph settings are unusable
and maintain the blacklist based on that.

Cheers,
Mika 
> 
> > 
> > > -- 
> > > 1.9.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 1/3] drm/i915: Disable fast link training if DP config changes

[Mika Kahola]

On Mon, 2016-01-04 at 18:42 +0200, Ville Syrjälä wrote:
> On Mon, Jan 04, 2016 at 01:21:22PM +0200, Mika Kahola wrote:
> > Disable DP link training optimization if DP link configuration
> > changes. If one of the DP link parameters i.e. link rate or
> > lane count changes the link training does no longer apply the
> > previously computed drive current and pre-emphasis level.
> > Instead, the link training is started with zero values.
> > 
> > v5: Commit message update. Split the original patch in two.
> >     This part considers only changes on link configuration.
> >     Removed unnecessary debug messages. (Ville)
> > 
> > v4: Parameter and debug message naming improvements.
> >     Fix for link parameter check (Ville)
> > 
> > v3: Remove cached old link parameters. Instead, disable
> >     fast link training feature when link parameters are
> >     set (Ville)
> > 
> > v2: Readout DPCD register to check if no aux handshaking is
> >     required in link training (Ander)
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c               | 5 +++++
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +++
> >  2 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 796e3d3..6b36d82 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1676,6 +1676,11 @@ found:
> >  void intel_dp_set_link_params(struct intel_dp *intel_dp,
> >  			      const struct intel_crtc_state *pipe_config)
> >  {
> > +	if (intel_dp->link_rate != pipe_config->port_clock ||
> > +	    intel_dp->lane_count != pipe_config->lane_count) {
> > +		intel_dp->train_set_valid = false;
> > +	}
> > +
> >  	intel_dp->link_rate = pipe_config->port_clock;
> >  	intel_dp->lane_count = pipe_config->lane_count;
> >  }
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index 8888793..59d59be 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -85,6 +85,9 @@ static bool
> >  intel_dp_reset_link_train(struct intel_dp *intel_dp,
> >  			uint8_t dp_train_pat)
> >  {
> > +	DRM_DEBUG_KMS("link training optimization: %s\n",
> > +		      intel_dp->train_set_valid ? "true" : "false");
> 
> yesno(intel_dp->train_set_valid)
> 
> With that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
Thanks for the review!

Cheers,
Mika

> > +
> >  	if (!intel_dp->train_set_valid)
> >  		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> >  	intel_dp_set_signal_levels(intel_dp);
> > -- 
> > 1.9.1
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v5 3/3] drm/i915: DP channel EQ check for use of DP link training optimization

[Ville Syrjälä]

On Tue, Jan 05, 2016 at 01:08:13PM +0200, Mika Kahola wrote:
> On Mon, 2016-01-04 at 18:53 +0200, Ville Syrjälä wrote:
> > On Mon, Jan 04, 2016 at 06:44:09PM +0200, Ville Syrjälä wrote:
> > > On Mon, Jan 04, 2016 at 01:21:24PM +0200, Mika Kahola wrote:
> > > > Don't use DP link training optimization if channel EQ is not ok. It has
> > > > been reported that in case of failure in channel EQ check the link training
> > > > optimization can be enabled and therefore may not be able to reuse the
> > > > previously computed drive current and pre-emphasis levels.
> > > > 
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 3137187..0cd1ccb 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -4354,6 +4354,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
> > > >  		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
> > > >  		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> > > >  			      intel_encoder->base.name);
> > > > +		intel_dp->train_set_valid = false;
> > > >  		intel_dp_start_link_train(intel_dp);
> > > >  		intel_dp_stop_link_train(intel_dp);
> > > >  	}
> > > 
> > > Should do the same for the MST case I suppose?
> > 
> > Also I wonder if we shold maintain some sort of blacklist of unstable
> > vswing/preemph settings so that we wouldn't even try to retrain with
> > values we know to be of questionable quality...
> I think it would be quite tricky to maintain such a list. There is quite
> a bunch of source/sink combinations out there. For eDP this would be
> easier if we could first learn which vsing/preemph settings are unusable
> and maintain the blacklist based on that.

That was what I meant, a purely runtime blacklist.

> 
> Cheers,
> Mika 
> > 
> > > 
> > > > -- 
> > > > 1.9.1
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel OTC
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx