* [U-Boot] [PATCH v2 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture
@ 2016-01-04 14:00 Purna Chandra Mandal
2016-01-05 19:20 ` Daniel Schwierzeck
0 siblings, 1 reply; 3+ messages in thread
From: Purna Chandra Mandal @ 2016-01-04 14:00 UTC (permalink / raw)
To: u-boot
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
---
Changes in v2:
- move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
- define register-base as physical address in header file
- add trivial ioremap support to convert physical address to MIPS KSEG1 address
- drop CONFIG_PIC32_SUPPORTS_FDT_BOOT as not required
arch/mips/Kconfig | 6 +++
arch/mips/Makefile | 1 +
arch/mips/mach-pic32/Kconfig | 17 +++++++
arch/mips/mach-pic32/Makefile | 7 +++
arch/mips/mach-pic32/cpu.c | 13 +++++
arch/mips/mach-pic32/include/mach/pic32.h | 79 +++++++++++++++++++++++++++++++
6 files changed, 123 insertions(+)
create mode 100644 arch/mips/mach-pic32/Kconfig
create mode 100644 arch/mips/mach-pic32/Makefile
create mode 100644 arch/mips/mach-pic32/cpu.c
create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 388e4c0..4b8174c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -53,6 +53,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
+config MACH_PIC32
+ bool "Support Microchip PIC32"
+ select OF_CONTROL
+ select DM
+
endchoice
source "board/dbau1x00/Kconfig"
@@ -60,6 +65,7 @@ source "board/imgtec/malta/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 90cd590..5c9da3a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
libs-y += $(machdirs)
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
new file mode 100644
index 0000000..98b0b88
--- /dev/null
+++ b/arch/mips/mach-pic32/Kconfig
@@ -0,0 +1,17 @@
+menu "Microchip PIC32 platforms"
+ depends on MACH_PIC32
+
+config SYS_SOC
+ default "none"
+
+choice
+ prompt "PIC32 SoC select"
+
+endchoice
+
+choice
+ prompt "Board select"
+
+endchoice
+
+endmenu
diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
new file mode 100644
index 0000000..cb42607
--- /dev/null
+++ b/arch/mips/mach-pic32/Makefile
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal at microchip.com.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
new file mode 100644
index 0000000..58fd3ab
--- /dev/null
+++ b/arch/mips/mach-pic32/cpu.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+ return 0;
+}
diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h
new file mode 100644
index 0000000..f618697
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/pic32.h
@@ -0,0 +1,79 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#include <asm/io.h>
+
+/* System Configuration */
+#define PIC32_CFG_BASE 0x1f800000
+
+/* System config register offsets */
+#define CFGCON 0x0000
+#define DEVID 0x0020
+#define SYSKEY 0x0030
+#define PMD1 0x0040
+#define PMD7 0x00a0
+#define CFGEBIA 0x00c0
+#define CFGEBIC 0x00d0
+#define CFGPG 0x00e0
+#define CFGMPLL 0x0100
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
+
+/* Oscillator Configuration */
+#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
+
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE 0x1f801400
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE 0x1f801500
+/* Pin Config */
+#define PINCTRL_BASE 0x1f860000
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE 0x1f8e3000
+#define PIC32_USB_CTRL_BASE 0x1f884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE 0x1f821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE 0x1f8e0000
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE 0x1f8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE 0x1f8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE 0x1f8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE 0x1f8e2000
+
+struct pic32_reg_atomic {
+ u32 raw;
+ u32 clr;
+ u32 set;
+ u32 inv;
+};
+
+#define _CLR_OFFSET 0x04
+#define _SET_OFFSET 0x08
+#define _INV_OFFSET 0x0c
+
+/* trival alternative of ioremap */
+static inline void __iomem *pic32_ioremap(phys_addr_t addr)
+{
+ return (void __iomem *)CKSEG1ADDR(addr);
+}
+
+#endif /* __PIC32_REGS_H__ */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v2 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture
2016-01-04 14:00 [U-Boot] [PATCH v2 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture Purna Chandra Mandal
@ 2016-01-05 19:20 ` Daniel Schwierzeck
2016-01-06 6:51 ` Purna Chandra Mandal
0 siblings, 1 reply; 3+ messages in thread
From: Daniel Schwierzeck @ 2016-01-05 19:20 UTC (permalink / raw)
To: u-boot
2016-01-04 15:00 GMT+01:00 Purna Chandra Mandal <purna.mandal@microchip.com>:
> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
>
> ---
>
> Changes in v2:
> - move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
> - define register-base as physical address in header file
> - add trivial ioremap support to convert physical address to MIPS KSEG1 address
> - drop CONFIG_PIC32_SUPPORTS_FDT_BOOT as not required
>
> arch/mips/Kconfig | 6 +++
> arch/mips/Makefile | 1 +
> arch/mips/mach-pic32/Kconfig | 17 +++++++
> arch/mips/mach-pic32/Makefile | 7 +++
> arch/mips/mach-pic32/cpu.c | 13 +++++
> arch/mips/mach-pic32/include/mach/pic32.h | 79 +++++++++++++++++++++++++++++++
> 6 files changed, 123 insertions(+)
> create mode 100644 arch/mips/mach-pic32/Kconfig
> create mode 100644 arch/mips/mach-pic32/Makefile
> create mode 100644 arch/mips/mach-pic32/cpu.c
> create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 388e4c0..4b8174c 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -53,6 +53,11 @@ config TARGET_PB1X00
> select SYS_MIPS_CACHE_INIT_RAM_LOAD
> select MIPS_TUNE_4KC
>
> +config MACH_PIC32
> + bool "Support Microchip PIC32"
> + select OF_CONTROL
> + select DM
> +
> endchoice
>
> source "board/dbau1x00/Kconfig"
> @@ -60,6 +65,7 @@ source "board/imgtec/malta/Kconfig"
> source "board/micronas/vct/Kconfig"
> source "board/pb1x00/Kconfig"
> source "board/qemu-mips/Kconfig"
> +source "arch/mips/mach-pic32/Kconfig"
>
> if MIPS
>
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 90cd590..5c9da3a 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
> libs-y += arch/mips/lib/
>
> machine-$(CONFIG_SOC_AU1X00) += au1x00
> +machine-$(CONFIG_MACH_PIC32) += pic32
>
> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
> libs-y += $(machdirs)
> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
> new file mode 100644
> index 0000000..98b0b88
> --- /dev/null
> +++ b/arch/mips/mach-pic32/Kconfig
> @@ -0,0 +1,17 @@
> +menu "Microchip PIC32 platforms"
> + depends on MACH_PIC32
> +
> +config SYS_SOC
> + default "none"
> +
> +choice
> + prompt "PIC32 SoC select"
> +
> +endchoice
> +
> +choice
> + prompt "Board select"
> +
> +endchoice
> +
> +endmenu
could you add this Kconfig file with path 06/13? At least the choice
blocks should be moved. Otherwise all other MIPS boards throw a
warning, e.g.:
u-boot-mips$ make malta_defconfig
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
SHIPPED scripts/kconfig/zconf.tab.c
SHIPPED scripts/kconfig/zconf.lex.c
SHIPPED scripts/kconfig/zconf.hash.c
HOSTCC scripts/kconfig/zconf.tab.o
HOSTLD scripts/kconfig/conf
arch/mips/mach-pic32/Kconfig:7:warning: config symbol defined without type
arch/mips/mach-pic32/Kconfig:12:warning: config symbol defined without type
> diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
> new file mode 100644
> index 0000000..cb42607
> --- /dev/null
> +++ b/arch/mips/mach-pic32/Makefile
> @@ -0,0 +1,7 @@
> +# (C) Copyright 2015
> +# Purna Chandra Mandal, purna.mandal at microchip.com.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y = cpu.o
> diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
> new file mode 100644
> index 0000000..58fd3ab
> --- /dev/null
> +++ b/arch/mips/mach-pic32/cpu.c
> @@ -0,0 +1,13 @@
> +/*
> + * Copyright (C) 2015
> + * Purna Chandra Mandal <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + */
> +#include <common.h>
> +
> +phys_size_t initdram(int board_type)
> +{
> + return 0;
> +}
> diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h
> new file mode 100644
> index 0000000..f618697
> --- /dev/null
> +++ b/arch/mips/mach-pic32/include/mach/pic32.h
> @@ -0,0 +1,79 @@
> +/*
> + * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + */
> +
> +#ifndef __PIC32_REGS_H__
> +#define __PIC32_REGS_H__
> +
> +#include <asm/io.h>
> +
> +/* System Configuration */
> +#define PIC32_CFG_BASE 0x1f800000
> +
> +/* System config register offsets */
> +#define CFGCON 0x0000
> +#define DEVID 0x0020
> +#define SYSKEY 0x0030
> +#define PMD1 0x0040
> +#define PMD7 0x00a0
> +#define CFGEBIA 0x00c0
> +#define CFGEBIC 0x00d0
> +#define CFGPG 0x00e0
> +#define CFGMPLL 0x0100
> +
> +/* Non Volatile Memory (NOR flash) */
> +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
> +
> +/* Oscillator Configuration */
> +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
> +
> +/* Peripheral Pin Select Input */
> +#define PPS_IN_BASE 0x1f801400
> +/* Peripheral Pin Select Output */
> +#define PPS_OUT_BASE 0x1f801500
> +/* Pin Config */
> +#define PINCTRL_BASE 0x1f860000
> +
> +/* USB Core */
> +#define PIC32_USB_CORE_BASE 0x1f8e3000
> +#define PIC32_USB_CTRL_BASE 0x1f884000
> +
> +/* SPI1-SPI6 */
> +#define PIC32_SPI1_BASE 0x1f821000
> +
> +/* Prefetch Module */
> +#define PREFETCH_BASE 0x1f8e0000
> +
> +/* DDR2 Controller */
> +#define PIC32_DDR2C_BASE 0x1f8e8000
> +
> +/* DDR2 PHY */
> +#define PIC32_DDR2P_BASE 0x1f8e9100
> +
> +/* EBI */
> +#define PIC32_EBI_BASE 0x1f8e1000
> +
> +/* SQI */
> +#define PIC32_SQI_BASE 0x1f8e2000
> +
> +struct pic32_reg_atomic {
> + u32 raw;
> + u32 clr;
> + u32 set;
> + u32 inv;
> +};
> +
> +#define _CLR_OFFSET 0x04
> +#define _SET_OFFSET 0x08
> +#define _INV_OFFSET 0x0c
> +
> +/* trival alternative of ioremap */
> +static inline void __iomem *pic32_ioremap(phys_addr_t addr)
> +{
> + return (void __iomem *)CKSEG1ADDR(addr);
> +}
> +
> +#endif /* __PIC32_REGS_H__ */
> --
> 1.8.3.1
>
>
--
- Daniel
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH v2 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture
2016-01-05 19:20 ` Daniel Schwierzeck
@ 2016-01-06 6:51 ` Purna Chandra Mandal
0 siblings, 0 replies; 3+ messages in thread
From: Purna Chandra Mandal @ 2016-01-06 6:51 UTC (permalink / raw)
To: u-boot
On 01/06/2016 12:50 AM, Daniel Schwierzeck wrote:
> 2016-01-04 15:00 GMT+01:00 Purna Chandra Mandal <purna.mandal@microchip.com>:
>> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
>>
>> ---
>>
>> Changes in v2:
>> - move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
>> - define register-base as physical address in header file
>> - add trivial ioremap support to convert physical address to MIPS KSEG1 address
>> - drop CONFIG_PIC32_SUPPORTS_FDT_BOOT as not required
>>
>> arch/mips/Kconfig | 6 +++
>> arch/mips/Makefile | 1 +
>> arch/mips/mach-pic32/Kconfig | 17 +++++++
>> arch/mips/mach-pic32/Makefile | 7 +++
>> arch/mips/mach-pic32/cpu.c | 13 +++++
>> arch/mips/mach-pic32/include/mach/pic32.h | 79 +++++++++++++++++++++++++++++++
>> 6 files changed, 123 insertions(+)
>> create mode 100644 arch/mips/mach-pic32/Kconfig
>> create mode 100644 arch/mips/mach-pic32/Makefile
>> create mode 100644 arch/mips/mach-pic32/cpu.c
>> create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 388e4c0..4b8174c 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -53,6 +53,11 @@ config TARGET_PB1X00
>> select SYS_MIPS_CACHE_INIT_RAM_LOAD
>> select MIPS_TUNE_4KC
>>
>> +config MACH_PIC32
>> + bool "Support Microchip PIC32"
>> + select OF_CONTROL
>> + select DM
>> +
>> endchoice
>>
>> source "board/dbau1x00/Kconfig"
>> @@ -60,6 +65,7 @@ source "board/imgtec/malta/Kconfig"
>> source "board/micronas/vct/Kconfig"
>> source "board/pb1x00/Kconfig"
>> source "board/qemu-mips/Kconfig"
>> +source "arch/mips/mach-pic32/Kconfig"
>>
>> if MIPS
>>
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index 90cd590..5c9da3a 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
>> libs-y += arch/mips/lib/
>>
>> machine-$(CONFIG_SOC_AU1X00) += au1x00
>> +machine-$(CONFIG_MACH_PIC32) += pic32
>>
>> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
>> libs-y += $(machdirs)
>> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
>> new file mode 100644
>> index 0000000..98b0b88
>> --- /dev/null
>> +++ b/arch/mips/mach-pic32/Kconfig
>> @@ -0,0 +1,17 @@
>> +menu "Microchip PIC32 platforms"
>> + depends on MACH_PIC32
>> +
>> +config SYS_SOC
>> + default "none"
>> +
>> +choice
>> + prompt "PIC32 SoC select"
>> +
>> +endchoice
>> +
>> +choice
>> + prompt "Board select"
>> +
>> +endchoice
>> +
>> +endmenu
> could you add this Kconfig file with path 06/13? At least the choice
> blocks should be moved. Otherwise all other MIPS boards throw a
> warning, e.g.:
Good catch. Will move the 'choice's to other patch where they would be used.
> u-boot-mips$ make malta_defconfig
> HOSTCC scripts/basic/fixdep
> HOSTCC scripts/kconfig/conf.o
> SHIPPED scripts/kconfig/zconf.tab.c
> SHIPPED scripts/kconfig/zconf.lex.c
> SHIPPED scripts/kconfig/zconf.hash.c
> HOSTCC scripts/kconfig/zconf.tab.o
> HOSTLD scripts/kconfig/conf
> arch/mips/mach-pic32/Kconfig:7:warning: config symbol defined without type
> arch/mips/mach-pic32/Kconfig:12:warning: config symbol defined without type
>
>
>> diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
>> new file mode 100644
>> index 0000000..cb42607
>> --- /dev/null
>> +++ b/arch/mips/mach-pic32/Makefile
>> @@ -0,0 +1,7 @@
>> +# (C) Copyright 2015
>> +# Purna Chandra Mandal, purna.mandal at microchip.com.
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y = cpu.o
>> diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
>> new file mode 100644
>> index 0000000..58fd3ab
>> --- /dev/null
>> +++ b/arch/mips/mach-pic32/cpu.c
>> @@ -0,0 +1,13 @@
>> +/*
>> + * Copyright (C) 2015
>> + * Purna Chandra Mandal <purna.mandal@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +#include <common.h>
>> +
>> +phys_size_t initdram(int board_type)
>> +{
>> + return 0;
>> +}
>> diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h
>> new file mode 100644
>> index 0000000..f618697
>> --- /dev/null
>> +++ b/arch/mips/mach-pic32/include/mach/pic32.h
>> @@ -0,0 +1,79 @@
>> +/*
>> + * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + */
>> +
>> +#ifndef __PIC32_REGS_H__
>> +#define __PIC32_REGS_H__
>> +
>> +#include <asm/io.h>
>> +
>> +/* System Configuration */
>> +#define PIC32_CFG_BASE 0x1f800000
>> +
>> +/* System config register offsets */
>> +#define CFGCON 0x0000
>> +#define DEVID 0x0020
>> +#define SYSKEY 0x0030
>> +#define PMD1 0x0040
>> +#define PMD7 0x00a0
>> +#define CFGEBIA 0x00c0
>> +#define CFGEBIC 0x00d0
>> +#define CFGPG 0x00e0
>> +#define CFGMPLL 0x0100
>> +
>> +/* Non Volatile Memory (NOR flash) */
>> +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
>> +
>> +/* Oscillator Configuration */
>> +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
>> +
>> +/* Peripheral Pin Select Input */
>> +#define PPS_IN_BASE 0x1f801400
>> +/* Peripheral Pin Select Output */
>> +#define PPS_OUT_BASE 0x1f801500
>> +/* Pin Config */
>> +#define PINCTRL_BASE 0x1f860000
>> +
>> +/* USB Core */
>> +#define PIC32_USB_CORE_BASE 0x1f8e3000
>> +#define PIC32_USB_CTRL_BASE 0x1f884000
>> +
>> +/* SPI1-SPI6 */
>> +#define PIC32_SPI1_BASE 0x1f821000
>> +
>> +/* Prefetch Module */
>> +#define PREFETCH_BASE 0x1f8e0000
>> +
>> +/* DDR2 Controller */
>> +#define PIC32_DDR2C_BASE 0x1f8e8000
>> +
>> +/* DDR2 PHY */
>> +#define PIC32_DDR2P_BASE 0x1f8e9100
>> +
>> +/* EBI */
>> +#define PIC32_EBI_BASE 0x1f8e1000
>> +
>> +/* SQI */
>> +#define PIC32_SQI_BASE 0x1f8e2000
>> +
>> +struct pic32_reg_atomic {
>> + u32 raw;
>> + u32 clr;
>> + u32 set;
>> + u32 inv;
>> +};
>> +
>> +#define _CLR_OFFSET 0x04
>> +#define _SET_OFFSET 0x08
>> +#define _INV_OFFSET 0x0c
>> +
>> +/* trival alternative of ioremap */
>> +static inline void __iomem *pic32_ioremap(phys_addr_t addr)
>> +{
>> + return (void __iomem *)CKSEG1ADDR(addr);
>> +}
>> +
>> +#endif /* __PIC32_REGS_H__ */
>> --
>> 1.8.3.1
>>
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2016-01-04 14:00 [U-Boot] [PATCH v2 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture Purna Chandra Mandal
2016-01-05 19:20 ` Daniel Schwierzeck
2016-01-06 6:51 ` Purna Chandra Mandal
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