[U-Boot] [PATCH 00/11] imx: introduce rdc and boot auxiliary core

[U-Boot] [PATCH 00/11] imx: introduce rdc and boot auxiliary core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

To i.MX6SX and i.MX7D, there is a M4 core embedded. Resources
can be shared or occupied exclusively by setting Resource
domain controller between A9/7 core and M4 core.

Refer "Chapter 52 Resource Domain Controller (RDC)" of i.MX 6SoloX
RM and "Chapter 3.2 Resource Domain Controller (RDC)" of i.MX 7Dual RM
for detailed infomation.

To bootup M4 core, a new command 'bootaux' is introduced. To i.MX7D,
we need to setting RDC when booting M4 core, so make RDC and boot
auxiliary core patches into one patch set.

Peng Fan (11):
  imx: mx6: introduce rdc regs
  imx: imx-common: introduce Resource Domain Controller support
  imx: mx6sx Add RDC mappings of masters and peripherals
  imx: mx7d: Add RDC support
  imx: mx7d: clock support for RDC
  imx: imx-common: introduce boot auxiliary core
  imx: mx6: implement functions to boot auxiliary core
  imx: mx6sxsabresd: add command and macros for boot m4 core
  imx: mx7: implement functions to boot auxiliary core
  imx: mx7dsabresd: add command and macros for boot m4 core
  imx: mx7d: isolate resources to domain 0 for A7 core

 arch/arm/cpu/armv7/mx6/soc.c               |  38 ++++++
 arch/arm/cpu/armv7/mx7/clock.c             |   6 +
 arch/arm/cpu/armv7/mx7/soc.c               | 100 ++++++++++++++++
 arch/arm/imx-common/Kconfig                |  14 +++
 arch/arm/imx-common/Makefile               |   2 +
 arch/arm/imx-common/imx_bootaux.c          |  59 +++++++++
 arch/arm/imx-common/rdc-sema.c             | 184 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-rdc.h    |  16 +++
 arch/arm/include/asm/arch-mx6/imx-regs.h   |  29 +++++
 arch/arm/include/asm/arch-mx6/mx6sx_rdc.h  | 155 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx7/imx-rdc.h    |  16 +++
 arch/arm/include/asm/arch-mx7/imx-regs.h   |   8 ++
 arch/arm/include/asm/arch-mx7/mx7d_rdc.h   | 163 +++++++++++++++++++++++++
 arch/arm/include/asm/imx-common/rdc-sema.h | 117 ++++++++++++++++++
 configs/mx7dsabresd_defconfig              |   2 +
 include/configs/mx6sxsabresd.h             |  24 ++++
 include/configs/mx7dsabresd.h              |  24 ++++
 17 files changed, 957 insertions(+)
 create mode 100644 arch/arm/imx-common/imx_bootaux.c
 create mode 100644 arch/arm/imx-common/rdc-sema.c
 create mode 100644 arch/arm/include/asm/arch-mx6/imx-rdc.h
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
 create mode 100644 arch/arm/include/asm/arch-mx7/imx-rdc.h
 create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_rdc.h
 create mode 100644 arch/arm/include/asm/imx-common/rdc-sema.h

-- 
2.6.2

[U-Boot] [PATCH 01/11] imx: mx6: introduce rdc regs

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Introudce rdc regs structure and rdc sema reg structure for i.MX6.
For now, to i.MX6, only i.MX6SX supports this.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-mx6/imx-regs.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f24525e..b1de751 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -356,6 +356,30 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
 
+struct rdc_regs {
+	u32	vir;		/* Version information */
+	u32	reserved1[8];
+	u32	stat;		/* Status */
+	u32	intctrl;	/* Interrupt and Control */
+	u32	intstat;	/* Interrupt Status */
+	u32	reserved2[116];
+	u32	mda[32];	/* Master Domain Assignment */
+	u32	reserved3[96];
+	u32	pdap[104];	/* Peripheral Domain Access Permissions */
+	u32	reserved4[88];
+	struct {
+		u32 mrsa;	/* Memory Region Start Address */
+		u32 mrea;	/* Memory Region End Address */
+		u32 mrc;	/* Memory Region Control */
+		u32 mrvs;	/* Memory Region Violation Status */
+	} mem_region[55];
+};
+
+struct rdc_sema_regs {
+	u8	gate[64];	/* Gate */
+	u16	rstgt;		/* Reset Gate */
+};
+
 /* WEIM registers */
 struct weim {
 	u32 cs0gcr1;
-- 
2.6.2

[U-Boot] [PATCH 02/11] imx: imx-common: introduce Resource Domain Controller support

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/imx-common/Kconfig                |   8 ++
 arch/arm/imx-common/Makefile               |   1 +
 arch/arm/imx-common/rdc-sema.c             | 184 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-rdc.h    |  12 ++
 arch/arm/include/asm/imx-common/rdc-sema.h | 117 ++++++++++++++++++
 5 files changed, 322 insertions(+)
 create mode 100644 arch/arm/imx-common/rdc-sema.c
 create mode 100644 arch/arm/include/asm/arch-mx6/imx-rdc.h
 create mode 100644 arch/arm/include/asm/imx-common/rdc-sema.h

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index 2296239..c4f48bb 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -3,3 +3,11 @@ config IMX_CONFIG
 
 config ROM_UNIFIED_SECTIONS
 	bool
+
+config IMX_RDC
+	bool "i.MX Resource domain controller driver"
+	depends on ARCH_MX6 || ARCH_MX7
+	help
+	  i.MX Resource domain controller is used to assign masters
+	  and peripherals to differet domains. This can be used to
+	  isolate resources.
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index e7190c3..568f41c 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y 	+= cache.o init.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c
new file mode 100644
index 0000000..7db1ec5
--- /dev/null
+++ b/arch/arm/imx-common/rdc-sema.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#include <asm-generic/errno.h>
+
+/*
+ * Check if the RDC Semaphore is required for this peripheral.
+ */
+static inline int imx_rdc_check_sema_required(int per_id)
+{
+	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+	u32 reg;
+
+	reg = readl(&imx_rdc->pdap[per_id]);
+	/*
+	 * No semaphore:
+	 * Intial value or this peripheral is assigned to only one domain
+	 */
+	if (!(reg & RDC_PDAP_SREQ_MASK))
+		return -ENOENT;
+
+	return 0;
+}
+
+/*
+ * Check the peripheral read / write access permission on Domain 0.
+ * (Always assume the main CPU is in Domain 0)
+ */
+int imx_rdc_check_permission(int per_id)
+{
+	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+	u32 reg;
+
+	reg = readl(&imx_rdc->pdap[per_id]);
+	if (!(reg & (RDC_PDAP_D0W_MASK | RDC_PDAP_D0R_MASK)))
+		return -EACCES;  /*No access*/
+
+	return 0;
+}
+
+/*
+ * Lock up the RDC semaphore for this peripheral if semaphore is required.
+ */
+int imx_rdc_sema_lock(int per_id)
+{
+	struct rdc_sema_regs *imx_rdc_sema;
+	int ret;
+	u8 reg;
+
+	ret = imx_rdc_check_sema_required(per_id);
+	if (ret)
+		return ret;
+
+	if (per_id < SEMA_GATES_NUM)
+		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
+	else
+		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
+
+	do {
+		writeb(RDC_SEMA_PROC_ID,
+		       &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+		reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+		if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
+			break;  /* Get the Semaphore*/
+	} while (1);
+
+	return 0;
+}
+
+/*
+ * Unlock the RDC semaphore for this peripheral if main CPU is the
+ * semaphore owner.
+ */
+int imx_rdc_sema_unlock(int per_id)
+{
+	struct rdc_sema_regs *imx_rdc_sema;
+	int ret;
+	u8 reg;
+
+	ret = imx_rdc_check_sema_required(per_id);
+	if (ret)
+		return ret;
+
+	if (per_id < SEMA_GATES_NUM)
+		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
+	else
+		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
+
+	reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+	if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
+		return 1;	/*Not the semaphore owner */
+
+	writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+
+	return 0;
+}
+
+/*
+ * Setup RDC setting for one peripheral
+ */
+int imx_rdc_setup_peri(rdc_peri_cfg_t p)
+{
+	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+	u32 reg = 0;
+	u32 share_count = 0;
+	u32 peri_id = p & RDC_PERI_MASK;
+	u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
+
+	/* No domain assigned */
+	if (domain == 0)
+		return -EINVAL;
+
+	reg |= domain;
+
+	share_count = (domain & 0x3)
+		+ ((domain >> 2) & 0x3)
+		+ ((domain >> 4) & 0x3)
+		+ ((domain >> 6) & 0x3);
+
+	if (share_count > 0x3)
+		reg |= RDC_PDAP_SREQ_MASK;
+
+	writel(reg, &imx_rdc->pdap[peri_id]);
+
+	return 0;
+}
+
+/*
+ * Setup RDC settings for multiple peripherals
+ */
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+				     unsigned count)
+{
+	rdc_peri_cfg_t const *p = peripherals_list;
+	int i, ret;
+
+	for (i = 0; i < count; i++) {
+		ret = imx_rdc_setup_peri(*p);
+		if (ret)
+			return ret;
+		p++;
+	}
+
+	return 0;
+}
+
+/*
+ * Setup RDC setting for one master
+ */
+int imx_rdc_setup_ma(rdc_ma_cfg_t p)
+{
+	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+	u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
+	u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
+
+	writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
+
+	return 0;
+}
+
+/*
+ * Setup RDC settings for multiple masters
+ */
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
+{
+	rdc_ma_cfg_t const *p = masters_list;
+	int i, ret;
+
+	for (i = 0; i < count; i++) {
+		ret = imx_rdc_setup_ma(*p);
+		if (ret)
+			return ret;
+		p++;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h
new file mode 100644
index 0000000..5754f04
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __IMX_RDC_H__
+#define __IMX_RDC_H__
+
+#error "Please select cpu"
+
+#endif	/* __IMX_RDC_H__*/
diff --git a/arch/arm/include/asm/imx-common/rdc-sema.h b/arch/arm/include/asm/imx-common/rdc-sema.h
new file mode 100644
index 0000000..4470709
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/rdc-sema.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __RDC_SEMA_H__
+#define __RDC_SEMA_H__
+
+/*
+ *   [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
+ *      d3      d2      d1       d0    | master id  |  peri id
+ *   d[x] means domain[x], x can be [3 - 0].
+ */
+typedef u32 rdc_peri_cfg_t;
+typedef u32 rdc_ma_cfg_t;
+
+#define RDC_PERI_SHIFT		0
+#define RDC_PERI_MASK		0xFF
+
+#define RDC_DOMAIN_SHIFT_BASE	16
+#define RDC_DOMAIN_MASK		0xFF0000
+#define RDC_DOMAIN_SHIFT(x)	(RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
+#define RDC_DOMAIN(x)		((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
+
+#define RDC_MASTER_SHIFT	8
+#define RDC_MASTER_MASK		0xFF00
+#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
+					(domain_id << RDC_DOMAIN_SHIFT_BASE))
+
+/* The Following macro definitions are common to i.MX6SX and i.MX7D */
+#define SEMA_GATES_NUM		64
+
+#define RDC_MDA_DID_SHIFT	0
+#define RDC_MDA_DID_MASK	(0x3 << RDC_MDA_DID_SHIFT)
+#define RDC_MDA_LCK_SHIFT	31
+#define RDC_MDA_LCK_MASK	(0x1 << RDC_MDA_LCK_SHIFT)
+
+#define RDC_PDAP_D0W_SHIFT	0
+#define RDC_PDAP_D0W_MASK	(0x1 << RDC_PDAP_D0W_SHIFT)
+#define RDC_PDAP_D0R_SHIFT	1
+#define RDC_PDAP_D0R_MASK	(0x1 << RDC_PDAP_D0R_SHIFT)
+#define RDC_PDAP_D1W_SHIFT	2
+#define RDC_PDAP_D1W_MASK	(0x1 << RDC_PDAP_D1W_SHIFT)
+#define RDC_PDAP_D1R_SHIFT	3
+#define RDC_PDAP_D1R_MASK	(0x1 << RDC_PDAP_D1R_SHIFT)
+#define RDC_PDAP_D2W_SHIFT	4
+#define RDC_PDAP_D2W_MASK	(0x1 << RDC_PDAP_D2W_SHIFT)
+#define RDC_PDAP_D2R_SHIFT	5
+#define RDC_PDAP_D2R_MASK	(0x1 << RDC_PDAP_D2R_SHIFT)
+#define RDC_PDAP_D3W_SHIFT	6
+#define RDC_PDAP_D3W_MASK	(0x1 << RDC_PDAP_D3W_SHIFT)
+#define RDC_PDAP_D3R_SHIFT	7
+#define RDC_PDAP_D3R_MASK	(0x1 << RDC_PDAP_D3R_SHIFT)
+#define RDC_PDAP_SREQ_SHIFT	30
+#define RDC_PDAP_SREQ_MASK	(0x1 << RDC_PDAP_SREQ_SHIFT)
+#define RDC_PDAP_LCK_SHIFT	31
+#define RDC_PDAP_LCK_MASK	(0x1 << RDC_PDAP_LCK_SHIFT)
+
+#define RDC_MRSA_SADR_SHIFT	7
+#define RDC_MRSA_SADR_MASK	(0x1ffffff << RDC_MRSA_SADR_SHIFT)
+
+#define RDC_MREA_EADR_SHIFT	7
+#define RDC_MREA_EADR_MASK	(0x1ffffff << RDC_MREA_EADR_SHIFT)
+
+#define RDC_MRC_D0W_SHIFT	0
+#define RDC_MRC_D0W_MASK	(0x1 << RDC_MRC_D0W_SHIFT)
+#define RDC_MRC_D0R_SHIFT	1
+#define RDC_MRC_D0R_MASK	(0x1 << RDC_MRC_D0R_SHIFT)
+#define RDC_MRC_D1W_SHIFT	2
+#define RDC_MRC_D1W_MASK	(0x1 << RDC_MRC_D1W_SHIFT)
+#define RDC_MRC_D1R_SHIFT	3
+#define RDC_MRC_D1R_MASK	(0x1 << RDC_MRC_D1R_SHIFT)
+#define RDC_MRC_D2W_SHIFT	4
+#define RDC_MRC_D2W_MASK	(0x1 << RDC_MRC_D2W_SHIFT)
+#define RDC_MRC_D2R_SHIFT	5
+#define RDC_MRC_D2R_MASK	(0x1 << RDC_MRC_D2R_SHIFT)
+#define RDC_MRC_D3W_SHIFT	6
+#define RDC_MRC_D3W_MASK	(0x1 << RDC_MRC_D3W_SHIFT)
+#define RDC_MRC_D3R_SHIFT	7
+#define RDC_MRC_D3R_MASK	(0x1 << RDC_MRC_D3R_SHIFT)
+#define RDC_MRC_ENA_SHIFT	30
+#define RDC_MRC_ENA_MASK	(0x1 << RDC_MRC_ENA_SHIFT)
+#define RDC_MRC_LCK_SHIFT	31
+#define RDC_MRC_LCK_MASK	(0x1 << RDC_MRC_LCK_SHIFT)
+
+#define RDC_MRVS_VDID_SHIFT	0
+#define RDC_MRVS_VDID_MASK	(0x3 << RDC_MRVS_VDID_SHIFT)
+#define RDC_MRVS_AD_SHIFT	4
+#define RDC_MRVS_AD_MASK	(0x1 << RDC_MRVS_AD_SHIFT)
+#define RDC_MRVS_VADDR_SHIFT	5
+#define RDC_MRVS_VADDR_MASK	(0x7ffffff << RDC_MRVS_VADDR_SHIFT)
+
+#define RDC_SEMA_GATE_GTFSM_SHIFT	0
+#define RDC_SEMA_GATE_GTFSM_MASK	(0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
+#define RDC_SEMA_GATE_LDOM_SHIFT	5
+#define RDC_SEMA_GATE_LDOM_MASK		(0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
+
+#define RDC_SEMA_RSTGT_RSTGDP_SHIFT	0
+#define RDC_SEMA_RSTGT_RSTGDP_MASK	(0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGSM_SHIFT	2
+#define RDC_SEMA_RSTGT_RSTGSM_MASK	(0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGMS_SHIFT	4
+#define RDC_SEMA_RSTGT_RSTGMS_MASK	(0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGTN_SHIFT	8
+#define RDC_SEMA_RSTGT_RSTGTN_MASK	(0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
+
+int imx_rdc_check_permission(int per_id);
+int imx_rdc_sema_lock(int per_id);
+int imx_rdc_sema_unlock(int per_id);
+int imx_rdc_setup_peri(rdc_peri_cfg_t p);
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+			      unsigned count);
+int imx_rdc_setup_ma(rdc_ma_cfg_t p);
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
+
+#endif	/* __RDC_SEMA_H__*/
-- 
2.6.2

[U-Boot] [PATCH 03/11] imx: mx6sx Add RDC mappings of masters and peripherals

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Add the definitions for the RDC mappings for i.MX6 SoloX.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-mx6/imx-rdc.h   |   4 +
 arch/arm/include/asm/arch-mx6/mx6sx_rdc.h | 155 ++++++++++++++++++++++++++++++
 2 files changed, 159 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6sx_rdc.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h
index 5754f04..c4d3bb4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-rdc.h
+++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
@@ -7,6 +7,10 @@
 #ifndef __IMX_RDC_H__
 #define __IMX_RDC_H__
 
+#if defined(CONFIG_MX6SX)
+#include "mx6sx_rdc.h"
+#else
 #error "Please select cpu"
+#endif /* CONFIG_MX6SX */
 
 #endif	/* __IMX_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
new file mode 100644
index 0000000..addfe01
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __MX6SX_RDC_H__
+#define __MX6SX_RDC_H__
+
+#define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
+
+enum {
+	RDC_PER_PWM1 = 0,
+	RDC_PER_PWM2,
+	RDC_PER_PWM3,
+	RDC_PER_PWM4,
+	RDC_PER_CAN1,
+	RDC_PER_CAN2,
+	RDC_PER_GPT,
+	RDC_PER_GPIO1,
+	RDC_PER_GPIO2,
+	RDC_PER_GPIO3,
+	RDC_PER_GPIO4,
+	RDC_PER_GPIO5,
+	RDC_PER_GPIO6,
+	RDC_PER_GPIO7,
+	RDC_PER_KPP,
+	RDC_PER_WDOG1,
+	RDC_PER_WODG2,
+	RDC_PER_CCM,
+	RDC_PER_ANATOPDIG,
+	RDC_PER_SNVSHP,
+	RDC_PER_EPIT1,
+	RDC_PER_EPIT2,
+	RDC_PER_SRC,
+	RDC_PER_GPC,
+	RDC_PER_IOMUXC,
+	RDC_PER_IOMUXCGPR,
+	RDC_PER_CANFD1,
+	RDC_PER_SDMA,
+	RDC_PER_CANFD2,
+	RDC_PER_SEMA1,
+	RDC_PER_SEMA2,
+	RDC_PER_RDC,
+	RDC_PER_AIPSTZ1_GE1,
+	RDC_PER_AIPSTZ2_GE2,
+	RDC_PER_USBO2H_PL301,
+	RDC_PER_USBO2H_USB,
+	RDC_PER_ENET1,
+	RDC_PER_MLB25,
+	RDC_PER_USDHC1,
+	RDC_PER_USDHC2,
+	RDC_PER_USDHC3,
+	RDC_PER_USDHC4,
+	RDC_PER_I2C1,
+	RDC_PER_I2C2,
+	RDC_PER_I2C3,
+	RDC_PER_ROMCP,
+	RDC_PER_MMDC,
+	RDC_PER_ENET2,
+	RDC_PER_EIM,
+	RDC_PER_OCOTP,
+	RDC_PER_CSU,
+	RDC_PER_PERFMON1,
+	RDC_PER_PERFMON2,
+	RDC_PER_AXIMON,
+	RDC_PER_TZASC1,
+	RDC_PER_SAI1,
+	RDC_PER_AUDMUX,
+	RDC_PER_SAI2,
+	RDC_PER_QSPI1,
+	RDC_PER_QSPI2,
+	RDC_PER_UART2,
+	RDC_PER_UART3,
+	RDC_PER_UART4,
+	RDC_PER_UART5,
+	RDC_PER_I2C4,
+	RDC_PER_QOSC,
+	RDC_PER_CAAM,
+	RDC_PER_DAP,
+	RDC_PER_ADC1,
+	RDC_PER_ADC2,
+	RDC_PER_WDOG3,
+	RDC_PER_ECSPI5,
+	RDC_PER_SEMA4,
+	RDC_PER_MUPORT1,
+	RDC_PER_CANFD_CPU,
+	RDC_PER_MUPORT2,
+	RDC_PER_UART6,
+	RDC_PER_PWM5,
+	RDC_PER_PWM6,
+	RDC_PER_PWM7,
+	RDC_PER_PWM8,
+	RDC_PER_AIPSTZ3_GE0,
+	RDC_PER_AIPSTZ3_GE1,
+	RDC_PER_RESERVED1,
+	RDC_PER_SPDIF,
+	RDC_PER_ECSPI1,
+	RDC_PER_ECSPI2,
+	RDC_PER_ECSPI3,
+	RDC_PER_ECSPI4,
+	RDC_PER_RESERVED2,
+	RDC_PER_RESERVED3,
+	RDC_PER_UART1,
+	RDC_PER_ESAI,
+	RDC_PER_SSI1,
+	RDC_PER_SSI2,
+	RDC_PER_SSI3,
+	RDC_PER_ASRC,
+	RDC_PER_RESERVED4,
+	RDC_PER_SPBA_MA,
+	RDC_PER_GIS,
+	RDC_PER_DCIC1,
+	RDC_PER_DCIC2,
+	RDC_PER_CSI1,
+	RDC_PER_PXP,
+	RDC_PER_CSI2,
+	RDC_PER_LCDIF1,
+	RDC_PER_LCDIF2,
+	RDC_PER_VADC,
+	RDC_PER_VDEC,
+	RDC_PER_SPBA_DISPLAYMIX,
+};
+
+enum {
+	RDC_MA_A9_L2CACHE = 0,
+	RDC_MA_M4,
+	RDC_MA_GPU,
+	RDC_MA_CSI1,
+	RDC_MA_CSI2,
+	RDC_MA_LCDIF1,
+	RDC_MA_LCDIF2,
+	RDC_MA_PXP,
+	RDC_MA_PCIE_CTRL,
+	RDC_MA_DAP,
+	RDC_MA_CAAM,
+	RDC_MA_SDMA_PERI,
+	RDC_MA_SDMA_BURST,
+	RDC_MA_APBHDMA,
+	RDC_MA_RAWNAND,
+	RDC_MA_USDHC1,
+	RDC_MA_USDHC2,
+	RDC_MA_USDHC3,
+	RDC_MA_USDHC4,
+	RDC_MA_USB,
+	RDC_MA_MLB,
+	RDC_MA_TEST,
+	RDC_MA_ENET1_TX,
+	RDC_MA_ENET1_RX,
+	RDC_MA_ENET2_TX,
+	RDC_MA_ENET2_RX,
+	RDC_MA_SDMA,
+};
+
+#endif	/* __MX6SX_RDC_H__*/
-- 
2.6.2

[U-Boot] [PATCH 04/11] imx: mx7d: Add RDC support

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Add the peripherals/masters definitions and registers base addresses
for mx7d RDC.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-mx7/imx-rdc.h  |  16 +++
 arch/arm/include/asm/arch-mx7/imx-regs.h |   3 +
 arch/arm/include/asm/arch-mx7/mx7d_rdc.h | 163 +++++++++++++++++++++++++++++++
 3 files changed, 182 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx7/imx-rdc.h
 create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_rdc.h

diff --git a/arch/arm/include/asm/arch-mx7/imx-rdc.h b/arch/arm/include/asm/arch-mx7/imx-rdc.h
new file mode 100644
index 0000000..dbeed56
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/imx-rdc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __IMX_RDC_H__
+#define __IMX_RDC_H__
+
+#if defined(CONFIG_MX7D)
+#include "mx7d_rdc.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX7D */
+
+#endif	/* __IMX_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 58a25c7..8e66d3d 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -212,6 +212,9 @@
 #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
 
 #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
+#define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
+#define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
+#define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
diff --git a/arch/arm/include/asm/arch-mx7/mx7d_rdc.h b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h
new file mode 100644
index 0000000..9073cbd
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __MX7D_RDC_H__
+#define __MX7D_RDC_H__
+
+#define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
+
+enum {
+	RDC_PER_GPIO1 = 0,
+	RDC_PER_GPIO2,
+	RDC_PER_GPIO3,
+	RDC_PER_GPIO4,
+	RDC_PER_GPIO5,
+	RDC_PER_GPIO6,
+	RDC_PER_GPIO7,
+	RDC_PER_IOMUXC_LPSR_GPR,
+	RDC_PER_WDOG1,
+	RDC_PER_WDOG2,
+	RDC_PER_WDOG3,
+	RDC_PER_WDOG4,
+	RDC_PER_IOMUXC_LPSR,
+	RDC_PER_GPT1,
+	RDC_PER_GPT2,
+	RDC_PER_GPT3,
+	RDC_PER_GPT4,
+	RDC_PER_ROMCP,
+	RDC_PER_KPP,
+	RDC_PER_IOMUXC,
+	RDC_PER_IOMUXCGPR,
+	RDC_PER_OCOTP,
+	RDC_PER_ANATOP_DIG,
+	RDC_PER_SNVS_HP,
+	RDC_PER_CCM,
+	RDC_PER_SRC,
+	RDC_PER_GPC,
+	RDC_PER_SEMA1,
+	RDC_PER_SEMA2,
+	RDC_PER_RDC,
+	RDC_PER_CSU,
+	RDC_PER_RESERVED1,
+	RDC_PER_RESERVED2,
+	RDC_PER_ADC1,
+	RDC_PER_ADC2,
+	RDC_PER_ECSPI4,
+	RDC_PER_FLEX_TIMER1,
+	RDC_PER_FLEX_TIMER2,
+	RDC_PER_PWM1,
+	RDC_PER_PWM2,
+	RDC_PER_PWM3,
+	RDC_PER_PWM4,
+	RDC_PER_SYSTEM_COUNTER_READ,
+	RDC_PER_SYSTEM_COUNTER_COMPARE,
+	RDC_PER_SYSTEM_COUNTER_CONTROL,
+	RDC_PER_PCIE_PHY,
+	RDC_PER_RESERVED3,
+	RDC_PER_EPDC,
+	RDC_PER_PXP,
+	RDC_PER_CSI,
+	RDC_PER_RESERVED4,
+	RDC_PER_LCDIF,
+	RDC_PER_RESERVED5,
+	RDC_PER_MIPI_CSI,
+	RDC_PER_MIPI_DSI,
+	RDC_PER_RESERVED6,
+	RDC_PER_TZASC,
+	RDC_PER_DDR_PHY,
+	RDC_PER_DDRC,
+	RDC_PER_RESERVED7,
+	RDC_PER_PERFMON1,
+	RDC_PER_PERFMON2,
+	RDC_PER_AXI_DEBUG_MON,
+	RDC_PER_QOSC,
+	RDC_PER_FLEXCAN1,
+	RDC_PER_FLEXCAN2,
+	RDC_PER_I2C1,
+	RDC_PER_I2C2,
+	RDC_PER_I2C3,
+	RDC_PER_I2C4,
+	RDC_PER_UART4,
+	RDC_PER_UART5,
+	RDC_PER_UART6,
+	RDC_PER_UART7,
+	RDC_PER_MU_A,
+	RDC_PER_MU_B,
+	RDC_PER_SEMAPHORE_HS,
+	RDC_PER_USB_PL301,
+	RDC_PER_RESERVED8,
+	RDC_PER_RESERVED9,
+	RDC_PER_RESERVED10,
+	RDC_PER_USB1,
+	RDC_PER_USB2,
+	RDC_PER_USB3,
+	RDC_PER_USDHC1,
+	RDC_PER_USDHC2,
+	RDC_PER_USDHC3,
+	RDC_PER_RESERVED11,
+	RDC_PER_RESERVED12,
+	RDC_PER_SIM1,
+	RDC_PER_SIM2,
+	RDC_PER_QSPI,
+	RDC_PER_WEIM,
+	RDC_PER_SDMA,
+	RDC_PER_ENET1,
+	RDC_PER_ENET2,
+	RDC_PER_RESERVED13,
+	RDC_PER_RESERVED14,
+	RDC_PER_ECSPI1,
+	RDC_PER_ECSPI2,
+	RDC_PER_ECSPI3,
+	RDC_PER_RESERVED15,
+	RDC_PER_UART1,
+	RDC_PER_UART2,
+	RDC_PER_UART3,
+	RDC_PER_RESERVED16,
+	RDC_PER_SAI1,
+	RDC_PER_SAI2,
+	RDC_PER_SAI3,
+	RDC_PER_RESERVED17,
+	RDC_PER_RESERVED18,
+	RDC_PER_SPBA,
+	RDC_PER_DAP,
+	RDC_PER_RESERVED19,
+	RDC_PER_RESERVED20,
+	RDC_PER_RESERVED21,
+	RDC_PER_CAAM,
+	RDC_PER_RESERVED22,
+};
+
+enum {
+	RDC_MA_A7 = 0,
+	RDC_MA_M4,
+	RDC_MA_PCIE,
+	RDC_MA_CSI,
+	RDC_MA_EPDC,
+	RDC_MA_LCDIF,
+	RDC_MA_DISPLAY_PORT,
+	RDC_MA_PXP,
+	RDC_MA_CORESIGHT,
+	RDC_MA_DAP,
+	RDC_MA_CAAM,
+	RDC_MA_SDMA_PERI,
+	RDC_MA_SDMA_BURST,
+	RDC_MA_APBHDMA,
+	RDC_MA_RAWNAND,
+	RDC_MA_USDHC1,
+	RDC_MA_USDHC2,
+	RDC_MA_USDHC3,
+	RDC_MA_NC1,
+	RDC_MA_USB,
+	RDC_MA_NC2,
+	RDC_MA_TEST,
+	RDC_MA_ENET1_TX,
+	RDC_MA_ENET1_RX,
+	RDC_MA_ENET2_TX,
+	RDC_MA_ENET2_RX,
+	RDC_MA_SDMA,
+};
+
+#endif	/* __MX7D_RDC_H__*/
-- 
2.6.2

[U-Boot] [PATCH 05/11] imx: mx7d: clock support for RDC

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/cpu/armv7/mx7/clock.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c
index 77db6e8..4d68ad2 100644
--- a/arch/arm/cpu/armv7/mx7/clock.c
+++ b/arch/arm/cpu/armv7/mx7/clock.c
@@ -1067,6 +1067,12 @@ void clock_init(void)
 #ifdef CONFIG_NAND_MXS
 	clock_enable(CCGR_RAWNAND, 1);
 #endif
+
+	if (IS_ENABLED(CONFIG_IMX_RDC)) {
+		clock_enable(CCGR_RDC, 1);
+		clock_enable(CCGR_SEMA1, 1);
+		clock_enable(CCGR_SEMA2, 1);
+	}
 }
 
 #ifdef CONFIG_SECURE_BOOT
-- 
2.6.2

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".
Introduce Kconfig option IMX_BOOTAUX.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/imx-common/Kconfig       |  6 ++++
 arch/arm/imx-common/Makefile      |  1 +
 arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 arch/arm/imx-common/imx_bootaux.c

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index c4f48bb..1b7da5a 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -11,3 +11,9 @@ config IMX_RDC
 	  i.MX Resource domain controller is used to assign masters
 	  and peripherals to differet domains. This can be used to
 	  isolate resources.
+
+config IMX_BOOTAUX
+	bool "Support boot auxiliary core"
+	depends on ARCH_MX7 || ARCH_MX6
+	help
+	  bootaux [addr] to boot auxiliary core.
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 568f41c..30e66ba 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -28,6 +28,7 @@ obj-y 	+= cache.o init.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
diff --git a/arch/arm/imx-common/imx_bootaux.c b/arch/arm/imx-common/imx_bootaux.c
new file mode 100644
index 0000000..da424a7
--- /dev/null
+++ b/arch/arm/imx-common/imx_bootaux.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* Allow for arch specific config before we boot */
+static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+	/* please define platform specific arch_auxiliary_core_up() */
+	return CMD_RET_FAILURE;
+}
+
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+	__attribute__((weak, alias("__arch_auxiliary_core_up")));
+
+/* Allow for arch specific config before we boot */
+static int __arch_auxiliary_core_check_up(u32 core_id)
+{
+	/* please define platform specific arch_auxiliary_core_check_up() */
+	return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+	__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
+
+int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	int ret, up;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	up = arch_auxiliary_core_check_up(0);
+	if (up) {
+		printf("## Auxiliary core is already up\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	printf("## Starting auxiliary core@0x%08lX ...\n", addr);
+
+	ret = arch_auxiliary_core_up(0, addr);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
+	"Start auxiliary core",
+	""
+);
-- 
2.6.2

[U-Boot] [PATCH 07/11] imx: mx6: implement functions to boot auxiliary core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/cpu/armv7/mx6/soc.c             | 38 ++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h |  5 +++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bf5ae8c..ab0ccb0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -491,3 +491,41 @@ void imx_setup_hdmi(void)
 	writel(reg, &mxc_ccm->chsccdr);
 }
 #endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+	struct src *src_reg;
+	u32 stack, pc;
+
+	if (!boot_private_data)
+		return -EINVAL;
+
+	stack = *(u32 *)boot_private_data;
+	pc = *(u32 *)(boot_private_data + 4);
+
+	/* Set the stack and pc to M4 bootROM */
+	writel(stack, M4_BOOTROM_BASE_ADDR);
+	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+	/* Enable M4 */
+	src_reg = (struct src *)SRC_BASE_ADDR;
+	clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
+			SRC_SCR_M4_ENABLE_MASK);
+
+	return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+	unsigned val;
+
+	val = readl(&src_reg->scr);
+
+	if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
+		return 0;  /* assert in reset */
+
+	return 1;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index b1de751..f5ce31c 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -438,6 +438,11 @@ struct src {
 	u32     gpr10;
 };
 
+#define SRC_SCR_M4_ENABLE_OFFSET                22
+#define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
+
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
 #define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
-- 
2.6.2

[U-Boot] [PATCH 08/11] imx: mx6sxsabresd: add command and macros for boot m4 core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Introduce macros and command to support booting M4 core for
i.MX6SX SabreSD board.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/configs/mx6sxsabresd.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index edf7d3f..aafbd97 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -26,7 +26,31 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
+#ifdef CONFIG_IMX_BOOTAUX
+/* Set to QSPI2 B flash at default */
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
+#define CONFIG_CMD_SETEXPR
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 1:0; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	UPDATE_M4_ENV \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
-- 
2.6.2

[U-Boot] [PATCH 09/11] imx: mx7: implement functions to boot auxiliary core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/cpu/armv7/mx7/soc.c             | 36 ++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx7/imx-regs.h |  5 +++++
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 1d8e470..2121ff2 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -211,6 +211,42 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif
 
+#ifdef CONFIG_IMX_BOOTAUX
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+	u32 stack, pc;
+	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+
+	if (!boot_private_data)
+		return 1;
+
+	stack = *(u32 *)boot_private_data;
+	pc = *(u32 *)(boot_private_data + 4);
+
+	/* Set the stack and pc to M4 bootROM */
+	writel(stack, M4_BOOTROM_BASE_ADDR);
+	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+	/* Enable M4 */
+	clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
+			SRC_M4RCR_ENABLE_M4_MASK);
+
+	return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+	uint32_t val;
+	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+
+	val = readl(&src_reg->m4rcr);
+	if (val & 0x00000001)
+		return 0; /* assert in reset */
+
+	return 1;
+}
+#endif
+
 void set_wdog_reset(struct wdog_regs *wdog)
 {
 	u32 reg = readw(&wdog->wcr);
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 8e66d3d..5253b1e 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -260,6 +260,11 @@ struct src {
 	u32 ddrc_rcr;
 };
 
+#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET	0
+#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK		(1 << 0)
+#define SRC_M4RCR_ENABLE_M4_OFFSET		3
+#define SRC_M4RCR_ENABLE_M4_MASK		(1 << 3)
+
 /* GPR0 Bit Fields */
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT    0
-- 
2.6.2

[U-Boot] [PATCH 10/11] imx: mx7dsabresd: add command and macros for boot m4 core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

Introduce macros and command to support booting M4 core for
i.MX7D SabreSD board.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/configs/mx7dsabresd.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index cc98547..329df66 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -57,6 +57,29 @@
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
 
+#ifdef CONFIG_IMX_BOOTAUX
+/* Set to QSPI1 A flash at default */
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
+#define CONFIG_CMD_SETEXPR
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 0:0; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
 #define CONFIG_MFG_ENV_SETTINGS \
 	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
 		"rdinit=/linuxrc " \
@@ -76,6 +99,7 @@
 		"rootfs part 0 2\0" \
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	UPDATE_M4_ENV \
 	CONFIG_MFG_ENV_SETTINGS \
 	CONFIG_DFU_ENV_SETTINGS \
 	"script=boot.scr\0" \
-- 
2.6.2

[U-Boot] [PATCH 11/11] imx: mx7d: isolate resources to domain 0 for A7 core

[Peng Fan]

From: Peng Fan <peng.fan@nxp.com>

In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.

This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/cpu/armv7/mx7/soc.c  | 64 +++++++++++++++++++++++++++++++++++++++++++
 configs/mx7dsabresd_defconfig |  2 ++
 2 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 2121ff2..ede7d53 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -12,6 +12,8 @@
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
 #include <asm/imx-common/hab.h>
+#include <asm/imx-common/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
 #include <asm/arch/crm_regs.h>
 #include <dm.h>
 #include <imx_thermal.h>
@@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = {
 };
 #endif
 
+#ifdef CONFIG_IMX_RDC
+/*
+ * In current design, if any peripheral was assigned to both A7 and M4,
+ * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
+ * low power mode. So M4 sleep will cause some peripherals fail to work
+ * at A7 core side. At default, all resources are in domain 0 - 3.
+ *
+ * There are 26 peripherals impacted by this IC issue:
+ * SIM2(sim2/emvsim2)
+ * SIM1(sim1/emvsim1)
+ * UART1/UART2/UART3/UART4/UART5/UART6/UART7
+ * SAI1/SAI2/SAI3
+ * WDOG1/WDOG2/WDOG3/WDOG4
+ * GPT1/GPT2/GPT3/GPT4
+ * PWM1/PWM2/PWM3/PWM4
+ * ENET1/ENET2
+ * Software Workaround:
+ * Here we setup some resources to domain 0 where M4 codes will move
+ * the M4 out of this domain. Then M4 is not able to access them any longer.
+ * This is a workaround for ic issue. So the peripherals are not shared
+ * by them. This way requires the uboot implemented the RDC driver and
+ * set the 26 IPs above to domain 0 only. M4 code will assign resource
+ * to its own domain, if it want to use the resource.
+ */
+static rdc_peri_cfg_t const resources[] = {
+	(RDC_PER_SIM1 | RDC_DOMAIN(0)),
+	(RDC_PER_SIM2 | RDC_DOMAIN(0)),
+	(RDC_PER_UART1 | RDC_DOMAIN(0)),
+	(RDC_PER_UART2 | RDC_DOMAIN(0)),
+	(RDC_PER_UART3 | RDC_DOMAIN(0)),
+	(RDC_PER_UART4 | RDC_DOMAIN(0)),
+	(RDC_PER_UART5 | RDC_DOMAIN(0)),
+	(RDC_PER_UART6 | RDC_DOMAIN(0)),
+	(RDC_PER_UART7 | RDC_DOMAIN(0)),
+	(RDC_PER_SAI1 | RDC_DOMAIN(0)),
+	(RDC_PER_SAI2 | RDC_DOMAIN(0)),
+	(RDC_PER_SAI3 | RDC_DOMAIN(0)),
+	(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
+	(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
+	(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
+	(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
+	(RDC_PER_GPT1 | RDC_DOMAIN(0)),
+	(RDC_PER_GPT2 | RDC_DOMAIN(0)),
+	(RDC_PER_GPT3 | RDC_DOMAIN(0)),
+	(RDC_PER_GPT4 | RDC_DOMAIN(0)),
+	(RDC_PER_PWM1 | RDC_DOMAIN(0)),
+	(RDC_PER_PWM2 | RDC_DOMAIN(0)),
+	(RDC_PER_PWM3 | RDC_DOMAIN(0)),
+	(RDC_PER_PWM4 | RDC_DOMAIN(0)),
+	(RDC_PER_ENET1 | RDC_DOMAIN(0)),
+	(RDC_PER_ENET2 | RDC_DOMAIN(0)),
+};
+
+static void isolate_resource(void)
+{
+	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
+}
+#endif
+
 #if defined(CONFIG_SECURE_BOOT)
 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 	.bank = 1,
@@ -163,6 +224,9 @@ int arch_cpu_init(void)
 	mxs_dma_init();
 #endif
 
+	if (IS_ENABLED(CONFIG_IMX_RDC))
+		isolate_resource();
+
 	return 0;
 }
 
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 420d13e..1d262c1 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX7=y
 CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMI is not set
-- 
2.6.2

[U-Boot] [PATCH 02/11] imx: imx-common: introduce Resource Domain Controller support

[Stefan Agner]

Hi Peng,

Some minor questions/remarks below.

On 2016-01-04 21:56, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Introduce Resource Domain Controller support for i.MX.
> Now i.MX6SX and i.MX7D supports this feature to assign masters
> and peripherals to different domains.
> 
> Signed-off-by: Ye.Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/imx-common/Kconfig                |   8 ++
>  arch/arm/imx-common/Makefile               |   1 +
>  arch/arm/imx-common/rdc-sema.c             | 184 +++++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-mx6/imx-rdc.h    |  12 ++
>  arch/arm/include/asm/imx-common/rdc-sema.h | 117 ++++++++++++++++++
>  5 files changed, 322 insertions(+)
>  create mode 100644 arch/arm/imx-common/rdc-sema.c
>  create mode 100644 arch/arm/include/asm/arch-mx6/imx-rdc.h
>  create mode 100644 arch/arm/include/asm/imx-common/rdc-sema.h
> 
> diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
> index 2296239..c4f48bb 100644
> --- a/arch/arm/imx-common/Kconfig
> +++ b/arch/arm/imx-common/Kconfig
> @@ -3,3 +3,11 @@ config IMX_CONFIG
>  
>  config ROM_UNIFIED_SECTIONS
>  	bool
> +
> +config IMX_RDC
> +	bool "i.MX Resource domain controller driver"
> +	depends on ARCH_MX6 || ARCH_MX7
> +	help
> +	  i.MX Resource domain controller is used to assign masters
> +	  and peripherals to differet domains. This can be used to
> +	  isolate resources.
> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
> index e7190c3..568f41c 100644
> --- a/arch/arm/imx-common/Makefile
> +++ b/arch/arm/imx-common/Makefile
> @@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
>  obj-y 	+= cache.o init.o
>  obj-$(CONFIG_CMD_SATA) += sata.o
>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
> +obj-$(CONFIG_IMX_RDC) += rdc-sema.o
>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>  endif
>  ifeq ($(SOC),$(filter $(SOC),vf610))
> diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c
> new file mode 100644
> index 0000000..7db1ec5
> --- /dev/null
> +++ b/arch/arm/imx-common/rdc-sema.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/rdc-sema.h>
> +#include <asm/arch/imx-rdc.h>
> +#include <asm-generic/errno.h>
> +
> +/*
> + * Check if the RDC Semaphore is required for this peripheral.
> + */
> +static inline int imx_rdc_check_sema_required(int per_id)
> +{
> +	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
> +	u32 reg;
> +
> +	reg = readl(&imx_rdc->pdap[per_id]);
> +	/*
> +	 * No semaphore:
> +	 * Intial value or this peripheral is assigned to only one domain
> +	 */
> +	if (!(reg & RDC_PDAP_SREQ_MASK))
> +		return -ENOENT;
> +
> +	return 0;
> +}
> +
> +/*
> + * Check the peripheral read / write access permission on Domain 0.
> + * (Always assume the main CPU is in Domain 0)

Hence you assuming that U-Boot is also always running on main CPU right?
I guess this is ok for now.

> + */
> +int imx_rdc_check_permission(int per_id)
> +{
> +	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
> +	u32 reg;
> +
> +	reg = readl(&imx_rdc->pdap[per_id]);
> +	if (!(reg & (RDC_PDAP_D0W_MASK | RDC_PDAP_D0R_MASK)))
> +		return -EACCES;  /*No access*/
> +
> +	return 0;
> +}
> +
> +/*
> + * Lock up the RDC semaphore for this peripheral if semaphore is required.
> + */
> +int imx_rdc_sema_lock(int per_id)
> +{
> +	struct rdc_sema_regs *imx_rdc_sema;
> +	int ret;
> +	u8 reg;
> +
> +	ret = imx_rdc_check_sema_required(per_id);
> +	if (ret)
> +		return ret;
> +
> +	if (per_id < SEMA_GATES_NUM)
> +		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
> +	else
> +		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
> +
> +	do {
> +		writeb(RDC_SEMA_PROC_ID,
> +		       &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
> +		reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
> +		if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
> +			break;  /* Get the Semaphore*/
> +	} while (1);
> +
> +	return 0;
> +}
> +
> +/*
> + * Unlock the RDC semaphore for this peripheral if main CPU is the
> + * semaphore owner.
> + */
> +int imx_rdc_sema_unlock(int per_id)
> +{
> +	struct rdc_sema_regs *imx_rdc_sema;
> +	int ret;
> +	u8 reg;
> +
> +	ret = imx_rdc_check_sema_required(per_id);
> +	if (ret)
> +		return ret;
> +
> +	if (per_id < SEMA_GATES_NUM)
> +		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
> +	else
> +		imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
> +
> +	reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
> +	if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
> +		return 1;	/*Not the semaphore owner */
> +
> +	writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
> +
> +	return 0;
> +}
> +
> +/*
> + * Setup RDC setting for one peripheral
> + */
> +int imx_rdc_setup_peri(rdc_peri_cfg_t p)
> +{
> +	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
> +	u32 reg = 0;
> +	u32 share_count = 0;
> +	u32 peri_id = p & RDC_PERI_MASK;
> +	u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
> +
> +	/* No domain assigned */
> +	if (domain == 0)
> +		return -EINVAL;
> +
> +	reg |= domain;
> +
> +	share_count = (domain & 0x3)
> +		+ ((domain >> 2) & 0x3)
> +		+ ((domain >> 4) & 0x3)
> +		+ ((domain >> 6) & 0x3);
> +
> +	if (share_count > 0x3)
> +		reg |= RDC_PDAP_SREQ_MASK;
> +
> +	writel(reg, &imx_rdc->pdap[peri_id]);
> +
> +	return 0;
> +}
> +
> +/*
> + * Setup RDC settings for multiple peripherals
> + */
> +int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
> +				     unsigned count)
> +{
> +	rdc_peri_cfg_t const *p = peripherals_list;
> +	int i, ret;
> +
> +	for (i = 0; i < count; i++) {
> +		ret = imx_rdc_setup_peri(*p);
> +		if (ret)
> +			return ret;
> +		p++;
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Setup RDC setting for one master
> + */
> +int imx_rdc_setup_ma(rdc_ma_cfg_t p)
> +{
> +	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
> +	u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
> +	u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
> +
> +	writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
> +
> +	return 0;
> +}
> +
> +/*
> + * Setup RDC settings for multiple masters
> + */
> +int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
> +{
> +	rdc_ma_cfg_t const *p = masters_list;
> +	int i, ret;
> +
> +	for (i = 0; i < count; i++) {
> +		ret = imx_rdc_setup_ma(*p);
> +		if (ret)
> +			return ret;
> +		p++;
> +	}
> +
> +	return 0;
> +}
> diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h
> b/arch/arm/include/asm/arch-mx6/imx-rdc.h
> new file mode 100644
> index 0000000..5754f04
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
> @@ -0,0 +1,12 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef __IMX_RDC_H__
> +#define __IMX_RDC_H__
> +
> +#error "Please select cpu"

I don't understand this, wouldn't lead this always to an error?

> +
> +#endif	/* __IMX_RDC_H__*/
> diff --git a/arch/arm/include/asm/imx-common/rdc-sema.h
> b/arch/arm/include/asm/imx-common/rdc-sema.h
> new file mode 100644
> index 0000000..4470709
> --- /dev/null
> +++ b/arch/arm/include/asm/imx-common/rdc-sema.h
> @@ -0,0 +1,117 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef __RDC_SEMA_H__
> +#define __RDC_SEMA_H__
> +
> +/*
> + *   [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
> + *      d3      d2      d1       d0    | master id  |  peri id
> + *   d[x] means domain[x], x can be [3 - 0].
> + */
> +typedef u32 rdc_peri_cfg_t;
> +typedef u32 rdc_ma_cfg_t;
> +
> +#define RDC_PERI_SHIFT		0
> +#define RDC_PERI_MASK		0xFF
> +
> +#define RDC_DOMAIN_SHIFT_BASE	16
> +#define RDC_DOMAIN_MASK		0xFF0000
> +#define RDC_DOMAIN_SHIFT(x)	(RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
> +#define RDC_DOMAIN(x)		((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
> +
> +#define RDC_MASTER_SHIFT	8
> +#define RDC_MASTER_MASK		0xFF00
> +#define RDC_MASTER_CFG(master_id, domain_id)
> (rdc_ma_cfg_t)((master_id << 8) | \
> +					(domain_id << RDC_DOMAIN_SHIFT_BASE))
> +
> +/* The Following macro definitions are common to i.MX6SX and i.MX7D */
> +#define SEMA_GATES_NUM		64
> +
> +#define RDC_MDA_DID_SHIFT	0
> +#define RDC_MDA_DID_MASK	(0x3 << RDC_MDA_DID_SHIFT)
> +#define RDC_MDA_LCK_SHIFT	31
> +#define RDC_MDA_LCK_MASK	(0x1 << RDC_MDA_LCK_SHIFT)
> +
> +#define RDC_PDAP_D0W_SHIFT	0
> +#define RDC_PDAP_D0W_MASK	(0x1 << RDC_PDAP_D0W_SHIFT)
> +#define RDC_PDAP_D0R_SHIFT	1
> +#define RDC_PDAP_D0R_MASK	(0x1 << RDC_PDAP_D0R_SHIFT)
> +#define RDC_PDAP_D1W_SHIFT	2
> +#define RDC_PDAP_D1W_MASK	(0x1 << RDC_PDAP_D1W_SHIFT)
> +#define RDC_PDAP_D1R_SHIFT	3
> +#define RDC_PDAP_D1R_MASK	(0x1 << RDC_PDAP_D1R_SHIFT)
> +#define RDC_PDAP_D2W_SHIFT	4
> +#define RDC_PDAP_D2W_MASK	(0x1 << RDC_PDAP_D2W_SHIFT)
> +#define RDC_PDAP_D2R_SHIFT	5
> +#define RDC_PDAP_D2R_MASK	(0x1 << RDC_PDAP_D2R_SHIFT)
> +#define RDC_PDAP_D3W_SHIFT	6
> +#define RDC_PDAP_D3W_MASK	(0x1 << RDC_PDAP_D3W_SHIFT)
> +#define RDC_PDAP_D3R_SHIFT	7
> +#define RDC_PDAP_D3R_MASK	(0x1 << RDC_PDAP_D3R_SHIFT)

Nit: How about RDC_PDAP_DXW_SHIFT(domain)   (2 * domain) style defines?
 
> +#define RDC_PDAP_SREQ_SHIFT	30
> +#define RDC_PDAP_SREQ_MASK	(0x1 << RDC_PDAP_SREQ_SHIFT)
> +#define RDC_PDAP_LCK_SHIFT	31
> +#define RDC_PDAP_LCK_MASK	(0x1 << RDC_PDAP_LCK_SHIFT)
> +
> +#define RDC_MRSA_SADR_SHIFT	7
> +#define RDC_MRSA_SADR_MASK	(0x1ffffff << RDC_MRSA_SADR_SHIFT)
> +
> +#define RDC_MREA_EADR_SHIFT	7
> +#define RDC_MREA_EADR_MASK	(0x1ffffff << RDC_MREA_EADR_SHIFT)
> +
> +#define RDC_MRC_D0W_SHIFT	0
> +#define RDC_MRC_D0W_MASK	(0x1 << RDC_MRC_D0W_SHIFT)
> +#define RDC_MRC_D0R_SHIFT	1
> +#define RDC_MRC_D0R_MASK	(0x1 << RDC_MRC_D0R_SHIFT)
> +#define RDC_MRC_D1W_SHIFT	2
> +#define RDC_MRC_D1W_MASK	(0x1 << RDC_MRC_D1W_SHIFT)
> +#define RDC_MRC_D1R_SHIFT	3
> +#define RDC_MRC_D1R_MASK	(0x1 << RDC_MRC_D1R_SHIFT)
> +#define RDC_MRC_D2W_SHIFT	4
> +#define RDC_MRC_D2W_MASK	(0x1 << RDC_MRC_D2W_SHIFT)
> +#define RDC_MRC_D2R_SHIFT	5
> +#define RDC_MRC_D2R_MASK	(0x1 << RDC_MRC_D2R_SHIFT)
> +#define RDC_MRC_D3W_SHIFT	6
> +#define RDC_MRC_D3W_MASK	(0x1 << RDC_MRC_D3W_SHIFT)
> +#define RDC_MRC_D3R_SHIFT	7
> +#define RDC_MRC_D3R_MASK	(0x1 << RDC_MRC_D3R_SHIFT)
> +#define RDC_MRC_ENA_SHIFT	30
> +#define RDC_MRC_ENA_MASK	(0x1 << RDC_MRC_ENA_SHIFT)
> +#define RDC_MRC_LCK_SHIFT	31
> +#define RDC_MRC_LCK_MASK	(0x1 << RDC_MRC_LCK_SHIFT)
> +
> +#define RDC_MRVS_VDID_SHIFT	0
> +#define RDC_MRVS_VDID_MASK	(0x3 << RDC_MRVS_VDID_SHIFT)
> +#define RDC_MRVS_AD_SHIFT	4
> +#define RDC_MRVS_AD_MASK	(0x1 << RDC_MRVS_AD_SHIFT)
> +#define RDC_MRVS_VADDR_SHIFT	5
> +#define RDC_MRVS_VADDR_MASK	(0x7ffffff << RDC_MRVS_VADDR_SHIFT)
> +
> +#define RDC_SEMA_GATE_GTFSM_SHIFT	0
> +#define RDC_SEMA_GATE_GTFSM_MASK	(0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
> +#define RDC_SEMA_GATE_LDOM_SHIFT	5
> +#define RDC_SEMA_GATE_LDOM_MASK		(0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
> +
> +#define RDC_SEMA_RSTGT_RSTGDP_SHIFT	0
> +#define RDC_SEMA_RSTGT_RSTGDP_MASK	(0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
> +#define RDC_SEMA_RSTGT_RSTGSM_SHIFT	2
> +#define RDC_SEMA_RSTGT_RSTGSM_MASK	(0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
> +#define RDC_SEMA_RSTGT_RSTGMS_SHIFT	4
> +#define RDC_SEMA_RSTGT_RSTGMS_MASK	(0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
> +#define RDC_SEMA_RSTGT_RSTGTN_SHIFT	8
> +#define RDC_SEMA_RSTGT_RSTGTN_MASK	(0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
> +
> +int imx_rdc_check_permission(int per_id);
> +int imx_rdc_sema_lock(int per_id);
> +int imx_rdc_sema_unlock(int per_id);
> +int imx_rdc_setup_peri(rdc_peri_cfg_t p);
> +int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
> +			      unsigned count);
> +int imx_rdc_setup_ma(rdc_ma_cfg_t p);
> +int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
> +
> +#endif	/* __RDC_SEMA_H__*/

[U-Boot] [PATCH 03/11] imx: mx6sx Add RDC mappings of masters and peripherals

[Stefan Agner]

On 2016-01-04 21:56, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add the definitions for the RDC mappings for i.MX6 SoloX.
> 
> Signed-off-by: Ye.Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/include/asm/arch-mx6/imx-rdc.h   |   4 +
>  arch/arm/include/asm/arch-mx6/mx6sx_rdc.h | 155 ++++++++++++++++++++++++++++++
>  2 files changed, 159 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
> 
> diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h
> b/arch/arm/include/asm/arch-mx6/imx-rdc.h
> index 5754f04..c4d3bb4 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-rdc.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
> @@ -7,6 +7,10 @@
>  #ifndef __IMX_RDC_H__
>  #define __IMX_RDC_H__
>  
> +#if defined(CONFIG_MX6SX)
> +#include "mx6sx_rdc.h"
> +#else
>  #error "Please select cpu"
> +#endif /* CONFIG_MX6SX */

Ah now I see, things start to make sense.

With that the previous patch is basically not usable by itself, but
since it is still hidden behind a configuration I guess it is ok.

--
Stefan

>  
>  #endif	/* __IMX_RDC_H__*/
> diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
> b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
> new file mode 100644
> index 0000000..addfe01
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
> @@ -0,0 +1,155 @@
> +/*
> + * Copyright (C) 2014 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef __MX6SX_RDC_H__
> +#define __MX6SX_RDC_H__
> +
> +#define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
> +
> +enum {
> +	RDC_PER_PWM1 = 0,
> +	RDC_PER_PWM2,
> +	RDC_PER_PWM3,
> +	RDC_PER_PWM4,
> +	RDC_PER_CAN1,
> +	RDC_PER_CAN2,
> +	RDC_PER_GPT,
> +	RDC_PER_GPIO1,
> +	RDC_PER_GPIO2,
> +	RDC_PER_GPIO3,
> +	RDC_PER_GPIO4,
> +	RDC_PER_GPIO5,
> +	RDC_PER_GPIO6,
> +	RDC_PER_GPIO7,
> +	RDC_PER_KPP,
> +	RDC_PER_WDOG1,
> +	RDC_PER_WODG2,
> +	RDC_PER_CCM,
> +	RDC_PER_ANATOPDIG,
> +	RDC_PER_SNVSHP,
> +	RDC_PER_EPIT1,
> +	RDC_PER_EPIT2,
> +	RDC_PER_SRC,
> +	RDC_PER_GPC,
> +	RDC_PER_IOMUXC,
> +	RDC_PER_IOMUXCGPR,
> +	RDC_PER_CANFD1,
> +	RDC_PER_SDMA,
> +	RDC_PER_CANFD2,
> +	RDC_PER_SEMA1,
> +	RDC_PER_SEMA2,
> +	RDC_PER_RDC,
> +	RDC_PER_AIPSTZ1_GE1,
> +	RDC_PER_AIPSTZ2_GE2,
> +	RDC_PER_USBO2H_PL301,
> +	RDC_PER_USBO2H_USB,
> +	RDC_PER_ENET1,
> +	RDC_PER_MLB25,
> +	RDC_PER_USDHC1,
> +	RDC_PER_USDHC2,
> +	RDC_PER_USDHC3,
> +	RDC_PER_USDHC4,
> +	RDC_PER_I2C1,
> +	RDC_PER_I2C2,
> +	RDC_PER_I2C3,
> +	RDC_PER_ROMCP,
> +	RDC_PER_MMDC,
> +	RDC_PER_ENET2,
> +	RDC_PER_EIM,
> +	RDC_PER_OCOTP,
> +	RDC_PER_CSU,
> +	RDC_PER_PERFMON1,
> +	RDC_PER_PERFMON2,
> +	RDC_PER_AXIMON,
> +	RDC_PER_TZASC1,
> +	RDC_PER_SAI1,
> +	RDC_PER_AUDMUX,
> +	RDC_PER_SAI2,
> +	RDC_PER_QSPI1,
> +	RDC_PER_QSPI2,
> +	RDC_PER_UART2,
> +	RDC_PER_UART3,
> +	RDC_PER_UART4,
> +	RDC_PER_UART5,
> +	RDC_PER_I2C4,
> +	RDC_PER_QOSC,
> +	RDC_PER_CAAM,
> +	RDC_PER_DAP,
> +	RDC_PER_ADC1,
> +	RDC_PER_ADC2,
> +	RDC_PER_WDOG3,
> +	RDC_PER_ECSPI5,
> +	RDC_PER_SEMA4,
> +	RDC_PER_MUPORT1,
> +	RDC_PER_CANFD_CPU,
> +	RDC_PER_MUPORT2,
> +	RDC_PER_UART6,
> +	RDC_PER_PWM5,
> +	RDC_PER_PWM6,
> +	RDC_PER_PWM7,
> +	RDC_PER_PWM8,
> +	RDC_PER_AIPSTZ3_GE0,
> +	RDC_PER_AIPSTZ3_GE1,
> +	RDC_PER_RESERVED1,
> +	RDC_PER_SPDIF,
> +	RDC_PER_ECSPI1,
> +	RDC_PER_ECSPI2,
> +	RDC_PER_ECSPI3,
> +	RDC_PER_ECSPI4,
> +	RDC_PER_RESERVED2,
> +	RDC_PER_RESERVED3,
> +	RDC_PER_UART1,
> +	RDC_PER_ESAI,
> +	RDC_PER_SSI1,
> +	RDC_PER_SSI2,
> +	RDC_PER_SSI3,
> +	RDC_PER_ASRC,
> +	RDC_PER_RESERVED4,
> +	RDC_PER_SPBA_MA,
> +	RDC_PER_GIS,
> +	RDC_PER_DCIC1,
> +	RDC_PER_DCIC2,
> +	RDC_PER_CSI1,
> +	RDC_PER_PXP,
> +	RDC_PER_CSI2,
> +	RDC_PER_LCDIF1,
> +	RDC_PER_LCDIF2,
> +	RDC_PER_VADC,
> +	RDC_PER_VDEC,
> +	RDC_PER_SPBA_DISPLAYMIX,
> +};
> +
> +enum {
> +	RDC_MA_A9_L2CACHE = 0,
> +	RDC_MA_M4,
> +	RDC_MA_GPU,
> +	RDC_MA_CSI1,
> +	RDC_MA_CSI2,
> +	RDC_MA_LCDIF1,
> +	RDC_MA_LCDIF2,
> +	RDC_MA_PXP,
> +	RDC_MA_PCIE_CTRL,
> +	RDC_MA_DAP,
> +	RDC_MA_CAAM,
> +	RDC_MA_SDMA_PERI,
> +	RDC_MA_SDMA_BURST,
> +	RDC_MA_APBHDMA,
> +	RDC_MA_RAWNAND,
> +	RDC_MA_USDHC1,
> +	RDC_MA_USDHC2,
> +	RDC_MA_USDHC3,
> +	RDC_MA_USDHC4,
> +	RDC_MA_USB,
> +	RDC_MA_MLB,
> +	RDC_MA_TEST,
> +	RDC_MA_ENET1_TX,
> +	RDC_MA_ENET1_RX,
> +	RDC_MA_ENET2_TX,
> +	RDC_MA_ENET2_RX,
> +	RDC_MA_SDMA,
> +};
> +
> +#endif	/* __MX6SX_RDC_H__*/

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Stefan Agner]

On 2016-01-04 21:56, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> To boot a auxiliary core in asymmetric multicore system, introduce the
> new command "bootaux" to do it. Example of boot auxliary core from
> 0x70000000 where stores the boot head information that should be
> parsed by auxiliary core, "bootaux 0x70000000".

This reminds me of a question which was nagging me lately:
Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
the boot head information"?


> Introduce Kconfig option IMX_BOOTAUX.
> 
> Signed-off-by: Ye.Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/imx-common/Kconfig       |  6 ++++
>  arch/arm/imx-common/Makefile      |  1 +
>  arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 66 insertions(+)
>  create mode 100644 arch/arm/imx-common/imx_bootaux.c
> 
> diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
> index c4f48bb..1b7da5a 100644
> --- a/arch/arm/imx-common/Kconfig
> +++ b/arch/arm/imx-common/Kconfig
> @@ -11,3 +11,9 @@ config IMX_RDC
>  	  i.MX Resource domain controller is used to assign masters
>  	  and peripherals to differet domains. This can be used to
>  	  isolate resources.
> +
> +config IMX_BOOTAUX
> +	bool "Support boot auxiliary core"
> +	depends on ARCH_MX7 || ARCH_MX6
> +	help
> +	  bootaux [addr] to boot auxiliary core.
> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
> index 568f41c..30e66ba 100644
> --- a/arch/arm/imx-common/Makefile
> +++ b/arch/arm/imx-common/Makefile
> @@ -28,6 +28,7 @@ obj-y 	+= cache.o init.o
>  obj-$(CONFIG_CMD_SATA) += sata.o
>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
>  obj-$(CONFIG_IMX_RDC) += rdc-sema.o
> +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>  endif
>  ifeq ($(SOC),$(filter $(SOC),vf610))
> diff --git a/arch/arm/imx-common/imx_bootaux.c
> b/arch/arm/imx-common/imx_bootaux.c
> new file mode 100644
> index 0000000..da424a7
> --- /dev/null
> +++ b/arch/arm/imx-common/imx_bootaux.c
> @@ -0,0 +1,59 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +
> +/* Allow for arch specific config before we boot */
> +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
> +{
> +	/* please define platform specific arch_auxiliary_core_up() */
> +	return CMD_RET_FAILURE;
> +}
> +
> +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
> +	__attribute__((weak, alias("__arch_auxiliary_core_up")));
> +
> +/* Allow for arch specific config before we boot */
> +static int __arch_auxiliary_core_check_up(u32 core_id)
> +{
> +	/* please define platform specific arch_auxiliary_core_check_up() */
> +	return 0;
> +}
> +
> +int arch_auxiliary_core_check_up(u32 core_id)
> +	__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
> +
> +int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +	ulong addr;
> +	int ret, up;
> +
> +	if (argc < 2)
> +		return CMD_RET_USAGE;
> +
> +	up = arch_auxiliary_core_check_up(0);
> +	if (up) {
> +		printf("## Auxiliary core is already up\n");
> +		return CMD_RET_SUCCESS;
> +	}
> +
> +	addr = simple_strtoul(argv[1], NULL, 16);
> +
> +	printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
> +
> +	ret = arch_auxiliary_core_up(0, addr);
> +	if (ret)
> +		return CMD_RET_FAILURE;
> +
> +	return CMD_RET_SUCCESS;
> +}
> +
> +U_BOOT_CMD(
> +	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
> +	"Start auxiliary core",

What kind of image are supported by the bootaux command? Afaik, this is
some special/binary only format right?

Probably another discussion, but before polluting the command namespace:
Is that what we generally want?

--
Stefan

> +	""
> +);

[U-Boot] [PATCH 11/11] imx: mx7d: isolate resources to domain 0 for A7 core

[Stefan Agner]

On 2016-01-04 21:56, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> In current design, if any peripheral was assigned to both A7 and M4,
> it will receive ipg_stop or ipg_wait when any of the 2 platforms
> enter low power mode. We will have a risk that, if A7 enter wait,
> M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
> asserted same time. Also if M4 enters stop mode, A7 will have no
> chance to access the peripheral.
> There are 26 peripherals impacted by this IC issue:

s/impacted/affected


> SIM2(sim2/emvsim2)
> SIM1(sim1/emvsim1)
> UART1/UART2/UART3/UART4/UART5/UART6/UART7
> SAI1/SAI2/SAI3
> WDOG1/WDOG2/WDOG3/WDOG4
> GPT1/GPT2/GPT3/GPT4
> PWM1/PWM2/PWM3/PWM4
> ENET1/ENET2
> Software Workaround:
> The solution is set M4 to a different domain with A core.

Set the M4 core to a different domain using A core? Or merely the
peripherals?

> So the peripherals are not shared by them. This way requires
> the uboot implemented the RDC driver and set the 26 IPs above
> to domain 0 only. M4 image will set the M4 to domain 1 and
> set peripheral which it will use to domain 1.

Hm, what happens if the M4 image is not doing that? Would that causing
problems?

--
Stefan

> 
> This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
> i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
> 
> Signed-off-by: Ye.Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/cpu/armv7/mx7/soc.c  | 64 +++++++++++++++++++++++++++++++++++++++++++
>  configs/mx7dsabresd_defconfig |  2 ++
>  2 files changed, 66 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
> index 2121ff2..ede7d53 100644
> --- a/arch/arm/cpu/armv7/mx7/soc.c
> +++ b/arch/arm/cpu/armv7/mx7/soc.c
> @@ -12,6 +12,8 @@
>  #include <asm/imx-common/boot_mode.h>
>  #include <asm/imx-common/dma.h>
>  #include <asm/imx-common/hab.h>
> +#include <asm/imx-common/rdc-sema.h>
> +#include <asm/arch/imx-rdc.h>
>  #include <asm/arch/crm_regs.h>
>  #include <dm.h>
>  #include <imx_thermal.h>
> @@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = {
>  };
>  #endif
>  
> +#ifdef CONFIG_IMX_RDC
> +/*
> + * In current design, if any peripheral was assigned to both A7 and M4,
> + * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
> + * low power mode. So M4 sleep will cause some peripherals fail to work
> + * at A7 core side. At default, all resources are in domain 0 - 3.
> + *
> + * There are 26 peripherals impacted by this IC issue:
> + * SIM2(sim2/emvsim2)
> + * SIM1(sim1/emvsim1)
> + * UART1/UART2/UART3/UART4/UART5/UART6/UART7
> + * SAI1/SAI2/SAI3
> + * WDOG1/WDOG2/WDOG3/WDOG4
> + * GPT1/GPT2/GPT3/GPT4
> + * PWM1/PWM2/PWM3/PWM4
> + * ENET1/ENET2
> + * Software Workaround:
> + * Here we setup some resources to domain 0 where M4 codes will move
> + * the M4 out of this domain. Then M4 is not able to access them any longer.
> + * This is a workaround for ic issue. So the peripherals are not shared
> + * by them. This way requires the uboot implemented the RDC driver and
> + * set the 26 IPs above to domain 0 only. M4 code will assign resource
> + * to its own domain, if it want to use the resource.
> + */
> +static rdc_peri_cfg_t const resources[] = {
> +	(RDC_PER_SIM1 | RDC_DOMAIN(0)),
> +	(RDC_PER_SIM2 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART1 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART2 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART3 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART4 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART5 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART6 | RDC_DOMAIN(0)),
> +	(RDC_PER_UART7 | RDC_DOMAIN(0)),
> +	(RDC_PER_SAI1 | RDC_DOMAIN(0)),
> +	(RDC_PER_SAI2 | RDC_DOMAIN(0)),
> +	(RDC_PER_SAI3 | RDC_DOMAIN(0)),
> +	(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
> +	(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
> +	(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
> +	(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
> +	(RDC_PER_GPT1 | RDC_DOMAIN(0)),
> +	(RDC_PER_GPT2 | RDC_DOMAIN(0)),
> +	(RDC_PER_GPT3 | RDC_DOMAIN(0)),
> +	(RDC_PER_GPT4 | RDC_DOMAIN(0)),
> +	(RDC_PER_PWM1 | RDC_DOMAIN(0)),
> +	(RDC_PER_PWM2 | RDC_DOMAIN(0)),
> +	(RDC_PER_PWM3 | RDC_DOMAIN(0)),
> +	(RDC_PER_PWM4 | RDC_DOMAIN(0)),
> +	(RDC_PER_ENET1 | RDC_DOMAIN(0)),
> +	(RDC_PER_ENET2 | RDC_DOMAIN(0)),
> +};
> +
> +static void isolate_resource(void)
> +{
> +	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
> +}
> +#endif
> +
>  #if defined(CONFIG_SECURE_BOOT)
>  struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
>  	.bank = 1,
> @@ -163,6 +224,9 @@ int arch_cpu_init(void)
>  	mxs_dma_init();
>  #endif
>  
> +	if (IS_ENABLED(CONFIG_IMX_RDC))
> +		isolate_resource();
> +
>  	return 0;
>  }
>  
> diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
> index 420d13e..1d262c1 100644
> --- a/configs/mx7dsabresd_defconfig
> +++ b/configs/mx7dsabresd_defconfig
> @@ -1,6 +1,8 @@
>  CONFIG_ARM=y
>  CONFIG_ARCH_MX7=y
>  CONFIG_TARGET_MX7DSABRESD=y
> +CONFIG_IMX_RDC=y
> +CONFIG_IMX_BOOTAUX=y
>
> CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
>  # CONFIG_CMD_BOOTD is not set
>  # CONFIG_CMD_IMI is not set

[U-Boot] [PATCH 02/11] imx: imx-common: introduce Resource Domain Controller support

[Peng Fan]

Hi Stefan,

On Wed, Jan 06, 2016 at 10:52:26PM -0800, Stefan Agner wrote:
>Hi Peng,
>
>Some minor questions/remarks below.
>
>On 2016-01-04 21:56, Peng Fan wrote:
>> From: Peng Fan <peng.fan@nxp.com>
>> 
>> Introduce Resource Domain Controller support for i.MX.
>> Now i.MX6SX and i.MX7D supports this feature to assign masters
>> and peripherals to different domains.
>> 
>> Signed-off-by: Ye.Li <ye.li@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm/imx-common/Kconfig                |   8 ++
>>  arch/arm/imx-common/Makefile               |   1 +
>>  arch/arm/imx-common/rdc-sema.c             | 184 +++++++++++++++++++++++++++++
>>  arch/arm/include/asm/arch-mx6/imx-rdc.h    |  12 ++
>>  arch/arm/include/asm/imx-common/rdc-sema.h | 117 ++++++++++++++++++
>>  5 files changed, 322 insertions(+)
>>  create mode 100644 arch/arm/imx-common/rdc-sema.c
>>  create mode 100644 arch/arm/include/asm/arch-mx6/imx-rdc.h
>>  create mode 100644 arch/arm/include/asm/imx-common/rdc-sema.h
>> 
>> diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
>> index 2296239..c4f48bb 100644
>> --- a/arch/arm/imx-common/Kconfig
>> +++ b/arch/arm/imx-common/Kconfig
>> @@ -3,3 +3,11 @@ config IMX_CONFIG
>>  
>>  config ROM_UNIFIED_SECTIONS
>>  	bool
>> +
>> +config IMX_RDC
>> +	bool "i.MX Resource domain controller driver"
>> +	depends on ARCH_MX6 || ARCH_MX7
>> +	help
>> +	  i.MX Resource domain controller is used to assign masters
>> +	  and peripherals to differet domains. This can be used to
>> +	  isolate resources.
>> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
>> index e7190c3..568f41c 100644
>> --- a/arch/arm/imx-common/Makefile
>> +++ b/arch/arm/imx-common/Makefile
>> @@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
>>  obj-y 	+= cache.o init.o
>>  obj-$(CONFIG_CMD_SATA) += sata.o
>>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
>> +obj-$(CONFIG_IMX_RDC) += rdc-sema.o
>>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>>  endif
>>  ifeq ($(SOC),$(filter $(SOC),vf610))
>> diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c
>> new file mode 100644
>> index 0000000..7db1ec5
>> --- /dev/null
>> +++ b/arch/arm/imx-common/rdc-sema.c
>> @@ -0,0 +1,184 @@
>> +/*
>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + */
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/imx-common/rdc-sema.h>
>> +#include <asm/arch/imx-rdc.h>
>> +#include <asm-generic/errno.h>
>> +
>> +/*
>> + * Check if the RDC Semaphore is required for this peripheral.
>> + */
>> +static inline int imx_rdc_check_sema_required(int per_id)
>> +{
>> +	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
>> +	u32 reg;
>> +
>> +	reg = readl(&imx_rdc->pdap[per_id]);
>> +	/*
>> +	 * No semaphore:
>> +	 * Intial value or this peripheral is assigned to only one domain
>> +	 */
>> +	if (!(reg & RDC_PDAP_SREQ_MASK))
>> +		return -ENOENT;
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * Check the peripheral read / write access permission on Domain 0.
>> + * (Always assume the main CPU is in Domain 0)
>
>Hence you assuming that U-Boot is also always running on main CPU right?

Yeah. To i.MX6SX and 7D, U-Boot is only run on the Cortex-Ax core.

>I guess this is ok for now.
>
>> + */
>> +int imx_rdc_check_permission(int per_id)
>> +{
>> +	struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
>> +	u32 reg;
>> +
>> +	reg = readl(&imx_rdc->pdap[per_id]);
>> +	if (!(reg & (RDC_PDAP_D0W_MASK | RDC_PDAP_D0R_MASK)))
>> +		return -EACCES;  /*No access*/
>> +
>> +	return 0;
>> +}

[..........]

>> diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h
>> b/arch/arm/include/asm/arch-mx6/imx-rdc.h
>> new file mode 100644
>> index 0000000..5754f04
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
>> @@ -0,0 +1,12 @@
>> +/*
>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + */
>> +
>> +#ifndef __IMX_RDC_H__
>> +#define __IMX_RDC_H__
>> +
>> +#error "Please select cpu"
>
>I don't understand this, wouldn't lead this always to an error?

The CONFIG is not enabled, when add i.MX6SX and 7D support. This will
be ok.

>

[............]

>> +
>> +#define RDC_PDAP_D0W_SHIFT	0
>> +#define RDC_PDAP_D0W_MASK	(0x1 << RDC_PDAP_D0W_SHIFT)
>> +#define RDC_PDAP_D0R_SHIFT	1
>> +#define RDC_PDAP_D0R_MASK	(0x1 << RDC_PDAP_D0R_SHIFT)
>> +#define RDC_PDAP_D1W_SHIFT	2
>> +#define RDC_PDAP_D1W_MASK	(0x1 << RDC_PDAP_D1W_SHIFT)
>> +#define RDC_PDAP_D1R_SHIFT	3
>> +#define RDC_PDAP_D1R_MASK	(0x1 << RDC_PDAP_D1R_SHIFT)
>> +#define RDC_PDAP_D2W_SHIFT	4
>> +#define RDC_PDAP_D2W_MASK	(0x1 << RDC_PDAP_D2W_SHIFT)
>> +#define RDC_PDAP_D2R_SHIFT	5
>> +#define RDC_PDAP_D2R_MASK	(0x1 << RDC_PDAP_D2R_SHIFT)
>> +#define RDC_PDAP_D3W_SHIFT	6
>> +#define RDC_PDAP_D3W_MASK	(0x1 << RDC_PDAP_D3W_SHIFT)
>> +#define RDC_PDAP_D3R_SHIFT	7
>> +#define RDC_PDAP_D3R_MASK	(0x1 << RDC_PDAP_D3R_SHIFT)
>
>Nit: How about RDC_PDAP_DXW_SHIFT(domain)   (2 * domain) style defines?

Will try this way.

[........]

Thanks,
Peng.
> 

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Peng Fan]

Hi Stefan,
On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:
>On 2016-01-04 21:56, Peng Fan wrote:
>> From: Peng Fan <peng.fan@nxp.com>
>> 
>> To boot a auxiliary core in asymmetric multicore system, introduce the
>> new command "bootaux" to do it. Example of boot auxliary core from
>> 0x70000000 where stores the boot head information that should be
>> parsed by auxiliary core, "bootaux 0x70000000".
>
>This reminds me of a question which was nagging me lately:
>Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
>the boot head information"?

There is no bootrom for m4 core. The bootimage for M4 contains stack
info and pc info. bootaux command will use the info extracted from bootimage.

See the following code:
"
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
	struct src *src_reg;
	u32 stack, pc;

	if (!boot_private_data)
		return 1;

	stack = *(u32 *)boot_private_data;
	pc = *(u32 *)(boot_private_data + 4);

	/* Set the stack and pc to M4 bootROM */
	writel(stack, M4_BOOTROM_BASE_ADDR);
	writel(pc, M4_BOOTROM_BASE_ADDR + 4);

	/* Enable M4 */
	src_reg = (struct src *)SRC_BASE_ADDR;
	setbits_le32(&src_reg->scr, 0x00400000);
	clrbits_le32(&src_reg->scr, 0x00000010);

	return 0;
}

"

>
>
>> Introduce Kconfig option IMX_BOOTAUX.
>> 
>> Signed-off-by: Ye.Li <ye.li@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm/imx-common/Kconfig       |  6 ++++
>>  arch/arm/imx-common/Makefile      |  1 +
>>  arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 66 insertions(+)
>>  create mode 100644 arch/arm/imx-common/imx_bootaux.c
>> 
>> diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
>> index c4f48bb..1b7da5a 100644
>> --- a/arch/arm/imx-common/Kconfig
>> +++ b/arch/arm/imx-common/Kconfig
>> @@ -11,3 +11,9 @@ config IMX_RDC
>>  	  i.MX Resource domain controller is used to assign masters
>>  	  and peripherals to differet domains. This can be used to
>>  	  isolate resources.
>> +
>> +config IMX_BOOTAUX
>> +	bool "Support boot auxiliary core"
>> +	depends on ARCH_MX7 || ARCH_MX6
>> +	help
>> +	  bootaux [addr] to boot auxiliary core.
>> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
>> index 568f41c..30e66ba 100644
>> --- a/arch/arm/imx-common/Makefile
>> +++ b/arch/arm/imx-common/Makefile
>> @@ -28,6 +28,7 @@ obj-y 	+= cache.o init.o
>>  obj-$(CONFIG_CMD_SATA) += sata.o
>>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
>>  obj-$(CONFIG_IMX_RDC) += rdc-sema.o
>> +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
>>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>>  endif
>>  ifeq ($(SOC),$(filter $(SOC),vf610))
>> diff --git a/arch/arm/imx-common/imx_bootaux.c
>> b/arch/arm/imx-common/imx_bootaux.c
>> new file mode 100644
>> index 0000000..da424a7
>> --- /dev/null
>> +++ b/arch/arm/imx-common/imx_bootaux.c
>> @@ -0,0 +1,59 @@
>> +/*
>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier:	GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <command.h>
>> +
>> +/* Allow for arch specific config before we boot */
>> +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>> +{
>> +	/* please define platform specific arch_auxiliary_core_up() */
>> +	return CMD_RET_FAILURE;
>> +}
>> +
>> +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>> +	__attribute__((weak, alias("__arch_auxiliary_core_up")));
>> +
>> +/* Allow for arch specific config before we boot */
>> +static int __arch_auxiliary_core_check_up(u32 core_id)
>> +{
>> +	/* please define platform specific arch_auxiliary_core_check_up() */
>> +	return 0;
>> +}
>> +
>> +int arch_auxiliary_core_check_up(u32 core_id)
>> +	__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
>> +
>> +int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> +{
>> +	ulong addr;
>> +	int ret, up;
>> +
>> +	if (argc < 2)
>> +		return CMD_RET_USAGE;
>> +
>> +	up = arch_auxiliary_core_check_up(0);
>> +	if (up) {
>> +		printf("## Auxiliary core is already up\n");
>> +		return CMD_RET_SUCCESS;
>> +	}
>> +
>> +	addr = simple_strtoul(argv[1], NULL, 16);
>> +
>> +	printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
>> +
>> +	ret = arch_auxiliary_core_up(0, addr);
>> +	if (ret)
>> +		return CMD_RET_FAILURE;
>> +
>> +	return CMD_RET_SUCCESS;
>> +}
>> +
>> +U_BOOT_CMD(
>> +	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
>> +	"Start auxiliary core",
>
>What kind of image are supported by the bootaux command? Afaik, this is
>some special/binary only format right?

Yeah. I just got the image from our rtos team, I do not have detail
info about the format.

>
>Probably another discussion, but before polluting the command namespace:
>Is that what we generally want?

Hmm, bootaux invokes
arch_auxiliary_core_check_up
arch_auxiliary_core_u

And arch code takes the responsibility to implement these two functions.

We try to make this common, but not sure whether this is ok for other SoCs.
So I move the command to arch/arm/imx-common

Thanks,
Peng.

>
>--
>Stefan
>
>> +	""
>> +);

[U-Boot] [PATCH 11/11] imx: mx7d: isolate resources to domain 0 for A7 core

[Peng Fan]

Hi Stefan,
On Wed, Jan 06, 2016 at 11:04:44PM -0800, Stefan Agner wrote:
>On 2016-01-04 21:56, Peng Fan wrote:
>> From: Peng Fan <peng.fan@nxp.com>
>> 
>> In current design, if any peripheral was assigned to both A7 and M4,
>> it will receive ipg_stop or ipg_wait when any of the 2 platforms
>> enter low power mode. We will have a risk that, if A7 enter wait,
>> M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
>> asserted same time. Also if M4 enters stop mode, A7 will have no
>> chance to access the peripheral.
>> There are 26 peripherals impacted by this IC issue:
>
>s/impacted/affected

Will fix in V2.

>
>
>> SIM2(sim2/emvsim2)
>> SIM1(sim1/emvsim1)
>> UART1/UART2/UART3/UART4/UART5/UART6/UART7
>> SAI1/SAI2/SAI3
>> WDOG1/WDOG2/WDOG3/WDOG4
>> GPT1/GPT2/GPT3/GPT4
>> PWM1/PWM2/PWM3/PWM4
>> ENET1/ENET2
>> Software Workaround:
>> The solution is set M4 to a different domain with A core.
>
>Set the M4 core to a different domain using A core? Or merely the
>peripherals?

peripherals. Thanks pointing this.

>
>> So the peripherals are not shared by them. This way requires
>> the uboot implemented the RDC driver and set the 26 IPs above
>> to domain 0 only. M4 image will set the M4 to domain 1 and
>> set peripheral which it will use to domain 1.
>
>Hm, what happens if the M4 image is not doing that? Would that causing
>problems?

If M4 A7 and all the peripherals are in one domain, if A7 runs into low
power idle or other low mode, it will send out ipg_stop/wait signal,
and m4 will not be able to access the peripherals. So need to
assign peripherals to different domains for M4 and A7.

Thanks,
Peng.

>
>--
>Stefan
>
>> 
>> This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
>> i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
>> 
>> Signed-off-by: Ye.Li <ye.li@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm/cpu/armv7/mx7/soc.c  | 64 +++++++++++++++++++++++++++++++++++++++++++
>>  configs/mx7dsabresd_defconfig |  2 ++
>>  2 files changed, 66 insertions(+)
>> 
>> diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
>> index 2121ff2..ede7d53 100644
>> --- a/arch/arm/cpu/armv7/mx7/soc.c
>> +++ b/arch/arm/cpu/armv7/mx7/soc.c
>> @@ -12,6 +12,8 @@
>>  #include <asm/imx-common/boot_mode.h>
>>  #include <asm/imx-common/dma.h>
>>  #include <asm/imx-common/hab.h>
>> +#include <asm/imx-common/rdc-sema.h>
>> +#include <asm/arch/imx-rdc.h>
>>  #include <asm/arch/crm_regs.h>
>>  #include <dm.h>
>>  #include <imx_thermal.h>
>> @@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = {
>>  };
>>  #endif
>>  
>> +#ifdef CONFIG_IMX_RDC
>> +/*
>> + * In current design, if any peripheral was assigned to both A7 and M4,
>> + * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
>> + * low power mode. So M4 sleep will cause some peripherals fail to work
>> + * at A7 core side. At default, all resources are in domain 0 - 3.
>> + *
>> + * There are 26 peripherals impacted by this IC issue:
>> + * SIM2(sim2/emvsim2)
>> + * SIM1(sim1/emvsim1)
>> + * UART1/UART2/UART3/UART4/UART5/UART6/UART7
>> + * SAI1/SAI2/SAI3
>> + * WDOG1/WDOG2/WDOG3/WDOG4
>> + * GPT1/GPT2/GPT3/GPT4
>> + * PWM1/PWM2/PWM3/PWM4
>> + * ENET1/ENET2
>> + * Software Workaround:
>> + * Here we setup some resources to domain 0 where M4 codes will move
>> + * the M4 out of this domain. Then M4 is not able to access them any longer.
>> + * This is a workaround for ic issue. So the peripherals are not shared
>> + * by them. This way requires the uboot implemented the RDC driver and
>> + * set the 26 IPs above to domain 0 only. M4 code will assign resource
>> + * to its own domain, if it want to use the resource.
>> + */
>> +static rdc_peri_cfg_t const resources[] = {
>> +	(RDC_PER_SIM1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_SIM2 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART2 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART3 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART4 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART5 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART6 | RDC_DOMAIN(0)),
>> +	(RDC_PER_UART7 | RDC_DOMAIN(0)),
>> +	(RDC_PER_SAI1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_SAI2 | RDC_DOMAIN(0)),
>> +	(RDC_PER_SAI3 | RDC_DOMAIN(0)),
>> +	(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
>> +	(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
>> +	(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
>> +	(RDC_PER_GPT1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_GPT2 | RDC_DOMAIN(0)),
>> +	(RDC_PER_GPT3 | RDC_DOMAIN(0)),
>> +	(RDC_PER_GPT4 | RDC_DOMAIN(0)),
>> +	(RDC_PER_PWM1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_PWM2 | RDC_DOMAIN(0)),
>> +	(RDC_PER_PWM3 | RDC_DOMAIN(0)),
>> +	(RDC_PER_PWM4 | RDC_DOMAIN(0)),
>> +	(RDC_PER_ENET1 | RDC_DOMAIN(0)),
>> +	(RDC_PER_ENET2 | RDC_DOMAIN(0)),
>> +};
>> +
>> +static void isolate_resource(void)
>> +{
>> +	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
>> +}
>> +#endif
>> +
>>  #if defined(CONFIG_SECURE_BOOT)
>>  struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
>>  	.bank = 1,
>> @@ -163,6 +224,9 @@ int arch_cpu_init(void)
>>  	mxs_dma_init();
>>  #endif
>>  
>> +	if (IS_ENABLED(CONFIG_IMX_RDC))
>> +		isolate_resource();
>> +
>>  	return 0;
>>  }
>>  
>> diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
>> index 420d13e..1d262c1 100644
>> --- a/configs/mx7dsabresd_defconfig
>> +++ b/configs/mx7dsabresd_defconfig
>> @@ -1,6 +1,8 @@
>>  CONFIG_ARM=y
>>  CONFIG_ARCH_MX7=y
>>  CONFIG_TARGET_MX7DSABRESD=y
>> +CONFIG_IMX_RDC=y
>> +CONFIG_IMX_BOOTAUX=y
>>
>> CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
>>  # CONFIG_CMD_BOOTD is not set
>>  # CONFIG_CMD_IMI is not set

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Ye Li]

Hi Stefan,

On 1/7/2016 4:52 PM, Peng Fan wrote:

Hi Stefan,
On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:


On 2016-01-04 21:56, Peng Fan wrote:


From: Peng Fan <peng.fan@nxp.com><mailto:peng.fan@nxp.com>

To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".



This reminds me of a question which was nagging me lately:
Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
the boot head information"?



There is no bootrom for m4 core. The bootimage for M4 contains stack
info and pc info. bootaux command will use the info extracted from bootimage.

See the following code:
"
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
        struct src *src_reg;
        u32 stack, pc;

        if (!boot_private_data)
                return 1;

        stack = *(u32 *)boot_private_data;
        pc = *(u32 *)(boot_private_data + 4);

        /* Set the stack and pc to M4 bootROM */
        writel(stack, M4_BOOTROM_BASE_ADDR);
        writel(pc, M4_BOOTROM_BASE_ADDR + 4);

        /* Enable M4 */
        src_reg = (struct src *)SRC_BASE_ADDR;
        setbits_le32(&src_reg->scr, 0x00400000);
        clrbits_le32(&src_reg->scr, 0x00000010);

        return 0;
}

"


Per the cortex-M reference manual, the reset vector of M4 needs to exist at 0x0 (TCMUL). The PC and SP are the first two addresses of that vector.  So to boot M4, the A core must build the M4's reset vector with getting the PC and SP from image and filling them to TCMUL. When M4 is kicked, it will load the PC and SP by itself. Freescale uses a back door (M4_BOOTROM_BASE_ADDR) at A core side for accessing the M4 TCMUL.









Introduce Kconfig option IMX_BOOTAUX.

Signed-off-by: Ye.Li <ye.li@nxp.com><mailto:ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com><mailto:peng.fan@nxp.com>
---
 arch/arm/imx-common/Kconfig       |  6 ++++
 arch/arm/imx-common/Makefile      |  1 +
 arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 arch/arm/imx-common/imx_bootaux.c

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index c4f48bb..1b7da5a 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -11,3 +11,9 @@ config IMX_RDC
          i.MX Resource domain controller is used to assign masters
          and peripherals to differet domains. This can be used to
          isolate resources.
+
+config IMX_BOOTAUX
+       bool "Support boot auxiliary core"
+       depends on ARCH_MX7 || ARCH_MX6
+       help
+         bootaux [addr] to boot auxiliary core.
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 568f41c..30e66ba 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -28,6 +28,7 @@ obj-y         += cache.o init.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
diff --git a/arch/arm/imx-common/imx_bootaux.c
b/arch/arm/imx-common/imx_bootaux.c
new file mode 100644
index 0000000..da424a7
--- /dev/null
+++ b/arch/arm/imx-common/imx_bootaux.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* Allow for arch specific config before we boot */
+static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+       /* please define platform specific arch_auxiliary_core_up() */
+       return CMD_RET_FAILURE;
+}
+
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+       __attribute__((weak, alias("__arch_auxiliary_core_up")));
+
+/* Allow for arch specific config before we boot */
+static int __arch_auxiliary_core_check_up(u32 core_id)
+{
+       /* please define platform specific arch_auxiliary_core_check_up() */
+       return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+       __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
+
+int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       ulong addr;
+       int ret, up;
+
+       if (argc < 2)
+               return CMD_RET_USAGE;
+
+       up = arch_auxiliary_core_check_up(0);
+       if (up) {
+               printf("## Auxiliary core is already up\n");
+               return CMD_RET_SUCCESS;
+       }
+
+       addr = simple_strtoul(argv[1], NULL, 16);
+
+       printf("## Starting auxiliary core@0x%08lX ...\n", addr);
+
+       ret = arch_auxiliary_core_up(0, addr);
+       if (ret)
+               return CMD_RET_FAILURE;
+
+       return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+       bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+       "Start auxiliary core",



What kind of image are supported by the bootaux command? Afaik, this is
some special/binary only format right?



Yeah. I just got the image from our rtos team, I do not have detail
info about the format.


bootaux command is designed to image independent. Only a image address is used as a parameter to this command but we don't define the image format. It is the arch/machine layer responsibility to determine and parse the format of the image which they want to support.
In 6SX and 7D arch implementation, we use a M4 image generated by Freescale MQX tool.  This binary file has M4 reset vector ahead of code.







Probably another discussion, but before polluting the command namespace:
Is that what we generally want?



Hmm, bootaux invokes
arch_auxiliary_core_check_up
arch_auxiliary_core_u

And arch code takes the responsibility to implement these two functions.

We try to make this common, but not sure whether this is ok for other SoCs.
So I move the command to arch/arm/imx-common

That's also the question from us. Any plan in u-boot to support heterogeneous cores? We hope this patch can bring some valuable opinions.




Thanks,
Peng.




--
Stefan



+       ""
+);





Best regards,
Ye Li

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Stefan Agner]

Hi,

I would like to keep the discussion going and shed some light on the
image format introduced here, see below...

On 2016-01-07 00:38, Peng Fan wrote:
> Hi Stefan,
> On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:
>>On 2016-01-04 21:56, Peng Fan wrote:
>>> From: Peng Fan <peng.fan@nxp.com>
>>>
>>> To boot a auxiliary core in asymmetric multicore system, introduce the
>>> new command "bootaux" to do it. Example of boot auxliary core from
>>> 0x70000000 where stores the boot head information that should be
>>> parsed by auxiliary core, "bootaux 0x70000000".
>>
>>This reminds me of a question which was nagging me lately:
>>Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
>>the boot head information"?
> 
> There is no bootrom for m4 core. The bootimage for M4 contains stack
> info and pc info. bootaux command will use the info extracted from bootimage.


So the image expected by bootaux is really a raw binary image, with the
only notion that the first two words need to be the stack pointer and
the reset handler (firmware entry point).

U-Boot has other commands which work with "raw" images, such as the
bootz command. The bootz command also expects a certain "raw" format,
hence I guess it is ok to introduce something like that also for the
auxiliary core.

Also, since every standard Cortex-M4 vector table begins with SP and
reset handler, it is very likely that a firmwares linker file put the
vector table also at the beginning of the image. Otherwise, one would
need to adopt the linker file to create a "compatible" image. Btw, as Ye
Li pointed out, the CPU needs those two words located at 0x0000000000,
this is what bootaux is actually doing, coping the information to the
right location for the M4 CPU. As an alternative, SCB_VTOR could be used
to point to the vector table. However that can only be controlled from
the M4 itself, hence is not an option for the bootaux command (as I did
it for the libopencm3 Cortex-M4 support for Vybrid, see
https://github.com/libopencm3/libopencm3/blob/master/lib/vf6xx/vector_chipset.c).

However, IMHO, this patch should at least add this
information/restriction to a README and maybe even give a hint in the
help text what is expected here....

The other restriction is that the binary needs to be loaded to the
location where the firmware has been linked to. Since the firmware is a
"raw" image, this information need to be carried along the binary (I
need to know that binary xyz.bin is linked to work at memory location
0x7F8000...). This is different to the bootz command: A raw Linux kernel
zImage has a position independent loader at the very beginning and hence
can be placed anywhere.

I don't really like that this information need to be carried along
separately.

In our downstream U-Boot for Vybrid, which has a M4 core too, I
introduced a m4boot command which makes use of the FIT image format to
carry this information, see:
http://git.toradex.com/cgit/u-boot-toradex.git/commit/?h=2015.04-toradex-next&id=d1d416f272e840e8139aec911f89a70fe5523eb2

It comes with the cost that each firmware need to be packed into a FIT
image using mkimage, but then one can just call m4boot <address of
image> and the command will make sure that the image is placed at the
right location in memory.

Another possible option would be to introduce elf support. I like this
approach since the Linux framework remoteproc also supports loading elf
firmwares, hence this would align nicely with what has been done in the
Linux kernel.

The elf format has all information required to load the firmware:
Sections and their location (in M4 terms) as well as the start address.
The platform data would only need to have a translation table for the
section addresses (0x1fff8000 <=> 0x7F8000) to be able to load the
firmware to the correct location. It comes with the cost of coping the
firmware to the right location, but it would be much easier to handle
elf firmware files.

Other opinions?

One more thing below:

> 
> See the following code:
> "
> int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
> {
> 	struct src *src_reg;
> 	u32 stack, pc;
> 
> 	if (!boot_private_data)
> 		return 1;
> 
> 	stack = *(u32 *)boot_private_data;
> 	pc = *(u32 *)(boot_private_data + 4);
> 
> 	/* Set the stack and pc to M4 bootROM */
> 	writel(stack, M4_BOOTROM_BASE_ADDR);
> 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
> 
> 	/* Enable M4 */
> 	src_reg = (struct src *)SRC_BASE_ADDR;
> 	setbits_le32(&src_reg->scr, 0x00400000);
> 	clrbits_le32(&src_reg->scr, 0x00000010);
> 
> 	return 0;
> }
> 
> "
> 
>>
>>
>>> Introduce Kconfig option IMX_BOOTAUX.
>>>
>>> Signed-off-by: Ye.Li <ye.li@nxp.com>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>>  arch/arm/imx-common/Kconfig       |  6 ++++
>>>  arch/arm/imx-common/Makefile      |  1 +
>>>  arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
>>>  3 files changed, 66 insertions(+)
>>>  create mode 100644 arch/arm/imx-common/imx_bootaux.c
>>>
>>> diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
>>> index c4f48bb..1b7da5a 100644
>>> --- a/arch/arm/imx-common/Kconfig
>>> +++ b/arch/arm/imx-common/Kconfig
>>> @@ -11,3 +11,9 @@ config IMX_RDC
>>>  	  i.MX Resource domain controller is used to assign masters
>>>  	  and peripherals to differet domains. This can be used to
>>>  	  isolate resources.
>>> +
>>> +config IMX_BOOTAUX
>>> +	bool "Support boot auxiliary core"
>>> +	depends on ARCH_MX7 || ARCH_MX6
>>> +	help
>>> +	  bootaux [addr] to boot auxiliary core.
>>> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
>>> index 568f41c..30e66ba 100644
>>> --- a/arch/arm/imx-common/Makefile
>>> +++ b/arch/arm/imx-common/Makefile
>>> @@ -28,6 +28,7 @@ obj-y 	+= cache.o init.o
>>>  obj-$(CONFIG_CMD_SATA) += sata.o
>>>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
>>>  obj-$(CONFIG_IMX_RDC) += rdc-sema.o
>>> +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
>>>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>>>  endif
>>>  ifeq ($(SOC),$(filter $(SOC),vf610))
>>> diff --git a/arch/arm/imx-common/imx_bootaux.c
>>> b/arch/arm/imx-common/imx_bootaux.c
>>> new file mode 100644
>>> index 0000000..da424a7
>>> --- /dev/null
>>> +++ b/arch/arm/imx-common/imx_bootaux.c
>>> @@ -0,0 +1,59 @@
>>> +/*
>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>> + *
>>> + * SPDX-License-Identifier:	GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <command.h>
>>> +
>>> +/* Allow for arch specific config before we boot */
>>> +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>>> +{
>>> +	/* please define platform specific arch_auxiliary_core_up() */
>>> +	return CMD_RET_FAILURE;
>>> +}
>>> +
>>> +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>>> +	__attribute__((weak, alias("__arch_auxiliary_core_up")));
>>> +
>>> +/* Allow for arch specific config before we boot */
>>> +static int __arch_auxiliary_core_check_up(u32 core_id)
>>> +{
>>> +	/* please define platform specific arch_auxiliary_core_check_up() */
>>> +	return 0;
>>> +}
>>> +
>>> +int arch_auxiliary_core_check_up(u32 core_id)
>>> +	__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
>>> +
>>> +int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>> +{
>>> +	ulong addr;
>>> +	int ret, up;
>>> +
>>> +	if (argc < 2)
>>> +		return CMD_RET_USAGE;
>>> +
>>> +	up = arch_auxiliary_core_check_up(0);
>>> +	if (up) {
>>> +		printf("## Auxiliary core is already up\n");
>>> +		return CMD_RET_SUCCESS;
>>> +	}
>>> +
>>> +	addr = simple_strtoul(argv[1], NULL, 16);
>>> +
>>> +	printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
>>> +

A dcache flush is required after loading the firmware. This could be
also part of this command e.g. by using flush_dcache_all.

If we would make use of the elf format, then the main CPU would copy the
data to the target memory address, and we could explicitly flush only
the range required by the auxiliary core.

--
Stefan

>>> +	ret = arch_auxiliary_core_up(0, addr);
>>> +	if (ret)
>>> +		return CMD_RET_FAILURE;
>>> +
>>> +	return CMD_RET_SUCCESS;
>>> +}
>>> +
>>> +U_BOOT_CMD(
>>> +	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
>>> +	"Start auxiliary core",
>>
>>What kind of image are supported by the bootaux command? Afaik, this is
>>some special/binary only format right?
> 
> Yeah. I just got the image from our rtos team, I do not have detail
> info about the format.
> 



>>
>>Probably another discussion, but before polluting the command namespace:
>>Is that what we generally want?
> 
> Hmm, bootaux invokes
> arch_auxiliary_core_check_up
> arch_auxiliary_core_u
> 
> And arch code takes the responsibility to implement these two functions.
> 
> We try to make this common, but not sure whether this is ok for other SoCs.
> So I move the command to arch/arm/imx-common
> 
> Thanks,
> Peng.
> 

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Tom Rini]

On Wed, Jan 13, 2016 at 12:45:05PM -0800, Stefan Agner wrote:
> Hi,
> 
> I would like to keep the discussion going and shed some light on the
> image format introduced here, see below...
> 
> On 2016-01-07 00:38, Peng Fan wrote:
> > Hi Stefan,
> > On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:
> >>On 2016-01-04 21:56, Peng Fan wrote:
> >>> From: Peng Fan <peng.fan@nxp.com>
> >>>
> >>> To boot a auxiliary core in asymmetric multicore system, introduce the
> >>> new command "bootaux" to do it. Example of boot auxliary core from
> >>> 0x70000000 where stores the boot head information that should be
> >>> parsed by auxiliary core, "bootaux 0x70000000".
> >>
> >>This reminds me of a question which was nagging me lately:
> >>Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
> >>the boot head information"?
> > 
> > There is no bootrom for m4 core. The bootimage for M4 contains stack
> > info and pc info. bootaux command will use the info extracted from bootimage.
> 
> 
> So the image expected by bootaux is really a raw binary image, with the
> only notion that the first two words need to be the stack pointer and
> the reset handler (firmware entry point).
> 
> U-Boot has other commands which work with "raw" images, such as the
> bootz command. The bootz command also expects a certain "raw" format,
> hence I guess it is ok to introduce something like that also for the
> auxiliary core.

I suppose my only contribution right now is that for another project
where we have U-Boot (on the M4) kicking off NuttX we've had to do a
custom command to stack pointer thing, I agree with the need to add some
way to easily kick these cases off.

-- 
Tom
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[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Simon Glass]

+Bin

Hi Peng,

On 4 January 2016 at 22:56, Peng Fan <van.freenix@gmail.com> wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> To boot a auxiliary core in asymmetric multicore system, introduce the
> new command "bootaux" to do it. Example of boot auxliary core from
> 0x70000000 where stores the boot head information that should be
> parsed by auxiliary core, "bootaux 0x70000000".
> Introduce Kconfig option IMX_BOOTAUX.
>
> Signed-off-by: Ye.Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/imx-common/Kconfig       |  6 ++++
>  arch/arm/imx-common/Makefile      |  1 +
>  arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 66 insertions(+)
>  create mode 100644 arch/arm/imx-common/imx_bootaux.c
>

Could this use the CPU uclass?

[snip]

Regards,
Simon

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Stefan Agner]

On 2016-01-14 09:15, Tom Rini wrote:
> On Wed, Jan 13, 2016 at 12:45:05PM -0800, Stefan Agner wrote:
>> Hi,
>>
>> I would like to keep the discussion going and shed some light on the
>> image format introduced here, see below...
>>
>> On 2016-01-07 00:38, Peng Fan wrote:
>> > Hi Stefan,
>> > On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:
>> >>On 2016-01-04 21:56, Peng Fan wrote:
>> >>> From: Peng Fan <peng.fan@nxp.com>
>> >>>
>> >>> To boot a auxiliary core in asymmetric multicore system, introduce the
>> >>> new command "bootaux" to do it. Example of boot auxliary core from
>> >>> 0x70000000 where stores the boot head information that should be
>> >>> parsed by auxiliary core, "bootaux 0x70000000".
>> >>
>> >>This reminds me of a question which was nagging me lately:
>> >>Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
>> >>the boot head information"?
>> >
>> > There is no bootrom for m4 core. The bootimage for M4 contains stack
>> > info and pc info. bootaux command will use the info extracted from bootimage.
>>
>>
>> So the image expected by bootaux is really a raw binary image, with the
>> only notion that the first two words need to be the stack pointer and
>> the reset handler (firmware entry point).
>>
>> U-Boot has other commands which work with "raw" images, such as the
>> bootz command. The bootz command also expects a certain "raw" format,
>> hence I guess it is ok to introduce something like that also for the
>> auxiliary core.
> 
> I suppose my only contribution right now is that for another project
> where we have U-Boot (on the M4) kicking off NuttX we've had to do a
> custom command to stack pointer thing, I agree with the need to add some
> way to easily kick these cases off.

So the NuttX image was also kind of a raw image? Is that command
upstream?

--
Stefan

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Tom Rini]

On Thu, Jan 14, 2016 at 09:54:24AM -0800, Stefan Agner wrote:
> On 2016-01-14 09:15, Tom Rini wrote:
> > On Wed, Jan 13, 2016 at 12:45:05PM -0800, Stefan Agner wrote:
> >> Hi,
> >>
> >> I would like to keep the discussion going and shed some light on the
> >> image format introduced here, see below...
> >>
> >> On 2016-01-07 00:38, Peng Fan wrote:
> >> > Hi Stefan,
> >> > On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:
> >> >>On 2016-01-04 21:56, Peng Fan wrote:
> >> >>> From: Peng Fan <peng.fan@nxp.com>
> >> >>>
> >> >>> To boot a auxiliary core in asymmetric multicore system, introduce the
> >> >>> new command "bootaux" to do it. Example of boot auxliary core from
> >> >>> 0x70000000 where stores the boot head information that should be
> >> >>> parsed by auxiliary core, "bootaux 0x70000000".
> >> >>
> >> >>This reminds me of a question which was nagging me lately:
> >> >>Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
> >> >>the boot head information"?
> >> >
> >> > There is no bootrom for m4 core. The bootimage for M4 contains stack
> >> > info and pc info. bootaux command will use the info extracted from bootimage.
> >>
> >>
> >> So the image expected by bootaux is really a raw binary image, with the
> >> only notion that the first two words need to be the stack pointer and
> >> the reset handler (firmware entry point).
> >>
> >> U-Boot has other commands which work with "raw" images, such as the
> >> bootz command. The bootz command also expects a certain "raw" format,
> >> hence I guess it is ok to introduce something like that also for the
> >> auxiliary core.
> > 
> > I suppose my only contribution right now is that for another project
> > where we have U-Boot (on the M4) kicking off NuttX we've had to do a
> > custom command to stack pointer thing, I agree with the need to add some
> > way to easily kick these cases off.
> 
> So the NuttX image was also kind of a raw image? Is that command
> upstream?

The NuttX image is the "normal" raw cortex-m image format (everyone else
just writes it to flash and boots directly).  I haven't pushed the
patches upstream as the rest of the platform also isn't ready to go
upstream.

-- 
Tom
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[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Peng Fan]

Hi Stefan,

Sorry for this late reply.

On Wed, Jan 13, 2016 at 12:45:05PM -0800, Stefan Agner wrote:
>Hi,
>
>I would like to keep the discussion going and shed some light on the
>image format introduced here, see below...
>
>On 2016-01-07 00:38, Peng Fan wrote:
>> Hi Stefan,
>> On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:
>>>On 2016-01-04 21:56, Peng Fan wrote:
>>>> From: Peng Fan <peng.fan@nxp.com>
>>>>
>>>> To boot a auxiliary core in asymmetric multicore system, introduce the
>>>> new command "bootaux" to do it. Example of boot auxliary core from
>>>> 0x70000000 where stores the boot head information that should be
>>>> parsed by auxiliary core, "bootaux 0x70000000".
>>>
>>>This reminds me of a question which was nagging me lately:
>>>Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing
>>>the boot head information"?
>> 
>> There is no bootrom for m4 core. The bootimage for M4 contains stack
>> info and pc info. bootaux command will use the info extracted from bootimage.
>
>
>So the image expected by bootaux is really a raw binary image, with the
>only notion that the first two words need to be the stack pointer and
>the reset handler (firmware entry point).

Yeah.

>
>U-Boot has other commands which work with "raw" images, such as the
>bootz command. The bootz command also expects a certain "raw" format,
>hence I guess it is ok to introduce something like that also for the
>auxiliary core.

Here bootaux will not let uboot lose control. bootz will let os get the control
to soc. But I agree we add a simliar command, I personally think boot[aux]
is good :).

>
>Also, since every standard Cortex-M4 vector table begins with SP and
>reset handler, it is very likely that a firmwares linker file put the
>vector table also at the beginning of the image. Otherwise, one would
>need to adopt the linker file to create a "compatible" image. Btw, as Ye
>Li pointed out, the CPU needs those two words located at 0x0000000000,
>this is what bootaux is actually doing, coping the information to the
>right location for the M4 CPU. As an alternative, SCB_VTOR could be used
>to point to the vector table. However that can only be controlled from
>the M4 itself, hence is not an option for the bootaux command (as I did
>it for the libopencm3 Cortex-M4 support for Vybrid, see
>https://github.com/libopencm3/libopencm3/blob/master/lib/vf6xx/vector_chipset.c).
>
>However, IMHO, this patch should at least add this
>information/restriction to a README and maybe even give a hint in the
>help text what is expected here....

Add a README for bootaux command? or you mean the image format?

>
>The other restriction is that the binary needs to be loaded to the
>location where the firmware has been linked to. Since the firmware is a
>"raw" image, this information need to be carried along the binary (I
>need to know that binary xyz.bin is linked to work at memory location
>0x7F8000...). This is different to the bootz command: A raw Linux kernel
>zImage has a position independent loader at the very beginning and hence
>can be placed anywhere.

Good point. How about let bootaux to handle libz compressed M4 image?
>
>I don't really like that this information need to be carried along
>separately.
>
>In our downstream U-Boot for Vybrid, which has a M4 core too, I
>introduced a m4boot command which makes use of the FIT image format to
>carry this information, see:
>http://git.toradex.com/cgit/u-boot-toradex.git/commit/?h=2015.04-toradex-next&id=d1d416f272e840e8139aec911f89a70fe5523eb2
>
>It comes with the cost that each firmware need to be packed into a FIT
>image using mkimage, but then one can just call m4boot <address of
>image> and the command will make sure that the image is placed at the
>right location in memory.
>
>Another possible option would be to introduce elf support. I like this
>approach since the Linux framework remoteproc also supports loading elf
>firmwares, hence this would align nicely with what has been done in the
>Linux kernel.
>
>The elf format has all information required to load the firmware:
>Sections and their location (in M4 terms) as well as the start address.
>The platform data would only need to have a translation table for the
>section addresses (0x1fff8000 <=> 0x7F8000) to be able to load the
>firmware to the correct location. It comes with the cost of coping the
>firmware to the right location, but it would be much easier to handle
>elf firmware files.

If we need to let uboot support more functions such as interact with M4 cores,
remoteproc maybe a better choice. For simple usage only needs to boot M4,
bootaux is enough, I think.


Regards,
Peng.

>
>Other opinions?
>
>One more thing below:
>
>> 
>> See the following code:
>> "
>> int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>> {
>> 	struct src *src_reg;
>> 	u32 stack, pc;
>> 
>> 	if (!boot_private_data)
>> 		return 1;
>> 
>> 	stack = *(u32 *)boot_private_data;
>> 	pc = *(u32 *)(boot_private_data + 4);
>> 
>> 	/* Set the stack and pc to M4 bootROM */
>> 	writel(stack, M4_BOOTROM_BASE_ADDR);
>> 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
>> 
>> 	/* Enable M4 */
>> 	src_reg = (struct src *)SRC_BASE_ADDR;
>> 	setbits_le32(&src_reg->scr, 0x00400000);
>> 	clrbits_le32(&src_reg->scr, 0x00000010);
>> 
>> 	return 0;
>> }
>> 
>> "
>> 
>>>
>>>
>>>> Introduce Kconfig option IMX_BOOTAUX.
>>>>
>>>> Signed-off-by: Ye.Li <ye.li@nxp.com>
>>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>>> ---
>>>>  arch/arm/imx-common/Kconfig       |  6 ++++
>>>>  arch/arm/imx-common/Makefile      |  1 +
>>>>  arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
>>>>  3 files changed, 66 insertions(+)
>>>>  create mode 100644 arch/arm/imx-common/imx_bootaux.c
>>>>
>>>> diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
>>>> index c4f48bb..1b7da5a 100644
>>>> --- a/arch/arm/imx-common/Kconfig
>>>> +++ b/arch/arm/imx-common/Kconfig
>>>> @@ -11,3 +11,9 @@ config IMX_RDC
>>>>  	  i.MX Resource domain controller is used to assign masters
>>>>  	  and peripherals to differet domains. This can be used to
>>>>  	  isolate resources.
>>>> +
>>>> +config IMX_BOOTAUX
>>>> +	bool "Support boot auxiliary core"
>>>> +	depends on ARCH_MX7 || ARCH_MX6
>>>> +	help
>>>> +	  bootaux [addr] to boot auxiliary core.
>>>> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
>>>> index 568f41c..30e66ba 100644
>>>> --- a/arch/arm/imx-common/Makefile
>>>> +++ b/arch/arm/imx-common/Makefile
>>>> @@ -28,6 +28,7 @@ obj-y 	+= cache.o init.o
>>>>  obj-$(CONFIG_CMD_SATA) += sata.o
>>>>  obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
>>>>  obj-$(CONFIG_IMX_RDC) += rdc-sema.o
>>>> +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
>>>>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>>>>  endif
>>>>  ifeq ($(SOC),$(filter $(SOC),vf610))
>>>> diff --git a/arch/arm/imx-common/imx_bootaux.c
>>>> b/arch/arm/imx-common/imx_bootaux.c
>>>> new file mode 100644
>>>> index 0000000..da424a7
>>>> --- /dev/null
>>>> +++ b/arch/arm/imx-common/imx_bootaux.c
>>>> @@ -0,0 +1,59 @@
>>>> +/*
>>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>>> + *
>>>> + * SPDX-License-Identifier:	GPL-2.0+
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <command.h>
>>>> +
>>>> +/* Allow for arch specific config before we boot */
>>>> +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>>>> +{
>>>> +	/* please define platform specific arch_auxiliary_core_up() */
>>>> +	return CMD_RET_FAILURE;
>>>> +}
>>>> +
>>>> +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
>>>> +	__attribute__((weak, alias("__arch_auxiliary_core_up")));
>>>> +
>>>> +/* Allow for arch specific config before we boot */
>>>> +static int __arch_auxiliary_core_check_up(u32 core_id)
>>>> +{
>>>> +	/* please define platform specific arch_auxiliary_core_check_up() */
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +int arch_auxiliary_core_check_up(u32 core_id)
>>>> +	__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
>>>> +
>>>> +int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>>> +{
>>>> +	ulong addr;
>>>> +	int ret, up;
>>>> +
>>>> +	if (argc < 2)
>>>> +		return CMD_RET_USAGE;
>>>> +
>>>> +	up = arch_auxiliary_core_check_up(0);
>>>> +	if (up) {
>>>> +		printf("## Auxiliary core is already up\n");
>>>> +		return CMD_RET_SUCCESS;
>>>> +	}
>>>> +
>>>> +	addr = simple_strtoul(argv[1], NULL, 16);
>>>> +
>>>> +	printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
>>>> +
>
>A dcache flush is required after loading the firmware. This could be
>also part of this command e.g. by using flush_dcache_all.
>
>If we would make use of the elf format, then the main CPU would copy the
>data to the target memory address, and we could explicitly flush only
>the range required by the auxiliary core.
>
>--
>Stefan
>
>>>> +	ret = arch_auxiliary_core_up(0, addr);
>>>> +	if (ret)
>>>> +		return CMD_RET_FAILURE;
>>>> +
>>>> +	return CMD_RET_SUCCESS;
>>>> +}
>>>> +
>>>> +U_BOOT_CMD(
>>>> +	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
>>>> +	"Start auxiliary core",
>>>
>>>What kind of image are supported by the bootaux command? Afaik, this is
>>>some special/binary only format right?
>> 
>> Yeah. I just got the image from our rtos team, I do not have detail
>> info about the format.
>> 
>
>
>
>>>
>>>Probably another discussion, but before polluting the command namespace:
>>>Is that what we generally want?
>> 
>> Hmm, bootaux invokes
>> arch_auxiliary_core_check_up
>> arch_auxiliary_core_u
>> 
>> And arch code takes the responsibility to implement these two functions.
>> 
>> We try to make this common, but not sure whether this is ok for other SoCs.
>> So I move the command to arch/arm/imx-common
>> 
>> Thanks,
>> Peng.
>> 
>

[U-Boot] [PATCH 06/11] imx: imx-common: introduce boot auxiliary core

[Peng Fan]

Hi Simon,

Sorry for this late reply.
On Thu, Jan 14, 2016 at 10:17:20AM -0700, Simon Glass wrote:
>+Bin
>
>Hi Peng,
>
>On 4 January 2016 at 22:56, Peng Fan <van.freenix@gmail.com> wrote:
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> To boot a auxiliary core in asymmetric multicore system, introduce the
>> new command "bootaux" to do it. Example of boot auxliary core from
>> 0x70000000 where stores the boot head information that should be
>> parsed by auxiliary core, "bootaux 0x70000000".
>> Introduce Kconfig option IMX_BOOTAUX.
>>
>> Signed-off-by: Ye.Li <ye.li@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm/imx-common/Kconfig       |  6 ++++
>>  arch/arm/imx-common/Makefile      |  1 +
>>  arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 66 insertions(+)
>>  create mode 100644 arch/arm/imx-common/imx_bootaux.c
>>
>
>Could this use the CPU uclass?

Here we are just talking what kind of image and what command to boot a M4
core.
I do not have plan to use CPU uclass for this, since we have not
covert to support dtb in uboot for i.MX.

Thanks,
Peng.

>
>[snip]
>
>Regards,
>Simon