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From: Xing Zheng <zhengxing@rock-chips.com>
To: heiko@sntech.de
Cc: keescook@google.com, leozwang@google.com,
	linux-rockchip@lists.infradead.org,
	Xing Zheng <zhengxing@rock-chips.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error
Date: Thu,  7 Jan 2016 20:17:34 +0800	[thread overview]
Message-ID: <1452169057-24467-3-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1452169057-24467-1-git-send-email-zhengxing@rock-chips.com>

Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, we should to fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3036.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7e3b41c..04b5249 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,11 +242,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(1), 8, GFLAGS),
 	COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
-			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
-			RK2928_CLKGATE_CON(1), 8, GFLAGS),
+			RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+			RK2928_CLKGATE_CON(1), 10, GFLAGS),
 	COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
-			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
-			RK2928_CLKGATE_CON(1), 8, GFLAGS),
+			RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+			RK2928_CLKGATE_CON(1), 12, GFLAGS),
 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(17), 0,
 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
-- 
1.7.9.5



WARNING: multiple messages have this Message-ID (diff)
From: zhengxing@rock-chips.com (Xing Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error
Date: Thu,  7 Jan 2016 20:17:34 +0800	[thread overview]
Message-ID: <1452169057-24467-3-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1452169057-24467-1-git-send-email-zhengxing@rock-chips.com>

Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, we should to fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3036.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7e3b41c..04b5249 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,11 +242,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(1), 8, GFLAGS),
 	COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
-			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
-			RK2928_CLKGATE_CON(1), 8, GFLAGS),
+			RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+			RK2928_CLKGATE_CON(1), 10, GFLAGS),
 	COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
-			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
-			RK2928_CLKGATE_CON(1), 8, GFLAGS),
+			RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+			RK2928_CLKGATE_CON(1), 12, GFLAGS),
 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(17), 0,
 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
-- 
1.7.9.5

  parent reply	other threads:[~2016-01-07 12:18 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-07 12:17 [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng
2016-01-07 12:17 ` Xing Zheng
2016-01-07 12:17 ` Xing Zheng
2016-01-07 12:17 ` [PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux Xing Zheng
2016-01-07 12:17   ` Xing Zheng
2016-01-07 12:17 ` Xing Zheng [this message]
2016-01-07 12:17   ` [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error Xing Zheng
2016-01-07 12:17 ` [PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock Xing Zheng
2016-01-07 12:17   ` Xing Zheng
2016-01-07 12:17 ` [PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock Xing Zheng
2016-01-07 12:17   ` Xing Zheng
2016-01-07 12:26 ` [PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac Xing Zheng
2016-01-07 12:26   ` Xing Zheng
2016-01-09 20:10 ` [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Heiko Stuebner
2016-01-09 20:10   ` Heiko Stuebner
2016-01-09 20:10   ` Heiko Stuebner
2016-01-10  7:26   ` Xing Zheng
2016-01-10  7:26     ` Xing Zheng

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