[PATCH 0/3] Enabling GuC Loading on Broxton

[PATCH 0/3] Enabling GuC Loading on Broxton

[Peter Antoine]

This set of patches will enable the GuC loading for BXT.
There is also a fix that is required for GuC submission with the BXT GuC
to make it reliable.

Peter Antoine (3):
  drm/i915: Adding Broxton GuC Loader Support
  drm/i915: resize the GuC WOPCM for rc6
  drm/i915: Wait after context init with GuC Submission

 drivers/gpu/drm/i915/i915_gem.c         | 10 ++++++++++
 drivers/gpu/drm/i915/i915_guc_reg.h     |  3 ++-
 drivers/gpu/drm/i915/intel_guc_loader.c | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c        | 11 +++++++++++
 4 files changed, 35 insertions(+), 1 deletion(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/3] drm/i915: Adding Broxton GuC Loader Support

[Peter Antoine]

This commits adds the Broxton target to the GuC loader

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 550921f..8182d11 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -62,6 +62,9 @@
 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
 
+#define I915_BXT_GUC_UCODE "i915/bxt_guc_ver3.bin"
+MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
+
 /* User-friendly representation of an enum */
 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
 {
@@ -587,6 +590,10 @@ void intel_guc_ucode_init(struct drm_device *dev)
 		fw_path = I915_SKL_GUC_UCODE;
 		guc_fw->guc_fw_major_wanted = 4;
 		guc_fw->guc_fw_minor_wanted = 3;
+	} else if (IS_BROXTON(dev)) {
+		fw_path = I915_BXT_GUC_UCODE;
+		guc_fw->guc_fw_major_wanted = 3;
+		guc_fw->guc_fw_minor_wanted = 0;
 	} else {
 		i915.enable_guc_submission = false;
 		fw_path = "";	/* unknown device */
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: resize the GuC WOPCM for rc6

[Peter Antoine]

This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h     | 3 ++-
 drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 685c799..cb938b0 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -58,7 +58,8 @@
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
+#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
+#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
 
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
 #define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8182d11..6b17d44 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -305,6 +305,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
 	/* init WOPCM */
 	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+	if (IS_BROXTON(dev))
+		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
+	else
+		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 
 	/* Enable MIA caching. GuC clock gating is disabled. */
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/3] drm/i915: Wait after context init with GuC Submission

[Peter Antoine]

Per-context initialisation GPU instructions (which are injected directly
into the ringbuffer rather than being submitted as a batch) should not
be allowed to mix with user-generated batches in the same submission; it
will cause confusion for the GuC (which might merge a subsequent
preemptive request with the non-preemptive initialisation code), and for
the scheduler, which wouldn't know how to re-inject a non-batch request
if it were the victim of preemption.

Therefore, we should wait for the initialisation request to complete
before making the newly-initialised context available for user-mode
submissions.

Here, we add a call to i915_wait_request() after each existing call to
i915_add_request_no_flush() (in i915_gem_init_hw(), for the default
per-engine contexts, and intel_lr_context_deferred_create(), for all
others).

Adapted from Dave Gordon's patch, which is adapted from Alex's earlier
patch, which added the wait only to intel_lr_context_render_state_init().

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c  | 10 ++++++++++
 drivers/gpu/drm/i915/intel_lrc.c | 11 +++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5be4433..e71bf90 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4847,6 +4847,16 @@ i915_gem_init_hw(struct drm_device *dev)
 		}
 
 		i915_add_request_no_flush(req);
+
+		/*
+		 * GuC firmware will try to collapse its DPC work queue if the
+		 * new one is for same context. So the following breadcrumb
+		 * could be amended to this batch and submitted as one batch.
+		 * Wait here to make sure the context state init is finished
+		 * before any other submission to GuC.
+		 */
+		if (i915.enable_guc_submission)
+			ret = i915_wait_request(req);
 	}
 
 out:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3aa6147..f18fb11 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2499,6 +2499,17 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
 			goto error_ringbuf;
 		}
 		i915_add_request_no_flush(req);
+
+		/*
+		 * GuC firmware will try to collapse its DPC work queue
+		 * if the new one is for same context. So the
+		 * following breadcrumb could be amended to this batch
+		 * and submitted as one batch. Wait here to make sure
+		 * the context state init is finished before any other
+		 * submission to GuC.
+		 */
+		if (i915.enable_guc_submission)
+			ret = i915_wait_request(req);
 	}
 	return 0;
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Wait after context init with GuC Submission

[Chris Wilson]

On Fri, Jan 08, 2016 at 03:03:54PM +0000, Peter Antoine wrote:
> Per-context initialisation GPU instructions (which are injected directly
> into the ringbuffer rather than being submitted as a batch) should not
> be allowed to mix with user-generated batches in the same submission; it
> will cause confusion for the GuC (which might merge a subsequent
> preemptive request with the non-preemptive initialisation code), and for
> the scheduler, which wouldn't know how to re-inject a non-batch request
> if it were the victim of preemption.

Move the context init into the first request. Problem solved.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ warning: Fi.CI.BAT

[Patchwork]

== Summary ==

Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest

Test gem_storedw_loop:
        Subgroup basic-render:
                pass       -> DMESG-WARN (skl-i5k-2) UNSTABLE
                dmesg-warn -> PASS       (bdw-ultra)
                dmesg-warn -> PASS       (skl-i7k-2) UNSTABLE
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                pass       -> DMESG-WARN (skl-i7k-2)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b:
                dmesg-warn -> PASS       (byt-nuc)

bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:138  pass:132  dwarn:0   dfail:0   fail:0   skip:6  
bsw-nuc-2        total:141  pass:114  dwarn:3   dfail:0   fail:0   skip:24 
byt-nuc          total:141  pass:119  dwarn:7   dfail:0   fail:0   skip:15 
hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
hsw-gt2          total:141  pass:137  dwarn:0   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:141  pass:100  dwarn:4   dfail:0   fail:0   skip:37 
skl-i5k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
skl-i7k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 

Results at /archive/results/CI_IGT_test/Patchwork_1117/

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Wait after context init with GuC Submission

[Antoine, Peter]

Ok,

Please ignore this patch.
It is really part of the pre-emption series. Was included as is being used in Android.

Peter.

-----Original Message-----
From: Chris Wilson [mailto:chris@chris-wilson.co.uk] 
Sent: Friday, January 8, 2016 3:20 PM
To: Antoine, Peter
Cc: intel-gfx@lists.freedesktop.org; daniel.vetter@ffwll.ch; Gordon, Dave
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Wait after context init with GuC Submission

On Fri, Jan 08, 2016 at 03:03:54PM +0000, Peter Antoine wrote:
> Per-context initialisation GPU instructions (which are injected 
> directly into the ringbuffer rather than being submitted as a batch) 
> should not be allowed to mix with user-generated batches in the same 
> submission; it will cause confusion for the GuC (which might merge a 
> subsequent preemptive request with the non-preemptive initialisation 
> code), and for the scheduler, which wouldn't know how to re-inject a 
> non-batch request if it were the victim of preemption.

Move the context init into the first request. Problem solved.
-Chris

--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/3] drm/i915: Adding Broxton GuC Loader Support

[Yu Dai]

Reviewed-by: Alex Dai <yu.dai@intel.com>

On 01/08/2016 07:03 AM, Peter Antoine wrote:
> This commits adds the Broxton target to the GuC loader
>
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 550921f..8182d11 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -62,6 +62,9 @@
>   #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
>   MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
>   
> +#define I915_BXT_GUC_UCODE "i915/bxt_guc_ver3.bin"
> +MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> +
>   /* User-friendly representation of an enum */
>   const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
>   {
> @@ -587,6 +590,10 @@ void intel_guc_ucode_init(struct drm_device *dev)
>   		fw_path = I915_SKL_GUC_UCODE;
>   		guc_fw->guc_fw_major_wanted = 4;
>   		guc_fw->guc_fw_minor_wanted = 3;
> +	} else if (IS_BROXTON(dev)) {
> +		fw_path = I915_BXT_GUC_UCODE;
> +		guc_fw->guc_fw_major_wanted = 3;
> +		guc_fw->guc_fw_minor_wanted = 0;
>   	} else {
>   		i915.enable_guc_submission = false;
>   		fw_path = "";	/* unknown device */

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: resize the GuC WOPCM for rc6

[Yu Dai]

Reviewed-by: Alex Dai <yu.dai@intel.com>

On 01/08/2016 07:03 AM, Peter Antoine wrote:
> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
> spaces do not overlap.
>
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h     | 3 ++-
>   drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
>   2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 685c799..cb938b0 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -58,7 +58,8 @@
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>   
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>   
>   /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>   #define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 8182d11..6b17d44 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -305,6 +305,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>   
>   	/* init WOPCM */
>   	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>   
>   	/* Enable MIA caching. GuC clock gating is disabled. */

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Wait after context init with GuC Submission

[Yu Dai]

Reviewed-by: Alex Dai <yu.dai@intel.com>

On 01/08/2016 07:03 AM, Peter Antoine wrote:
> Per-context initialisation GPU instructions (which are injected directly
> into the ringbuffer rather than being submitted as a batch) should not
> be allowed to mix with user-generated batches in the same submission; it
> will cause confusion for the GuC (which might merge a subsequent
> preemptive request with the non-preemptive initialisation code), and for
> the scheduler, which wouldn't know how to re-inject a non-batch request
> if it were the victim of preemption.
>
> Therefore, we should wait for the initialisation request to complete
> before making the newly-initialised context available for user-mode
> submissions.
>
> Here, we add a call to i915_wait_request() after each existing call to
> i915_add_request_no_flush() (in i915_gem_init_hw(), for the default
> per-engine contexts, and intel_lr_context_deferred_create(), for all
> others).
>
> Adapted from Dave Gordon's patch, which is adapted from Alex's earlier
> patch, which added the wait only to intel_lr_context_render_state_init().
>
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem.c  | 10 ++++++++++
>   drivers/gpu/drm/i915/intel_lrc.c | 11 +++++++++++
>   2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 5be4433..e71bf90 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4847,6 +4847,16 @@ i915_gem_init_hw(struct drm_device *dev)
>   		}
>   
>   		i915_add_request_no_flush(req);
> +
> +		/*
> +		 * GuC firmware will try to collapse its DPC work queue if the
> +		 * new one is for same context. So the following breadcrumb
> +		 * could be amended to this batch and submitted as one batch.
> +		 * Wait here to make sure the context state init is finished
> +		 * before any other submission to GuC.
> +		 */
> +		if (i915.enable_guc_submission)
> +			ret = i915_wait_request(req);
>   	}
>   
>   out:
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 3aa6147..f18fb11 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2499,6 +2499,17 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
>   			goto error_ringbuf;
>   		}
>   		i915_add_request_no_flush(req);
> +
> +		/*
> +		 * GuC firmware will try to collapse its DPC work queue
> +		 * if the new one is for same context. So the
> +		 * following breadcrumb could be amended to this batch
> +		 * and submitted as one batch. Wait here to make sure
> +		 * the context state init is finished before any other
> +		 * submission to GuC.
> +		 */
> +		if (i915.enable_guc_submission)
> +			ret = i915_wait_request(req);
>   	}
>   	return 0;
>   

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ warning: Fi.CI.BAT

[Daniel Vetter]

On Mon, Jan 11, 2016 at 10:13:53AM -0000, Patchwork wrote:
> == Summary ==
> 
> Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest
> 
> Test gem_storedw_loop:
>         Subgroup basic-render:
>                 pass       -> DMESG-WARN (skl-i5k-2) UNSTABLE
>                 dmesg-warn -> PASS       (bdw-ultra)
>                 dmesg-warn -> PASS       (skl-i7k-2) UNSTABLE
> Test kms_flip:
>         Subgroup basic-flip-vs-modeset:
>                 pass       -> DMESG-WARN (skl-i7k-2)

Seem to have a regression here, and passing BAT is now required.
-Daniel

> Test kms_pipe_crc_basic:
>         Subgroup read-crc-pipe-b:
>                 dmesg-warn -> PASS       (byt-nuc)
> 
> bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
> bdw-ultra        total:138  pass:132  dwarn:0   dfail:0   fail:0   skip:6  
> bsw-nuc-2        total:141  pass:114  dwarn:3   dfail:0   fail:0   skip:24 
> byt-nuc          total:141  pass:119  dwarn:7   dfail:0   fail:0   skip:15 
> hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
> hsw-gt2          total:141  pass:137  dwarn:0   dfail:0   fail:0   skip:4  
> ilk-hp8440p      total:141  pass:100  dwarn:4   dfail:0   fail:0   skip:37 
> skl-i5k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
> skl-i7k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
> snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
> snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1117/
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: resize the GuC WOPCM for rc6

[Yu Dai]

On 01/08/2016 07:03 AM, Peter Antoine wrote:
> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
> spaces do not overlap.
>
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h     | 3 ++-
>   drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
>   2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 685c799..cb938b0 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -58,7 +58,8 @@
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>   
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>   
>   /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>   #define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 8182d11..6b17d44 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -305,6 +305,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>   
>   	/* init WOPCM */
>   	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);

Just found a problem here. This line above needs to be deleted. This 
GUC_WOPCM_SIZE is written-once register. It will be locked after first 
write.

Thanks,
Alex
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>   
>   	/* Enable MIA caching. GuC clock gating is disabled. */

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: resize the GuC WOPCM for rc6

[Jeff McGee]

On Fri, Jan 08, 2016 at 03:03:53PM +0000, Peter Antoine wrote:
> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
> spaces do not overlap.
> 
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_reg.h     | 3 ++-
>  drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 685c799..cb938b0 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -58,7 +58,8 @@
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>  
>  #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>  
>  /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>  #define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
There seems to be other references to GUC_WOPCM_SIZE_VALUE including this
one that need to be updated for BXT.
-Jeff

> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 8182d11..6b17d44 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -305,6 +305,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  
>  	/* init WOPCM */
>  	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>  
>  	/* Enable MIA caching. GuC clock gating is disabled. */
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx