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* [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size
@ 2016-01-08 16:58 Mika Kuoppala
  2016-01-08 16:58 ` [PATCH 2/2] drm/i915/gen9: Calculate edram size Mika Kuoppala
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Mika Kuoppala @ 2016-01-08 16:58 UTC (permalink / raw)
  To: intel-gfx

Store the edram capabilities instead of only the size of
edram. This is preparatory patch to allow edram size calculation
based on edram capability bits for gen9+.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h     |  7 +++++--
 drivers/gpu/drm/i915/i915_gem.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c | 39 +++++++++++++++++++++++++------------
 6 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e3377abc0d4d..039ace6e4524 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2401,7 +2401,7 @@ static int i915_llc(struct seq_file *m, void *data)
 
 	/* Size calculation for LLC is a bit of a pain. Ignore for now. */
 	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
-	seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
+	seq_printf(m, "eLLC: %zuMB\n", intel_uncore_edram_size_mb(dev_priv));
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6ef03eea3518..c81f537b2da7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1846,7 +1846,7 @@ struct drm_i915_private {
 	struct intel_l3_parity l3_parity;
 
 	/* Cannot be determined by PCIID. You must always read a register. */
-	size_t ellc_size;
+	u32 edram_cap;
 
 	/* gen6+ rps state */
 	struct intel_gen6_power_mgmt rps;
@@ -2567,8 +2567,9 @@ struct drm_i915_cmd_table {
 #define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
 #define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
 #define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
+#define HAS_EDRAM(dev)		(__I915__(dev)->edram_cap & EDRAM_ENABLED)
 #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
-				 __I915__(dev)->ellc_size)
+				 HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
@@ -2735,6 +2736,8 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 					enum forcewake_domains domains);
 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 					enum forcewake_domains domains);
+unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv);
+
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
 static inline bool intel_vgpu_active(struct drm_device *dev)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8efc9dfbc48..0a5e5524def3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4799,7 +4799,7 @@ i915_gem_init_hw(struct drm_device *dev)
 	/* Double layer security blanket, see i915_gem_init() */
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (dev_priv->ellc_size)
+	if (HAS_EDRAM(dev_priv))
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
 	if (IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56f4f2e58d53..1d1933130b7a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3157,7 +3157,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else if (INTEL_INFO(dev)->gen < 8) {
 		gtt->gtt_probe = gen6_gmch_probe;
 		gtt->base.cleanup = gen6_gmch_remove;
-		if (IS_HASWELL(dev) && dev_priv->ellc_size)
+		if (HAS_EDRAM(dev))
 			gtt->base.pte_encode = iris_pte_encode;
 		else if (IS_HASWELL(dev))
 			gtt->base.pte_encode = hsw_pte_encode;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 556a458d669e..f88b75ec5047 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6818,7 +6818,7 @@ enum skl_disp_power_wells {
 
 #define  HSW_IDICR				_MMIO(0x9008)
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
-#define  HSW_EDRAM_PRESENT			_MMIO(0x120010)
+#define  HSW_EDRAM_CAP				_MMIO(0x120010)
 #define    EDRAM_ENABLED			0x1
 
 #define GEN6_UCGCTL1				_MMIO(0x9400)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d0973e08e7eb..0c9059cb3d13 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -310,21 +310,36 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void intel_uncore_ellc_detect(struct drm_device *dev)
+unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	if (!HAS_EDRAM(dev_priv))
+		return 0;
+
+	/* The docs do not explain exactly how the calculation can be
+	 * made. It is somewhat guessable, but for now, it's always
+	 * 128MB.
+	 */
+
+	return 128;
+}
 
-	if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
-	     INTEL_INFO(dev)->gen >= 9) &&
-	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
-		/* The docs do not explain exactly how the calculation can be
-		 * made. It is somewhat guessable, but for now, it's always
-		 * 128MB.
-		 * NB: We can't write IDICR yet because we do not have gt funcs
+static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
+{
+	if (IS_HASWELL(dev_priv) ||
+	    IS_BROADWELL(dev_priv) ||
+	    INTEL_INFO(dev_priv)->gen >= 9) {
+		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
+							HSW_EDRAM_CAP);
+
+		/* NB: We can't write IDICR yet because we do not have gt funcs
 		 * set up */
-		dev_priv->ellc_size = 128;
-		DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
+	} else {
+		dev_priv->edram_cap = 0;
 	}
+
+	if (HAS_EDRAM(dev_priv))
+		DRM_INFO("Found %zuMB of eLLC\n",
+			 intel_uncore_edram_size_mb(dev_priv));
 }
 
 static bool
@@ -1239,7 +1254,7 @@ void intel_uncore_init(struct drm_device *dev)
 
 	i915_check_vgpu(dev);
 
-	intel_uncore_ellc_detect(dev);
+	intel_uncore_edram_detect(dev_priv);
 	intel_uncore_fw_domains_init(dev);
 	__intel_uncore_early_sanitize(dev, false);
 
-- 
2.5.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/gen9: Calculate edram size
  2016-01-08 16:58 [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size Mika Kuoppala
@ 2016-01-08 16:58 ` Mika Kuoppala
  2016-01-11  7:50   ` Daniel Vetter
  2016-01-11 10:27 ` ✗ failure: Fi.CI.BAT Patchwork
  2016-01-11 10:27 ` ✗ warning: Fi.CI.BAT Patchwork
  2 siblings, 1 reply; 6+ messages in thread
From: Mika Kuoppala @ 2016-01-08 16:58 UTC (permalink / raw)
  To: intel-gfx

With gen9+ the edram capabilities are defined so
that we can calculate the edram (ellc) size accordingly.

Note that there are undefined combinations for some subset of
edram capability bits. Return the closest size for undefined indexes.
Even if we get it wrong with beginning of future gen enabling, the size
information is currently only used for boot message and in debugfs entry.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_uncore.c |  9 +++++----
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f88b75ec5047..52283c44a0c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6820,6 +6820,20 @@ enum skl_disp_power_wells {
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
 #define    EDRAM_ENABLED			0x1
+#define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
+#define    __EDRAM_WAYS(cap)			(((cap) >> 5) & 0x7)
+#define    EDRAM_NUM_WAYS(cap)			({ \
+			int __ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; \
+			__ways[__EDRAM_WAYS(cap)]; \
+})
+#define    __EDRAM_SETS(cap)			(((cap) >> 8) & 0x3)
+#define    EDRAM_NUM_SETS(cap)			({ \
+			int __sets[4] = { 1, 1, 2, 2 }; \
+			__sets[__EDRAM_SETS(cap)]; \
+})
+#define    EDRAM_SIZE(cap)			(EDRAM_NUM_BANKS(cap) * \
+						 EDRAM_NUM_WAYS(cap) * \
+						 EDRAM_NUM_SETS(cap))
 
 #define GEN6_UCGCTL1				_MMIO(0x9400)
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0c9059cb3d13..c5fb1937b82d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -315,12 +315,13 @@ unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv)
 	if (!HAS_EDRAM(dev_priv))
 		return 0;
 
-	/* The docs do not explain exactly how the calculation can be
-	 * made. It is somewhat guessable, but for now, it's always
-	 * 128MB.
+	/* The needed capability bits for size calculation
+	 * are not there with pre gen9 so return 128MB always.
 	 */
+	if (INTEL_INFO(dev_priv)->gen < 9)
+		return 128;
 
-	return 128;
+	return EDRAM_SIZE(dev_priv->edram_cap);
 }
 
 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
-- 
2.5.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/gen9: Calculate edram size
  2016-01-08 16:58 ` [PATCH 2/2] drm/i915/gen9: Calculate edram size Mika Kuoppala
@ 2016-01-11  7:50   ` Daniel Vetter
  2016-01-11  9:00     ` Chris Wilson
  0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2016-01-11  7:50 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

On Fri, Jan 08, 2016 at 06:58:45PM +0200, Mika Kuoppala wrote:
> With gen9+ the edram capabilities are defined so
> that we can calculate the edram (ellc) size accordingly.
> 
> Note that there are undefined combinations for some subset of
> edram capability bits. Return the closest size for undefined indexes.
> Even if we get it wrong with beginning of future gen enabling, the size
> information is currently only used for boot message and in debugfs entry.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_uncore.c |  9 +++++----
>  2 files changed, 19 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f88b75ec5047..52283c44a0c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6820,6 +6820,20 @@ enum skl_disp_power_wells {
>  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
>  #define  HSW_EDRAM_CAP				_MMIO(0x120010)
>  #define    EDRAM_ENABLED			0x1
> +#define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
> +#define    __EDRAM_WAYS(cap)			(((cap) >> 5) & 0x7)
> +#define    EDRAM_NUM_WAYS(cap)			({ \
> +			int __ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; \
> +			__ways[__EDRAM_WAYS(cap)]; \
> +})
> +#define    __EDRAM_SETS(cap)			(((cap) >> 8) & 0x3)
> +#define    EDRAM_NUM_SETS(cap)			({ \
> +			int __sets[4] = { 1, 1, 2, 2 }; \
> +			__sets[__EDRAM_SETS(cap)]; \
> +})
> +#define    EDRAM_SIZE(cap)			(EDRAM_NUM_BANKS(cap) * \
> +						 EDRAM_NUM_WAYS(cap) * \
> +						 EDRAM_NUM_SETS(cap))

Please just make a function out of this, no reason to make it into a
hard-to-read macro. E.g. gen9_edram_size or whatever is the first gen this
starts to be valid for.
-Daniel

>  
>  #define GEN6_UCGCTL1				_MMIO(0x9400)
>  # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0c9059cb3d13..c5fb1937b82d 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -315,12 +315,13 @@ unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv)
>  	if (!HAS_EDRAM(dev_priv))
>  		return 0;
>  
> -	/* The docs do not explain exactly how the calculation can be
> -	 * made. It is somewhat guessable, but for now, it's always
> -	 * 128MB.
> +	/* The needed capability bits for size calculation
> +	 * are not there with pre gen9 so return 128MB always.
>  	 */
> +	if (INTEL_INFO(dev_priv)->gen < 9)
> +		return 128;
>  
> -	return 128;
> +	return EDRAM_SIZE(dev_priv->edram_cap);
>  }
>  
>  static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/gen9: Calculate edram size
  2016-01-11  7:50   ` Daniel Vetter
@ 2016-01-11  9:00     ` Chris Wilson
  0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2016-01-11  9:00 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx

On Mon, Jan 11, 2016 at 08:50:43AM +0100, Daniel Vetter wrote:
> On Fri, Jan 08, 2016 at 06:58:45PM +0200, Mika Kuoppala wrote:
> > With gen9+ the edram capabilities are defined so
> > that we can calculate the edram (ellc) size accordingly.
> > 
> > Note that there are undefined combinations for some subset of
> > edram capability bits. Return the closest size for undefined indexes.
> > Even if we get it wrong with beginning of future gen enabling, the size
> > information is currently only used for boot message and in debugfs entry.
> > 
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     | 14 ++++++++++++++
> >  drivers/gpu/drm/i915/intel_uncore.c |  9 +++++----
> >  2 files changed, 19 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f88b75ec5047..52283c44a0c1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6820,6 +6820,20 @@ enum skl_disp_power_wells {
> >  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
> >  #define  HSW_EDRAM_CAP				_MMIO(0x120010)
> >  #define    EDRAM_ENABLED			0x1
> > +#define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
> > +#define    __EDRAM_WAYS(cap)			(((cap) >> 5) & 0x7)
> > +#define    EDRAM_NUM_WAYS(cap)			({ \
> > +			int __ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; \
> > +			__ways[__EDRAM_WAYS(cap)]; \
> > +})
> > +#define    __EDRAM_SETS(cap)			(((cap) >> 8) & 0x3)
> > +#define    EDRAM_NUM_SETS(cap)			({ \
> > +			int __sets[4] = { 1, 1, 2, 2 }; \
> > +			__sets[__EDRAM_SETS(cap)]; \
> > +})
> > +#define    EDRAM_SIZE(cap)			(EDRAM_NUM_BANKS(cap) * \
> > +						 EDRAM_NUM_WAYS(cap) * \
> > +						 EDRAM_NUM_SETS(cap))
> 
> Please just make a function out of this, no reason to make it into a
> hard-to-read macro. E.g. gen9_edram_size or whatever is the first gen this
> starts to be valid for.

May I humbly suggest intel_uncore_edram_size_mb() ? ;)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* ✗ failure: Fi.CI.BAT
  2016-01-08 16:58 [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size Mika Kuoppala
  2016-01-08 16:58 ` [PATCH 2/2] drm/i915/gen9: Calculate edram size Mika Kuoppala
@ 2016-01-11 10:27 ` Patchwork
  2016-01-11 10:27 ` ✗ warning: Fi.CI.BAT Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-01-11 10:27 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

== Summary ==

Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest

Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (bdw-ultra)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                dmesg-warn -> PASS       (ilk-hp8440p)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b:
                pass       -> DMESG-WARN (bdw-ultra)
                dmesg-warn -> PASS       (byt-nuc)

bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:138  pass:131  dwarn:1   dfail:0   fail:0   skip:6  
bsw-nuc-2        total:141  pass:114  dwarn:3   dfail:0   fail:0   skip:24 
byt-nuc          total:141  pass:119  dwarn:7   dfail:0   fail:0   skip:15 
hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
hsw-gt2          total:141  pass:137  dwarn:0   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:141  pass:101  dwarn:3   dfail:0   fail:0   skip:37 
skl-i5k-2        total:141  pass:132  dwarn:1   dfail:0   fail:0   skip:8  
skl-i7k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 

HANGED ivb-t430s in igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b

Results at /archive/results/CI_IGT_test/Patchwork_1118/

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* ✗ warning: Fi.CI.BAT
  2016-01-08 16:58 [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size Mika Kuoppala
  2016-01-08 16:58 ` [PATCH 2/2] drm/i915/gen9: Calculate edram size Mika Kuoppala
  2016-01-11 10:27 ` ✗ failure: Fi.CI.BAT Patchwork
@ 2016-01-11 10:27 ` Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-01-11 10:27 UTC (permalink / raw)
  To: Mika Kuoppala; +Cc: intel-gfx

== Summary ==

Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest

Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (bdw-ultra)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                dmesg-warn -> PASS       (ilk-hp8440p)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b:
                pass       -> DMESG-WARN (bdw-ultra)
                dmesg-warn -> PASS       (byt-nuc)

bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:138  pass:131  dwarn:1   dfail:0   fail:0   skip:6  
bsw-nuc-2        total:141  pass:114  dwarn:3   dfail:0   fail:0   skip:24 
byt-nuc          total:141  pass:119  dwarn:7   dfail:0   fail:0   skip:15 
hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
hsw-gt2          total:141  pass:137  dwarn:0   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:141  pass:101  dwarn:3   dfail:0   fail:0   skip:37 
skl-i5k-2        total:141  pass:132  dwarn:1   dfail:0   fail:0   skip:8  
skl-i7k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 

HANGED ivb-t430s in igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b

Results at /archive/results/CI_IGT_test/Patchwork_1118/

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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-11 10:27 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-08 16:58 [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size Mika Kuoppala
2016-01-08 16:58 ` [PATCH 2/2] drm/i915/gen9: Calculate edram size Mika Kuoppala
2016-01-11  7:50   ` Daniel Vetter
2016-01-11  9:00     ` Chris Wilson
2016-01-11 10:27 ` ✗ failure: Fi.CI.BAT Patchwork
2016-01-11 10:27 ` ✗ warning: Fi.CI.BAT Patchwork

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