[RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

The NAND Flash controller for SAMA5D2 has small differences that make it
impossible to use the existing driver for SAMA5D3. This patchset uses the
device tree's compatible string to get those differences, and the code is
slightly modified to handle them.

Applies on the Atmel Linux 4.1 branch for now, but only the dtsi file
differs from the mainline.

Compile tested for all SAMA5 chips for now, and tested on SAMA5D3xek as
there is no existing SAMA5D2 board with NAND Flash memory (yet).

Romain Izard (4):
  mtd: atmel_nand: Do not warn on bitflips
  mtd: atmel_nand: Support variable RB_EDGE interrupts
  mtd: atmel_nand: Support 32-bit ECC strength
  ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

 .../devicetree/bindings/mtd/atmel-nand.txt         | 12 ++-
 arch/arm/boot/dts/sama5d2.dtsi                     | 38 ++++++++++
 drivers/mtd/nand/atmel_nand.c                      | 86 ++++++++++++++++++----
 drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
 drivers/mtd/nand/atmel_nand_nfc.h                  |  5 +-
 5 files changed, 128 insertions(+), 22 deletions(-)

-- 
2.5.0

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[RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

The NAND Flash controller for SAMA5D2 has small differences that make it
impossible to use the existing driver for SAMA5D3. This patchset uses the
device tree's compatible string to get those differences, and the code is
slightly modified to handle them.

Applies on the Atmel Linux 4.1 branch for now, but only the dtsi file
differs from the mainline.

Compile tested for all SAMA5 chips for now, and tested on SAMA5D3xek as
there is no existing SAMA5D2 board with NAND Flash memory (yet).

Romain Izard (4):
  mtd: atmel_nand: Do not warn on bitflips
  mtd: atmel_nand: Support variable RB_EDGE interrupts
  mtd: atmel_nand: Support 32-bit ECC strength
  ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

 .../devicetree/bindings/mtd/atmel-nand.txt         | 12 ++-
 arch/arm/boot/dts/sama5d2.dtsi                     | 38 ++++++++++
 drivers/mtd/nand/atmel_nand.c                      | 86 ++++++++++++++++++----
 drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
 drivers/mtd/nand/atmel_nand_nfc.h                  |  5 +-
 5 files changed, 128 insertions(+), 22 deletions(-)

-- 
2.5.0

[RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips

[Romain Izard]

When using multi-bit ECC, it is normal for the NAND Flash driver to
correct bit errors during the life of the product. Those errors will
only be cleared once a threshold has been reached, and corrections can
occur regularly before this.

Use only dev_dbg and not dev_info to report the bitflips, to keep the
system log clean when everything works correctly.

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/mtd/nand/atmel_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 46010bd895b1..9d71f9e6a8de 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -824,7 +824,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 			*(buf + byte_pos) ^= (1 << bit_pos);
 
 			pos = sector_num * host->pmecc_sector_size + byte_pos;
-			dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, *(buf + byte_pos));
 		} else {
 			/* Bit flip in OOB area */
@@ -834,7 +834,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 			ecc[tmp] ^= (1 << bit_pos);
 
 			pos = tmp + nand_chip->ecc.layout->eccpos[0];
-			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, ecc[tmp]);
 		}
 
-- 
2.5.0

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[RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips

[Romain Izard]

When using multi-bit ECC, it is normal for the NAND Flash driver to
correct bit errors during the life of the product. Those errors will
only be cleared once a threshold has been reached, and corrections can
occur regularly before this.

Use only dev_dbg and not dev_info to report the bitflips, to keep the
system log clean when everything works correctly.

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
 drivers/mtd/nand/atmel_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 46010bd895b1..9d71f9e6a8de 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -824,7 +824,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 			*(buf + byte_pos) ^= (1 << bit_pos);
 
 			pos = sector_num * host->pmecc_sector_size + byte_pos;
-			dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, *(buf + byte_pos));
 		} else {
 			/* Bit flip in OOB area */
@@ -834,7 +834,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 			ecc[tmp] ^= (1 << bit_pos);
 
 			pos = tmp + nand_chip->ecc.layout->eccpos[0];
-			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, ecc[tmp]);
 		}
 
-- 
2.5.0

[RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Romain Izard]

The NFC controller used to accelerate the NAND transfers on SAMA5 chips
can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.

Use the controller's compatible string to select the correct bit.

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-
 drivers/mtd/nand/atmel_nand.c                      | 39 +++++++++++++++++-----
 drivers/mtd/nand/atmel_nand_nfc.h                  |  5 ++-
 3 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 7d4c8eb775a5..89b0db9801b0 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -34,7 +34,7 @@ Optional properties:
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
   - Required properties:
-    - compatible : "atmel,sama5d3-nfc".
+    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
     - reg : should specify the address and size used for NFC command registers,
             NFC registers and NFC Sram. NFC Sram address and size can be absent
             if don't want to use it.
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 9d71f9e6a8de..e5d7e7e63f49 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -67,6 +67,10 @@ struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
 };
 
+struct atmel_nand_nfc_priv {
+	uint32_t rb_edge;
+};
+
 /* oob layout for large page size
  * bad block info is on bytes 0 and 1
  * the bytes have to be consecutives to avoid
@@ -111,6 +115,7 @@ struct atmel_nfc {
 	/* Point to the sram bank which include readed data via NFC */
 	void			*data_in_sram;
 	bool			will_write_sram;
+	uint32_t		rb_edge;
 };
 static struct atmel_nfc	nand_nfc;
 
@@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
 		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
 		ret = IRQ_HANDLED;
 	}
-	if (pending & NFC_SR_RB_EDGE) {
+	if (pending & host->nfc->rb_edge) {
 		complete(&host->nfc->comp_ready);
-		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
+		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->rb_edge);
 		ret = IRQ_HANDLED;
 	}
 	if (pending & NFC_SR_CMD_DONE) {
@@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		init_completion(&host->nfc->comp_xfer_done);
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->rb_edge)
 		init_completion(&host->nfc->comp_ready);
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		comp[index++] = &host->nfc->comp_xfer_done;
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->rb_edge)
 		comp[index++] = &host->nfc->comp_ready;
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
 		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
 				mask & status);
 
-	return status & NFC_SR_RB_EDGE;
+	return status & host->nfc->rb_edge;
 }
 
 static void nfc_select_chip(struct mtd_info *mtd, int chip)
@@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 		}
 		/* fall through */
 	default:
-		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
-		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
+		nfc_prepare_interrupt(host, host->nfc->rb_edge);
+		nfc_wait_interrupt(host, host->nfc->rb_edge);
 	}
 }
 
@@ -2318,9 +2323,12 @@ static const struct of_device_id atmel_nand_dt_ids[] = {
 
 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
 
+static const struct of_device_id atmel_nand_nfc_match[];
+
 static int atmel_nand_nfc_probe(struct platform_device *pdev)
 {
 	struct atmel_nfc *nfc = &nand_nfc;
+	const struct atmel_nand_nfc_priv *priv;
 	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
 	int ret;
 
@@ -2352,6 +2360,12 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
 		}
 	}
 
+	priv = of_match_device(atmel_nand_nfc_match, &pdev->dev)->data;
+	if (NULL == priv)
+		return -ENODEV;
+
+	nfc->rb_edge = priv->rb_edge;
+
 	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
 	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
 
@@ -2380,8 +2394,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static struct atmel_nand_nfc_priv sama5d3_nfc_priv = {
+	.rb_edge = NFC_SR_RB_EDGE0,
+};
+
+static struct atmel_nand_nfc_priv sama5d4_nfc_priv = {
+	.rb_edge = NFC_SR_RB_EDGE3,
+};
+
 static const struct of_device_id atmel_nand_nfc_match[] = {
-	{ .compatible = "atmel,sama5d3-nfc" },
+	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_priv },
+	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_priv },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
index 4d5d26221a7e..2cd9c57b1e53 100644
--- a/drivers/mtd/nand/atmel_nand_nfc.h
+++ b/drivers/mtd/nand/atmel_nand_nfc.h
@@ -42,7 +42,10 @@
 #define		NFC_SR_UNDEF		(1 << 21)
 #define		NFC_SR_AWB		(1 << 22)
 #define		NFC_SR_ASE		(1 << 23)
-#define		NFC_SR_RB_EDGE		(1 << 24)
+#define		NFC_SR_RB_EDGE0		(1 << 24)
+#define		NFC_SR_RB_EDGE1		(1 << 25)
+#define		NFC_SR_RB_EDGE2		(1 << 26)
+#define		NFC_SR_RB_EDGE3		(1 << 27)
 
 #define ATMEL_HSMC_NFC_IER	0x0c
 #define ATMEL_HSMC_NFC_IDR	0x10
-- 
2.5.0

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[RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Romain Izard]

The NFC controller used to accelerate the NAND transfers on SAMA5 chips
can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.

Use the controller's compatible string to select the correct bit.

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-
 drivers/mtd/nand/atmel_nand.c                      | 39 +++++++++++++++++-----
 drivers/mtd/nand/atmel_nand_nfc.h                  |  5 ++-
 3 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 7d4c8eb775a5..89b0db9801b0 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -34,7 +34,7 @@ Optional properties:
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
   - Required properties:
-    - compatible : "atmel,sama5d3-nfc".
+    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
     - reg : should specify the address and size used for NFC command registers,
             NFC registers and NFC Sram. NFC Sram address and size can be absent
             if don't want to use it.
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 9d71f9e6a8de..e5d7e7e63f49 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -67,6 +67,10 @@ struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
 };
 
+struct atmel_nand_nfc_priv {
+	uint32_t rb_edge;
+};
+
 /* oob layout for large page size
  * bad block info is on bytes 0 and 1
  * the bytes have to be consecutives to avoid
@@ -111,6 +115,7 @@ struct atmel_nfc {
 	/* Point to the sram bank which include readed data via NFC */
 	void			*data_in_sram;
 	bool			will_write_sram;
+	uint32_t		rb_edge;
 };
 static struct atmel_nfc	nand_nfc;
 
@@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
 		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
 		ret = IRQ_HANDLED;
 	}
-	if (pending & NFC_SR_RB_EDGE) {
+	if (pending & host->nfc->rb_edge) {
 		complete(&host->nfc->comp_ready);
-		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
+		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->rb_edge);
 		ret = IRQ_HANDLED;
 	}
 	if (pending & NFC_SR_CMD_DONE) {
@@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		init_completion(&host->nfc->comp_xfer_done);
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->rb_edge)
 		init_completion(&host->nfc->comp_ready);
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		comp[index++] = &host->nfc->comp_xfer_done;
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->rb_edge)
 		comp[index++] = &host->nfc->comp_ready;
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
 		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
 				mask & status);
 
-	return status & NFC_SR_RB_EDGE;
+	return status & host->nfc->rb_edge;
 }
 
 static void nfc_select_chip(struct mtd_info *mtd, int chip)
@@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 		}
 		/* fall through */
 	default:
-		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
-		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
+		nfc_prepare_interrupt(host, host->nfc->rb_edge);
+		nfc_wait_interrupt(host, host->nfc->rb_edge);
 	}
 }
 
@@ -2318,9 +2323,12 @@ static const struct of_device_id atmel_nand_dt_ids[] = {
 
 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
 
+static const struct of_device_id atmel_nand_nfc_match[];
+
 static int atmel_nand_nfc_probe(struct platform_device *pdev)
 {
 	struct atmel_nfc *nfc = &nand_nfc;
+	const struct atmel_nand_nfc_priv *priv;
 	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
 	int ret;
 
@@ -2352,6 +2360,12 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
 		}
 	}
 
+	priv = of_match_device(atmel_nand_nfc_match, &pdev->dev)->data;
+	if (NULL == priv)
+		return -ENODEV;
+
+	nfc->rb_edge = priv->rb_edge;
+
 	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
 	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
 
@@ -2380,8 +2394,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static struct atmel_nand_nfc_priv sama5d3_nfc_priv = {
+	.rb_edge = NFC_SR_RB_EDGE0,
+};
+
+static struct atmel_nand_nfc_priv sama5d4_nfc_priv = {
+	.rb_edge = NFC_SR_RB_EDGE3,
+};
+
 static const struct of_device_id atmel_nand_nfc_match[] = {
-	{ .compatible = "atmel,sama5d3-nfc" },
+	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_priv },
+	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_priv },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
index 4d5d26221a7e..2cd9c57b1e53 100644
--- a/drivers/mtd/nand/atmel_nand_nfc.h
+++ b/drivers/mtd/nand/atmel_nand_nfc.h
@@ -42,7 +42,10 @@
 #define		NFC_SR_UNDEF		(1 << 21)
 #define		NFC_SR_AWB		(1 << 22)
 #define		NFC_SR_ASE		(1 << 23)
-#define		NFC_SR_RB_EDGE		(1 << 24)
+#define		NFC_SR_RB_EDGE0		(1 << 24)
+#define		NFC_SR_RB_EDGE1		(1 << 25)
+#define		NFC_SR_RB_EDGE2		(1 << 26)
+#define		NFC_SR_RB_EDGE3		(1 << 27)
 
 #define ATMEL_HSMC_NFC_IER	0x0c
 #define ATMEL_HSMC_NFC_IDR	0x10
-- 
2.5.0

[RFC PATCH 3/4] mtd: atmel_nand: Support 32-bit ECC strength

[Romain Izard]

Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
controller that can correct 32 bits in each sector. This controller is
not 100% compatible with the previous revision that corrected a maximum
of 24 bits by sector, as some register addresses overlap.

Using information from the device tree, we can configure the driver to
work with both versions.

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/mtd/atmel-nand.txt         | 10 +++--
 drivers/mtd/nand/atmel_nand.c                      | 43 +++++++++++++++++++---
 drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++++-
 3 files changed, 52 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 89b0db9801b0..ef0db8e2a0fd 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,7 +1,10 @@
 Atmel NAND flash
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand".
+- compatible: The possible values are:
+	"atmel,at91rm9200-nand"
+	"atmel,sama5d2-nand"
+	"atmel,sama5d4-nand"
 - reg : should specify localbus address and size used for the chip,
 	and hardware ECC controller if available.
 	If the hardware ECC is PMECC, it should contain address and size for
@@ -22,9 +25,10 @@ Optional properties:
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
-  Only supported by at91sam9x5 or later sam9 product.
+  Supported by AT91SAM9x5 or later SAM9 chips, and SAMA5 chips.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
-  Controller. Supported values are: 2, 4, 8, 12, 24.
+  Controller. Supported values are: 2, 4, 8, 12, 24. SAMA5D2 also supports
+  32.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
   are: 512, 1024.
 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index e5d7e7e63f49..cd55d54a9a7d 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -65,6 +65,7 @@ module_param(on_flash_bbt, int, 0);
 
 struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
+	uint8_t pmecc_max_correction;
 };
 
 struct atmel_nand_nfc_priv {
@@ -146,6 +147,7 @@ struct atmel_nand_host {
 	int			pmecc_cw_len;	/* Length of codeword */
 
 	void __iomem		*pmerrloc_base;
+	void __iomem		*pmerrloc_el_base;
 	void __iomem		*pmecc_rom_base;
 
 	/* lookup table for alpha_to and index_of */
@@ -472,6 +474,7 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  *                8-bits                13-bytes                 14-bytes
  *               12-bits                20-bytes                 21-bytes
  *               24-bits                39-bytes                 42-bytes
+ *               32-bits                52-bytes                 56-bytes
  */
 static int pmecc_get_ecc_bytes(int cap, int sector_size)
 {
@@ -817,7 +820,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 	sector_size = host->pmecc_sector_size;
 
 	while (err_nbr) {
-		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
+		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
 		byte_pos = tmp / 8;
 		bit_pos  = tmp % 8;
 
@@ -1081,6 +1084,9 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 
 	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
 	if (host->pmecc_corr_cap == 0) {
+		if (*cap > host->caps->pmecc_max_correction)
+			return -EINVAL;
+
 		/* use the most fitable ecc bits (the near bigger one ) */
 		if (*cap <= 2)
 			host->pmecc_corr_cap = 2;
@@ -1092,6 +1098,8 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 			host->pmecc_corr_cap = 12;
 		else if (*cap <= 24)
 			host->pmecc_corr_cap = 24;
+		else if (*cap <= 32)
+			host->pmecc_corr_cap = 32;
 		else
 			return -EINVAL;
 	}
@@ -1208,6 +1216,8 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		err_no = PTR_ERR(host->pmerrloc_base);
 		goto err;
 	}
+	host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
+		(host->caps->pmecc_max_correction + 1) * 4;
 
 	if (!host->has_no_lookup_table) {
 		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
@@ -1550,10 +1560,16 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * them from NAND ONFI parameters.
 	 */
 	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
-		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
-				(val != 24)) {
+		if (val > host->caps->pmecc_max_correction) {
+			dev_err(host->dev,
+				"Required ECC strength too high: %u max %u\n",
+				val, host->caps->pmecc_max_correction);
+			return -EINVAL;
+		}
+		if ((val != 2)  && (val != 4)  && (val != 8) &&
+		    (val != 12) && (val != 24) && (val != 32)) {
 			dev_err(host->dev,
-				"Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
+				"Required ECC strength not supported: %u\n",
 				val);
 			return -EINVAL;
 		}
@@ -1563,7 +1579,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
 		if ((val != 512) && (val != 1024)) {
 			dev_err(host->dev,
-				"Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
+				"Required ECC sector size not supported: %u\n",
 				val);
 			return -EINVAL;
 		}
@@ -2307,17 +2323,34 @@ static int atmel_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+/*
+ * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
+ * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
+ * devices from the SAM9 family that have those.
+ */
 static struct atmel_nand_caps at91rm9200_caps = {
 	.pmecc_correct_erase_page = false,
+	.pmecc_max_correction = 24,
 };
 
 static struct atmel_nand_caps sama5d4_caps = {
 	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 24,
+};
+
+/*
+ * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
+ * as the increased correction strength requires more registers.
+ */
+static struct atmel_nand_caps sama5d2_caps = {
+	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 32,
 };
 
 static const struct of_device_id atmel_nand_dt_ids[] = {
 	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
 	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
+	{ .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index 668e7358f19b..b1d436d8bb7a 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -43,6 +43,7 @@
 #define		PMECC_CFG_BCH_ERR8		(2 << 0)
 #define		PMECC_CFG_BCH_ERR12		(3 << 0)
 #define		PMECC_CFG_BCH_ERR24		(4 << 0)
+#define		PMECC_CFG_BCH_ERR25		(5 << 0)
 
 #define		PMECC_CFG_SECTOR512		(0 << 4)
 #define		PMECC_CFG_SECTOR1024		(1 << 4)
@@ -108,7 +109,11 @@
 #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
 #define		PMERRLOC_CALC_DONE		(1 << 0)
 #define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
-#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
+
+/*
+ * The ATMEL_PMERRLOC_ELx register location depends from the number of
+ * bits corrected by the PMECC controller. Do not use it.
+ */
 
 /* Register access macros for PMECC */
 #define pmecc_readl_relaxed(addr, reg) \
@@ -136,7 +141,7 @@
 	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
 
 #define pmerrloc_readl_el_relaxed(addr, n) \
-	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
+	readl_relaxed((addr) + ((n) * 4))
 
 /* Galois field dimension */
 #define PMECC_GF_DIMENSION_13			13
-- 
2.5.0

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[RFC PATCH 3/4] mtd: atmel_nand: Support 32-bit ECC strength

[Romain Izard]

Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
controller that can correct 32 bits in each sector. This controller is
not 100% compatible with the previous revision that corrected a maximum
of 24 bits by sector, as some register addresses overlap.

Using information from the device tree, we can configure the driver to
work with both versions.

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt         | 10 +++--
 drivers/mtd/nand/atmel_nand.c                      | 43 +++++++++++++++++++---
 drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++++-
 3 files changed, 52 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 89b0db9801b0..ef0db8e2a0fd 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,7 +1,10 @@
 Atmel NAND flash
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand".
+- compatible: The possible values are:
+	"atmel,at91rm9200-nand"
+	"atmel,sama5d2-nand"
+	"atmel,sama5d4-nand"
 - reg : should specify localbus address and size used for the chip,
 	and hardware ECC controller if available.
 	If the hardware ECC is PMECC, it should contain address and size for
@@ -22,9 +25,10 @@ Optional properties:
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
-  Only supported by at91sam9x5 or later sam9 product.
+  Supported by AT91SAM9x5 or later SAM9 chips, and SAMA5 chips.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
-  Controller. Supported values are: 2, 4, 8, 12, 24.
+  Controller. Supported values are: 2, 4, 8, 12, 24. SAMA5D2 also supports
+  32.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
   are: 512, 1024.
 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index e5d7e7e63f49..cd55d54a9a7d 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -65,6 +65,7 @@ module_param(on_flash_bbt, int, 0);
 
 struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
+	uint8_t pmecc_max_correction;
 };
 
 struct atmel_nand_nfc_priv {
@@ -146,6 +147,7 @@ struct atmel_nand_host {
 	int			pmecc_cw_len;	/* Length of codeword */
 
 	void __iomem		*pmerrloc_base;
+	void __iomem		*pmerrloc_el_base;
 	void __iomem		*pmecc_rom_base;
 
 	/* lookup table for alpha_to and index_of */
@@ -472,6 +474,7 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  *                8-bits                13-bytes                 14-bytes
  *               12-bits                20-bytes                 21-bytes
  *               24-bits                39-bytes                 42-bytes
+ *               32-bits                52-bytes                 56-bytes
  */
 static int pmecc_get_ecc_bytes(int cap, int sector_size)
 {
@@ -817,7 +820,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 	sector_size = host->pmecc_sector_size;
 
 	while (err_nbr) {
-		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
+		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
 		byte_pos = tmp / 8;
 		bit_pos  = tmp % 8;
 
@@ -1081,6 +1084,9 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 
 	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
 	if (host->pmecc_corr_cap == 0) {
+		if (*cap > host->caps->pmecc_max_correction)
+			return -EINVAL;
+
 		/* use the most fitable ecc bits (the near bigger one ) */
 		if (*cap <= 2)
 			host->pmecc_corr_cap = 2;
@@ -1092,6 +1098,8 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 			host->pmecc_corr_cap = 12;
 		else if (*cap <= 24)
 			host->pmecc_corr_cap = 24;
+		else if (*cap <= 32)
+			host->pmecc_corr_cap = 32;
 		else
 			return -EINVAL;
 	}
@@ -1208,6 +1216,8 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		err_no = PTR_ERR(host->pmerrloc_base);
 		goto err;
 	}
+	host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
+		(host->caps->pmecc_max_correction + 1) * 4;
 
 	if (!host->has_no_lookup_table) {
 		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
@@ -1550,10 +1560,16 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * them from NAND ONFI parameters.
 	 */
 	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
-		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
-				(val != 24)) {
+		if (val > host->caps->pmecc_max_correction) {
+			dev_err(host->dev,
+				"Required ECC strength too high: %u max %u\n",
+				val, host->caps->pmecc_max_correction);
+			return -EINVAL;
+		}
+		if ((val != 2)  && (val != 4)  && (val != 8) &&
+		    (val != 12) && (val != 24) && (val != 32)) {
 			dev_err(host->dev,
-				"Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
+				"Required ECC strength not supported: %u\n",
 				val);
 			return -EINVAL;
 		}
@@ -1563,7 +1579,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
 		if ((val != 512) && (val != 1024)) {
 			dev_err(host->dev,
-				"Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
+				"Required ECC sector size not supported: %u\n",
 				val);
 			return -EINVAL;
 		}
@@ -2307,17 +2323,34 @@ static int atmel_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+/*
+ * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
+ * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
+ * devices from the SAM9 family that have those.
+ */
 static struct atmel_nand_caps at91rm9200_caps = {
 	.pmecc_correct_erase_page = false,
+	.pmecc_max_correction = 24,
 };
 
 static struct atmel_nand_caps sama5d4_caps = {
 	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 24,
+};
+
+/*
+ * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
+ * as the increased correction strength requires more registers.
+ */
+static struct atmel_nand_caps sama5d2_caps = {
+	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 32,
 };
 
 static const struct of_device_id atmel_nand_dt_ids[] = {
 	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
 	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
+	{ .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index 668e7358f19b..b1d436d8bb7a 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -43,6 +43,7 @@
 #define		PMECC_CFG_BCH_ERR8		(2 << 0)
 #define		PMECC_CFG_BCH_ERR12		(3 << 0)
 #define		PMECC_CFG_BCH_ERR24		(4 << 0)
+#define		PMECC_CFG_BCH_ERR25		(5 << 0)
 
 #define		PMECC_CFG_SECTOR512		(0 << 4)
 #define		PMECC_CFG_SECTOR1024		(1 << 4)
@@ -108,7 +109,11 @@
 #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
 #define		PMERRLOC_CALC_DONE		(1 << 0)
 #define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
-#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
+
+/*
+ * The ATMEL_PMERRLOC_ELx register location depends from the number of
+ * bits corrected by the PMECC controller. Do not use it.
+ */
 
 /* Register access macros for PMECC */
 #define pmecc_readl_relaxed(addr, reg) \
@@ -136,7 +141,7 @@
 	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
 
 #define pmerrloc_readl_el_relaxed(addr, n) \
-	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
+	readl_relaxed((addr) + ((n) * 4))
 
 /* Galois field dimension */
 #define PMECC_GF_DIMENSION_13			13
-- 
2.5.0

[RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Romain Izard]

Both nodes are required to access NAND Flash memory. Additional
settings will be necessary at the board level to use it.

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sama5d2.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index aee571448342..80420177ec1a 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -265,6 +265,44 @@
 			cache-level = <2>;
 		};
 
+		nand0: nand@80000000 {
+			compatible = "atmel,sama5d2-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = < /* EBI CS3 */
+				0x80000000 0x08000000
+				/* SMC PMECC regs */
+				0xf8014070 0x00000490
+				/* SMC PMECC Error Location regs */
+				0xf8014500 0x00000200
+				/* ROM Galois tables */
+				0x00040000 0x00018000
+				>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			atmel,nand-has-dma;
+			atmel,has-pmecc;
+			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
+			status = "disabled";
+
+			nfc@90000000 {
+				compatible = "atmel,sama5d4-nfc";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = < /* NFC Command Registers */
+					0xC0000000 0x08000000
+					/* NFC HSMC regs */
+					0xf8014000 0x00000070
+					/* NFC SRAM banks */
+					0x00100000 0x00100000
+					>;
+				clocks = <&hsmc_clk>;
+				atmel,write-by-sram;
+			};
+		};
+
 		sdmmc0: sdio-host@a0000000 {
 			compatible = "atmel,sama5d2-sdhci";
 			reg = <0xa0000000 0x300>;
-- 
2.5.0

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[RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Romain Izard]

Both nodes are required to access NAND Flash memory. Additional
settings will be necessary at the board level to use it.

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
 arch/arm/boot/dts/sama5d2.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index aee571448342..80420177ec1a 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -265,6 +265,44 @@
 			cache-level = <2>;
 		};
 
+		nand0: nand@80000000 {
+			compatible = "atmel,sama5d2-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = < /* EBI CS3 */
+				0x80000000 0x08000000
+				/* SMC PMECC regs */
+				0xf8014070 0x00000490
+				/* SMC PMECC Error Location regs */
+				0xf8014500 0x00000200
+				/* ROM Galois tables */
+				0x00040000 0x00018000
+				>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			atmel,nand-has-dma;
+			atmel,has-pmecc;
+			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
+			status = "disabled";
+
+			nfc@90000000 {
+				compatible = "atmel,sama5d4-nfc";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = < /* NFC Command Registers */
+					0xC0000000 0x08000000
+					/* NFC HSMC regs */
+					0xf8014000 0x00000070
+					/* NFC SRAM banks */
+					0x00100000 0x00100000
+					>;
+				clocks = <&hsmc_clk>;
+				atmel,write-by-sram;
+			};
+		};
+
 		sdmmc0: sdio-host@a0000000 {
 			compatible = "atmel,sama5d2-sdhci";
 			reg = <0xa0000000 0x300>;
-- 
2.5.0

Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 12/01/2016 15:33, Romain Izard a écrit :
> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
> 
> Applies on the Atmel Linux 4.1 branch for now, but only the dtsi file
> differs from the mainline.
> 
> Compile tested for all SAMA5 chips for now, and tested on SAMA5D3xek as
> there is no existing SAMA5D2 board with NAND Flash memory (yet).

Hi Romain,

The maintainers for this driver changed very recently, so you'll have to
includes these names to your CC list:

M:      Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
M:      Josh Wu <rainyfeeling-1ViLX0X+lBJBDgjK7y7TUQ@public.gmane.org>

I also think that Wenyou did some work regarding this support. So you'll
have to coordinat together.

Thanks, bye,

> Romain Izard (4):
>   mtd: atmel_nand: Do not warn on bitflips
>   mtd: atmel_nand: Support variable RB_EDGE interrupts
>   mtd: atmel_nand: Support 32-bit ECC strength
>   ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 12 ++-
>  arch/arm/boot/dts/sama5d2.dtsi                     | 38 ++++++++++
>  drivers/mtd/nand/atmel_nand.c                      | 86 ++++++++++++++++++----
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  5 +-
>  5 files changed, 128 insertions(+), 22 deletions(-)
> 


-- 
Nicolas Ferre
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Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 12/01/2016 15:33, Romain Izard a écrit :
> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
> 
> Applies on the Atmel Linux 4.1 branch for now, but only the dtsi file
> differs from the mainline.
> 
> Compile tested for all SAMA5 chips for now, and tested on SAMA5D3xek as
> there is no existing SAMA5D2 board with NAND Flash memory (yet).

Hi Romain,

The maintainers for this driver changed very recently, so you'll have to
includes these names to your CC list:

M:      Wenyou Yang <wenyou.yang@atmel.com>
M:      Josh Wu <rainyfeeling@outlook.com>

I also think that Wenyou did some work regarding this support. So you'll
have to coordinat together.

Thanks, bye,

> Romain Izard (4):
>   mtd: atmel_nand: Do not warn on bitflips
>   mtd: atmel_nand: Support variable RB_EDGE interrupts
>   mtd: atmel_nand: Support 32-bit ECC strength
>   ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 12 ++-
>  arch/arm/boot/dts/sama5d2.dtsi                     | 38 ++++++++++
>  drivers/mtd/nand/atmel_nand.c                      | 86 ++++++++++++++++++----
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  5 +-
>  5 files changed, 128 insertions(+), 22 deletions(-)
> 


-- 
Nicolas Ferre

Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

Hi Nicolas,

2016-01-12 16:45 GMT+01:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>
> The maintainers for this driver changed very recently, so you'll have to
> includes these names to your CC list:
>
> M:      Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> M:      Josh Wu <rainyfeeling-1ViLX0X+lBJBDgjK7y7TUQ@public.gmane.org>

Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's atmel
address now bounces, and it is still referenced there.

>
> I also think that Wenyou did some work regarding this support. So you'll
> have to coordinat together.

Is it possible to know what are the developments in progress regarding SAMA5D2
drivers? The github repository does not expose any working trees, and only the
current "stable" trees are visible.

Best regards,
-- 
Romain Izard
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

Hi Nicolas,

2016-01-12 16:45 GMT+01:00 Nicolas Ferre <nicolas.ferre@atmel.com>:
>
> The maintainers for this driver changed very recently, so you'll have to
> includes these names to your CC list:
>
> M:      Wenyou Yang <wenyou.yang@atmel.com>
> M:      Josh Wu <rainyfeeling@outlook.com>

Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's atmel
address now bounces, and it is still referenced there.

>
> I also think that Wenyou did some work regarding this support. So you'll
> have to coordinat together.

Is it possible to know what are the developments in progress regarding SAMA5D2
drivers? The github repository does not expose any working trees, and only the
current "stable" trees are visible.

Best regards,
-- 
Romain Izard

Re: [RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips

[Yang, Wenyou]

Hi Romain,

On 2016/1/12 22:33, Romain Izard wrote:
> When using multi-bit ECC, it is normal for the NAND Flash driver to
> correct bit errors during the life of the product. Those errors will
> only be cleared once a threshold has been reached, and corrections can
> occur regularly before this.
>
> Use only dev_dbg and not dev_info to report the bitflips, to keep the
> system log clean when everything works correctly.
>
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

Acked-by:  Wenyou Yang <wenyou.yang@atmel.com>

> ---
>   drivers/mtd/nand/atmel_nand.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 46010bd895b1..9d71f9e6a8de 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -824,7 +824,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
>   			*(buf + byte_pos) ^= (1 << bit_pos);
>   
>   			pos = sector_num * host->pmecc_sector_size + byte_pos;
> -			dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
>   				pos, bit_pos, err_byte, *(buf + byte_pos));
>   		} else {
>   			/* Bit flip in OOB area */
> @@ -834,7 +834,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
>   			ecc[tmp] ^= (1 << bit_pos);
>   
>   			pos = tmp + nand_chip->ecc.layout->eccpos[0];
> -			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
>   				pos, bit_pos, err_byte, ecc[tmp]);
>   		}
>   

Best Regards,
Wenyou Yang

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips

[Yang, Wenyou]

Hi Romain,

On 2016/1/12 22:33, Romain Izard wrote:
> When using multi-bit ECC, it is normal for the NAND Flash driver to
> correct bit errors during the life of the product. Those errors will
> only be cleared once a threshold has been reached, and corrections can
> occur regularly before this.
>
> Use only dev_dbg and not dev_info to report the bitflips, to keep the
> system log clean when everything works correctly.
>
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

Acked-by:  Wenyou Yang <wenyou.yang@atmel.com>

> ---
>   drivers/mtd/nand/atmel_nand.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 46010bd895b1..9d71f9e6a8de 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -824,7 +824,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
>   			*(buf + byte_pos) ^= (1 << bit_pos);
>   
>   			pos = sector_num * host->pmecc_sector_size + byte_pos;
> -			dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
>   				pos, bit_pos, err_byte, *(buf + byte_pos));
>   		} else {
>   			/* Bit flip in OOB area */
> @@ -834,7 +834,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
>   			ecc[tmp] ^= (1 << bit_pos);
>   
>   			pos = tmp + nand_chip->ecc.layout->eccpos[0];
> -			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
>   				pos, bit_pos, err_byte, ecc[tmp]);
>   		}
>   

Best Regards,
Wenyou Yang

RE: [RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips
> 
> When using multi-bit ECC, it is normal for the NAND Flash driver to correct bit
> errors during the life of the product. Those errors will only be cleared once a
> threshold has been reached, and corrections can occur regularly before this.
> 
> Use only dev_dbg and not dev_info to report the bitflips, to keep the system log
> clean when everything works correctly.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

Acked-by Wenyou Yang <wenyou.yang@atmel.com>

> ---
>  drivers/mtd/nand/atmel_nand.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index
> 46010bd895b1..9d71f9e6a8de 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -824,7 +824,7 @@ static void pmecc_correct_data(struct mtd_info *mtd,
> uint8_t *buf, uint8_t *ecc,
>  			*(buf + byte_pos) ^= (1 << bit_pos);
> 
>  			pos = sector_num * host->pmecc_sector_size + byte_pos;
> -			dev_info(host->dev, "Bit flip in data area, byte_pos: %d,
> bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d,
> bit_pos:
> +%d, 0x%02x -> 0x%02x\n",
>  				pos, bit_pos, err_byte, *(buf + byte_pos));
>  		} else {
>  			/* Bit flip in OOB area */
> @@ -834,7 +834,7 @@ static void pmecc_correct_data(struct mtd_info *mtd,
> uint8_t *buf, uint8_t *ecc,
>  			ecc[tmp] ^= (1 << bit_pos);
> 
>  			pos = tmp + nand_chip->ecc.layout->eccpos[0];
> -			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d,
> bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d,
> bit_pos: %d,
> +0x%02x -> 0x%02x\n",
>  				pos, bit_pos, err_byte, ecc[tmp]);
>  		}
> 
> --
> 2.5.0
> 
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/


Best Regards,
Wenyou Yang
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

RE: [RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 1/4] mtd: atmel_nand: Do not warn on bitflips
> 
> When using multi-bit ECC, it is normal for the NAND Flash driver to correct bit
> errors during the life of the product. Those errors will only be cleared once a
> threshold has been reached, and corrections can occur regularly before this.
> 
> Use only dev_dbg and not dev_info to report the bitflips, to keep the system log
> clean when everything works correctly.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

Acked-by Wenyou Yang <wenyou.yang@atmel.com>

> ---
>  drivers/mtd/nand/atmel_nand.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index
> 46010bd895b1..9d71f9e6a8de 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -824,7 +824,7 @@ static void pmecc_correct_data(struct mtd_info *mtd,
> uint8_t *buf, uint8_t *ecc,
>  			*(buf + byte_pos) ^= (1 << bit_pos);
> 
>  			pos = sector_num * host->pmecc_sector_size + byte_pos;
> -			dev_info(host->dev, "Bit flip in data area, byte_pos: %d,
> bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d,
> bit_pos:
> +%d, 0x%02x -> 0x%02x\n",
>  				pos, bit_pos, err_byte, *(buf + byte_pos));
>  		} else {
>  			/* Bit flip in OOB area */
> @@ -834,7 +834,7 @@ static void pmecc_correct_data(struct mtd_info *mtd,
> uint8_t *buf, uint8_t *ecc,
>  			ecc[tmp] ^= (1 << bit_pos);
> 
>  			pos = tmp + nand_chip->ecc.layout->eccpos[0];
> -			dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d,
> bit_pos: %d, 0x%02x -> 0x%02x\n",
> +			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d,
> bit_pos: %d,
> +0x%02x -> 0x%02x\n",
>  				pos, bit_pos, err_byte, ecc[tmp]);
>  		}
> 
> --
> 2.5.0
> 
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/


Best Regards,
Wenyou Yang

RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Yang, Wenyou]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 2498 bytes --]



> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016Äê1ÔÂ12ÈÕ 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
> Both nodes are required to access NAND Flash memory. Additional settings will
> be necessary at the board level to use it.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> ---
>  arch/arm/boot/dts/sama5d2.dtsi | 38
> ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index
> aee571448342..80420177ec1a 100644
> --- a/arch/arm/boot/dts/sama5d2.dtsi
> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> @@ -265,6 +265,44 @@
>  			cache-level = <2>;
>  		};
> 
> +		nand0: nand@80000000 {
> +			compatible = "atmel,sama5d2-nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			reg = < /* EBI CS3 */
> +				0x80000000 0x08000000
> +				/* SMC PMECC regs */
> +				0xf8014070 0x00000490
> +				/* SMC PMECC Error Location regs */
> +				0xf8014500 0x00000200
> +				/* ROM Galois tables */
> +				0x00040000 0x00018000

As there is no PMECC lookup table in ROM exported, remove this line.

> +				>;
> +			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
> +			atmel,nand-addr-offset = <21>;
> +			atmel,nand-cmd-offset = <22>;
> +			atmel,nand-has-dma;
> +			atmel,has-pmecc;
> +			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;

Ditto, remove this line.

> +			status = "disabled";
> +
> +			nfc@90000000 {
> +				compatible = "atmel,sama5d4-nfc";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = < /* NFC Command Registers */
> +					0xC0000000 0x08000000
> +					/* NFC HSMC regs */
> +					0xf8014000 0x00000070
> +					/* NFC SRAM banks */
> +					0x00100000 0x00100000
> +					>;
> +				clocks = <&hsmc_clk>;
> +				atmel,write-by-sram;
> +			};
> +		};
> +
>  		sdmmc0: sdio-host@a0000000 {
>  			compatible = "atmel,sama5d2-sdhci";
>  			reg = <0xa0000000 0x300>;
> --
> 2.5.0
> 


Best Regards,
Wenyou Yang


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RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
> Both nodes are required to access NAND Flash memory. Additional settings will
> be necessary at the board level to use it.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> ---
>  arch/arm/boot/dts/sama5d2.dtsi | 38
> ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index
> aee571448342..80420177ec1a 100644
> --- a/arch/arm/boot/dts/sama5d2.dtsi
> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> @@ -265,6 +265,44 @@
>  			cache-level = <2>;
>  		};
> 
> +		nand0: nand@80000000 {
> +			compatible = "atmel,sama5d2-nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			reg = < /* EBI CS3 */
> +				0x80000000 0x08000000
> +				/* SMC PMECC regs */
> +				0xf8014070 0x00000490
> +				/* SMC PMECC Error Location regs */
> +				0xf8014500 0x00000200
> +				/* ROM Galois tables */
> +				0x00040000 0x00018000

As there is no PMECC lookup table in ROM exported, remove this line.

> +				>;
> +			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
> +			atmel,nand-addr-offset = <21>;
> +			atmel,nand-cmd-offset = <22>;
> +			atmel,nand-has-dma;
> +			atmel,has-pmecc;
> +			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;

Ditto, remove this line.

> +			status = "disabled";
> +
> +			nfc@90000000 {
> +				compatible = "atmel,sama5d4-nfc";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = < /* NFC Command Registers */
> +					0xC0000000 0x08000000
> +					/* NFC HSMC regs */
> +					0xf8014000 0x00000070
> +					/* NFC SRAM banks */
> +					0x00100000 0x00100000
> +					>;
> +				clocks = <&hsmc_clk>;
> +				atmel,write-by-sram;
> +			};
> +		};
> +
>  		sdmmc0: sdio-host@a0000000 {
>  			compatible = "atmel,sama5d2-sdhci";
>  			reg = <0xa0000000 0x300>;
> --
> 2.5.0
> 


Best Regards,
Wenyou Yang

RE: [RFC PATCH 3/4] mtd: atmel_nand: Support 32-bit ECC strength

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 3/4] mtd: atmel_nand: Support 32-bit ECC strength
> 
> Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
> controller that can correct 32 bits in each sector. This controller is not 100%
> compatible with the previous revision that corrected a maximum of 24 bits by
> sector, as some register addresses overlap.
> 
> Using information from the device tree, we can configure the driver to work with
> both versions.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

First this patch contains one more topic, 32-ECC, error-location. it should be split.


> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 10 +++--
>  drivers/mtd/nand/atmel_nand.c                      | 43 +++++++++++++++++++---
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++++-
>  3 files changed, 52 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 89b0db9801b0..ef0db8e2a0fd 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -1,7 +1,10 @@
>  Atmel NAND flash
> 
>  Required properties:
> -- compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand".
> +- compatible: The possible values are:
> +	"atmel,at91rm9200-nand"
> +	"atmel,sama5d2-nand"
> +	"atmel,sama5d4-nand"
>  - reg : should specify localbus address and size used for the chip,
>  	and hardware ECC controller if available.
>  	If the hardware ECC is PMECC, it should contain address and size for
> @@ -22,9 +25,10 @@ Optional properties:
>    Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
>    "soft_bch".
>  - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
> -  Only supported by at91sam9x5 or later sam9 product.
> +  Supported by AT91SAM9x5 or later SAM9 chips, and SAMA5 chips.
>  - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
> -  Controller. Supported values are: 2, 4, 8, 12, 24.
> +  Controller. Supported values are: 2, 4, 8, 12, 24. SAMA5D2 also
> + supports  32.
>  - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
>    are: 512, 1024.
>  - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index
> e5d7e7e63f49..cd55d54a9a7d 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -65,6 +65,7 @@ module_param(on_flash_bbt, int, 0);
> 
>  struct atmel_nand_caps {
>  	bool pmecc_correct_erase_page;
> +	uint8_t pmecc_max_correction;
>  };
> 
>  struct atmel_nand_nfc_priv {
> @@ -146,6 +147,7 @@ struct atmel_nand_host {
>  	int			pmecc_cw_len;	/* Length of codeword */
> 
>  	void __iomem		*pmerrloc_base;
> +	void __iomem		*pmerrloc_el_base;
>  	void __iomem		*pmecc_rom_base;
> 
>  	/* lookup table for alpha_to and index_of */ @@ -472,6 +474,7 @@ static
> void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
>   *                8-bits                13-bytes                 14-bytes
>   *               12-bits                20-bytes                 21-bytes
>   *               24-bits                39-bytes                 42-bytes
> + *               32-bits                52-bytes                 56-bytes
>   */

It seems, something missed after
         case 24:
                 val = PMECC_CFG_BCH_ERR24;
                 break;

such as,

         case 32:
                 val = PMECC_CFG_BCH_ERR32;
                 break



>  static int pmecc_get_ecc_bytes(int cap, int sector_size)  { @@ -817,7 +820,7
> @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t
> *ecc,
>  	sector_size = host->pmecc_sector_size;
> 
>  	while (err_nbr) {
> -		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
> +		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
>  		byte_pos = tmp / 8;
>  		bit_pos  = tmp % 8;
> 
> @@ -1081,6 +1084,9 @@ static int pmecc_choose_ecc(struct atmel_nand_host
> *host,
> 
>  	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
>  	if (host->pmecc_corr_cap == 0) {
> +		if (*cap > host->caps->pmecc_max_correction)
> +			return -EINVAL;
> +
>  		/* use the most fitable ecc bits (the near bigger one ) */
>  		if (*cap <= 2)
>  			host->pmecc_corr_cap = 2;
> @@ -1092,6 +1098,8 @@ static int pmecc_choose_ecc(struct atmel_nand_host
> *host,
>  			host->pmecc_corr_cap = 12;
>  		else if (*cap <= 24)
>  			host->pmecc_corr_cap = 24;
> +		else if (*cap <= 32)
> +			host->pmecc_corr_cap = 32;
>  		else
>  			return -EINVAL;
>  	}
> @@ -1208,6 +1216,8 @@ static int atmel_pmecc_nand_init_params(struct
> platform_device *pdev,
>  		err_no = PTR_ERR(host->pmerrloc_base);
>  		goto err;
>  	}
> +	host->pmerrloc_el_base = host->pmerrloc_base +
> ATMEL_PMERRLOC_SIGMAx +
> +		(host->caps->pmecc_max_correction + 1) * 4;
> 
>  	if (!host->has_no_lookup_table) {
>  		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM,
> 3); @@ -1550,10 +1560,16 @@ static int atmel_of_init_port(struct
> atmel_nand_host *host,
>  	 * them from NAND ONFI parameters.
>  	 */
>  	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
> -		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
> -				(val != 24)) {
> +		if (val > host->caps->pmecc_max_correction) {
> +			dev_err(host->dev,
> +				"Required ECC strength too high: %u max %u\n",
> +				val, host->caps->pmecc_max_correction);
> +			return -EINVAL;
> +		}
> +		if ((val != 2)  && (val != 4)  && (val != 8) &&
> +		    (val != 12) && (val != 24) && (val != 32)) {
>  			dev_err(host->dev,
> -				"Unsupported PMECC correction capability: %d;
> should be 2, 4, 8, 12 or 24\n",
> +				"Required ECC strength not supported: %u\n",
>  				val);
>  			return -EINVAL;
>  		}
> @@ -1563,7 +1579,7 @@ static int atmel_of_init_port(struct atmel_nand_host
> *host,
>  	if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
>  		if ((val != 512) && (val != 1024)) {
>  			dev_err(host->dev,
> -				"Unsupported PMECC sector size: %d; should be
> 512 or 1024 bytes\n",
> +				"Required ECC sector size not supported: %u\n",
>  				val);
>  			return -EINVAL;
>  		}
> @@ -2307,17 +2323,34 @@ static int atmel_nand_remove(struct platform_device
> *pdev)
>  	return 0;
>  }
> 
> +/*
> + * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
> + * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
> + * devices from the SAM9 family that have those.
> + */
>  static struct atmel_nand_caps at91rm9200_caps = {
>  	.pmecc_correct_erase_page = false,
> +	.pmecc_max_correction = 24,
>  };
> 
>  static struct atmel_nand_caps sama5d4_caps = {
>  	.pmecc_correct_erase_page = true,
> +	.pmecc_max_correction = 24,
> +};
> +
> +/*
> + * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
> + * as the increased correction strength requires more registers.
> + */
> +static struct atmel_nand_caps sama5d2_caps = {
> +	.pmecc_correct_erase_page = true,
> +	.pmecc_max_correction = 32,
>  };
> 
>  static const struct of_device_id atmel_nand_dt_ids[] = {
>  	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
>  	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
> +	{ .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
>  	{ /* sentinel */ }
>  };
> 
> diff --git a/drivers/mtd/nand/atmel_nand_ecc.h
> b/drivers/mtd/nand/atmel_nand_ecc.h
> index 668e7358f19b..b1d436d8bb7a 100644
> --- a/drivers/mtd/nand/atmel_nand_ecc.h
> +++ b/drivers/mtd/nand/atmel_nand_ecc.h
> @@ -43,6 +43,7 @@
>  #define		PMECC_CFG_BCH_ERR8		(2 << 0)
>  #define		PMECC_CFG_BCH_ERR12		(3 << 0)
>  #define		PMECC_CFG_BCH_ERR24		(4 << 0)
> +#define		PMECC_CFG_BCH_ERR25		(5 << 0)

s/ PMECC_CFG_BCH_ERR25/ PMECC_CFG_BCH_ERR32

> 
>  #define		PMECC_CFG_SECTOR512		(0 << 4)
>  #define		PMECC_CFG_SECTOR1024		(1 << 4)
> @@ -108,7 +109,11 @@
>  #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
>  #define		PMERRLOC_CALC_DONE		(1 << 0)
>  #define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x
> */
> -#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
> +
> +/*
> + * The ATMEL_PMERRLOC_ELx register location depends from the number of
> + * bits corrected by the PMECC controller. Do not use it.
> + */
> 
>  /* Register access macros for PMECC */
>  #define pmecc_readl_relaxed(addr, reg) \ @@ -136,7 +141,7 @@
>  	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
> 
>  #define pmerrloc_readl_el_relaxed(addr, n) \
> -	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
> +	readl_relaxed((addr) + ((n) * 4))
> 
>  /* Galois field dimension */
>  #define PMECC_GF_DIMENSION_13			13
> --
> 2.5.0
> 
> 

Best Regards,
Wenyou Yang

RE: [RFC PATCH 3/4] mtd: atmel_nand: Support 32-bit ECC strength

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 3/4] mtd: atmel_nand: Support 32-bit ECC strength
> 
> Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
> controller that can correct 32 bits in each sector. This controller is not 100%
> compatible with the previous revision that corrected a maximum of 24 bits by
> sector, as some register addresses overlap.
> 
> Using information from the device tree, we can configure the driver to work with
> both versions.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

First this patch contains one more topic, 32-ECC, error-location. it should be split.


> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 10 +++--
>  drivers/mtd/nand/atmel_nand.c                      | 43 +++++++++++++++++++---
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++++-
>  3 files changed, 52 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 89b0db9801b0..ef0db8e2a0fd 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -1,7 +1,10 @@
>  Atmel NAND flash
> 
>  Required properties:
> -- compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand".
> +- compatible: The possible values are:
> +	"atmel,at91rm9200-nand"
> +	"atmel,sama5d2-nand"
> +	"atmel,sama5d4-nand"
>  - reg : should specify localbus address and size used for the chip,
>  	and hardware ECC controller if available.
>  	If the hardware ECC is PMECC, it should contain address and size for
> @@ -22,9 +25,10 @@ Optional properties:
>    Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
>    "soft_bch".
>  - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
> -  Only supported by at91sam9x5 or later sam9 product.
> +  Supported by AT91SAM9x5 or later SAM9 chips, and SAMA5 chips.
>  - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
> -  Controller. Supported values are: 2, 4, 8, 12, 24.
> +  Controller. Supported values are: 2, 4, 8, 12, 24. SAMA5D2 also
> + supports  32.
>  - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
>    are: 512, 1024.
>  - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index
> e5d7e7e63f49..cd55d54a9a7d 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -65,6 +65,7 @@ module_param(on_flash_bbt, int, 0);
> 
>  struct atmel_nand_caps {
>  	bool pmecc_correct_erase_page;
> +	uint8_t pmecc_max_correction;
>  };
> 
>  struct atmel_nand_nfc_priv {
> @@ -146,6 +147,7 @@ struct atmel_nand_host {
>  	int			pmecc_cw_len;	/* Length of codeword */
> 
>  	void __iomem		*pmerrloc_base;
> +	void __iomem		*pmerrloc_el_base;
>  	void __iomem		*pmecc_rom_base;
> 
>  	/* lookup table for alpha_to and index_of */ @@ -472,6 +474,7 @@ static
> void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
>   *                8-bits                13-bytes                 14-bytes
>   *               12-bits                20-bytes                 21-bytes
>   *               24-bits                39-bytes                 42-bytes
> + *               32-bits                52-bytes                 56-bytes
>   */

It seems, something missed after
         case 24:
                 val = PMECC_CFG_BCH_ERR24;
                 break;

such as,

         case 32:
                 val = PMECC_CFG_BCH_ERR32;
                 break



>  static int pmecc_get_ecc_bytes(int cap, int sector_size)  { @@ -817,7 +820,7
> @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t
> *ecc,
>  	sector_size = host->pmecc_sector_size;
> 
>  	while (err_nbr) {
> -		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
> +		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
>  		byte_pos = tmp / 8;
>  		bit_pos  = tmp % 8;
> 
> @@ -1081,6 +1084,9 @@ static int pmecc_choose_ecc(struct atmel_nand_host
> *host,
> 
>  	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
>  	if (host->pmecc_corr_cap == 0) {
> +		if (*cap > host->caps->pmecc_max_correction)
> +			return -EINVAL;
> +
>  		/* use the most fitable ecc bits (the near bigger one ) */
>  		if (*cap <= 2)
>  			host->pmecc_corr_cap = 2;
> @@ -1092,6 +1098,8 @@ static int pmecc_choose_ecc(struct atmel_nand_host
> *host,
>  			host->pmecc_corr_cap = 12;
>  		else if (*cap <= 24)
>  			host->pmecc_corr_cap = 24;
> +		else if (*cap <= 32)
> +			host->pmecc_corr_cap = 32;
>  		else
>  			return -EINVAL;
>  	}
> @@ -1208,6 +1216,8 @@ static int atmel_pmecc_nand_init_params(struct
> platform_device *pdev,
>  		err_no = PTR_ERR(host->pmerrloc_base);
>  		goto err;
>  	}
> +	host->pmerrloc_el_base = host->pmerrloc_base +
> ATMEL_PMERRLOC_SIGMAx +
> +		(host->caps->pmecc_max_correction + 1) * 4;
> 
>  	if (!host->has_no_lookup_table) {
>  		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM,
> 3); @@ -1550,10 +1560,16 @@ static int atmel_of_init_port(struct
> atmel_nand_host *host,
>  	 * them from NAND ONFI parameters.
>  	 */
>  	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
> -		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
> -				(val != 24)) {
> +		if (val > host->caps->pmecc_max_correction) {
> +			dev_err(host->dev,
> +				"Required ECC strength too high: %u max %u\n",
> +				val, host->caps->pmecc_max_correction);
> +			return -EINVAL;
> +		}
> +		if ((val != 2)  && (val != 4)  && (val != 8) &&
> +		    (val != 12) && (val != 24) && (val != 32)) {
>  			dev_err(host->dev,
> -				"Unsupported PMECC correction capability: %d;
> should be 2, 4, 8, 12 or 24\n",
> +				"Required ECC strength not supported: %u\n",
>  				val);
>  			return -EINVAL;
>  		}
> @@ -1563,7 +1579,7 @@ static int atmel_of_init_port(struct atmel_nand_host
> *host,
>  	if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
>  		if ((val != 512) && (val != 1024)) {
>  			dev_err(host->dev,
> -				"Unsupported PMECC sector size: %d; should be
> 512 or 1024 bytes\n",
> +				"Required ECC sector size not supported: %u\n",
>  				val);
>  			return -EINVAL;
>  		}
> @@ -2307,17 +2323,34 @@ static int atmel_nand_remove(struct platform_device
> *pdev)
>  	return 0;
>  }
> 
> +/*
> + * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
> + * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
> + * devices from the SAM9 family that have those.
> + */
>  static struct atmel_nand_caps at91rm9200_caps = {
>  	.pmecc_correct_erase_page = false,
> +	.pmecc_max_correction = 24,
>  };
> 
>  static struct atmel_nand_caps sama5d4_caps = {
>  	.pmecc_correct_erase_page = true,
> +	.pmecc_max_correction = 24,
> +};
> +
> +/*
> + * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
> + * as the increased correction strength requires more registers.
> + */
> +static struct atmel_nand_caps sama5d2_caps = {
> +	.pmecc_correct_erase_page = true,
> +	.pmecc_max_correction = 32,
>  };
> 
>  static const struct of_device_id atmel_nand_dt_ids[] = {
>  	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
>  	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
> +	{ .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
>  	{ /* sentinel */ }
>  };
> 
> diff --git a/drivers/mtd/nand/atmel_nand_ecc.h
> b/drivers/mtd/nand/atmel_nand_ecc.h
> index 668e7358f19b..b1d436d8bb7a 100644
> --- a/drivers/mtd/nand/atmel_nand_ecc.h
> +++ b/drivers/mtd/nand/atmel_nand_ecc.h
> @@ -43,6 +43,7 @@
>  #define		PMECC_CFG_BCH_ERR8		(2 << 0)
>  #define		PMECC_CFG_BCH_ERR12		(3 << 0)
>  #define		PMECC_CFG_BCH_ERR24		(4 << 0)
> +#define		PMECC_CFG_BCH_ERR25		(5 << 0)

s/ PMECC_CFG_BCH_ERR25/ PMECC_CFG_BCH_ERR32

> 
>  #define		PMECC_CFG_SECTOR512		(0 << 4)
>  #define		PMECC_CFG_SECTOR1024		(1 << 4)
> @@ -108,7 +109,11 @@
>  #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
>  #define		PMERRLOC_CALC_DONE		(1 << 0)
>  #define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x
> */
> -#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
> +
> +/*
> + * The ATMEL_PMERRLOC_ELx register location depends from the number of
> + * bits corrected by the PMECC controller. Do not use it.
> + */
> 
>  /* Register access macros for PMECC */
>  #define pmecc_readl_relaxed(addr, reg) \ @@ -136,7 +141,7 @@
>  	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
> 
>  #define pmerrloc_readl_el_relaxed(addr, n) \
> -	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
> +	readl_relaxed((addr) + ((n) * 4))
> 
>  /* Galois field dimension */
>  #define PMECC_GF_DIMENSION_13			13
> --
> 2.5.0
> 
> 

Best Regards,
Wenyou Yang

RE: [RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE
> interrupts
> 
> The NFC controller used to accelerate the NAND transfers on SAMA5 chips can
> use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.
> 
> Use the controller's compatible string to select the correct bit.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

Reviewed-by: Wenyou Yang <Wenyou.yang@atmel.com>


> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-
>  drivers/mtd/nand/atmel_nand.c                      | 39 +++++++++++++++++-----
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  5 ++-
>  3 files changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 7d4c8eb775a5..89b0db9801b0 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -34,7 +34,7 @@ Optional properties:
>  - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
>  - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
>    - Required properties:
> -    - compatible : "atmel,sama5d3-nfc".
> +    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
>      - reg : should specify the address and size used for NFC command registers,
>              NFC registers and NFC Sram. NFC Sram address and size can be
> absent
>              if don't want to use it.
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index
> 9d71f9e6a8de..e5d7e7e63f49 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -67,6 +67,10 @@ struct atmel_nand_caps {
>  	bool pmecc_correct_erase_page;
>  };
> 
> +struct atmel_nand_nfc_priv {
> +	uint32_t rb_edge;
> +};
> +
>  /* oob layout for large page size
>   * bad block info is on bytes 0 and 1
>   * the bytes have to be consecutives to avoid @@ -111,6 +115,7 @@ struct
> atmel_nfc {
>  	/* Point to the sram bank which include readed data via NFC */
>  	void			*data_in_sram;
>  	bool			will_write_sram;
> +	uint32_t		rb_edge;
>  };
>  static struct atmel_nfc	nand_nfc;
> 
> @@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
>  		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
>  		ret = IRQ_HANDLED;
>  	}
> -	if (pending & NFC_SR_RB_EDGE) {
> +	if (pending & host->nfc->rb_edge) {
>  		complete(&host->nfc->comp_ready);
> -		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
> +		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->rb_edge);
>  		ret = IRQ_HANDLED;
>  	}
>  	if (pending & NFC_SR_CMD_DONE) {
> @@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct
> atmel_nand_host *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		init_completion(&host->nfc->comp_xfer_done);
> 
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		init_completion(&host->nfc->comp_ready);
> 
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host
> *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		comp[index++] = &host->nfc->comp_xfer_done;
> 
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		comp[index++] = &host->nfc->comp_ready;
> 
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
>  		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
>  				mask & status);
> 
> -	return status & NFC_SR_RB_EDGE;
> +	return status & host->nfc->rb_edge;
>  }
> 
>  static void nfc_select_chip(struct mtd_info *mtd, int chip) @@ -1954,8 +1959,8
> @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>  		}
>  		/* fall through */
>  	default:
> -		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
> -		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
> +		nfc_prepare_interrupt(host, host->nfc->rb_edge);
> +		nfc_wait_interrupt(host, host->nfc->rb_edge);
>  	}
>  }
> 
> @@ -2318,9 +2323,12 @@ static const struct of_device_id atmel_nand_dt_ids[] =
> {
> 
>  MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
> 
> +static const struct of_device_id atmel_nand_nfc_match[];
> +
>  static int atmel_nand_nfc_probe(struct platform_device *pdev)  {
>  	struct atmel_nfc *nfc = &nand_nfc;
> +	const struct atmel_nand_nfc_priv *priv;
>  	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
>  	int ret;
> 
> @@ -2352,6 +2360,12 @@ static int atmel_nand_nfc_probe(struct
> platform_device *pdev)
>  		}
>  	}
> 
> +	priv = of_match_device(atmel_nand_nfc_match, &pdev->dev)->data;
> +	if (NULL == priv)
> +		return -ENODEV;
> +
> +	nfc->rb_edge = priv->rb_edge;
> +
>  	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
>  	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
> 
> @@ -2380,8 +2394,17 @@ static int atmel_nand_nfc_remove(struct
> platform_device *pdev)
>  	return 0;
>  }
> 
> +static struct atmel_nand_nfc_priv sama5d3_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE0,
> +};
> +
> +static struct atmel_nand_nfc_priv sama5d4_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE3,
> +};
> +
>  static const struct of_device_id atmel_nand_nfc_match[] = {
> -	{ .compatible = "atmel,sama5d3-nfc" },
> +	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_priv },
> +	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_priv },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match); diff --git
> a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
> index 4d5d26221a7e..2cd9c57b1e53 100644
> --- a/drivers/mtd/nand/atmel_nand_nfc.h
> +++ b/drivers/mtd/nand/atmel_nand_nfc.h
> @@ -42,7 +42,10 @@
>  #define		NFC_SR_UNDEF		(1 << 21)
>  #define		NFC_SR_AWB		(1 << 22)
>  #define		NFC_SR_ASE		(1 << 23)
> -#define		NFC_SR_RB_EDGE		(1 << 24)
> +#define		NFC_SR_RB_EDGE0		(1 << 24)
> +#define		NFC_SR_RB_EDGE1		(1 << 25)
> +#define		NFC_SR_RB_EDGE2		(1 << 26)
> +#define		NFC_SR_RB_EDGE3		(1 << 27)
> 
>  #define ATMEL_HSMC_NFC_IER	0x0c
>  #define ATMEL_HSMC_NFC_IDR	0x10
> --
> 2.5.0
> 

Best Regards,
Wenyou Yang

RE: [RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Yang, Wenyou]

> -----Original Message-----
> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
> Romain Izard
> Sent: 2016年1月12日 22:34
> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
> Subject: [RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE
> interrupts
> 
> The NFC controller used to accelerate the NAND transfers on SAMA5 chips can
> use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.
> 
> Use the controller's compatible string to select the correct bit.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>

Reviewed-by: Wenyou Yang <Wenyou.yang@atmel.com>


> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-
>  drivers/mtd/nand/atmel_nand.c                      | 39 +++++++++++++++++-----
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  5 ++-
>  3 files changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 7d4c8eb775a5..89b0db9801b0 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -34,7 +34,7 @@ Optional properties:
>  - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
>  - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
>    - Required properties:
> -    - compatible : "atmel,sama5d3-nfc".
> +    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
>      - reg : should specify the address and size used for NFC command registers,
>              NFC registers and NFC Sram. NFC Sram address and size can be
> absent
>              if don't want to use it.
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index
> 9d71f9e6a8de..e5d7e7e63f49 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -67,6 +67,10 @@ struct atmel_nand_caps {
>  	bool pmecc_correct_erase_page;
>  };
> 
> +struct atmel_nand_nfc_priv {
> +	uint32_t rb_edge;
> +};
> +
>  /* oob layout for large page size
>   * bad block info is on bytes 0 and 1
>   * the bytes have to be consecutives to avoid @@ -111,6 +115,7 @@ struct
> atmel_nfc {
>  	/* Point to the sram bank which include readed data via NFC */
>  	void			*data_in_sram;
>  	bool			will_write_sram;
> +	uint32_t		rb_edge;
>  };
>  static struct atmel_nfc	nand_nfc;
> 
> @@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
>  		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
>  		ret = IRQ_HANDLED;
>  	}
> -	if (pending & NFC_SR_RB_EDGE) {
> +	if (pending & host->nfc->rb_edge) {
>  		complete(&host->nfc->comp_ready);
> -		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
> +		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->rb_edge);
>  		ret = IRQ_HANDLED;
>  	}
>  	if (pending & NFC_SR_CMD_DONE) {
> @@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct
> atmel_nand_host *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		init_completion(&host->nfc->comp_xfer_done);
> 
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		init_completion(&host->nfc->comp_ready);
> 
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host
> *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		comp[index++] = &host->nfc->comp_xfer_done;
> 
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		comp[index++] = &host->nfc->comp_ready;
> 
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
>  		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
>  				mask & status);
> 
> -	return status & NFC_SR_RB_EDGE;
> +	return status & host->nfc->rb_edge;
>  }
> 
>  static void nfc_select_chip(struct mtd_info *mtd, int chip) @@ -1954,8 +1959,8
> @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>  		}
>  		/* fall through */
>  	default:
> -		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
> -		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
> +		nfc_prepare_interrupt(host, host->nfc->rb_edge);
> +		nfc_wait_interrupt(host, host->nfc->rb_edge);
>  	}
>  }
> 
> @@ -2318,9 +2323,12 @@ static const struct of_device_id atmel_nand_dt_ids[] =
> {
> 
>  MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
> 
> +static const struct of_device_id atmel_nand_nfc_match[];
> +
>  static int atmel_nand_nfc_probe(struct platform_device *pdev)  {
>  	struct atmel_nfc *nfc = &nand_nfc;
> +	const struct atmel_nand_nfc_priv *priv;
>  	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
>  	int ret;
> 
> @@ -2352,6 +2360,12 @@ static int atmel_nand_nfc_probe(struct
> platform_device *pdev)
>  		}
>  	}
> 
> +	priv = of_match_device(atmel_nand_nfc_match, &pdev->dev)->data;
> +	if (NULL == priv)
> +		return -ENODEV;
> +
> +	nfc->rb_edge = priv->rb_edge;
> +
>  	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
>  	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
> 
> @@ -2380,8 +2394,17 @@ static int atmel_nand_nfc_remove(struct
> platform_device *pdev)
>  	return 0;
>  }
> 
> +static struct atmel_nand_nfc_priv sama5d3_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE0,
> +};
> +
> +static struct atmel_nand_nfc_priv sama5d4_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE3,
> +};
> +
>  static const struct of_device_id atmel_nand_nfc_match[] = {
> -	{ .compatible = "atmel,sama5d3-nfc" },
> +	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_priv },
> +	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_priv },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match); diff --git
> a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
> index 4d5d26221a7e..2cd9c57b1e53 100644
> --- a/drivers/mtd/nand/atmel_nand_nfc.h
> +++ b/drivers/mtd/nand/atmel_nand_nfc.h
> @@ -42,7 +42,10 @@
>  #define		NFC_SR_UNDEF		(1 << 21)
>  #define		NFC_SR_AWB		(1 << 22)
>  #define		NFC_SR_ASE		(1 << 23)
> -#define		NFC_SR_RB_EDGE		(1 << 24)
> +#define		NFC_SR_RB_EDGE0		(1 << 24)
> +#define		NFC_SR_RB_EDGE1		(1 << 25)
> +#define		NFC_SR_RB_EDGE2		(1 << 26)
> +#define		NFC_SR_RB_EDGE3		(1 << 27)
> 
>  #define ATMEL_HSMC_NFC_IER	0x0c
>  #define ATMEL_HSMC_NFC_IDR	0x10
> --
> 2.5.0
> 

Best Regards,
Wenyou Yang

Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[romain izard]

2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>
>> -----Original Message-----
>> From: linux-mtd [mailto:linux-mtd-bounces-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org] On Behalf Of
>> Romain Izard
>> Sent: 2016年1月12日 22:34
>> To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: Wu, Josh <Josh.wu-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>; Romain Izard
>> <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>; Ferre, Nicolas <Nicolas.FERRE-AIFe0yeh4nA@public.gmane.orgm>
>> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
>>
>> Both nodes are required to access NAND Flash memory. Additional settings will
>> be necessary at the board level to use it.
>>
>> Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  arch/arm/boot/dts/sama5d2.dtsi | 38
>> ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 38 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index
>> aee571448342..80420177ec1a 100644
>> --- a/arch/arm/boot/dts/sama5d2.dtsi
>> +++ b/arch/arm/boot/dts/sama5d2.dtsi
>> @@ -265,6 +265,44 @@
>>                       cache-level = <2>;
>>               };
>>
>> +             nand0: nand@80000000 {
>> +                     compatible = "atmel,sama5d2-nand";
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     ranges;
>> +                     reg = < /* EBI CS3 */
>> +                             0x80000000 0x08000000
>> +                             /* SMC PMECC regs */
>> +                             0xf8014070 0x00000490
>> +                             /* SMC PMECC Error Location regs */
>> +                             0xf8014500 0x00000200
>> +                             /* ROM Galois tables */
>> +                             0x00040000 0x00018000
>
> As there is no PMECC lookup table in ROM exported, remove this line.
>

From what I see in the SAMA5D2 xplained board on my table, it is not the
case. Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data
that looks identical to the Galois tables in the Atmel example code.

U-Boot> md.w 0x40000
00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527

U-Boot> md.w 0x48000
00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828


This location matches the information in the SAMA5D2 datasheet from
chapter 6, "Memories", but not the contradicting information from chapter
14, "Standard Boot Strategies".

>> +                             >;
>> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
>> +                     atmel,nand-addr-offset = <21>;
>> +                     atmel,nand-cmd-offset = <22>;
>> +                     atmel,nand-has-dma;
>> +                     atmel,has-pmecc;
>> +                     atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
>
> Ditto, remove this line.
>
>> +                     status = "disabled";
>> +
>> +                     nfc@90000000 {
>> +                             compatible = "atmel,sama5d4-nfc";
>> +                             #address-cells = <1>;
>> +                             #size-cells = <1>;
>> +                             reg = < /* NFC Command Registers */
>> +                                     0xC0000000 0x08000000
>> +                                     /* NFC HSMC regs */
>> +                                     0xf8014000 0x00000070
>> +                                     /* NFC SRAM banks */
>> +                                     0x00100000 0x00100000
>> +                                     >;
>> +                             clocks = <&hsmc_clk>;
>> +                             atmel,write-by-sram;
>> +                     };
>> +             };
>> +
>>               sdmmc0: sdio-host@a0000000 {
>>                       compatible = "atmel,sama5d2-sdhci";
>>                       reg = <0xa0000000 0x300>;
>> --
>> 2.5.0
>>


Best regards
-- 
Romain Izard
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Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[romain izard]

2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang@atmel.com>:
>
>> -----Original Message-----
>> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
>> Romain Izard
>> Sent: 2016年1月12日 22:34
>> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
>> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
>> <romain.izard.pro@gmail.com>; Ferre, Nicolas <Nicolas.FERRE@atmel.com>
>> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
>>
>> Both nodes are required to access NAND Flash memory. Additional settings will
>> be necessary at the board level to use it.
>>
>> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
>> ---
>>  arch/arm/boot/dts/sama5d2.dtsi | 38
>> ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 38 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index
>> aee571448342..80420177ec1a 100644
>> --- a/arch/arm/boot/dts/sama5d2.dtsi
>> +++ b/arch/arm/boot/dts/sama5d2.dtsi
>> @@ -265,6 +265,44 @@
>>                       cache-level = <2>;
>>               };
>>
>> +             nand0: nand@80000000 {
>> +                     compatible = "atmel,sama5d2-nand";
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     ranges;
>> +                     reg = < /* EBI CS3 */
>> +                             0x80000000 0x08000000
>> +                             /* SMC PMECC regs */
>> +                             0xf8014070 0x00000490
>> +                             /* SMC PMECC Error Location regs */
>> +                             0xf8014500 0x00000200
>> +                             /* ROM Galois tables */
>> +                             0x00040000 0x00018000
>
> As there is no PMECC lookup table in ROM exported, remove this line.
>

>From what I see in the SAMA5D2 xplained board on my table, it is not the
case. Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data
that looks identical to the Galois tables in the Atmel example code.

U-Boot> md.w 0x40000
00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527

U-Boot> md.w 0x48000
00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828


This location matches the information in the SAMA5D2 datasheet from
chapter 6, "Memories", but not the contradicting information from chapter
14, "Standard Boot Strategies".

>> +                             >;
>> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
>> +                     atmel,nand-addr-offset = <21>;
>> +                     atmel,nand-cmd-offset = <22>;
>> +                     atmel,nand-has-dma;
>> +                     atmel,has-pmecc;
>> +                     atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
>
> Ditto, remove this line.
>
>> +                     status = "disabled";
>> +
>> +                     nfc@90000000 {
>> +                             compatible = "atmel,sama5d4-nfc";
>> +                             #address-cells = <1>;
>> +                             #size-cells = <1>;
>> +                             reg = < /* NFC Command Registers */
>> +                                     0xC0000000 0x08000000
>> +                                     /* NFC HSMC regs */
>> +                                     0xf8014000 0x00000070
>> +                                     /* NFC SRAM banks */
>> +                                     0x00100000 0x00100000
>> +                                     >;
>> +                             clocks = <&hsmc_clk>;
>> +                             atmel,write-by-sram;
>> +                     };
>> +             };
>> +
>>               sdmmc0: sdio-host@a0000000 {
>>                       compatible = "atmel,sama5d2-sdhci";
>>                       reg = <0xa0000000 0x300>;
>> --
>> 2.5.0
>>


Best regards
-- 
Romain Izard

RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Yang, Wenyou]

Hi Romain,

> -----Original Message-----
> From: romain izard [mailto:romain.izard@mobile-devices.fr]
> Sent: 2016年1月13日 17:41
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre, Nicolas
> <Nicolas.FERRE@atmel.com>
> Subject: Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> nodes
> 
> 2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang@atmel.com>:
> >
> >> -----Original Message-----
> >> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
> >> Behalf Of Romain Izard
> >> Sent: 2016年1月12日 22:34
> >> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> >> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> >> <romain.izard.pro@gmail.com>; Ferre, Nicolas
> >> <Nicolas.FERRE@atmel.com>
> >> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> >> nodes
> >>
> >> Both nodes are required to access NAND Flash memory. Additional
> >> settings will be necessary at the board level to use it.
> >>
> >> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> >> ---
> >>  arch/arm/boot/dts/sama5d2.dtsi | 38
> >> ++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 38 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sama5d2.dtsi
> >> b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a
> >> 100644
> >> --- a/arch/arm/boot/dts/sama5d2.dtsi
> >> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> >> @@ -265,6 +265,44 @@
> >>                       cache-level = <2>;
> >>               };
> >>
> >> +             nand0: nand@80000000 {
> >> +                     compatible = "atmel,sama5d2-nand";
> >> +                     #address-cells = <1>;
> >> +                     #size-cells = <1>;
> >> +                     ranges;
> >> +                     reg = < /* EBI CS3 */
> >> +                             0x80000000 0x08000000
> >> +                             /* SMC PMECC regs */
> >> +                             0xf8014070 0x00000490
> >> +                             /* SMC PMECC Error Location regs */
> >> +                             0xf8014500 0x00000200
> >> +                             /* ROM Galois tables */
> >> +                             0x00040000 0x00018000
> >
> > As there is no PMECC lookup table in ROM exported, remove this line.
> >
> 
> From what I see in the SAMA5D2 xplained board on my table, it is not the case.
> Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data that looks
> identical to the Galois tables in the Atmel example code.
> 
> U-Boot> md.w 0x40000
> 00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
> 00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
> 00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
> 00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
> 00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
> 00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
> 00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
> 00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527
> 
> U-Boot> md.w 0x48000
> 00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
> 00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
> 00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
> 00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
> 00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
> 00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
> 00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
> 00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828
> 
> 
> This location matches the information in the SAMA5D2 datasheet from chapter 6,
> "Memories", but not the contradicting information from chapter 14, "Standard Boot
> Strategies".

As I known, the Galois Field Table should not exported since SAMA5D4, I will check with the system team.

> 
> >> +                             >;
> >> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
> >> +                     atmel,nand-addr-offset = <21>;
> >> +                     atmel,nand-cmd-offset = <22>;
> >> +                     atmel,nand-has-dma;
> >> +                     atmel,has-pmecc;
> >> +                     atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
> >
> > Ditto, remove this line.
> >
> >> +                     status = "disabled";
> >> +
> >> +                     nfc@90000000 {
> >> +                             compatible = "atmel,sama5d4-nfc";
> >> +                             #address-cells = <1>;
> >> +                             #size-cells = <1>;
> >> +                             reg = < /* NFC Command Registers */
> >> +                                     0xC0000000 0x08000000
> >> +                                     /* NFC HSMC regs */
> >> +                                     0xf8014000 0x00000070
> >> +                                     /* NFC SRAM banks */
> >> +                                     0x00100000 0x00100000
> >> +                                     >;
> >> +                             clocks = <&hsmc_clk>;
> >> +                             atmel,write-by-sram;
> >> +                     };
> >> +             };
> >> +
> >>               sdmmc0: sdio-host@a0000000 {
> >>                       compatible = "atmel,sama5d2-sdhci";
> >>                       reg = <0xa0000000 0x300>;
> >> --
> >> 2.5.0
> >>
> 
> 
> Best regards
> --
> Romain Izard


Best Regards,
Wenyou Yang

RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Yang, Wenyou]

Hi Romain,

> -----Original Message-----
> From: romain izard [mailto:romain.izard@mobile-devices.fr]
> Sent: 2016年1月13日 17:41
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre, Nicolas
> <Nicolas.FERRE@atmel.com>
> Subject: Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> nodes
> 
> 2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang@atmel.com>:
> >
> >> -----Original Message-----
> >> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
> >> Behalf Of Romain Izard
> >> Sent: 2016年1月12日 22:34
> >> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> >> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> >> <romain.izard.pro@gmail.com>; Ferre, Nicolas
> >> <Nicolas.FERRE@atmel.com>
> >> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> >> nodes
> >>
> >> Both nodes are required to access NAND Flash memory. Additional
> >> settings will be necessary at the board level to use it.
> >>
> >> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> >> ---
> >>  arch/arm/boot/dts/sama5d2.dtsi | 38
> >> ++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 38 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sama5d2.dtsi
> >> b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a
> >> 100644
> >> --- a/arch/arm/boot/dts/sama5d2.dtsi
> >> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> >> @@ -265,6 +265,44 @@
> >>                       cache-level = <2>;
> >>               };
> >>
> >> +             nand0: nand@80000000 {
> >> +                     compatible = "atmel,sama5d2-nand";
> >> +                     #address-cells = <1>;
> >> +                     #size-cells = <1>;
> >> +                     ranges;
> >> +                     reg = < /* EBI CS3 */
> >> +                             0x80000000 0x08000000
> >> +                             /* SMC PMECC regs */
> >> +                             0xf8014070 0x00000490
> >> +                             /* SMC PMECC Error Location regs */
> >> +                             0xf8014500 0x00000200
> >> +                             /* ROM Galois tables */
> >> +                             0x00040000 0x00018000
> >
> > As there is no PMECC lookup table in ROM exported, remove this line.
> >
> 
> From what I see in the SAMA5D2 xplained board on my table, it is not the case.
> Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data that looks
> identical to the Galois tables in the Atmel example code.
> 
> U-Boot> md.w 0x40000
> 00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
> 00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
> 00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
> 00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
> 00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
> 00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
> 00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
> 00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527
> 
> U-Boot> md.w 0x48000
> 00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
> 00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
> 00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
> 00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
> 00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
> 00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
> 00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
> 00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828
> 
> 
> This location matches the information in the SAMA5D2 datasheet from chapter 6,
> "Memories", but not the contradicting information from chapter 14, "Standard Boot
> Strategies".

As I known, the Galois Field Table should not exported since SAMA5D4, I will check with the system team.

> 
> >> +                             >;
> >> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
> >> +                     atmel,nand-addr-offset = <21>;
> >> +                     atmel,nand-cmd-offset = <22>;
> >> +                     atmel,nand-has-dma;
> >> +                     atmel,has-pmecc;
> >> +                     atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
> >
> > Ditto, remove this line.
> >
> >> +                     status = "disabled";
> >> +
> >> +                     nfc@90000000 {
> >> +                             compatible = "atmel,sama5d4-nfc";
> >> +                             #address-cells = <1>;
> >> +                             #size-cells = <1>;
> >> +                             reg = < /* NFC Command Registers */
> >> +                                     0xC0000000 0x08000000
> >> +                                     /* NFC HSMC regs */
> >> +                                     0xf8014000 0x00000070
> >> +                                     /* NFC SRAM banks */
> >> +                                     0x00100000 0x00100000
> >> +                                     >;
> >> +                             clocks = <&hsmc_clk>;
> >> +                             atmel,write-by-sram;
> >> +                     };
> >> +             };
> >> +
> >>               sdmmc0: sdio-host@a0000000 {
> >>                       compatible = "atmel,sama5d2-sdhci";
> >>                       reg = <0xa0000000 0x300>;
> >> --
> >> 2.5.0
> >>
> 
> 
> Best regards
> --
> Romain Izard


Best Regards,
Wenyou Yang

Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 12/01/2016 17:55, Romain Izard a écrit :
> Hi Nicolas,
> 
> 2016-01-12 16:45 GMT+01:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>>
>> The maintainers for this driver changed very recently, so you'll have to
>> includes these names to your CC list:
>>
>> M:      Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
>> M:      Josh Wu <rainyfeeling-1ViLX0X+lBJBDgjK7y7TUQ@public.gmane.org>
> 
> Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's atmel
> address now bounces, and it is still referenced there.

It's already done and pushed to arm-soc. It's in linux-next:
http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/MAINTAINERS#n2000

It will appear in Linus' tree in a couple of days ;-)

>> I also think that Wenyou did some work regarding this support. So you'll
>> have to coordinat together.
> 
> Is it possible to know what are the developments in progress regarding SAMA5D2
> drivers? The github repository does not expose any working trees, and only the

Which github repository are you talking about?

The Linux4SAM github contains all that is need to work with sama5d2
(linux-4.1-at91 branch):
https://github.com/linux4sam/linux-at91/tree/linux-4.1-at91

Developments in progress are listed in the Linux4SAM page:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage

I admit that it's not copleted, but you'll have an idea here as well:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage

Bye,
-- 
Nicolas Ferre
--
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Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 12/01/2016 17:55, Romain Izard a écrit :
> Hi Nicolas,
> 
> 2016-01-12 16:45 GMT+01:00 Nicolas Ferre <nicolas.ferre@atmel.com>:
>>
>> The maintainers for this driver changed very recently, so you'll have to
>> includes these names to your CC list:
>>
>> M:      Wenyou Yang <wenyou.yang@atmel.com>
>> M:      Josh Wu <rainyfeeling@outlook.com>
> 
> Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's atmel
> address now bounces, and it is still referenced there.

It's already done and pushed to arm-soc. It's in linux-next:
http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/MAINTAINERS#n2000

It will appear in Linus' tree in a couple of days ;-)

>> I also think that Wenyou did some work regarding this support. So you'll
>> have to coordinat together.
> 
> Is it possible to know what are the developments in progress regarding SAMA5D2
> drivers? The github repository does not expose any working trees, and only the

Which github repository are you talking about?

The Linux4SAM github contains all that is need to work with sama5d2
(linux-4.1-at91 branch):
https://github.com/linux4sam/linux-at91/tree/linux-4.1-at91

Developments in progress are listed in the Linux4SAM page:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage

I admit that it's not copleted, but you'll have an idea here as well:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage

Bye,
-- 
Nicolas Ferre

RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Yang, Wenyou]

Hi Romain,

Confirmed. 

You are right. The tables are accessible.

Please ignore my comments.


Best Regards,
Wenyou Yang

> -----Original Message-----
> From: Yang, Wenyou
> Sent: 2016年1月13日 19:29
> To: 'romain izard' <romain.izard@mobile-devices.fr>
> Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre, Nicolas
> <Nicolas.FERRE@atmel.com>
> Subject: RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> nodes
> 
> Hi Romain,
> 
> > -----Original Message-----
> > From: romain izard [mailto:romain.izard@mobile-devices.fr]
> > Sent: 2016年1月13日 17:41
> > To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> > Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre,
> > Nicolas <Nicolas.FERRE@atmel.com>
> > Subject: Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> > nodes
> >
> > 2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang@atmel.com>:
> > >
> > >> -----Original Message-----
> > >> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
> > >> Behalf Of Romain Izard
> > >> Sent: 2016年1月12日 22:34
> > >> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> > >> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> > >> <romain.izard.pro@gmail.com>; Ferre, Nicolas
> > >> <Nicolas.FERRE@atmel.com>
> > >> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> > >> nodes
> > >>
> > >> Both nodes are required to access NAND Flash memory. Additional
> > >> settings will be necessary at the board level to use it.
> > >>
> > >> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> > >> ---
> > >>  arch/arm/boot/dts/sama5d2.dtsi | 38
> > >> ++++++++++++++++++++++++++++++++++++++
> > >>  1 file changed, 38 insertions(+)
> > >>
> > >> diff --git a/arch/arm/boot/dts/sama5d2.dtsi
> > >> b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a
> > >> 100644
> > >> --- a/arch/arm/boot/dts/sama5d2.dtsi
> > >> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> > >> @@ -265,6 +265,44 @@
> > >>                       cache-level = <2>;
> > >>               };
> > >>
> > >> +             nand0: nand@80000000 {
> > >> +                     compatible = "atmel,sama5d2-nand";
> > >> +                     #address-cells = <1>;
> > >> +                     #size-cells = <1>;
> > >> +                     ranges;
> > >> +                     reg = < /* EBI CS3 */
> > >> +                             0x80000000 0x08000000
> > >> +                             /* SMC PMECC regs */
> > >> +                             0xf8014070 0x00000490
> > >> +                             /* SMC PMECC Error Location regs */
> > >> +                             0xf8014500 0x00000200
> > >> +                             /* ROM Galois tables */
> > >> +                             0x00040000 0x00018000
> > >
> > > As there is no PMECC lookup table in ROM exported, remove this line.
> > >
> >
> > From what I see in the SAMA5D2 xplained board on my table, it is not the case.
> > Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data that
> > looks identical to the Galois tables in the Atmel example code.
> >
> > U-Boot> md.w 0x40000
> > 00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
> > 00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
> > 00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
> > 00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
> > 00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
> > 00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
> > 00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
> > 00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527
> >
> > U-Boot> md.w 0x48000
> > 00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
> > 00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
> > 00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
> > 00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
> > 00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
> > 00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
> > 00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
> > 00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828
> >
> >
> > This location matches the information in the SAMA5D2 datasheet from
> > chapter 6, "Memories", but not the contradicting information from
> > chapter 14, "Standard Boot Strategies".
> 
> As I known, the Galois Field Table should not exported since SAMA5D4, I will
> check with the system team.
> 
> >
> > >> +                             >;
> > >> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
> > >> +                     atmel,nand-addr-offset = <21>;
> > >> +                     atmel,nand-cmd-offset = <22>;
> > >> +                     atmel,nand-has-dma;
> > >> +                     atmel,has-pmecc;
> > >> +                     atmel,pmecc-lookup-table-offset = <0x0
> > >> + 0x8000>;
> > >
> > > Ditto, remove this line.
> > >
> > >> +                     status = "disabled";
> > >> +
> > >> +                     nfc@90000000 {
> > >> +                             compatible = "atmel,sama5d4-nfc";
> > >> +                             #address-cells = <1>;
> > >> +                             #size-cells = <1>;
> > >> +                             reg = < /* NFC Command Registers */
> > >> +                                     0xC0000000 0x08000000
> > >> +                                     /* NFC HSMC regs */
> > >> +                                     0xf8014000 0x00000070
> > >> +                                     /* NFC SRAM banks */
> > >> +                                     0x00100000 0x00100000
> > >> +                                     >;
> > >> +                             clocks = <&hsmc_clk>;
> > >> +                             atmel,write-by-sram;
> > >> +                     };
> > >> +             };
> > >> +
> > >>               sdmmc0: sdio-host@a0000000 {
> > >>                       compatible = "atmel,sama5d2-sdhci";
> > >>                       reg = <0xa0000000 0x300>;
> > >> --
> > >> 2.5.0
> > >>
> >
> >
> > Best regards
> > --
> > Romain Izard
> 
> 
> Best Regards,
> Wenyou Yang

RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Yang, Wenyou]

Hi Romain,

Confirmed. 

You are right. The tables are accessible.

Please ignore my comments.


Best Regards,
Wenyou Yang

> -----Original Message-----
> From: Yang, Wenyou
> Sent: 2016年1月13日 19:29
> To: 'romain izard' <romain.izard@mobile-devices.fr>
> Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre, Nicolas
> <Nicolas.FERRE@atmel.com>
> Subject: RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> nodes
> 
> Hi Romain,
> 
> > -----Original Message-----
> > From: romain izard [mailto:romain.izard@mobile-devices.fr]
> > Sent: 2016年1月13日 17:41
> > To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> > Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre,
> > Nicolas <Nicolas.FERRE@atmel.com>
> > Subject: Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> > nodes
> >
> > 2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang@atmel.com>:
> > >
> > >> -----Original Message-----
> > >> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
> > >> Behalf Of Romain Izard
> > >> Sent: 2016年1月12日 22:34
> > >> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
> > >> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
> > >> <romain.izard.pro@gmail.com>; Ferre, Nicolas
> > >> <Nicolas.FERRE@atmel.com>
> > >> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
> > >> nodes
> > >>
> > >> Both nodes are required to access NAND Flash memory. Additional
> > >> settings will be necessary at the board level to use it.
> > >>
> > >> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> > >> ---
> > >>  arch/arm/boot/dts/sama5d2.dtsi | 38
> > >> ++++++++++++++++++++++++++++++++++++++
> > >>  1 file changed, 38 insertions(+)
> > >>
> > >> diff --git a/arch/arm/boot/dts/sama5d2.dtsi
> > >> b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a
> > >> 100644
> > >> --- a/arch/arm/boot/dts/sama5d2.dtsi
> > >> +++ b/arch/arm/boot/dts/sama5d2.dtsi
> > >> @@ -265,6 +265,44 @@
> > >>                       cache-level = <2>;
> > >>               };
> > >>
> > >> +             nand0: nand@80000000 {
> > >> +                     compatible = "atmel,sama5d2-nand";
> > >> +                     #address-cells = <1>;
> > >> +                     #size-cells = <1>;
> > >> +                     ranges;
> > >> +                     reg = < /* EBI CS3 */
> > >> +                             0x80000000 0x08000000
> > >> +                             /* SMC PMECC regs */
> > >> +                             0xf8014070 0x00000490
> > >> +                             /* SMC PMECC Error Location regs */
> > >> +                             0xf8014500 0x00000200
> > >> +                             /* ROM Galois tables */
> > >> +                             0x00040000 0x00018000
> > >
> > > As there is no PMECC lookup table in ROM exported, remove this line.
> > >
> >
> > From what I see in the SAMA5D2 xplained board on my table, it is not the case.
> > Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data that
> > looks identical to the Galois tables in the Atmel example code.
> >
> > U-Boot> md.w 0x40000
> > 00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
> > 00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
> > 00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
> > 00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
> > 00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
> > 00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
> > 00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
> > 00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527
> >
> > U-Boot> md.w 0x48000
> > 00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
> > 00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
> > 00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
> > 00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
> > 00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
> > 00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
> > 00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
> > 00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828
> >
> >
> > This location matches the information in the SAMA5D2 datasheet from
> > chapter 6, "Memories", but not the contradicting information from
> > chapter 14, "Standard Boot Strategies".
> 
> As I known, the Galois Field Table should not exported since SAMA5D4, I will
> check with the system team.
> 
> >
> > >> +                             >;
> > >> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
> > >> +                     atmel,nand-addr-offset = <21>;
> > >> +                     atmel,nand-cmd-offset = <22>;
> > >> +                     atmel,nand-has-dma;
> > >> +                     atmel,has-pmecc;
> > >> +                     atmel,pmecc-lookup-table-offset = <0x0
> > >> + 0x8000>;
> > >
> > > Ditto, remove this line.
> > >
> > >> +                     status = "disabled";
> > >> +
> > >> +                     nfc@90000000 {
> > >> +                             compatible = "atmel,sama5d4-nfc";
> > >> +                             #address-cells = <1>;
> > >> +                             #size-cells = <1>;
> > >> +                             reg = < /* NFC Command Registers */
> > >> +                                     0xC0000000 0x08000000
> > >> +                                     /* NFC HSMC regs */
> > >> +                                     0xf8014000 0x00000070
> > >> +                                     /* NFC SRAM banks */
> > >> +                                     0x00100000 0x00100000
> > >> +                                     >;
> > >> +                             clocks = <&hsmc_clk>;
> > >> +                             atmel,write-by-sram;
> > >> +                     };
> > >> +             };
> > >> +
> > >>               sdmmc0: sdio-host@a0000000 {
> > >>                       compatible = "atmel,sama5d2-sdhci";
> > >>                       reg = <0xa0000000 0x300>;
> > >> --
> > >> 2.5.0
> > >>
> >
> >
> > Best regards
> > --
> > Romain Izard
> 
> 
> Best Regards,
> Wenyou Yang

Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

2016-01-13 12:46 GMT+01:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>> Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's
>> atmel address now bounces, and it is still referenced there.
>
> It's already done and pushed to arm-soc. It's in linux-next:
> http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/MAINTAINERS#n2000
>
> It will appear in Linus' tree in a couple of days ;-)
>
Good. As I based my developments on the linux-4.1-at91 branch from the Linux4SAM
github which does not contain the update, I missed it.

>>> I also think that Wenyou did some work regarding this support. So you'll
>>> have to coordinat together.
>>
>> Is it possible to know what are the developments in progress regarding
>> SAMA5D2 drivers? The github repository does not expose any working trees,
>> and only the
>
> Which github repository are you talking about?
>
> The Linux4SAM github contains all that is need to work with sama5d2
> (linux-4.1-at91 branch):
> https://github.com/linux4sam/linux-at91/tree/linux-4.1-at91

That's the one. My point is that there is no hint in there that Wenyou worked
on supporting the NAND controller for SAMA5D2. So I wondered if there were
other repositories I missed with more recent information.

> Developments in progress are listed in the Linux4SAM page:
> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage
>
> I admit that it's not copleted, but you'll have an idea here as well:
> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage
>
Both URLs are the same, are you sure it's the correct link? It's a very
informative page and I often use it when I need information on the SAMA5D2.
But I have a hard time finding something about work in progress in it.


Best regards,
-- 
Romain Izard
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Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

2016-01-13 12:46 GMT+01:00 Nicolas Ferre <nicolas.ferre@atmel.com>:
>> Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's
>> atmel address now bounces, and it is still referenced there.
>
> It's already done and pushed to arm-soc. It's in linux-next:
> http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/MAINTAINERS#n2000
>
> It will appear in Linus' tree in a couple of days ;-)
>
Good. As I based my developments on the linux-4.1-at91 branch from the Linux4SAM
github which does not contain the update, I missed it.

>>> I also think that Wenyou did some work regarding this support. So you'll
>>> have to coordinat together.
>>
>> Is it possible to know what are the developments in progress regarding
>> SAMA5D2 drivers? The github repository does not expose any working trees,
>> and only the
>
> Which github repository are you talking about?
>
> The Linux4SAM github contains all that is need to work with sama5d2
> (linux-4.1-at91 branch):
> https://github.com/linux4sam/linux-at91/tree/linux-4.1-at91

That's the one. My point is that there is no hint in there that Wenyou worked
on supporting the NAND controller for SAMA5D2. So I wondered if there were
other repositories I missed with more recent information.

> Developments in progress are listed in the Linux4SAM page:
> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage
>
> I admit that it's not copleted, but you'll have an idea here as well:
> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage
>
Both URLs are the same, are you sure it's the correct link? It's a very
informative page and I often use it when I need information on the SAMA5D2.
But I have a hard time finding something about work in progress in it.


Best regards,
-- 
Romain Izard

Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 13/01/2016 13:56, Romain Izard a écrit :
> 2016-01-13 12:46 GMT+01:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>>> Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's
>>> atmel address now bounces, and it is still referenced there.
>>
>> It's already done and pushed to arm-soc. It's in linux-next:
>> http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/MAINTAINERS#n2000
>>
>> It will appear in Linus' tree in a couple of days ;-)
>>
> Good. As I based my developments on the linux-4.1-at91 branch from the Linux4SAM
> github which does not contain the update, I missed it.
> 
>>>> I also think that Wenyou did some work regarding this support. So you'll
>>>> have to coordinat together.
>>>
>>> Is it possible to know what are the developments in progress regarding
>>> SAMA5D2 drivers? The github repository does not expose any working trees,
>>> and only the
>>
>> Which github repository are you talking about?
>>
>> The Linux4SAM github contains all that is need to work with sama5d2
>> (linux-4.1-at91 branch):
>> https://github.com/linux4sam/linux-at91/tree/linux-4.1-at91
> 
> That's the one. My point is that there is no hint in there that Wenyou worked
> on supporting the NAND controller for SAMA5D2. So I wondered if there were
> other repositories I missed with more recent information.

Yes, that's very recent actually and we were testing internally just
before releasing it.
The reason is also that we didn't have a NAND flash on our reference
platform which is the SAMA5D2 Xplained. So we had to wait for a new
hardware from our colleagues of the HW team and bring it up before
working on this NAND flash support (24 bits ECC and sama5d2 new
modifications in fact).

>> Developments in progress are listed in the Linux4SAM page:
>> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage
>>
>> I admit that it's not copleted, but you'll have an idea here as well:
>> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage

Yes, I was meaning:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/LinuxKernel#Tags

> Both URLs are the same, are you sure it's the correct link? It's a very
> informative page and I often use it when I need information on the SAMA5D2.
> But I have a hard time finding something about work in progress in it.

Yes, we lack this kind of important information. It's scattered on some
messages on the arm-linux-kernel mailing-list as we tend to publish
pretty early in our work process (Cf. the new ADC driver by Ludovic). I
don't promise but we will try to enhance this aspect in the near
future... ;-)

Thanks for your work and your feedback.

Bye,
-- 
Nicolas Ferre
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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Re: [RFC PATCH 0/4] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 13/01/2016 13:56, Romain Izard a écrit :
> 2016-01-13 12:46 GMT+01:00 Nicolas Ferre <nicolas.ferre@atmel.com>:
>>> Ok. It might be a good idea to update the MAINTAINERS file, as Josh Wu's
>>> atmel address now bounces, and it is still referenced there.
>>
>> It's already done and pushed to arm-soc. It's in linux-next:
>> http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/MAINTAINERS#n2000
>>
>> It will appear in Linus' tree in a couple of days ;-)
>>
> Good. As I based my developments on the linux-4.1-at91 branch from the Linux4SAM
> github which does not contain the update, I missed it.
> 
>>>> I also think that Wenyou did some work regarding this support. So you'll
>>>> have to coordinat together.
>>>
>>> Is it possible to know what are the developments in progress regarding
>>> SAMA5D2 drivers? The github repository does not expose any working trees,
>>> and only the
>>
>> Which github repository are you talking about?
>>
>> The Linux4SAM github contains all that is need to work with sama5d2
>> (linux-4.1-at91 branch):
>> https://github.com/linux4sam/linux-at91/tree/linux-4.1-at91
> 
> That's the one. My point is that there is no hint in there that Wenyou worked
> on supporting the NAND controller for SAMA5D2. So I wondered if there were
> other repositories I missed with more recent information.

Yes, that's very recent actually and we were testing internally just
before releasing it.
The reason is also that we didn't have a NAND flash on our reference
platform which is the SAMA5D2 Xplained. So we had to wait for a new
hardware from our colleagues of the HW team and bring it up before
working on this NAND flash support (24 bits ECC and sama5d2 new
modifications in fact).

>> Developments in progress are listed in the Linux4SAM page:
>> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage
>>
>> I admit that it's not copleted, but you'll have an idea here as well:
>> http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d2XplainedMainPage

Yes, I was meaning:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/LinuxKernel#Tags

> Both URLs are the same, are you sure it's the correct link? It's a very
> informative page and I often use it when I need information on the SAMA5D2.
> But I have a hard time finding something about work in progress in it.

Yes, we lack this kind of important information. It's scattered on some
messages on the arm-linux-kernel mailing-list as we tend to publish
pretty early in our work process (Cf. the new ADC driver by Ludovic). I
don't promise but we will try to enhance this aspect in the near
future... ;-)

Thanks for your work and your feedback.

Bye,
-- 
Nicolas Ferre

Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Nicolas Ferre]

Le 13/01/2016 13:39, Yang, Wenyou a écrit :
> Hi Romain,
> 
> Confirmed. 
> 
> You are right. The tables are accessible.

Yes, confirmed by my colleague who wrote the ROMCode. It's different
from the sama5d4.

Gallois fields in ROM on sama5d2:

512 Bytes:  @ 0x40000 (32 KBytes)
1024 Bytes: @ 0x48000 (96 KBytes)

even if the datasheet is not completely updated yet...

Bye,


> Please ignore my comments.
> 
> 
> Best Regards,
> Wenyou Yang
> 
>> -----Original Message-----
>> From: Yang, Wenyou
>> Sent: 2016年1月13日 19:29
>> To: 'romain izard' <romain.izard-Tny/h2m1dROW3RwJEphJ61AUjnlXr6A1@public.gmane.org>
>> Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Ferre, Nicolas
>> <Nicolas.FERRE-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
>> Subject: RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
>> nodes
>>
>> Hi Romain,
>>
>>> -----Original Message-----
>>> From: romain izard [mailto:romain.izard-Tny/h2m1dROW3RwJEphJ61AUjnlXr6A1@public.gmane.org]
>>> Sent: 2016年1月13日 17:41
>>> To: Yang, Wenyou <Wenyou.Yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
>>> Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Ferre,
>>> Nicolas <Nicolas.FERRE-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
>>> Subject: Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
>>> nodes
>>>
>>> 2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>>>>
>>>>> -----Original Message-----
>>>>> From: linux-mtd [mailto:linux-mtd-bounces-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org] On
>>>>> Behalf Of Romain Izard
>>>>> Sent: 2016年1月12日 22:34
>>>>> To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>>>> Cc: Wu, Josh <Josh.wu-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>; Romain Izard
>>>>> <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>; Ferre, Nicolas
>>>>> <Nicolas.FERRE-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
>>>>> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
>>>>> nodes
>>>>>
>>>>> Both nodes are required to access NAND Flash memory. Additional
>>>>> settings will be necessary at the board level to use it.
>>>>>
>>>>> Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>>>> ---
>>>>>  arch/arm/boot/dts/sama5d2.dtsi | 38
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>>  1 file changed, 38 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sama5d2.dtsi
>>>>> b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a
>>>>> 100644
>>>>> --- a/arch/arm/boot/dts/sama5d2.dtsi
>>>>> +++ b/arch/arm/boot/dts/sama5d2.dtsi
>>>>> @@ -265,6 +265,44 @@
>>>>>                       cache-level = <2>;
>>>>>               };
>>>>>
>>>>> +             nand0: nand@80000000 {
>>>>> +                     compatible = "atmel,sama5d2-nand";
>>>>> +                     #address-cells = <1>;
>>>>> +                     #size-cells = <1>;
>>>>> +                     ranges;
>>>>> +                     reg = < /* EBI CS3 */
>>>>> +                             0x80000000 0x08000000
>>>>> +                             /* SMC PMECC regs */
>>>>> +                             0xf8014070 0x00000490
>>>>> +                             /* SMC PMECC Error Location regs */
>>>>> +                             0xf8014500 0x00000200
>>>>> +                             /* ROM Galois tables */
>>>>> +                             0x00040000 0x00018000
>>>>
>>>> As there is no PMECC lookup table in ROM exported, remove this line.
>>>>
>>>
>>> From what I see in the SAMA5D2 xplained board on my table, it is not the case.
>>> Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data that
>>> looks identical to the Galois tables in the Atmel example code.
>>>
>>> U-Boot> md.w 0x40000
>>> 00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
>>> 00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
>>> 00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
>>> 00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
>>> 00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
>>> 00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
>>> 00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
>>> 00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527
>>>
>>> U-Boot> md.w 0x48000
>>> 00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
>>> 00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
>>> 00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
>>> 00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
>>> 00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
>>> 00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
>>> 00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
>>> 00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828
>>>
>>>
>>> This location matches the information in the SAMA5D2 datasheet from
>>> chapter 6, "Memories", but not the contradicting information from
>>> chapter 14, "Standard Boot Strategies".
>>
>> As I known, the Galois Field Table should not exported since SAMA5D4, I will
>> check with the system team.
>>
>>>
>>>>> +                             >;
>>>>> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
>>>>> +                     atmel,nand-addr-offset = <21>;
>>>>> +                     atmel,nand-cmd-offset = <22>;
>>>>> +                     atmel,nand-has-dma;
>>>>> +                     atmel,has-pmecc;
>>>>> +                     atmel,pmecc-lookup-table-offset = <0x0
>>>>> + 0x8000>;
>>>>
>>>> Ditto, remove this line.
>>>>
>>>>> +                     status = "disabled";
>>>>> +
>>>>> +                     nfc@90000000 {
>>>>> +                             compatible = "atmel,sama5d4-nfc";
>>>>> +                             #address-cells = <1>;
>>>>> +                             #size-cells = <1>;
>>>>> +                             reg = < /* NFC Command Registers */
>>>>> +                                     0xC0000000 0x08000000
>>>>> +                                     /* NFC HSMC regs */
>>>>> +                                     0xf8014000 0x00000070
>>>>> +                                     /* NFC SRAM banks */
>>>>> +                                     0x00100000 0x00100000
>>>>> +                                     >;
>>>>> +                             clocks = <&hsmc_clk>;
>>>>> +                             atmel,write-by-sram;
>>>>> +                     };
>>>>> +             };
>>>>> +
>>>>>               sdmmc0: sdio-host@a0000000 {
>>>>>                       compatible = "atmel,sama5d2-sdhci";
>>>>>                       reg = <0xa0000000 0x300>;
>>>>> --
>>>>> 2.5.0
>>>>>
>>>
>>>
>>> Best regards
>>> --
>>> Romain Izard
>>
>>
>> Best Regards,
>> Wenyou Yang


-- 
Nicolas Ferre
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Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Nicolas Ferre]

Le 13/01/2016 13:39, Yang, Wenyou a écrit :
> Hi Romain,
> 
> Confirmed. 
> 
> You are right. The tables are accessible.

Yes, confirmed by my colleague who wrote the ROMCode. It's different
from the sama5d4.

Gallois fields in ROM on sama5d2:

512 Bytes:  @ 0x40000 (32 KBytes)
1024 Bytes: @ 0x48000 (96 KBytes)

even if the datasheet is not completely updated yet...

Bye,


> Please ignore my comments.
> 
> 
> Best Regards,
> Wenyou Yang
> 
>> -----Original Message-----
>> From: Yang, Wenyou
>> Sent: 2016年1月13日 19:29
>> To: 'romain izard' <romain.izard@mobile-devices.fr>
>> Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre, Nicolas
>> <Nicolas.FERRE@atmel.com>
>> Subject: RE: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
>> nodes
>>
>> Hi Romain,
>>
>>> -----Original Message-----
>>> From: romain izard [mailto:romain.izard@mobile-devices.fr]
>>> Sent: 2016年1月13日 17:41
>>> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
>>> Cc: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org; Ferre,
>>> Nicolas <Nicolas.FERRE@atmel.com>
>>> Subject: Re: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
>>> nodes
>>>
>>> 2016-01-13 7:06 GMT+01:00 Yang, Wenyou <Wenyou.Yang@atmel.com>:
>>>>
>>>>> -----Original Message-----
>>>>> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On
>>>>> Behalf Of Romain Izard
>>>>> Sent: 2016年1月12日 22:34
>>>>> To: linux-mtd@lists.infradead.org; devicetree@vger.kernel.org
>>>>> Cc: Wu, Josh <Josh.wu@atmel.com>; Romain Izard
>>>>> <romain.izard.pro@gmail.com>; Ferre, Nicolas
>>>>> <Nicolas.FERRE@atmel.com>
>>>>> Subject: [RFC PATCH 4/4] ARM: at91/dt: sama5d2: add nand0 and nfc0
>>>>> nodes
>>>>>
>>>>> Both nodes are required to access NAND Flash memory. Additional
>>>>> settings will be necessary at the board level to use it.
>>>>>
>>>>> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
>>>>> ---
>>>>>  arch/arm/boot/dts/sama5d2.dtsi | 38
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>>  1 file changed, 38 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sama5d2.dtsi
>>>>> b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a
>>>>> 100644
>>>>> --- a/arch/arm/boot/dts/sama5d2.dtsi
>>>>> +++ b/arch/arm/boot/dts/sama5d2.dtsi
>>>>> @@ -265,6 +265,44 @@
>>>>>                       cache-level = <2>;
>>>>>               };
>>>>>
>>>>> +             nand0: nand@80000000 {
>>>>> +                     compatible = "atmel,sama5d2-nand";
>>>>> +                     #address-cells = <1>;
>>>>> +                     #size-cells = <1>;
>>>>> +                     ranges;
>>>>> +                     reg = < /* EBI CS3 */
>>>>> +                             0x80000000 0x08000000
>>>>> +                             /* SMC PMECC regs */
>>>>> +                             0xf8014070 0x00000490
>>>>> +                             /* SMC PMECC Error Location regs */
>>>>> +                             0xf8014500 0x00000200
>>>>> +                             /* ROM Galois tables */
>>>>> +                             0x00040000 0x00018000
>>>>
>>>> As there is no PMECC lookup table in ROM exported, remove this line.
>>>>
>>>
>>> From what I see in the SAMA5D2 xplained board on my table, it is not the case.
>>> Reading at addresses 0x40000 and 0x48000 from U-Boot, I see data that
>>> looks identical to the Galois tables in the Atmel example code.
>>>
>>> U-Boot> md.w 0x40000
>>> 00040000: ffff 0000 0001 03a6 0002 074c 03a7 18c0
>>> 00040010: 0003 1c66 074d 01ea 03a8 005d 18c1 0af2
>>> 00040020: 0004 0e98 1c67 183e 074e 1181 01eb 0403
>>> 00040030: 03a9 119c 005e 000d 18c2 0590 0af3 1877
>>> 00040040: 0005 1c1d 0e99 191d 1c68 0d6f 183f 0936
>>> 00040050: 074f 13d9 1182 1542 01ec 03b3 0404 1395
>>> 00040060: 03aa 1aaa 119d 123e 005f 1be4 000e 0bda
>>> 00040070: 18c3 07a9 0591 1d35 0af4 19ae 1878 1527
>>>
>>> U-Boot> md.w 0x48000
>>> 00048000: ffff 0000 0001 0572 0002 0ae4 0573 015b
>>> 00048010: 0003 06cd 0ae5 1ad9 0574 012e 015c 1056
>>> 00048020: 0004 15c8 06ce 288d 0ae6 02b6 1ada 06a0
>>> 00048030: 0575 2ed2 012f 0c3f 015d 204b 1057 3812
>>> 00048040: 0005 3d84 15c9 0289 06cf 347d 288e 25bd
>>> 00048050: 0ae7 10d1 02b7 3444 1adb 11b1 06a1 109c
>>> 00048060: 0576 1c34 2ed3 1b3a 0130 2dff 0c40 2238
>>> 00048070: 015e 0c12 204c 3d67 1058 3f47 3813 0828
>>>
>>>
>>> This location matches the information in the SAMA5D2 datasheet from
>>> chapter 6, "Memories", but not the contradicting information from
>>> chapter 14, "Standard Boot Strategies".
>>
>> As I known, the Galois Field Table should not exported since SAMA5D4, I will
>> check with the system team.
>>
>>>
>>>>> +                             >;
>>>>> +                     interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
>>>>> +                     atmel,nand-addr-offset = <21>;
>>>>> +                     atmel,nand-cmd-offset = <22>;
>>>>> +                     atmel,nand-has-dma;
>>>>> +                     atmel,has-pmecc;
>>>>> +                     atmel,pmecc-lookup-table-offset = <0x0
>>>>> + 0x8000>;
>>>>
>>>> Ditto, remove this line.
>>>>
>>>>> +                     status = "disabled";
>>>>> +
>>>>> +                     nfc@90000000 {
>>>>> +                             compatible = "atmel,sama5d4-nfc";
>>>>> +                             #address-cells = <1>;
>>>>> +                             #size-cells = <1>;
>>>>> +                             reg = < /* NFC Command Registers */
>>>>> +                                     0xC0000000 0x08000000
>>>>> +                                     /* NFC HSMC regs */
>>>>> +                                     0xf8014000 0x00000070
>>>>> +                                     /* NFC SRAM banks */
>>>>> +                                     0x00100000 0x00100000
>>>>> +                                     >;
>>>>> +                             clocks = <&hsmc_clk>;
>>>>> +                             atmel,write-by-sram;
>>>>> +                     };
>>>>> +             };
>>>>> +
>>>>>               sdmmc0: sdio-host@a0000000 {
>>>>>                       compatible = "atmel,sama5d2-sdhci";
>>>>>                       reg = <0xa0000000 0x300>;
>>>>> --
>>>>> 2.5.0
>>>>>
>>>
>>>
>>> Best regards
>>> --
>>> Romain Izard
>>
>>
>> Best Regards,
>> Wenyou Yang


-- 
Nicolas Ferre

Re: [RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Rob Herring]

On Tue, Jan 12, 2016 at 03:33:41PM +0100, Romain Izard wrote:
> The NFC controller used to accelerate the NAND transfers on SAMA5 chips
> can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.
> 
> Use the controller's compatible string to select the correct bit.
> 
> Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

>  drivers/mtd/nand/atmel_nand.c                      | 39 +++++++++++++++++-----
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  5 ++-
>  3 files changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 7d4c8eb775a5..89b0db9801b0 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -34,7 +34,7 @@ Optional properties:
>  - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
>  - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
>    - Required properties:
> -    - compatible : "atmel,sama5d3-nfc".
> +    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
>      - reg : should specify the address and size used for NFC command registers,
>              NFC registers and NFC Sram. NFC Sram address and size can be absent
>              if don't want to use it.
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 9d71f9e6a8de..e5d7e7e63f49 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -67,6 +67,10 @@ struct atmel_nand_caps {
>  	bool pmecc_correct_erase_page;
>  };
>  
> +struct atmel_nand_nfc_priv {
> +	uint32_t rb_edge;
> +};
> +
>  /* oob layout for large page size
>   * bad block info is on bytes 0 and 1
>   * the bytes have to be consecutives to avoid
> @@ -111,6 +115,7 @@ struct atmel_nfc {
>  	/* Point to the sram bank which include readed data via NFC */
>  	void			*data_in_sram;
>  	bool			will_write_sram;
> +	uint32_t		rb_edge;
>  };
>  static struct atmel_nfc	nand_nfc;
>  
> @@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
>  		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
>  		ret = IRQ_HANDLED;
>  	}
> -	if (pending & NFC_SR_RB_EDGE) {
> +	if (pending & host->nfc->rb_edge) {
>  		complete(&host->nfc->comp_ready);
> -		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
> +		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->rb_edge);
>  		ret = IRQ_HANDLED;
>  	}
>  	if (pending & NFC_SR_CMD_DONE) {
> @@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		init_completion(&host->nfc->comp_xfer_done);
>  
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		init_completion(&host->nfc->comp_ready);
>  
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		comp[index++] = &host->nfc->comp_xfer_done;
>  
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		comp[index++] = &host->nfc->comp_ready;
>  
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
>  		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
>  				mask & status);
>  
> -	return status & NFC_SR_RB_EDGE;
> +	return status & host->nfc->rb_edge;
>  }
>  
>  static void nfc_select_chip(struct mtd_info *mtd, int chip)
> @@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>  		}
>  		/* fall through */
>  	default:
> -		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
> -		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
> +		nfc_prepare_interrupt(host, host->nfc->rb_edge);
> +		nfc_wait_interrupt(host, host->nfc->rb_edge);
>  	}
>  }
>  
> @@ -2318,9 +2323,12 @@ static const struct of_device_id atmel_nand_dt_ids[] = {
>  
>  MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
>  
> +static const struct of_device_id atmel_nand_nfc_match[];
> +
>  static int atmel_nand_nfc_probe(struct platform_device *pdev)
>  {
>  	struct atmel_nfc *nfc = &nand_nfc;
> +	const struct atmel_nand_nfc_priv *priv;
>  	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
>  	int ret;
>  
> @@ -2352,6 +2360,12 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	priv = of_match_device(atmel_nand_nfc_match, &pdev->dev)->data;
> +	if (NULL == priv)
> +		return -ENODEV;
> +
> +	nfc->rb_edge = priv->rb_edge;
> +
>  	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
>  	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
>  
> @@ -2380,8 +2394,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static struct atmel_nand_nfc_priv sama5d3_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE0,
> +};
> +
> +static struct atmel_nand_nfc_priv sama5d4_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE3,
> +};
> +
>  static const struct of_device_id atmel_nand_nfc_match[] = {
> -	{ .compatible = "atmel,sama5d3-nfc" },
> +	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_priv },
> +	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_priv },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
> diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
> index 4d5d26221a7e..2cd9c57b1e53 100644
> --- a/drivers/mtd/nand/atmel_nand_nfc.h
> +++ b/drivers/mtd/nand/atmel_nand_nfc.h
> @@ -42,7 +42,10 @@
>  #define		NFC_SR_UNDEF		(1 << 21)
>  #define		NFC_SR_AWB		(1 << 22)
>  #define		NFC_SR_ASE		(1 << 23)
> -#define		NFC_SR_RB_EDGE		(1 << 24)
> +#define		NFC_SR_RB_EDGE0		(1 << 24)
> +#define		NFC_SR_RB_EDGE1		(1 << 25)
> +#define		NFC_SR_RB_EDGE2		(1 << 26)
> +#define		NFC_SR_RB_EDGE3		(1 << 27)
>  
>  #define ATMEL_HSMC_NFC_IER	0x0c
>  #define ATMEL_HSMC_NFC_IDR	0x10
> -- 
> 2.5.0
> 
> --
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Re: [RFC PATCH 2/4] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Rob Herring]

On Tue, Jan 12, 2016 at 03:33:41PM +0100, Romain Izard wrote:
> The NFC controller used to accelerate the NAND transfers on SAMA5 chips
> can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.
> 
> Use the controller's compatible string to select the correct bit.
> 
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> ---
>  .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mtd/nand/atmel_nand.c                      | 39 +++++++++++++++++-----
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  5 ++-
>  3 files changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 7d4c8eb775a5..89b0db9801b0 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -34,7 +34,7 @@ Optional properties:
>  - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
>  - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
>    - Required properties:
> -    - compatible : "atmel,sama5d3-nfc".
> +    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
>      - reg : should specify the address and size used for NFC command registers,
>              NFC registers and NFC Sram. NFC Sram address and size can be absent
>              if don't want to use it.
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 9d71f9e6a8de..e5d7e7e63f49 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -67,6 +67,10 @@ struct atmel_nand_caps {
>  	bool pmecc_correct_erase_page;
>  };
>  
> +struct atmel_nand_nfc_priv {
> +	uint32_t rb_edge;
> +};
> +
>  /* oob layout for large page size
>   * bad block info is on bytes 0 and 1
>   * the bytes have to be consecutives to avoid
> @@ -111,6 +115,7 @@ struct atmel_nfc {
>  	/* Point to the sram bank which include readed data via NFC */
>  	void			*data_in_sram;
>  	bool			will_write_sram;
> +	uint32_t		rb_edge;
>  };
>  static struct atmel_nfc	nand_nfc;
>  
> @@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
>  		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
>  		ret = IRQ_HANDLED;
>  	}
> -	if (pending & NFC_SR_RB_EDGE) {
> +	if (pending & host->nfc->rb_edge) {
>  		complete(&host->nfc->comp_ready);
> -		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
> +		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->rb_edge);
>  		ret = IRQ_HANDLED;
>  	}
>  	if (pending & NFC_SR_CMD_DONE) {
> @@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		init_completion(&host->nfc->comp_xfer_done);
>  
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		init_completion(&host->nfc->comp_ready);
>  
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
>  	if (flag & NFC_SR_XFR_DONE)
>  		comp[index++] = &host->nfc->comp_xfer_done;
>  
> -	if (flag & NFC_SR_RB_EDGE)
> +	if (flag & host->nfc->rb_edge)
>  		comp[index++] = &host->nfc->comp_ready;
>  
>  	if (flag & NFC_SR_CMD_DONE)
> @@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
>  		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
>  				mask & status);
>  
> -	return status & NFC_SR_RB_EDGE;
> +	return status & host->nfc->rb_edge;
>  }
>  
>  static void nfc_select_chip(struct mtd_info *mtd, int chip)
> @@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
>  		}
>  		/* fall through */
>  	default:
> -		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
> -		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
> +		nfc_prepare_interrupt(host, host->nfc->rb_edge);
> +		nfc_wait_interrupt(host, host->nfc->rb_edge);
>  	}
>  }
>  
> @@ -2318,9 +2323,12 @@ static const struct of_device_id atmel_nand_dt_ids[] = {
>  
>  MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
>  
> +static const struct of_device_id atmel_nand_nfc_match[];
> +
>  static int atmel_nand_nfc_probe(struct platform_device *pdev)
>  {
>  	struct atmel_nfc *nfc = &nand_nfc;
> +	const struct atmel_nand_nfc_priv *priv;
>  	struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
>  	int ret;
>  
> @@ -2352,6 +2360,12 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	priv = of_match_device(atmel_nand_nfc_match, &pdev->dev)->data;
> +	if (NULL == priv)
> +		return -ENODEV;
> +
> +	nfc->rb_edge = priv->rb_edge;
> +
>  	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
>  	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
>  
> @@ -2380,8 +2394,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static struct atmel_nand_nfc_priv sama5d3_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE0,
> +};
> +
> +static struct atmel_nand_nfc_priv sama5d4_nfc_priv = {
> +	.rb_edge = NFC_SR_RB_EDGE3,
> +};
> +
>  static const struct of_device_id atmel_nand_nfc_match[] = {
> -	{ .compatible = "atmel,sama5d3-nfc" },
> +	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_priv },
> +	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_priv },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
> diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
> index 4d5d26221a7e..2cd9c57b1e53 100644
> --- a/drivers/mtd/nand/atmel_nand_nfc.h
> +++ b/drivers/mtd/nand/atmel_nand_nfc.h
> @@ -42,7 +42,10 @@
>  #define		NFC_SR_UNDEF		(1 << 21)
>  #define		NFC_SR_AWB		(1 << 22)
>  #define		NFC_SR_ASE		(1 << 23)
> -#define		NFC_SR_RB_EDGE		(1 << 24)
> +#define		NFC_SR_RB_EDGE0		(1 << 24)
> +#define		NFC_SR_RB_EDGE1		(1 << 25)
> +#define		NFC_SR_RB_EDGE2		(1 << 26)
> +#define		NFC_SR_RB_EDGE3		(1 << 27)
>  
>  #define ATMEL_HSMC_NFC_IER	0x0c
>  #define ATMEL_HSMC_NFC_IDR	0x10
> -- 
> 2.5.0
> 
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