* [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4
@ 2016-01-12 20:48 Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 1/6] net: pcnet: refactor mapping of virtual addresses to physical ones Daniel Schwierzeck
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
This patch series updates all MIPS asm header files containing
I/O code as well as processor, register and assembly definitions.
The source of the update are the MIPS asm header files of linux-4.4.
The main goal is to get a complete set of I/O accessors on MIPS and
to support platform-specific address spaces and mappings. Also a
working ioremap() implementation will be added, which supports
platform-specific callbacks. Furthermore support for bit manipulating
I/O accessors (clrbits_X, setbits_X, clrsetbits_X) will be added.
The patch series is also available on git://git.denx.de/u-boot-mips.git
in branch mips_io_v2 and based on next branch.
Changes in v3:
- newly added due to a regression on MIPS Malta board
- rebased to u-boot-mips/next
Changes in v2:
- fix __ioremap_node() implementation for 64 Bit
Daniel Schwierzeck (6):
net: pcnet: refactor mapping of virtual addresses to physical ones
MIPS: sync I/O related header files with linux-4.4
MIPS: sync processor and register definitions with linux-4.4
MIPS: fix SPDX license identifier in remaining arch header files
MIPS: implement bit manipulating I/O accessors
MIPS: DO NOT MERGE: test I/O accessors
arch/mips/Makefile | 5 +-
arch/mips/include/asm/addrspace.h | 10 +-
arch/mips/include/asm/asm.h | 126 +-
arch/mips/include/asm/bitops.h | 6 +-
arch/mips/include/asm/byteorder.h | 6 +-
arch/mips/include/asm/cachectl.h | 6 +-
arch/mips/include/asm/cacheops.h | 6 +-
arch/mips/include/asm/const.h | 31 +
arch/mips/include/asm/cpu-features.h | 30 +
arch/mips/include/asm/io.h | 813 ++++++-----
arch/mips/include/asm/isadep.h | 6 +-
.../asm/mach-generic/cpu-feature-overrides.h | 11 +
arch/mips/include/asm/mach-generic/ioremap.h | 32 +
arch/mips/include/asm/mach-generic/mangle-port.h | 50 +
arch/mips/include/asm/mach-generic/spaces.h | 102 ++
arch/mips/include/asm/mipsregs.h | 1495 ++++++++++++++------
arch/mips/include/asm/pgtable-bits.h | 283 ++++
arch/mips/include/asm/posix_types.h | 9 +-
arch/mips/include/asm/processor.h | 6 +-
arch/mips/include/asm/ptrace.h | 99 +-
arch/mips/include/asm/reboot.h | 6 +-
arch/mips/include/asm/reg.h | 6 +-
arch/mips/include/asm/regdef.h | 12 +-
arch/mips/include/asm/sgidefs.h | 6 +-
arch/mips/include/asm/string.h | 6 +-
arch/mips/include/asm/system.h | 6 +-
arch/mips/include/asm/types.h | 6 +-
arch/mips/include/asm/unaligned.h | 6 +-
arch/mips/lib/cache.c | 4 +-
arch/mips/lib/cache_init.S | 16 +-
arch/mips/lib/io.c | 183 +++
drivers/net/pcnet.c | 28 +-
32 files changed, 2440 insertions(+), 977 deletions(-)
create mode 100644 arch/mips/include/asm/const.h
create mode 100644 arch/mips/include/asm/cpu-features.h
create mode 100644 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
create mode 100644 arch/mips/include/asm/mach-generic/ioremap.h
create mode 100644 arch/mips/include/asm/mach-generic/mangle-port.h
create mode 100644 arch/mips/include/asm/mach-generic/spaces.h
create mode 100644 arch/mips/include/asm/pgtable-bits.h
--
2.5.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 1/6] net: pcnet: refactor mapping of virtual addresses to physical ones
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
@ 2016-01-12 20:48 ` Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 2/6] MIPS: sync I/O related header files with linux-4.4 Daniel Schwierzeck
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
pci_virt_to_mem() uses virt_to_phys() to get the physical address.
But pci_virt_to_mem() is also called with uncached addresses which
is wrong according to the documentation of virt_to_phys().
Refactor the PCI_TO_MEM() macro to optionally map an uncached address
back to a cached one before calling pci_virt_to_mem().
Currently pcnet works because virt_to_phys() is incorrectly implemented
on MIPS. With the upcoming asm header file update for MIPS, the
virt_to_phys() implementation will be fixed. Thus this patch is needed
to keep pcnet working on MIPS Malta board.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
@Joe, MIPS Malta board is the only user of pcnet and the patch is required
for my patch series which updates the MIPS asm header files. Thus I'd like
to merge this via the MIPS tree.
Changes in v3:
- newly added due to a regression on MIPS Malta board
Changes in v2: None
drivers/net/pcnet.c | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index cfcb1b4..16a7512 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -134,8 +134,17 @@ static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
-#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
-#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
+static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
+ void *addr, bool uncached)
+{
+ pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+ void *virt_addr = addr;
+
+ if (uncached)
+ virt_addr = (void *)CKSEG0ADDR(addr);
+
+ return pci_virt_to_mem(devbusfn, virt_addr);
+}
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
@@ -352,7 +361,8 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]);
+ addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+ uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1
@@ -383,8 +393,10 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
- uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
+ addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+ uc->init_block.rx_ring = cpu_to_le32(addr);
+ addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+ uc->init_block.tx_ring = cpu_to_le32(addr);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
uc->init_block.tlen_rlen,
@@ -394,7 +406,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
* Tell the controller where the Init Block is located.
*/
barrier();
- addr = PCI_TO_MEM(dev, &lp->uc->init_block);
+ addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
pcnet_write_csr(dev, 1, addr & 0xffff);
pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
@@ -424,6 +436,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
int i, status;
+ u32 addr;
struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
@@ -451,9 +464,10 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
+ addr = pcnet_virt_to_mem(dev, packet, false);
writew(-pkt_len, &entry->length);
writel(0, &entry->misc);
- writel(PCI_TO_MEM(dev, packet), &entry->base);
+ writel(addr, &entry->base);
writew(0x8300, &entry->status);
/* Trigger an immediate send poll. */
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 2/6] MIPS: sync I/O related header files with linux-4.4
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 1/6] net: pcnet: refactor mapping of virtual addresses to physical ones Daniel Schwierzeck
@ 2016-01-12 20:48 ` Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 3/6] MIPS: sync processor and register definitions " Daniel Schwierzeck
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
Mainly sync asm/io.h to get a working ioremap() implementation
as well as the full set of I/O accessors. Pull in additional
header files to make this work.
Furthermore port over the directory 'arch/mips/include/asm/mach-generic/'
with contains default definitions for I/O and memory spaces and default
implementations for mapping those spaces. All files in that directory
can be overwritten by a SoC/machine.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
Changes in v3: None
Changes in v2:
- fix __ioremap_node() implementation for 64 Bit
arch/mips/Makefile | 5 +-
arch/mips/include/asm/addrspace.h | 4 +-
arch/mips/include/asm/const.h | 27 +
arch/mips/include/asm/cpu-features.h | 30 +
arch/mips/include/asm/io.h | 761 +++++++++++----------
.../asm/mach-generic/cpu-feature-overrides.h | 11 +
arch/mips/include/asm/mach-generic/ioremap.h | 32 +
arch/mips/include/asm/mach-generic/mangle-port.h | 50 ++
arch/mips/include/asm/mach-generic/spaces.h | 102 +++
arch/mips/include/asm/pgtable-bits.h | 283 ++++++++
10 files changed, 941 insertions(+), 364 deletions(-)
create mode 100644 arch/mips/include/asm/const.h
create mode 100644 arch/mips/include/asm/cpu-features.h
create mode 100644 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
create mode 100644 arch/mips/include/asm/mach-generic/ioremap.h
create mode 100644 arch/mips/include/asm/mach-generic/mangle-port.h
create mode 100644 arch/mips/include/asm/mach-generic/spaces.h
create mode 100644 arch/mips/include/asm/pgtable-bits.h
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 90cd590..2133e7e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -25,4 +25,7 @@ tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
-PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
+# Include default header files
+cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
+
+PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index b768bb5..e7fe6ed 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -10,6 +10,8 @@
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
+#include <spaces.h>
+
/*
* Configure language
*/
@@ -50,7 +52,7 @@
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
- _CONST64_(0x000000ffffffffff))
+ _CONST64_(0x0000ffffffffffff))
#ifdef CONFIG_64BIT
diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h
new file mode 100644
index 0000000..c872bfd
--- /dev/null
+++ b/arch/mips/include/asm/const.h
@@ -0,0 +1,27 @@
+/* const.h: Macros for dealing with constants. */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code. Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally. We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define __AC(X,Y) (X##Y)
+#define _AC(X,Y) __AC(X,Y)
+#define _AT(T,X) ((T)(X))
+#endif
+
+#define _BITUL(x) (_AC(1,UL) << (x))
+#define _BITULL(x) (_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
new file mode 100644
index 0000000..a6e9d94
--- /dev/null
+++ b/arch/mips/include/asm/cpu-features.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <cpu-feature-overrides.h>
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 1
+# endif
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index a7ab087..eb06afa 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -1,21 +1,28 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 FSMLabs, Inc.
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
+ * Author: Maciej W. Rozycki <macro@mips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#if 0
-#include <linux/pagemap.h>
-#endif
+#include <linux/compiler.h>
+#include <linux/types.h>
+
#include <asm/addrspace.h>
#include <asm/byteorder.h>
+#include <asm/cpu-features.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+#include <asm/string.h>
+
+#include <ioremap.h>
+#include <mangle-port.h>
+#include <spaces.h>
/*
* Slowdown I/O port space accesses for antique hardware.
@@ -23,44 +30,20 @@
#undef CONF_SLOWDOWN_IO
/*
- * Sane hardware offers swapping of I/O space accesses in hardware; less
- * sane hardware forces software to fiddle with this ...
+ * Raw operations are never swapped in software. OTOH values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware. An example use would be for flash memory that's used for
+ * execute in place.
*/
-#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
+# define __raw_ioswabb(a, x) (x)
+# define __raw_ioswabw(a, x) (x)
+# define __raw_ioswabl(a, x) (x)
+# define __raw_ioswabq(a, x) (x)
+# define ____raw_ioswabq(a, x) (x)
-#define __ioswab8(x) (x)
-#define __ioswab16(x) swab16(x)
-#define __ioswab32(x) swab32(x)
-
-#else
-
-#define __ioswab8(x) (x)
-#define __ioswab16(x) (x)
-#define __ioswab32(x) (x)
-
-#endif
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
-/*
- * This file contains the definitions for the MIPS counterpart of the
- * x86 in/out instructions. This heap of macros and C results in much
- * better code than the approach of doing it in plain C. The macros
- * result in code that is to fast for certain hardware. On the other
- * side the performance of the string functions should be improved for
- * sake of certain devices like EIDE disks that do highspeed polled I/O.
- *
- * Ralf
- *
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
+#define IO_SPACE_LIMIT 0xffff
/*
* On MIPS I/O ports are memory mapped, so we access them using normal
@@ -84,6 +67,7 @@ extern const unsigned long mips_io_port_base;
static inline void set_io_port_base(unsigned long base)
{
* (unsigned long *) &mips_io_port_base = base;
+ barrier();
}
/*
@@ -114,378 +98,429 @@ static inline void set_io_port_base(unsigned long base)
#endif
/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/MIPS mapping
+ * virt_to_phys - map virtual addresses to physical
+ * @address: address to remap
+ *
+ * The returned physical address is the physical (CPU) mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses directly mapped or allocated via kmalloc.
+ *
+ * This function does not give bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
*/
-static inline phys_addr_t virt_to_phys(volatile void * address)
+static inline unsigned long virt_to_phys(volatile const void *address)
{
-#ifndef CONFIG_64BIT
- return CPHYSADDR(address);
+ unsigned long addr = (unsigned long)address;
+
+ /* this corresponds to kernel implementation of __pa() */
+#ifdef CONFIG_64BIT
+ if (addr < CKSEG0)
+ return XPHYSADDR(addr);
+
+ return CPHYSADDR(addr);
#else
- return XPHYSADDR(address);
+ return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
}
-static inline void * phys_to_virt(unsigned long address)
+/*
+ * phys_to_virt - map physical address to virtual
+ * @address: address to remap
+ *
+ * The returned virtual address is a current CPU mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses that have a kernel mapping
+ *
+ * This function does not handle bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+static inline void *phys_to_virt(unsigned long address)
{
-#ifndef CONFIG_64BIT
- return (void *)KSEG0ADDR(address);
-#else
- return (void *)CKSEG0ADDR(address);
-#endif
+ return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}
/*
- * IO bus memory addresses are also 1:1 with the physical address
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
*/
-static inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long isa_virt_to_bus(volatile void *address)
{
-#ifndef CONFIG_64BIT
- return CPHYSADDR(address);
-#else
- return XPHYSADDR(address);
-#endif
+ return (unsigned long)address - PAGE_OFFSET;
}
-static inline void * bus_to_virt(unsigned long address)
+static inline void *isa_bus_to_virt(unsigned long address)
{
-#ifndef CONFIG_64BIT
- return (void *)KSEG0ADDR(address);
-#else
- return (void *)CKSEG0ADDR(address);
-#endif
+ return (void *)(address + PAGE_OFFSET);
}
+#define isa_page_to_bus page_to_phys
+
/*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
*/
-extern unsigned long isa_slot_offset;
-
-extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
-#if 0
-static inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
{
- return __ioremap(offset, size, _CACHE_UNCACHED);
-}
+ void __iomem *addr;
+ phys_addr_t phys_addr;
-static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
-{
- return __ioremap(offset, size, _CACHE_UNCACHED);
-}
+ addr = plat_ioremap(offset, size, flags);
+ if (addr)
+ return addr;
-extern void iounmap(void *addr);
-#endif
+ phys_addr = fixup_bigphys_addr(offset, size);
+ return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
+}
/*
- * XXX We need system specific versions of these to handle EISA address bits
- * 24-31 on SNI.
- * XXX more SNI hacks.
+ * ioremap - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
*/
-#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
-#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
-#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
-#define readb(addr) __raw_readb((addr))
-#define readw(addr) __ioswab16(__raw_readw((addr)))
-#define readl(addr) __ioswab32(__raw_readl((addr)))
-
-#define __raw_writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
-#define __raw_writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
-#define __raw_writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
-#define writeb(b, addr) __raw_writeb((b), (addr))
-#define writew(b, addr) __raw_writew(__ioswab16(b), (addr))
-#define writel(b, addr) __raw_writel(__ioswab32(b), (addr))
-
-#define memset_io(a,b,c) memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-
-/* END SNI HACKS ... */
+#define ioremap(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
+ * ioremap_nocache - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * on the CPU as well as honouring existing caching rules from things like
+ * the PCI bus. Note that there are other caches and buffers on many
+ * busses. In particular driver authors should read up on PCI writes
+ *
+ * It's useful if some control registers are in such an area and
+ * write combining or read caching is not desirable:
*/
-#define __ISA_IO_base ((char *)(PAGE_OFFSET))
+#define ioremap_nocache(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+#define ioremap_uc ioremap_nocache
-#define isa_readb(a) readb(a)
-#define isa_readw(a) readw(a)
-#define isa_readl(a) readl(a)
-#define isa_writeb(b,a) writeb(b,a)
-#define isa_writew(w,a) writew(w,a)
-#define isa_writel(l,a) writel(l,a)
-
-#define isa_memset_io(a,b,c) memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
+/*
+ * ioremap_cachable - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU. Also enables full write-combining. Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size) \
+ __ioremap_mode((offset), (size), _page_cachable_default)
/*
- * We don't have csum_partial_copy_fromio() yet, so we cheat here and
- * just copy it. The net code will then do the checksum later.
+ * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
+ * requests a cachable mapping, ioremap_uncached_accelerated requests a
+ * mapping using the uncached accelerated mode which isn't supported on
+ * all processors.
*/
-#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
-#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
+#define ioremap_cacheable_cow(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
-static inline int check_signature(unsigned long io_addr,
- const unsigned char *signature, int length)
+static inline void iounmap(const volatile void __iomem *addr)
{
- int retval = 0;
- do {
- if (readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
+ plat_iounmap(addr);
}
-#define isa_check_signature(io, s, l) check_signature(i,s,l)
-/*
- * Talk about misusing macros..
- */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define war_octeon_io_reorder_wmb() wmb()
+#else
+#define war_octeon_io_reorder_wmb() do { } while (0)
+#endif
-#define __OUT1(s) \
-static inline void __out##s(unsigned int value, unsigned int port) {
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
+ \
+static inline void pfx##write##bwlq(type val, \
+ volatile void __iomem *mem) \
+{ \
+ volatile type *__mem; \
+ type __val; \
+ \
+ war_octeon_io_reorder_wmb(); \
+ \
+ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
+ \
+ __val = pfx##ioswab##bwlq(__mem, val); \
+ \
+ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+ *__mem = __val; \
+ else if (cpu_has_64bits) { \
+ type __tmp; \
+ \
+ __asm__ __volatile__( \
+ ".set arch=r4000" "\t\t# __writeq""\n\t" \
+ "dsll32 %L0, %L0, 0" "\n\t" \
+ "dsrl32 %L0, %L0, 0" "\n\t" \
+ "dsll32 %M0, %M0, 0" "\n\t" \
+ "or %L0, %L0, %M0" "\n\t" \
+ "sd %L0, %2" "\n\t" \
+ ".set mips0" "\n" \
+ : "=r" (__tmp) \
+ : "0" (__val), "m" (*__mem)); \
+ } else \
+ BUG(); \
+} \
+ \
+static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
+{ \
+ volatile type *__mem; \
+ type __val; \
+ \
+ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
+ \
+ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+ __val = *__mem; \
+ else if (cpu_has_64bits) { \
+ __asm__ __volatile__( \
+ ".set arch=r4000" "\t\t# __readq" "\n\t" \
+ "ld %L0, %1" "\n\t" \
+ "dsra32 %M0, %L0, 0" "\n\t" \
+ "sll %L0, %L0, 0" "\n\t" \
+ ".set mips0" "\n" \
+ : "=r" (__val) \
+ : "m" (*__mem)); \
+ } else { \
+ __val = 0; \
+ BUG(); \
+ } \
+ \
+ return pfx##ioswab##bwlq(__mem, __val); \
+}
-#define __OUT2(m) \
-__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
+ \
+static inline void pfx##out##bwlq##p(type val, unsigned long port) \
+{ \
+ volatile type *__addr; \
+ type __val; \
+ \
+ war_octeon_io_reorder_wmb(); \
+ \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ \
+ __val = pfx##ioswab##bwlq(__addr, val); \
+ \
+ /* Really, we want this to be atomic */ \
+ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
+ \
+ *__addr = __val; \
+ slow; \
+} \
+ \
+static inline type pfx##in##bwlq##p(unsigned long port) \
+{ \
+ volatile type *__addr; \
+ type __val; \
+ \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ \
+ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
+ \
+ __val = *__addr; \
+ slow; \
+ \
+ return pfx##ioswab##bwlq(__addr, __val); \
+}
-#define __OUT(m,s,w) \
-__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
-__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
-__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
- SLOW_DOWN_IO; } \
-__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
- SLOW_DOWN_IO; }
+#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
+ \
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
+
+#define BUILDIO_MEM(bwlq, type) \
+ \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
+__BUILD_MEMORY_PFX(, bwlq, type) \
+__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
+
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+
+#define BUILDIO_IOPORT(bwlq, type) \
+ __BUILD_IOPORT_PFX(, bwlq, type) \
+ __BUILD_IOPORT_PFX(__mem_, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
-#define __IN1(t,s) \
-static inline t __in##s(unsigned int port) { t _v;
+#define __BUILDIO(bwlq, type) \
+ \
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
+
+__BUILDIO(q, u64)
+
+#define readb_relaxed readb
+#define readw_relaxed readw
+#define readl_relaxed readl
+#define readq_relaxed readq
+
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
+#define writeq_relaxed writeq
+
+#define readb_be(addr) \
+ __raw_readb((__force unsigned *)(addr))
+#define readw_be(addr) \
+ be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr) \
+ be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr) \
+ be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr) \
+ __raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr) \
+ __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr) \
+ __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr) \
+ __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
/*
- * Required nops will be inserted by the assembler
+ * Some code tests for these symbols
*/
-#define __IN2(m) \
-__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
-
-#define __IN(t,m,s,w) \
-__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
-__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
-__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
-__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
-
-#define __INS1(s) \
-static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-
-#define __INS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,%4(%5)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,(%0)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), \
- "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__INS1(s##c) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), \
- "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-#define __OUTS1(s) \
-static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,(%0)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,%4(%5)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__OUTS1(s##c) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-__IN(unsigned char,b,b,8)
-__IN(unsigned short,h,w,16)
-__IN(unsigned int,w,l,32)
-
-__OUT(b,b,8)
-__OUT(h,w,16)
-__OUT(w,l,32)
-
-__INS(b,b,1)
-__INS(h,w,2)
-__INS(w,l,4)
-
-__OUTS(b,b,1)
-__OUTS(h,w,2)
-__OUTS(w,l,4)
+#define readq readq
+#define writeq writeq
+
+#define __BUILD_MEMORY_STRING(bwlq, type) \
+ \
+static inline void writes##bwlq(volatile void __iomem *mem, \
+ const void *addr, unsigned int count) \
+{ \
+ const volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ __mem_write##bwlq(*__addr, mem); \
+ __addr++; \
+ } \
+} \
+ \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
+ unsigned int count) \
+{ \
+ volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ *__addr = __mem_read##bwlq(mem); \
+ __addr++; \
+ } \
+}
+#define __BUILD_IOPORT_STRING(bwlq, type) \
+ \
+static inline void outs##bwlq(unsigned long port, const void *addr, \
+ unsigned int count) \
+{ \
+ const volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ __mem_out##bwlq(*__addr, port); \
+ __addr++; \
+ } \
+} \
+ \
+static inline void ins##bwlq(unsigned long port, void *addr, \
+ unsigned int count) \
+{ \
+ volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ *__addr = __mem_in##bwlq(port); \
+ __addr++; \
+ } \
+}
-/*
- * Note that due to the way __builtin_constant_p() works, you
- * - can't use it inside an inline function (it will never be true)
- * - you don't have to worry about side effects within the __builtin..
- */
-#define outb(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc((val),(port)) : \
- __outb((val),(port)))
-
-#define inb(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc(port) : \
- __inb(port))
-
-#define outb_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc_p((val),(port)) : \
- __outb_p((val),(port)))
-
-#define inb_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc_p(port) : \
- __inb_p(port))
-
-#define outw(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc((val),(port)) : \
- __outw((val),(port)))
-
-#define inw(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc(port) : \
- __inw(port))
-
-#define outw_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc_p((val),(port)) : \
- __outw_p((val),(port)))
-
-#define inw_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc_p(port) : \
- __inw_p(port))
-
-#define outl(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc((val),(port)) : \
- __outl((val),(port)))
-
-#define inl(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc(port) : \
- __inl(port))
-
-#define outl_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc_p((val),(port)) : \
- __outl_p((val),(port)))
-
-#define inl_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc_p(port) : \
- __inl_p(port))
-
-
-#define outsb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outsbc((port),(addr),(count)) : \
- __outsb ((port),(addr),(count)))
-
-#define insb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __insbc((port),(addr),(count)) : \
- __insb((port),(addr),(count)))
-
-#define outsw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outswc((port),(addr),(count)) : \
- __outsw ((port),(addr),(count)))
-
-#define insw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inswc((port),(addr),(count)) : \
- __insw((port),(addr),(count)))
-
-#define outsl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outslc((port),(addr),(count)) : \
- __outsl ((port),(addr),(count)))
-
-#define insl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inslc((port),(addr),(count)) : \
- __insl((port),(addr),(count)))
+#define BUILDSTRING(bwlq, type) \
+ \
+__BUILD_MEMORY_STRING(bwlq, type) \
+__BUILD_IOPORT_STRING(bwlq, type)
-#define IO_SPACE_LIMIT 0xffff
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
+BUILDSTRING(q, u64)
+#endif
-/*
- * The caches on some architectures aren't dma-coherent and have need to
- * handle this in software. There are three types of operations that
- * can be applied to dma buffers.
- *
- * - dma_cache_wback_inv(start, size) makes caches and coherent by
- * writing the content of the caches back to memory, if necessary.
- * The function also invalidates the affected part of the caches as
- * necessary before DMA transfers from outside to memory.
- * - dma_cache_wback(start, size) makes caches and coherent by
- * writing the content of the caches back to memory, if necessary.
- * The function also invalidates the affected part of the caches as
- * necessary before DMA transfers from outside to memory.
- * - dma_cache_inv(start, size) invalidates the affected parts of the
- * caches. Dirty lines of the caches may be written back or simply
- * be discarded. This operation is necessary before dma operations
- * to the memory.
- */
-extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
-#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
-#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define mmiowb() wmb()
+#else
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+#endif
-static inline void sync(void)
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+ memset((void __force *)addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+ memcpy(dst, (void __force *)src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
+ memcpy((void __force *)dst, src, count);
}
/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
*/
-#define MAP_NOCACHE (0)
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
+
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+
+/*
+ * U-Boot specific
+ */
+#define sync() mmiowb()
+
+#define MAP_NOCACHE (1)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
@@ -493,6 +528,9 @@ static inline void sync(void)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+ if (flags == MAP_NOCACHE)
+ return ioremap(paddr, len);
+
return (void *)paddr;
}
@@ -501,7 +539,6 @@ map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
-
}
#endif /* _ASM_IO_H */
diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
new file mode 100644
index 0000000..613f844
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ... */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
new file mode 100644
index 0000000..6b191d5
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return 0;
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
new file mode 100644
index 0000000..f18e53f
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port) (port)
+#define __swizzle_addr_w(port) (port)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time. Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses. The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) le16_to_cpu(x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) le32_to_cpu(x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) le64_to_cpu(x)
+# define __mem_ioswabq(a, x) (x)
+
+#else
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
new file mode 100644
index 0000000..ab06674
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002 Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <asm/const.h>
+
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET _AC(0, UL)
+#endif
+
+#ifdef CONFIG_32BIT
+#ifdef CONFIG_KVM_GUEST
+#define CAC_BASE _AC(0x40000000, UL)
+#else
+#define CAC_BASE _AC(0x80000000, UL)
+#endif
+#ifndef IO_BASE
+#define IO_BASE _AC(0xa0000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE _AC(0xa0000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#ifdef CONFIG_KVM_GUEST
+#define MAP_BASE _AC(0x60000000, UL)
+#else
+#define MAP_BASE _AC(0xc0000000, UL)
+#endif
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START _AC(0x20000000, UL)
+#endif
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifndef CAC_BASE
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE _AC(0x9800000000000000, UL)
+#else
+#define CAC_BASE _AC(0xa800000000000000, UL)
+#endif
+#endif
+
+#ifndef IO_BASE
+#define IO_BASE _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef UNCAC_BASE
+#define UNCAC_BASE _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#define MAP_BASE _AC(0xc000000000000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future. Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
+#endif
+
+#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
+#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET)
+#endif
+
+#ifndef FIXADDR_TOP
+#ifdef CONFIG_KVM_GUEST
+#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000)
+#else
+#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
+#endif
+#endif
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
new file mode 100644
index 0000000..9e5fa98
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software. We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page. On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things. The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_NO_EXEC_SHIFT 0
+#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK (7 << _CACHE_SHIFT)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT (24)
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+/*
+ * Bits for extended EntryLo0/EntryLo1 registers
+ */
+#define _PFNX_MASK 0xffffff
+
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT (0)
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
+#define _CACHE_MASK _CACHE_UNCACHED
+
+#define _PFN_SHIFT PAGE_SHIFT
+
+#else
+/*
+ * Below are the "Normal" R4K cases
+ */
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT 0
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#else
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#endif
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+/* Huge TLB page */
+#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
+#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
+#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
+#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+/* XI - page cannot be executed */
+#ifdef _PAGE_SPLITTING_SHIFT
+#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
+
+/* RI - page cannot be read */
+#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
+#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
+#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
+#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
+
+#if defined(_PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
+#elif defined(_PAGE_SPLITTING_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK (7 << _CACHE_SHIFT)
+
+#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
+
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC 0
+#endif
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ 0
+#endif
+
+#define _PAGE_SILENT_READ _PAGE_VALID
+#define _PAGE_SILENT_WRITE _PAGE_DIRTY
+
+#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
+
+/*
+ * The final layouts of the PTE bits are:
+ *
+ * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
+ * 32-bit, R1 or earler: CCC D V G M A W R P
+ * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
+ * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
+ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * pte_to_entrylo converts a page table entry (PTE) into a Mips
+ * entrylo0/1 value.
+ */
+static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+{
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+ if (cpu_has_rixi) {
+ int sa;
+#ifdef CONFIG_32BIT
+ sa = 31 - _PAGE_NO_READ_SHIFT;
+#else
+ sa = 63 - _PAGE_NO_READ_SHIFT;
+#endif
+ /*
+ * C has no way to express that this is a DSRL
+ * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
+ * in the fast path this is done in assembly
+ */
+ return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+ ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+ }
+#endif
+
+ return pte_val >> _PAGE_GLOBAL_SHIFT;
+}
+#endif
+
+/*
+ * Cache attributes
+ */
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
+
+#elif defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+ use it for "noncoherent" spaces, too. Shouldn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+
+#elif defined(CONFIG_CPU_LOONGSON3)
+
+/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
+#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
+
+#elif defined(CONFIG_MACH_INGENIC)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
+#endif
+
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
+#endif
+
+#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
+#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
+ _PFN_MASK | _CACHE_MASK)
+
+#endif /* _ASM_PGTABLE_BITS_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 3/6] MIPS: sync processor and register definitions with linux-4.4
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 1/6] net: pcnet: refactor mapping of virtual addresses to physical ones Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 2/6] MIPS: sync I/O related header files with linux-4.4 Daniel Schwierzeck
@ 2016-01-12 20:48 ` Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 4/6] MIPS: fix SPDX license identifier in remaining arch header files Daniel Schwierzeck
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
Update definitions for processor, registers as well as assemby
macros.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
Changes in v3: None
Changes in v2: None
arch/mips/include/asm/asm.h | 126 ++--
arch/mips/include/asm/isadep.h | 6 +-
arch/mips/include/asm/mipsregs.h | 1495 ++++++++++++++++++++++++++-----------
arch/mips/include/asm/processor.h | 6 +-
arch/mips/include/asm/ptrace.h | 99 ++-
arch/mips/include/asm/regdef.h | 12 +-
arch/mips/lib/cache.c | 4 +-
arch/mips/lib/cache_init.S | 16 +-
8 files changed, 1211 insertions(+), 553 deletions(-)
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 8c9c4e2..44694a3 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -1,8 +1,4 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
@@ -13,6 +9,8 @@
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
@@ -33,58 +31,58 @@
* Not used for the kernel but here seems to be the right place.
*/
#ifdef __PIC__
-#define CPRESTORE(register) \
+#define CPRESTORE(register) \
.cprestore register
-#define CPADD(register) \
+#define CPADD(register) \
.cpadd register
-#define CPLOAD(register) \
- .cpload register
+#define CPLOAD(register) \
+ .cpload register
#else
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
-#define ENTRY(symbol) \
- .globl symbol; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define ENTRY(symbol) \
+ .globl symbol; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
symbol:
/*
* LEAF - declare leaf routine
*/
-#define LEAF(symbol) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define LEAF(symbol) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
.section .text.symbol, "x"; \
symbol: .frame sp, 0, ra
/*
* NESTED - declare nested routine entry point
*/
-#define NESTED(symbol, framesize, rpc) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define NESTED(symbol, framesize, rpc) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
.section .text.symbol, "x"; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
-#define END(function) \
- .end function; \
+#define END(function) \
+ .end function; \
.size function, .-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
- .globl symbol; \
+ .globl symbol; \
symbol:
/*
@@ -98,16 +96,16 @@ symbol:
/*
* ABS - export absolute symbol
*/
-#define ABS(symbol,value) \
- .globl symbol; \
+#define ABS(symbol,value) \
+ .globl symbol; \
symbol = value
-#define PANIC(msg) \
+#define PANIC(msg) \
.set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal panic; \
-9: b 9b; \
+ .set reorder; \
+ PTR_LA a0, 8f; \
+ jal panic; \
+9: b 9b; \
.set pop; \
TEXT(msg)
@@ -115,31 +113,31 @@ symbol = value
* Print formatted string
*/
#ifdef CONFIG_PRINTK
-#define PRINT(string) \
+#define PRINT(string) \
.set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal printk; \
+ .set reorder; \
+ PTR_LA a0, 8f; \
+ jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#endif
-#define TEXT(msg) \
+#define TEXT(msg) \
.pushsection .data; \
-8: .asciiz msg; \
+8: .asciiz msg; \
.popsection;
/*
* Build text tables
*/
-#define TTABLE(string) \
+#define TTABLE(string) \
.pushsection .text; \
- .word 1f; \
+ .word 1f; \
.popsection \
.pushsection .data; \
-1: .asciiz string; \
+1: .asciiz string; \
.popsection
/*
@@ -151,21 +149,29 @@ symbol = value
*/
#ifdef CONFIG_CPU_HAS_PREFETCH
-#define PREF(hint,addr) \
+#define PREF(hint, addr) \
.set push; \
- .set mips4; \
+ .set arch=r5000; \
pref hint, addr; \
.set pop
-#define PREFX(hint,addr) \
+#define PREFE(hint, addr) \
+ .set push; \
+ .set mips0; \
+ .set eva; \
+ prefe hint, addr; \
+ .set pop
+
+#define PREFX(hint, addr) \
.set push; \
- .set mips4; \
+ .set arch=r5000; \
prefx hint, addr; \
.set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint, addr)
+#define PREFE(hint, addr)
#define PREFX(hint, addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */
@@ -174,42 +180,42 @@ symbol = value
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
.set push; \
.set reorder; \
- beqz rt, 9f; \
- move rd, rs; \
+ beqz rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
.set push; \
.set reorder; \
- bnez rt, 9f; \
- move rd, rs; \
+ bnez rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
.set push; \
.set noreorder; \
- bnezl rt, 9f; \
- move rd, rs; \
+ bnezl rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
.set push; \
.set noreorder; \
- beqzl rt, 9f; \
- move rd, rs; \
+ beqzl rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
movn rd, rs, rt
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
movz rd, rs, rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
@@ -304,6 +310,7 @@ symbol = value
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
+#define LONG_SP swp
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
@@ -326,6 +333,7 @@ symbol = value
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
+#define LONG_SP sdp
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h
index 24c6cda..3d79ebc 100644
--- a/arch/mips/include/asm/isadep.h
+++ b/arch/mips/include/asm/isadep.h
@@ -4,6 +4,8 @@
* of Coprocessor 0 registers.
*
* Copyright (c) 1998 Harald Koerfgen
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ISADEP_H
@@ -18,7 +20,7 @@
* kernel or user mode? (CP0_STATUS)
*/
#define KU_MASK 0x08
-#define KU_USER 0x08
+#define KU_USER 0x08
#define KU_KERN 0x00
#else
@@ -26,7 +28,7 @@
* kernel or user mode?
*/
#define KU_MASK 0x18
-#define KU_USER 0x10
+#define KU_USER 0x10
#define KU_KERN 0x00
#endif
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c7a0849..3185dc7 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1,22 +1,16 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink at mips.com and Carsten Langgaard, carstenl at mips.com
* Copyright (C) 2000, 07 MIPS Technologies, Inc.
* Copyright (C) 2003, 2004 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
-#if 0
-#include <linux/linkage.h>
-#endif
-
/*
* The following macros are especially useful for __asm__
* inline assembler.
@@ -49,7 +43,9 @@
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
#define CP0_INFO $7
+#define CP0_HWRENA $7, 0
#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
@@ -57,7 +53,11 @@
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
+#define CP0_EBASE $15, 1
+#define CP0_CMGCRBASE $15, 3
#define CP0_CONFIG $16
+#define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG5 $16, 5
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
@@ -98,74 +98,36 @@
/*
* Coprocessor 0 Set 2 register names
*/
-#define CP0_S2_SRSCTL $12 /* MIPSR2 */
+#define CP0_S2_SRSCTL $12 /* MIPSR2 */
/*
* Coprocessor 0 Set 3 register names
*/
-#define CP0_S3_SRSMAP $12 /* MIPSR2 */
+#define CP0_S3_SRSMAP $12 /* MIPSR2 */
/*
* TX39 Series
*/
#define CP0_TX39_CACHE $7
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION $0
-#define CP1_STATUS $31
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
+/* Generic EntryLo bit definitions */
+#define ENTRYLO_G (_ULCAST_(1) << 0)
+#define ENTRYLO_V (_ULCAST_(1) << 1)
+#define ENTRYLO_D (_ULCAST_(1) << 2)
+#define ENTRYLO_C_SHIFT 3
+#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
-#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
-#define FPU_CSR_COND 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
-#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
-#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
-#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
-#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
-#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
-#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
+/* R3000 EntryLo bit definitions */
+#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
+#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
+#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
+#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
- */
-#define FPU_CSR_ALL_X 0x0003f000
-#define FPU_CSR_UNI_X 0x00020000
-#define FPU_CSR_INV_X 0x00010000
-#define FPU_CSR_DIV_X 0x00008000
-#define FPU_CSR_OVF_X 0x00004000
-#define FPU_CSR_UDF_X 0x00002000
-#define FPU_CSR_INE_X 0x00001000
-
-#define FPU_CSR_ALL_E 0x00000f80
-#define FPU_CSR_INV_E 0x00000800
-#define FPU_CSR_DIV_E 0x00000400
-#define FPU_CSR_OVF_E 0x00000200
-#define FPU_CSR_UDF_E 0x00000100
-#define FPU_CSR_INE_E 0x00000080
-
-#define FPU_CSR_ALL_S 0x0000007c
-#define FPU_CSR_INV_S 0x00000040
-#define FPU_CSR_DIV_S 0x00000020
-#define FPU_CSR_OVF_S 0x00000010
-#define FPU_CSR_UDF_S 0x00000008
-#define FPU_CSR_INE_S 0x00000004
-
-/* rounding mode */
-#define FPU_CSR_RN 0x0 /* nearest */
-#define FPU_CSR_RZ 0x1 /* towards zero */
-#define FPU_CSR_RU 0x2 /* towards +Infinity */
-#define FPU_CSR_RD 0x3 /* towards -Infinity */
+/* MIPS32/64 EntryLo bit definitions */
+#define MIPS_ENTRYLO_PFN_SHIFT 6
+#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
/*
* Values for PageMask register
@@ -183,14 +145,22 @@
#else
#define PM_4K 0x00000000
+#define PM_8K 0x00002000
#define PM_16K 0x00006000
+#define PM_32K 0x0000e000
#define PM_64K 0x0001e000
+#define PM_128K 0x0003e000
#define PM_256K 0x0007e000
+#define PM_512K 0x000fe000
#define PM_1M 0x001fe000
+#define PM_2M 0x003fe000
#define PM_4M 0x007fe000
+#define PM_8M 0x00ffe000
#define PM_16M 0x01ffe000
+#define PM_32M 0x03ffe000
#define PM_64M 0x07ffe000
#define PM_256M 0x1fffe000
+#define PM_1G 0x7fffe000
#endif
@@ -208,10 +178,22 @@
#define PL_256M 28
/*
+ * PageGrain bits
+ */
+#define PG_RIE (_ULCAST_(1) << 31)
+#define PG_XIE (_ULCAST_(1) << 30)
+#define PG_ELPA (_ULCAST_(1) << 29)
+#define PG_ESP (_ULCAST_(1) << 28)
+#define PG_IEC (_ULCAST_(1) << 27)
+
+/* MIPS32/64 EntryHI bit definitions */
+#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
+
+/*
* R4x00 interrupt enable / cause bits
*/
-#define IE_SW0 (_ULCAST_(1) << 8)
-#define IE_SW1 (_ULCAST_(1) << 9)
+#define IE_SW0 (_ULCAST_(1) << 8)
+#define IE_SW1 (_ULCAST_(1) << 9)
#define IE_IRQ0 (_ULCAST_(1) << 10)
#define IE_IRQ1 (_ULCAST_(1) << 11)
#define IE_IRQ2 (_ULCAST_(1) << 12)
@@ -222,8 +204,8 @@
/*
* R4x00 interrupt cause bits
*/
-#define C_SW0 (_ULCAST_(1) << 8)
-#define C_SW1 (_ULCAST_(1) << 9)
+#define C_SW0 (_ULCAST_(1) << 8)
+#define C_SW1 (_ULCAST_(1) << 9)
#define C_IRQ0 (_ULCAST_(1) << 10)
#define C_IRQ1 (_ULCAST_(1) << 11)
#define C_IRQ2 (_ULCAST_(1) << 12)
@@ -271,7 +253,7 @@
/*
* Bits specific to the R4640/R4650
*/
-#define ST0_UM (_ULCAST_(1) << 4)
+#define ST0_UM (_ULCAST_(1) << 4)
#define ST0_IL (_ULCAST_(1) << 23)
#define ST0_DL (_ULCAST_(1) << 24)
@@ -281,75 +263,43 @@
#define ST0_MX 0x01000000
/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT 19
-#define TX39_CONF_ICS_MASK 0x00380000
-#define TX39_CONF_ICS_1KB 0x00000000
-#define TX39_CONF_ICS_2KB 0x00080000
-#define TX39_CONF_ICS_4KB 0x00100000
-#define TX39_CONF_ICS_8KB 0x00180000
-#define TX39_CONF_ICS_16KB 0x00200000
-
-#define TX39_CONF_DCS_SHIFT 16
-#define TX39_CONF_DCS_MASK 0x00070000
-#define TX39_CONF_DCS_1KB 0x00000000
-#define TX39_CONF_DCS_2KB 0x00010000
-#define TX39_CONF_DCS_4KB 0x00020000
-#define TX39_CONF_DCS_8KB 0x00030000
-#define TX39_CONF_DCS_16KB 0x00040000
-
-#define TX39_CONF_CWFON 0x00004000
-#define TX39_CONF_WBON 0x00002000
-#define TX39_CONF_RF_SHIFT 10
-#define TX39_CONF_RF_MASK 0x00000c00
-#define TX39_CONF_DOZE 0x00000200
-#define TX39_CONF_HALT 0x00000100
-#define TX39_CONF_LOCK 0x00000080
-#define TX39_CONF_ICE 0x00000020
-#define TX39_CONF_DCE 0x00000010
-#define TX39_CONF_IRSIZE_SHIFT 2
-#define TX39_CONF_IRSIZE_MASK 0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT 0
-#define TX39_CONF_DRSIZE_MASK 0x00000003
-
-/*
* Status register bits available in all MIPS CPUs.
*/
#define ST0_IM 0x0000ff00
-#define STATUSB_IP0 8
-#define STATUSF_IP0 (_ULCAST_(1) << 8)
-#define STATUSB_IP1 9
-#define STATUSF_IP1 (_ULCAST_(1) << 9)
-#define STATUSB_IP2 10
-#define STATUSF_IP2 (_ULCAST_(1) << 10)
-#define STATUSB_IP3 11
-#define STATUSF_IP3 (_ULCAST_(1) << 11)
-#define STATUSB_IP4 12
-#define STATUSF_IP4 (_ULCAST_(1) << 12)
-#define STATUSB_IP5 13
-#define STATUSF_IP5 (_ULCAST_(1) << 13)
-#define STATUSB_IP6 14
-#define STATUSF_IP6 (_ULCAST_(1) << 14)
-#define STATUSB_IP7 15
-#define STATUSF_IP7 (_ULCAST_(1) << 15)
-#define STATUSB_IP8 0
-#define STATUSF_IP8 (_ULCAST_(1) << 0)
-#define STATUSB_IP9 1
-#define STATUSF_IP9 (_ULCAST_(1) << 1)
-#define STATUSB_IP10 2
-#define STATUSF_IP10 (_ULCAST_(1) << 2)
-#define STATUSB_IP11 3
-#define STATUSF_IP11 (_ULCAST_(1) << 3)
-#define STATUSB_IP12 4
-#define STATUSF_IP12 (_ULCAST_(1) << 4)
-#define STATUSB_IP13 5
-#define STATUSF_IP13 (_ULCAST_(1) << 5)
-#define STATUSB_IP14 6
-#define STATUSF_IP14 (_ULCAST_(1) << 6)
-#define STATUSB_IP15 7
-#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define STATUSB_IP0 8
+#define STATUSF_IP0 (_ULCAST_(1) << 8)
+#define STATUSB_IP1 9
+#define STATUSF_IP1 (_ULCAST_(1) << 9)
+#define STATUSB_IP2 10
+#define STATUSF_IP2 (_ULCAST_(1) << 10)
+#define STATUSB_IP3 11
+#define STATUSF_IP3 (_ULCAST_(1) << 11)
+#define STATUSB_IP4 12
+#define STATUSF_IP4 (_ULCAST_(1) << 12)
+#define STATUSB_IP5 13
+#define STATUSF_IP5 (_ULCAST_(1) << 13)
+#define STATUSB_IP6 14
+#define STATUSF_IP6 (_ULCAST_(1) << 14)
+#define STATUSB_IP7 15
+#define STATUSF_IP7 (_ULCAST_(1) << 15)
+#define STATUSB_IP8 0
+#define STATUSF_IP8 (_ULCAST_(1) << 0)
+#define STATUSB_IP9 1
+#define STATUSF_IP9 (_ULCAST_(1) << 1)
+#define STATUSB_IP10 2
+#define STATUSF_IP10 (_ULCAST_(1) << 2)
+#define STATUSB_IP11 3
+#define STATUSF_IP11 (_ULCAST_(1) << 3)
+#define STATUSB_IP12 4
+#define STATUSF_IP12 (_ULCAST_(1) << 4)
+#define STATUSB_IP13 5
+#define STATUSF_IP13 (_ULCAST_(1) << 5)
+#define STATUSB_IP14 6
+#define STATUSF_IP14 (_ULCAST_(1) << 6)
+#define STATUSB_IP15 7
+#define STATUSF_IP15 (_ULCAST_(1) << 7)
#define ST0_CH 0x00040000
+#define ST0_NMI 0x00080000
#define ST0_SR 0x00100000
#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
@@ -363,36 +313,52 @@
#define ST0_XX 0x80000000 /* MIPS IV naming */
/*
+ * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
+ */
+#define INTCTLB_IPFDC 23
+#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
+#define INTCTLB_IPPCI 26
+#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
+#define INTCTLB_IPTI 29
+#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
+
+/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
-#define CAUSEB_EXCCODE 2
-#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
-#define CAUSEB_IP 8
-#define CAUSEF_IP (_ULCAST_(255) << 8)
-#define CAUSEB_IP0 8
-#define CAUSEF_IP0 (_ULCAST_(1) << 8)
-#define CAUSEB_IP1 9
-#define CAUSEF_IP1 (_ULCAST_(1) << 9)
-#define CAUSEB_IP2 10
-#define CAUSEF_IP2 (_ULCAST_(1) << 10)
-#define CAUSEB_IP3 11
-#define CAUSEF_IP3 (_ULCAST_(1) << 11)
-#define CAUSEB_IP4 12
-#define CAUSEF_IP4 (_ULCAST_(1) << 12)
-#define CAUSEB_IP5 13
-#define CAUSEF_IP5 (_ULCAST_(1) << 13)
-#define CAUSEB_IP6 14
-#define CAUSEF_IP6 (_ULCAST_(1) << 14)
-#define CAUSEB_IP7 15
-#define CAUSEF_IP7 (_ULCAST_(1) << 15)
-#define CAUSEB_IV 23
-#define CAUSEF_IV (_ULCAST_(1) << 23)
-#define CAUSEB_CE 28
-#define CAUSEF_CE (_ULCAST_(3) << 28)
-#define CAUSEB_BD 31
-#define CAUSEF_BD (_ULCAST_(1) << 31)
+#define CAUSEB_EXCCODE 2
+#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
+#define CAUSEB_IP 8
+#define CAUSEF_IP (_ULCAST_(255) << 8)
+#define CAUSEB_IP0 8
+#define CAUSEF_IP0 (_ULCAST_(1) << 8)
+#define CAUSEB_IP1 9
+#define CAUSEF_IP1 (_ULCAST_(1) << 9)
+#define CAUSEB_IP2 10
+#define CAUSEF_IP2 (_ULCAST_(1) << 10)
+#define CAUSEB_IP3 11
+#define CAUSEF_IP3 (_ULCAST_(1) << 11)
+#define CAUSEB_IP4 12
+#define CAUSEF_IP4 (_ULCAST_(1) << 12)
+#define CAUSEB_IP5 13
+#define CAUSEF_IP5 (_ULCAST_(1) << 13)
+#define CAUSEB_IP6 14
+#define CAUSEF_IP6 (_ULCAST_(1) << 14)
+#define CAUSEB_IP7 15
+#define CAUSEF_IP7 (_ULCAST_(1) << 15)
+#define CAUSEB_FDCI 21
+#define CAUSEF_FDCI (_ULCAST_(1) << 21)
+#define CAUSEB_IV 23
+#define CAUSEF_IV (_ULCAST_(1) << 23)
+#define CAUSEB_PCI 26
+#define CAUSEF_PCI (_ULCAST_(1) << 26)
+#define CAUSEB_CE 28
+#define CAUSEF_CE (_ULCAST_(3) << 28)
+#define CAUSEB_TI 30
+#define CAUSEF_TI (_ULCAST_(1) << 30)
+#define CAUSEB_BD 31
+#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
* Bits in the coprocessor 0 config register.
@@ -410,43 +376,43 @@
#define CONF_BE (_ULCAST_(1) << 15)
/* Bits common to various processors. */
-#define CONF_CU (_ULCAST_(1) << 3)
-#define CONF_DB (_ULCAST_(1) << 4)
-#define CONF_IB (_ULCAST_(1) << 5)
-#define CONF_DC (_ULCAST_(7) << 6)
-#define CONF_IC (_ULCAST_(7) << 9)
+#define CONF_CU (_ULCAST_(1) << 3)
+#define CONF_DB (_ULCAST_(1) << 4)
+#define CONF_IB (_ULCAST_(1) << 5)
+#define CONF_DC (_ULCAST_(7) << 6)
+#define CONF_IC (_ULCAST_(7) << 9)
#define CONF_EB (_ULCAST_(1) << 13)
#define CONF_EM (_ULCAST_(1) << 14)
#define CONF_SM (_ULCAST_(1) << 16)
#define CONF_SC (_ULCAST_(1) << 17)
#define CONF_EW (_ULCAST_(3) << 18)
-#define CONF_EP (_ULCAST_(15)<< 24)
+#define CONF_EP (_ULCAST_(15) << 24)
#define CONF_EC (_ULCAST_(7) << 28)
#define CONF_CM (_ULCAST_(1) << 31)
-/* Bits specific to the R4xx0. */
+/* Bits specific to the R4xx0. */
#define R4K_CONF_SW (_ULCAST_(1) << 20)
#define R4K_CONF_SS (_ULCAST_(1) << 21)
#define R4K_CONF_SB (_ULCAST_(3) << 22)
-/* Bits specific to the R5000. */
+/* Bits specific to the R5000. */
#define R5K_CONF_SE (_ULCAST_(1) << 12)
#define R5K_CONF_SS (_ULCAST_(3) << 20)
-/* Bits specific to the RM7000. */
-#define RM7K_CONF_SE (_ULCAST_(1) << 3)
+/* Bits specific to the RM7000. */
+#define RM7K_CONF_SE (_ULCAST_(1) << 3)
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
-/* Bits specific to the R10000. */
-#define R10K_CONF_DN (_ULCAST_(3) << 3)
-#define R10K_CONF_CT (_ULCAST_(1) << 5)
-#define R10K_CONF_PE (_ULCAST_(1) << 6)
-#define R10K_CONF_PM (_ULCAST_(3) << 7)
-#define R10K_CONF_EC (_ULCAST_(15)<< 9)
+/* Bits specific to the R10000. */
+#define R10K_CONF_DN (_ULCAST_(3) << 3)
+#define R10K_CONF_CT (_ULCAST_(1) << 5)
+#define R10K_CONF_PE (_ULCAST_(1) << 6)
+#define R10K_CONF_PM (_ULCAST_(3) << 7)
+#define R10K_CONF_EC (_ULCAST_(15) << 9)
#define R10K_CONF_SB (_ULCAST_(1) << 13)
#define R10K_CONF_SK (_ULCAST_(1) << 14)
#define R10K_CONF_SS (_ULCAST_(7) << 16)
@@ -454,14 +420,14 @@
#define R10K_CONF_DC (_ULCAST_(7) << 26)
#define R10K_CONF_IC (_ULCAST_(7) << 29)
-/* Bits specific to the VR41xx. */
+/* Bits specific to the VR41xx. */
#define VR41_CONF_CS (_ULCAST_(1) << 12)
#define VR41_CONF_P4K (_ULCAST_(1) << 13)
#define VR41_CONF_BP (_ULCAST_(1) << 16)
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
#define VR41_CONF_AD (_ULCAST_(1) << 23)
-/* Bits specific to the R30xx. */
+/* Bits specific to the R30xx. */
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
@@ -478,8 +444,10 @@
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
-/* Bits specific to the MIPS32/64 PRA. */
-#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+/* Bits specific to the MIPS32/64 PRA. */
+#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
+#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
@@ -487,50 +455,245 @@
/*
* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
*/
-#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
-#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
-#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
-#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
-#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
-#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
-#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
-#define MIPS_CONF1_DA_SHIFT 7
-#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
-#define MIPS_CONF1_DL_SHIFT 10
+#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
+#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
+#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
+#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
+#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
+#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
+#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
+#define MIPS_CONF1_DA_SHF 7
+#define MIPS_CONF1_DA_SZ 3
+#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
+#define MIPS_CONF1_DL_SHF 10
+#define MIPS_CONF1_DL_SZ 3
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS_SHIFT 13
+#define MIPS_CONF1_DS_SHF 13
+#define MIPS_CONF1_DS_SZ 3
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA_SHIFT 16
+#define MIPS_CONF1_IA_SHF 16
+#define MIPS_CONF1_IA_SZ 3
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL_SHIFT 19
+#define MIPS_CONF1_IL_SHF 19
+#define MIPS_CONF1_IL_SZ 3
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS_SHIFT 22
+#define MIPS_CONF1_IS_SHF 22
+#define MIPS_CONF1_IS_SZ 3
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
-#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
-#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
-#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
+#define MIPS_CONF1_TLBS_SHIFT (25)
+#define MIPS_CONF1_TLBS_SIZE (6)
+#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
+
+#define MIPS_CONF2_SA (_ULCAST_(15) << 0)
+#define MIPS_CONF2_SL (_ULCAST_(15) << 4)
+#define MIPS_CONF2_SS (_ULCAST_(15) << 8)
+#define MIPS_CONF2_SU (_ULCAST_(15) << 12)
+#define MIPS_CONF2_TA (_ULCAST_(15) << 16)
+#define MIPS_CONF2_TL (_ULCAST_(15) << 20)
+#define MIPS_CONF2_TS (_ULCAST_(15) << 24)
#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
-#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
-#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
-#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
-#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
-#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
-#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
-#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
+#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
+#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
+#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
+#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
+#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
+#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
+#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
+#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
+#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
+#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
+#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
+#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
+#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
+
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
+#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT (0)
+#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
+#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
+/* bits 10:8 in FTLB-only configurations */
+#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+/* bits 12:8 in VTLB-FTLB only configurations */
+#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
+#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
+
+#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
+#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
+#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
+#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
+#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
+#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
+#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
+#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
+#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
+#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
+#define MIPS_CONF5_K (_ULCAST_(1) << 30)
+
+#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
+/* proAptiv FTLB on/off bit */
+#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
+/* FTLB probability bits */
+#define MIPS_CONF6_FTLBP_SHIFT (16)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+/* FTLB probability bits for R6 */
+#define MIPS_CONF7_FTLBP_SHIFT (18)
+
+/* MAAR bit definitions */
+#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
+#define MIPS_MAAR_ADDR_SHIFT 12
+#define MIPS_MAAR_S (_ULCAST_(1) << 1)
+#define MIPS_MAAR_V (_ULCAST_(1) << 0)
+
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE 11
+#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT 9
+#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT 4
+#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT 3
+#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT 0
+#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK _ULCAST_(7)
+#define MIPS_SEGCFG_USK _ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
+#define MIPS_SEGCFG_MUSK _ULCAST_(3)
+#define MIPS_SEGCFG_MSK _ULCAST_(2)
+#define MIPS_SEGCFG_MK _ULCAST_(1)
+#define MIPS_SEGCFG_UK _ULCAST_(0)
+
+#define MIPS_PWFIELD_GDI_SHIFT 24
+#define MIPS_PWFIELD_GDI_MASK 0x3f000000
+#define MIPS_PWFIELD_UDI_SHIFT 18
+#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
+#define MIPS_PWFIELD_MDI_SHIFT 12
+#define MIPS_PWFIELD_MDI_MASK 0x0003f000
+#define MIPS_PWFIELD_PTI_SHIFT 6
+#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
+#define MIPS_PWFIELD_PTEI_SHIFT 0
+#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
+
+#define MIPS_PWSIZE_GDW_SHIFT 24
+#define MIPS_PWSIZE_GDW_MASK 0x3f000000
+#define MIPS_PWSIZE_UDW_SHIFT 18
+#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
+#define MIPS_PWSIZE_MDW_SHIFT 12
+#define MIPS_PWSIZE_MDW_MASK 0x0003f000
+#define MIPS_PWSIZE_PTW_SHIFT 6
+#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
+#define MIPS_PWSIZE_PTEW_SHIFT 0
+#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
+
+#define MIPS_PWCTL_PWEN_SHIFT 31
+#define MIPS_PWCTL_PWEN_MASK 0x80000000
+#define MIPS_PWCTL_DPH_SHIFT 7
+#define MIPS_PWCTL_DPH_MASK 0x00000080
+#define MIPS_PWCTL_HUGEPG_SHIFT 6
+#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
+#define MIPS_PWCTL_PSN_SHIFT 0
+#define MIPS_PWCTL_PSN_MASK 0x0000003f
+
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT 19
+#define TX39_CONF_ICS_MASK 0x00380000
+#define TX39_CONF_ICS_1KB 0x00000000
+#define TX39_CONF_ICS_2KB 0x00080000
+#define TX39_CONF_ICS_4KB 0x00100000
+#define TX39_CONF_ICS_8KB 0x00180000
+#define TX39_CONF_ICS_16KB 0x00200000
+
+#define TX39_CONF_DCS_SHIFT 16
+#define TX39_CONF_DCS_MASK 0x00070000
+#define TX39_CONF_DCS_1KB 0x00000000
+#define TX39_CONF_DCS_2KB 0x00010000
+#define TX39_CONF_DCS_4KB 0x00020000
+#define TX39_CONF_DCS_8KB 0x00030000
+#define TX39_CONF_DCS_16KB 0x00040000
+
+#define TX39_CONF_CWFON 0x00004000
+#define TX39_CONF_WBON 0x00002000
+#define TX39_CONF_RF_SHIFT 10
+#define TX39_CONF_RF_MASK 0x00000c00
+#define TX39_CONF_DOZE 0x00000200
+#define TX39_CONF_HALT 0x00000100
+#define TX39_CONF_LOCK 0x00000080
+#define TX39_CONF_ICE 0x00000020
+#define TX39_CONF_DCE 0x00000010
+#define TX39_CONF_IRSIZE_SHIFT 2
+#define TX39_CONF_IRSIZE_MASK 0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT 0
+#define TX39_CONF_DRSIZE_MASK 0x00000003
+
+/*
+ * Interesting Bits in the R10K CP0 Branch Diagnostic Register
+ */
+/* Disable Branch Target Address Cache */
+#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
+/* Enable Branch Prediction Global History */
+#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
+/* Disable Branch Return Cache */
+#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION $0
+#define CP1_UFR $1
+#define CP1_UNFR $4
+#define CP1_FCCR $25
+#define CP1_FEXR $26
+#define CP1_FENR $28
+#define CP1_STATUS $31
+
+
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
@@ -541,11 +704,150 @@
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
+ */
+#define MIPS_FCCR_CONDX_S 0
+#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S 0
+#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S 1
+#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S 2
+#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S 3
+#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S 4
+#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S 5
+#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S 6
+#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S 7
+#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S 2
+#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
+
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_COND_S 23 /* $fcc0 */
+#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
+#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
+#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25 /* $fcc1 */
+#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26 /* $fcc2 */
+#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27 /* $fcc3 */
+#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28 /* $fcc4 */
+#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29 /* $fcc5 */
+#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30 /* $fcc6 */
+#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31 /* $fcc7 */
+#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
+
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
+
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X 0x00020000
+#define FPU_CSR_INV_X 0x00010000
+#define FPU_CSR_DIV_X 0x00008000
+#define FPU_CSR_OVF_X 0x00004000
+#define FPU_CSR_UDF_X 0x00002000
+#define FPU_CSR_INE_X 0x00001000
+
+#define FPU_CSR_ALL_E 0x00000f80
+#define FPU_CSR_INV_E 0x00000800
+#define FPU_CSR_DIV_E 0x00000400
+#define FPU_CSR_OVF_E 0x00000200
+#define FPU_CSR_UDF_E 0x00000100
+#define FPU_CSR_INE_E 0x00000080
+
+#define FPU_CSR_ALL_S 0x0000007c
+#define FPU_CSR_INV_S 0x00000040
+#define FPU_CSR_DIV_S 0x00000020
+#define FPU_CSR_OVF_S 0x00000010
+#define FPU_CSR_UDF_S 0x00000008
+#define FPU_CSR_INE_S 0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM 0x00000003
+#define FPU_CSR_RN 0x0 /* nearest */
+#define FPU_CSR_RZ 0x1 /* towards zero */
+#define FPU_CSR_RU 0x2 /* towards +Infinity */
+#define FPU_CSR_RD 0x3 /* towards -Infinity */
+
#ifndef __ASSEMBLY__
/*
- * Functions to access the R10000 performance counters. These are basically
+ * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
+ */
+#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
+ defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
+#define get_isa16_mode(x) ((x) & 0x1)
+#define msk_isa16_mode(x) ((x) & ~0x1)
+#define set_isa16_mode(x) do { (x) |= 0x1; } while (0)
+#else
+#define get_isa16_mode(x) 0
+#define msk_isa16_mode(x) (x)
+#define set_isa16_mode(x) do { } while (0)
+#endif
+
+/*
+ * microMIPS instructions can be 16-bit or 32-bit in length. This
+ * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
+ */
+static inline int mm_insn_16bit(u16 insn)
+{
+ u16 opcode = (insn >> 10) & 0x7;
+
+ return (opcode >= 1 && opcode <= 3) ? 1 : 0;
+}
+
+/*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".word 0x42000004\n\t" /* tlbinvf */
+ ".set pop");
+}
+
+
+/*
+ * Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
* performance counter number encoded into bits 1 ... 5 of the instruction.
* Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
@@ -589,6 +891,7 @@ do { \
: "r" (val), "i" (counter)); \
} while (0)
+
/*
* Macros to access the system control coprocessor
*/
@@ -705,8 +1008,8 @@ do { \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
+ "dsra\t%M0, %M0, 32\n\t" \
+ "dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
else \
@@ -714,8 +1017,8 @@ do { \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
+ "dsra\t%M0, %M0, 32\n\t" \
+ "dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
local_irq_restore(__flags); \
@@ -751,15 +1054,57 @@ do { \
local_irq_restore(__flags); \
} while (0)
+#define __readx_32bit_c0_register(source) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " .set mips32r2 \n" \
+ " .insn \n" \
+ " # mfhc0 $1, %1 \n" \
+ " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (source)); \
+ __res; \
+})
+
+#define __writex_32bit_c0_register(register, value) \
+({ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " .set mips32r2 \n" \
+ " move $1, %0 \n" \
+ " # mthc0 $1, %1 \n" \
+ " .insn \n" \
+ " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
+ " .set pop \n" \
+ : \
+ : "r" (value), "i" (register)); \
+})
+
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
+#define read_c0_random() __read_32bit_c0_register($1, 0)
+#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
+
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
+#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
+#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
+
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
+#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
+#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
+
#define read_c0_conf() __read_32bit_c0_register($3, 0)
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
@@ -767,17 +1112,20 @@ do { \
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
-#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
+#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
+
#define read_c0_wired() __read_32bit_c0_register($6, 0)
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
#define read_c0_info() __read_32bit_c0_register($7, 0)
-#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
+#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
@@ -805,19 +1153,8 @@ do { \
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
-#ifdef CONFIG_MIPS_MT_SMTC
-#define write_c0_status(val) \
-do { \
- __write_32bit_c0_register($12, 0, val); \
- __ehb(); \
-} while (0)
-#else
-/*
- * Legacy non-SMTC code, which may be hazardous
- * but which might not support EHB
- */
+
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
-#endif /* CONFIG_MIPS_MT_SMTC */
#define read_c0_cause() __read_32bit_c0_register($13, 0)
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
@@ -827,6 +1164,8 @@ do { \
#define read_c0_prid() __read_32bit_c0_register($15, 0)
+#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
+
#define read_c0_config() __read_32bit_c0_register($16, 0)
#define read_c0_config1() __read_32bit_c0_register($16, 1)
#define read_c0_config2() __read_32bit_c0_register($16, 2)
@@ -844,8 +1183,15 @@ do { \
#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
+#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
+#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
+#define read_c0_maar() __read_ulong_c0_register($17, 1)
+#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
+#define read_c0_maari() __read_32bit_c0_register($17, 2)
+#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
+
/*
- * The WatchLo register. There may be upto 8 of them.
+ * The WatchLo register. There may be up to 8 of them.
*/
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
@@ -865,7 +1211,7 @@ do { \
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
/*
- * The WatchHi register. There may be upto 8 of them.
+ * The WatchHi register. There may be up to 8 of them.
*/
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
@@ -892,15 +1238,15 @@ do { \
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
-
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
#define read_c0_diag() __read_32bit_c0_register($22, 0)
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
+/* R10K CP0 Branch Diagnostic register is 64bits wide */
+#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
+#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
+
#define read_c0_diag1() __read_32bit_c0_register($22, 1)
#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
@@ -926,36 +1272,40 @@ do { \
* MIPS32 / MIPS64 performance counters
*/
#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
-#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
-#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
-#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
-#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
-#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
-#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
-#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
-#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
-
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
@@ -963,6 +1313,12 @@ do { \
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
+#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo() __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
+
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
@@ -985,271 +1341,524 @@ do { \
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
+#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
+
+/* MIPSR3 */
+#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
+
+/* Hardware Page Table Walker */
+#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
+#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
+
+#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
+#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
+
+#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
+#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
+
+#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
+#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
+
+/* Cavium OCTEON (cnMIPS) */
+#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
+#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
+
+#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
+#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
+
+#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
+#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
/*
- * Macros to access the floating point coprocessor control registers
+ * The cacheerr registers are not standardized. On OCTEON, they are
+ * 64 bits wide.
*/
-#define read_32bit_cp1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc1\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
+#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
+#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
-#define rddsp(mask) \
+#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
+#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
+
+/* BMIPS3300 */
+#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS43xx */
+#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define _read_32bit_cp1_register(source, gas_hardfloat) \
({ \
unsigned int __res; \
\
__asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # rddsp $1, %x1 \n" \
- " .word 0x7c000cb8 | (%x1 << 16) \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__res) \
- : "i" (mask)); \
+ " .set push \n" \
+ " .set reorder \n" \
+ " # gas fails to assemble cfc1 for some archs, \n" \
+ " # like Octeon. \n" \
+ " .set mips1 \n" \
+ " "STR(gas_hardfloat)" \n" \
+ " cfc1 %0,"STR(source)" \n" \
+ " .set pop \n" \
+ : "=r" (__res)); \
__res; \
})
-#define wrdsp(val, mask) \
-do { \
+#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
- " .set noat \n" \
- " move $1, %0 \n" \
- " # wrdsp $1, %x1 \n" \
- " .word 0x7c2004f8 | (%x1 << 11) \n" \
+ " .set reorder \n" \
+ " "STR(gas_hardfloat)" \n" \
+ " ctc1 %0,"STR(dest)" \n" \
" .set pop \n" \
+ : : "r" (val)); \
+})
+
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source) \
+ _read_32bit_cp1_register(source, .set hardfloat)
+#define write_32bit_cp1_register(dest, val) \
+ _write_32bit_cp1_register(dest, val, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source) \
+ _read_32bit_cp1_register(source, )
+#define write_32bit_cp1_register(dest, val) \
+ _write_32bit_cp1_register(dest, val, )
+#endif
+
+#ifdef HAVE_AS_DSP
+#define rddsp(mask) \
+({ \
+ unsigned int __dspctl; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " rddsp %0, %x1 \n" \
+ " .set pop \n" \
+ : "=r" (__dspctl) \
+ : "i" (mask)); \
+ __dspctl; \
+})
+
+#define wrdsp(val, mask) \
+({ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " wrdsp %0, %x1 \n" \
+ " .set pop \n" \
: \
: "r" (val), "i" (mask)); \
-} while (0)
+})
+
+#define mflo0() \
+({ \
+ long mflo0; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac0 \n" \
+ " .set pop \n" \
+ : "=r" (mflo0)); \
+ mflo0; \
+})
+
+#define mflo1() \
+({ \
+ long mflo1; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac1 \n" \
+ " .set pop \n" \
+ : "=r" (mflo1)); \
+ mflo1; \
+})
+
+#define mflo2() \
+({ \
+ long mflo2; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac2 \n" \
+ " .set pop \n" \
+ : "=r" (mflo2)); \
+ mflo2; \
+})
+
+#define mflo3() \
+({ \
+ long mflo3; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac3 \n" \
+ " .set pop \n" \
+ : "=r" (mflo3)); \
+ mflo3; \
+})
#define mfhi0() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac0 \n" \
- " .word 0x00000810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi0; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac0 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi0)); \
+ mfhi0; \
})
#define mfhi1() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac1 \n" \
- " .word 0x00200810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi1; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac1 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi1)); \
+ mfhi1; \
})
#define mfhi2() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac2 \n" \
- " .word 0x00400810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi2; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac2 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi2)); \
+ mfhi2; \
})
#define mfhi3() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac3 \n" \
- " .word 0x00600810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi3; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac3 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi3)); \
+ mfhi3; \
})
-#define mflo0() \
+
+#define mtlo0(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac0 \n" \
- " .word 0x00000812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac0 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo1() \
+#define mtlo1(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac1 \n" \
- " .word 0x00200812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac1 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo2() \
+#define mtlo2(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac2 \n" \
- " .word 0x00400812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac2 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo3() \
+#define mtlo3(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac3 \n" \
- " .word 0x00600812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac3 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
#define mthi0(x) \
-do { \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac0 \n" \
- " .word 0x00200011 \n" \
- " .set pop \n" \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac0 \n" \
+ " .set pop \n" \
: \
: "r" (x)); \
-} while (0)
+})
#define mthi1(x) \
-do { \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac1 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#define mthi2(x) \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac2 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#define mthi3(x) \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac3 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#else
+
+#ifdef CONFIG_CPU_MICROMIPS
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac1 \n" \
- " .word 0x00200811 \n" \
+ " # rddsp $1, %x1 \n" \
+ " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
+ " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
-#define mthi2(x) \
-do { \
+#define wrdsp(val, mask) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mthi $1, $ac2 \n" \
- " .word 0x00201011 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
+ " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (mask)); \
+})
-#define mthi3(x) \
-do { \
+#define _umips_dsp_mfxxx(ins) \
+({ \
+ unsigned long __treg; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac3 \n" \
- " .word 0x00201811 \n" \
+ " .hword 0x0001 \n" \
+ " .hword %x1 \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__treg) \
+ : "i" (ins)); \
+ __treg; \
+})
-#define mtlo0(x) \
-do { \
+#define _umips_dsp_mtxxx(val, ins) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac0 \n" \
- " .word 0x00200013 \n" \
+ " .hword 0x0001 \n" \
+ " .hword %x1 \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (ins)); \
+})
-#define mtlo1(x) \
-do { \
+#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
+#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
+
+#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
+#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
+
+#define mflo0() _umips_dsp_mflo(0)
+#define mflo1() _umips_dsp_mflo(1)
+#define mflo2() _umips_dsp_mflo(2)
+#define mflo3() _umips_dsp_mflo(3)
+
+#define mfhi0() _umips_dsp_mfhi(0)
+#define mfhi1() _umips_dsp_mfhi(1)
+#define mfhi2() _umips_dsp_mfhi(2)
+#define mfhi3() _umips_dsp_mfhi(3)
+
+#define mtlo0(x) _umips_dsp_mtlo(x, 0)
+#define mtlo1(x) _umips_dsp_mtlo(x, 1)
+#define mtlo2(x) _umips_dsp_mtlo(x, 2)
+#define mtlo3(x) _umips_dsp_mtlo(x, 3)
+
+#define mthi0(x) _umips_dsp_mthi(x, 0)
+#define mthi1(x) _umips_dsp_mthi(x, 1)
+#define mthi2(x) _umips_dsp_mthi(x, 2)
+#define mthi3(x) _umips_dsp_mthi(x, 3)
+
+#else /* !CONFIG_CPU_MICROMIPS */
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # rddsp $1, %x1 \n" \
+ " .word 0x7c000cb8 | (%x1 << 16) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
+
+#define wrdsp(val, mask) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac1 \n" \
- " .word 0x00200813 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .word 0x7c2004f8 | (%x1 << 11) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (mask)); \
+})
-#define mtlo2(x) \
-do { \
+#define _dsp_mfxxx(ins) \
+({ \
+ unsigned long __treg; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mtlo $1, $ac2 \n" \
- " .word 0x00201013 \n" \
+ " .word (0x00000810 | %1) \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__treg) \
+ : "i" (ins)); \
+ __treg; \
+})
-#define mtlo3(x) \
-do { \
+#define _dsp_mtxxx(val, ins) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac3 \n" \
- " .word 0x00201813 \n" \
+ " .word (0x00200011 | %1) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (ins)); \
+})
+
+#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
+#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
+
+#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
+#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
+
+#define mflo0() _dsp_mflo(0)
+#define mflo1() _dsp_mflo(1)
+#define mflo2() _dsp_mflo(2)
+#define mflo3() _dsp_mflo(3)
+
+#define mfhi0() _dsp_mfhi(0)
+#define mfhi1() _dsp_mfhi(1)
+#define mfhi2() _dsp_mfhi(2)
+#define mfhi3() _dsp_mfhi(3)
+
+#define mtlo0(x) _dsp_mtlo(x, 0)
+#define mtlo1(x) _dsp_mtlo(x, 1)
+#define mtlo2(x) _dsp_mtlo(x, 2)
+#define mtlo3(x) _dsp_mtlo(x, 3)
+
+#define mthi0(x) _dsp_mthi(x, 0)
+#define mthi1(x) _dsp_mthi(x, 1)
+#define mthi2(x) _dsp_mthi(x, 2)
+#define mthi3(x) _dsp_mthi(x, 3)
+
+#endif /* CONFIG_CPU_MICROMIPS */
+#endif
/*
* TLB operations.
@@ -1324,11 +1933,11 @@ static inline void tlb_write_random(void)
static inline unsigned int \
set_c0_##name(unsigned int set) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res |= set; \
- write_c0_##name(res); \
+ new = res | set; \
+ write_c0_##name(new); \
\
return res; \
} \
@@ -1336,24 +1945,24 @@ set_c0_##name(unsigned int set) \
static inline unsigned int \
clear_c0_##name(unsigned int clear) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res &= ~clear; \
- write_c0_##name(res); \
+ new = res & ~clear; \
+ write_c0_##name(new); \
\
return res; \
} \
\
static inline unsigned int \
-change_c0_##name(unsigned int change, unsigned int new) \
+change_c0_##name(unsigned int change, unsigned int val) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res &= ~change; \
- res |= (new & change); \
- write_c0_##name(res); \
+ new = res & ~change; \
+ new |= (val & change); \
+ write_c0_##name(new); \
\
return res; \
}
@@ -1361,9 +1970,27 @@ change_c0_##name(unsigned int change, unsigned int new) \
__BUILD_SET_C0(status)
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
+__BUILD_SET_C0(config5)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
+
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+ return read_c0_ebase() & 0x3ff;
+}
#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index ba7f538..02a3b16 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -1,12 +1,10 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 5659c0c..da051f6 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -1,35 +1,27 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_PTRACE_H
#define _ASM_PTRACE_H
-/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
-#define FPR_BASE 32
-#define PC 64
-#define CAUSE 65
-#define BADVADDR 66
-#define MMHI 67
-#define MMLO 68
-#define FPC_CSR 69
-#define FPC_EIR 70
-#define DSP_BASE 71 /* 3 more hi / lo register pairs */
-#define DSP_CONTROL 77
-#define ACX 78
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/isadep.h>
/*
* This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved.
+ *
+ * If you add a register here, also add it to regoffset_table[] in
+ * arch/mips/kernel/ptrace.c.
*/
struct pt_regs {
#ifdef CONFIG_32BIT
/* Pad bytes for argument save space on the stack. */
- unsigned long pad0[6];
+ unsigned long pad0[8];
#endif
/* Saved main processor registers. */
@@ -45,34 +37,50 @@ struct pt_regs {
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
- unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-} __attribute__ ((aligned (8)));
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[6]; /* MTM{0-5} */
+ unsigned long long mtp[6]; /* MTP{0-5} */
+#endif
+ unsigned long __last[0];
+} __aligned(8);
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-/* #define PTRACE_GETFPXREGS 18 */
-/* #define PTRACE_SETFPXREGS 19 */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+ return regs->regs[31];
+}
-#define PTRACE_OLDSETOPTIONS 21
+/*
+ * Don't use asm-generic/ptrace.h it defines FP accessors that don't make
+ * sense on MIPS. We rather want an error if they get invoked.
+ */
-#define PTRACE_GET_THREAD_AREA 25
-#define PTRACE_SET_THREAD_AREA 26
+static inline void instruction_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ regs->cp0_epc = val;
+}
-/* Calls to trace a 64bit program from a 32bit program. */
-#define PTRACE_PEEKTEXT_3264 0xc0
-#define PTRACE_PEEKDATA_3264 0xc1
-#define PTRACE_POKETEXT_3264 0xc2
-#define PTRACE_POKEDATA_3264 0xc3
-#define PTRACE_GET_THREAD_AREA_3264 0xc4
+/* Query offset/name of register from its name/offset */
+extern int regs_query_register_offset(const char *name);
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
-#ifdef __KERNEL__
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs: pt_regs from which register value is gotten.
+ * @offset: offset number of the register.
+ *
+ * regs_get_register returns the value of a register. The @offset is the
+ * offset of the register in struct pt_regs address which specified by @regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+ unsigned int offset)
+{
+ if (unlikely(offset > MAX_REG_OFFSET))
+ return 0;
-#include <asm/isadep.h>
+ return *(unsigned long *)((unsigned long)regs + offset);
+}
/*
* Does the process account for user or for system time?
@@ -82,6 +90,17 @@ struct pt_regs {
#define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs)
-#endif
+/* Helpers for working with the user stack pointer */
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+ return regs->regs[29];
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ regs->regs[29] = val;
+}
#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 2e65cc3..f1efc45 100644
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -1,11 +1,11 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ * written by Ralf Baechle <ralf@linux-mips.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
@@ -30,9 +30,13 @@
#define t2 $10
#define t3 $11
#define t4 $12
+#define ta0 $12
#define t5 $13
+#define ta1 $13
#define t6 $14
+#define ta2 $14
#define t7 $15
+#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index e245614..bf8ff59 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -27,7 +27,7 @@ static inline unsigned long icache_line_size(void)
{
unsigned long conf1, il;
conf1 = read_c0_config1();
- il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+ il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
return 0;
return 2 << il;
@@ -37,7 +37,7 @@ static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
conf1 = read_c0_config1();
- dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+ dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
return 0;
return 2 << dl;
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 137d728..14cc2c4 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -54,24 +54,24 @@
mfc0 $1, CP0_CONFIG, 1
/* detect line size */
- srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
- andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+ srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
+ andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
move \sz, zero
beqz \line_sz, 10f
li \sz, 2
sllv \line_sz, \sz, \line_sz
/* detect associativity */
- srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
- andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
+ srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
+ andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
addi \sz, \sz, 1
/* sz *= line_sz */
mul \sz, \sz, \line_sz
/* detect log32(sets) */
- srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
- andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+ srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
+ andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
addiu $1, $1, 1
andi $1, $1, 0x7
@@ -103,14 +103,14 @@ LEAF(mips_cache_reset)
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
#else
- l1_info t2, t8, MIPS_CONF1_IA_SHIFT
+ l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifdef CONFIG_SYS_DCACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
#else
- l1_info t3, t9, MIPS_CONF1_DA_SHIFT
+ l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 4/6] MIPS: fix SPDX license identifier in remaining arch header files
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
` (2 preceding siblings ...)
2016-01-12 20:48 ` [U-Boot] [PATCH v3 3/6] MIPS: sync processor and register definitions " Daniel Schwierzeck
@ 2016-01-12 20:48 ` Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 5/6] MIPS: implement bit manipulating I/O accessors Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 6/6] MIPS: DO NOT MERGE: test " Daniel Schwierzeck
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
Add a SPDX license identifier to MIPS header files where it is
still missing.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
Changes in v3: None
Changes in v2: None
arch/mips/include/asm/addrspace.h | 6 ++----
arch/mips/include/asm/bitops.h | 6 ++----
arch/mips/include/asm/byteorder.h | 6 ++----
arch/mips/include/asm/cachectl.h | 6 ++----
arch/mips/include/asm/cacheops.h | 6 ++----
arch/mips/include/asm/const.h | 6 +++++-
arch/mips/include/asm/posix_types.h | 9 +++------
arch/mips/include/asm/reboot.h | 6 ++----
arch/mips/include/asm/reg.h | 6 ++----
arch/mips/include/asm/sgidefs.h | 6 ++----
arch/mips/include/asm/string.h | 6 ++----
arch/mips/include/asm/system.h | 6 ++----
arch/mips/include/asm/types.h | 6 ++----
arch/mips/include/asm/unaligned.h | 6 ++----
14 files changed, 32 insertions(+), 55 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index e7fe6ed..0994e96 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -1,11 +1,9 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index c31ff6e..cce6995 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -1,10 +1,8 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf at gnu.org)
* Copyright (c) 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index b5e685f..67fdf71 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -1,9 +1,7 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
index f3ce721..5e77dfa 100644
--- a/arch/mips/include/asm/cachectl.h
+++ b/arch/mips/include/asm/cachectl.h
@@ -1,9 +1,7 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index af2adc7..a3b07c6 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -1,12 +1,10 @@
/*
* Cache operations for the cache instruction.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h
index c872bfd..f600e7a 100644
--- a/arch/mips/include/asm/const.h
+++ b/arch/mips/include/asm/const.h
@@ -1,4 +1,8 @@
-/* const.h: Macros for dealing with constants. */
+/*
+ * const.h: Macros for dealing with constants.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
#ifndef _LINUX_CONST_H
#define _LINUX_CONST_H
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 4deac52..90c0aff 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -1,10 +1,7 @@
-/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
+/*
* Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_POSIX_TYPES_H
#define _ASM_POSIX_TYPES_H
diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h
index 978d206..2a6b724 100644
--- a/arch/mips/include/asm/reboot.h
+++ b/arch/mips/include/asm/reboot.h
@@ -1,10 +1,8 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_REBOOT_H
#define _ASM_REBOOT_H
diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h
index fc6bc0c..af6fbb4 100644
--- a/arch/mips/include/asm/reg.h
+++ b/arch/mips/include/asm/reg.h
@@ -2,12 +2,10 @@
* Various register offset definitions for debuggers, core file
* examiners and whatnot.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1995, 1999 by Ralf Baechle
* Copyright (C) 1995, 1999 Silicon Graphics
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_MIPS_REG_H
#define __ASM_MIPS_REG_H
diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h
index 67f2658..2a03886 100644
--- a/arch/mips/include/asm/sgidefs.h
+++ b/arch/mips/include/asm/sgidefs.h
@@ -1,11 +1,9 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 1999, 2001 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_SGIDEFS_H
#define __ASM_SGIDEFS_H
diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h
index 579a591..1fbe899 100644
--- a/arch/mips/include/asm/string.h
+++ b/arch/mips/include/asm/string.h
@@ -1,11 +1,9 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
* Copyright (c) 2000 by Silicon Graphics, Inc.
* Copyright (c) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_STRING_H
#define _ASM_STRING_H
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index d56f73b..e6435cc 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -1,8 +1,4 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994 - 1999 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1994 - 1999 by Ralf Baechle
@@ -12,6 +8,8 @@
*
* Kevin D. Kissell, kevink at mips.org and Carsten Langgaard, carstenl at mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index aebafdb..627440d 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -1,10 +1,8 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
index c25a846..eebe06a 100644
--- a/arch/mips/include/asm/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
@@ -1,9 +1,7 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 2007 Ralf Baechle (ralf at linux-mips.org)
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MIPS_UNALIGNED_H
#define _ASM_MIPS_UNALIGNED_H
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 5/6] MIPS: implement bit manipulating I/O accessors
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
` (3 preceding siblings ...)
2016-01-12 20:48 ` [U-Boot] [PATCH v3 4/6] MIPS: fix SPDX license identifier in remaining arch header files Daniel Schwierzeck
@ 2016-01-12 20:48 ` Daniel Schwierzeck
2016-01-15 14:54 ` [U-Boot] [PATCH v4 " Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 6/6] MIPS: DO NOT MERGE: test " Daniel Schwierzeck
5 siblings, 1 reply; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
Add support for functions clrbits_X(), setbits_X() and clrsetbits_X()
on MIPS.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
Changes in v3: None
Changes in v2: None
arch/mips/include/asm/io.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index eb06afa..43b4326 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -541,4 +541,58 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
+#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_SETBITS(bwlq, sfx, end, type) \
+ \
+static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
+ type clr, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, type) \
+ \
+__BUILD_CLRBITS(bwlq, sfx, sfx, type) \
+__BUILD_SETBITS(bwlq, sfx, sfx, type) \
+__BUILD_CLRSETBITS(bwlq, sfx, sfx, type)
+
+#define __to_cpu(v) (v)
+#define cpu_to__(v) (v)
+
+__BUILD_CLRBITS(b, 8, _, u8)
+__BUILD_SETBITS(b, 8, _, u8)
+__BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, u16)
+BUILD_CLRSETBITS(w, be16, u16)
+BUILD_CLRSETBITS(l, le32, u32)
+BUILD_CLRSETBITS(l, be32, u32)
+BUILD_CLRSETBITS(q, le64, u64)
+BUILD_CLRSETBITS(q, be64, u64)
+
#endif /* _ASM_IO_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 6/6] MIPS: DO NOT MERGE: test I/O accessors
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
` (4 preceding siblings ...)
2016-01-12 20:48 ` [U-Boot] [PATCH v3 5/6] MIPS: implement bit manipulating I/O accessors Daniel Schwierzeck
@ 2016-01-12 20:48 ` Daniel Schwierzeck
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-12 20:48 UTC (permalink / raw)
To: u-boot
Test patch for compile testing and disassembly analysis of
the updated and new I/O accessors.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
Changes in v3:
- rebased to u-boot-mips/next
Changes in v2: None
arch/mips/lib/io.c | 183 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
diff --git a/arch/mips/lib/io.c b/arch/mips/lib/io.c
index b2d4a09..e80990e 100644
--- a/arch/mips/lib/io.c
+++ b/arch/mips/lib/io.c
@@ -5,8 +5,191 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
+#include <asm/io.h>
+
/*
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
const unsigned long mips_io_port_base = -1;
+
+static const void __iomem *addr1 = (const void __iomem *)CKSEG1ADDR(0x80000000);
+static void __iomem *addr2 = (void __iomem *)CKSEG1ADDR(0x80001000);
+
+void test_readb(void)
+{
+ u8 val = readb(addr1);
+ writeb(val, addr2);
+}
+
+void test_readw(void)
+{
+ u16 val = readw(addr1);
+ writew(val, addr2);
+}
+
+void test_readl(void)
+{
+ u32 val = readl(addr1);
+ writel(val, addr2);
+}
+
+void test_readq(void)
+{
+ u32 val = readq(addr1);
+ writeq(val, addr2);
+}
+
+void test_readb_be(void)
+{
+ u8 val = readb_be(addr1);
+ writeb_be(val, addr2);
+}
+
+void test_readw_be(void)
+{
+ u16 val = readw_be(addr1);
+ writew_be(val, addr2);
+}
+
+void test_readl_be(void)
+{
+ u32 val = readl_be(addr1);
+ writel_be(val, addr2);
+}
+
+void test_readq_be(void)
+{
+ u32 val = readq_be(addr1);
+ writeq_be(val, addr2);
+}
+
+void test_raw_readb(void)
+{
+ u8 val = __raw_readb(addr1);
+ __raw_writeb(val, addr2);
+}
+
+void test_raw_readw(void)
+{
+ u16 val = __raw_readw(addr1);
+ __raw_writew(val, addr2);
+}
+
+void test_raw_readl(void)
+{
+ u32 val = __raw_readl(addr1);
+ __raw_writel(val, addr2);
+}
+
+void test_raw_readq(void)
+{
+ u32 val = __raw_readq(addr1);
+ __raw_writeq(val, addr2);
+}
+
+void test_clrbits_8(void)
+{
+ clrbits_8(addr2, BIT(2));
+}
+
+void test_setbits_8(void)
+{
+ setbits_8(addr2, BIT(3));
+}
+
+void test_clrsetbits_8(void)
+{
+ clrsetbits_8(addr2, BIT(2), BIT(3));
+}
+
+void test_clrbits_le16(void)
+{
+ clrbits_le16(addr2, BIT(9));
+}
+
+void test_setbits_le16(void)
+{
+ setbits_le16(addr2, BIT(10));
+}
+
+void test_clrsetbits_le16(void)
+{
+ clrsetbits_le16(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be16(void)
+{
+ clrbits_be16(addr2, BIT(9));
+}
+
+void test_setbits_be16(void)
+{
+ setbits_be16(addr2, BIT(10));
+}
+
+void test_clrsetbits_be16(void)
+{
+ clrsetbits_be16(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_le32(void)
+{
+ clrbits_le32(addr2, BIT(9));
+}
+
+void test_setbits_le32(void)
+{
+ setbits_le32(addr2, BIT(10));
+}
+
+void test_clrsetbits_le32(void)
+{
+ clrsetbits_le32(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be32(void)
+{
+ clrbits_be32(addr2, BIT(9));
+}
+
+void test_setbits_be32(void)
+{
+ setbits_be32(addr2, BIT(10));
+}
+
+void test_clrsetbits_be32(void)
+{
+ clrsetbits_be32(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_le64(void)
+{
+ clrbits_le64(addr2, BIT(9));
+}
+
+void test_setbits_le64(void)
+{
+ setbits_le64(addr2, BIT(10));
+}
+
+void test_clrsetbits_le64(void)
+{
+ clrsetbits_le64(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be64(void)
+{
+ clrbits_be64(addr2, BIT(9));
+}
+
+void test_setbits_be64(void)
+{
+ setbits_be64(addr2, BIT(10));
+}
+
+void test_clrsetbits_be64(void)
+{
+ clrsetbits_be64(addr2, BIT(9), BIT(10));
+}
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v4 5/6] MIPS: implement bit manipulating I/O accessors
2016-01-12 20:48 ` [U-Boot] [PATCH v3 5/6] MIPS: implement bit manipulating I/O accessors Daniel Schwierzeck
@ 2016-01-15 14:54 ` Daniel Schwierzeck
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2016-01-15 14:54 UTC (permalink / raw)
To: u-boot
Add support for functions clrbits_X(), setbits_X() and clrsetbits_X()
on MIPS.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
@Wills, after rebasing my own SoC code to this series and trying to use the new accessors
I've hit the same problems with endianess in a driver. My drivers have to support Big and
Little Endian, thus I have to use __raw_readX/__raw_writeX. So I also added variants
of the new accessors without swapping and a similar behaviour as __raw_readX/__raw_writeX.
This should address your concers too.
Changes in v4:
- added clrbits_X(), setbits_X() and clrsetbits_X() variants without endianess swapping
Changes in v3: None
Changes in v2: None
arch/mips/include/asm/io.h | 55 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index eb06afa..b8ac5a5 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -541,4 +541,59 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
+#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_SETBITS(bwlq, sfx, end, type) \
+ \
+static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
+ type clr, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+__BUILD_CLRBITS(bwlq, sfx, end, type) \
+__BUILD_SETBITS(bwlq, sfx, end, type) \
+__BUILD_CLRSETBITS(bwlq, sfx, end, type)
+
+#define __to_cpu(v) (v)
+#define cpu_to__(v) (v)
+
+BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, le16, u16)
+BUILD_CLRSETBITS(w, be16, be16, u16)
+BUILD_CLRSETBITS(w, 16, _, u16)
+BUILD_CLRSETBITS(l, le32, le32, u32)
+BUILD_CLRSETBITS(l, be32, be32, u32)
+BUILD_CLRSETBITS(l, 32, _, u32)
+BUILD_CLRSETBITS(q, le64, le64, u64)
+BUILD_CLRSETBITS(q, be64, be64, u64)
+BUILD_CLRSETBITS(q, 64, _, u64)
+
#endif /* _ASM_IO_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-01-15 14:54 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-12 20:48 [U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4 Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 1/6] net: pcnet: refactor mapping of virtual addresses to physical ones Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 2/6] MIPS: sync I/O related header files with linux-4.4 Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 3/6] MIPS: sync processor and register definitions " Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 4/6] MIPS: fix SPDX license identifier in remaining arch header files Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 5/6] MIPS: implement bit manipulating I/O accessors Daniel Schwierzeck
2016-01-15 14:54 ` [U-Boot] [PATCH v4 " Daniel Schwierzeck
2016-01-12 20:48 ` [U-Boot] [PATCH v3 6/6] MIPS: DO NOT MERGE: test " Daniel Schwierzeck
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