[RFC 0/4] MIPS: ath79: introduce AR9331 devicetree support

[RFC 0/4] MIPS: ath79: introduce AR9331 devicetree support

[Antony Pavlov]

This patchseries also can be found on github:

     https://github.com/frantony/linux/tree/20160118.v4.4-mr3020-dt

Antony Pavlov (4):
  WIP: MIPS: ath79: make ar933x clks more devicetree-friendly
  MIPS: dts: qca: introduces AR9331 devicetree
  MIPS: ath79: add initial support for TP-LINK MR3020
  WIP: MIPS: add tl-mr3020-dt-raw_defconfig

 arch/mips/ath79/Kconfig                      |   5 ++
 arch/mips/ath79/clock.c                      |  20 +++--
 arch/mips/boot/dts/qca/Makefile              |   1 +
 arch/mips/boot/dts/qca/ar9331.dtsi           | 113 +++++++++++++++++++++++++++
 arch/mips/boot/dts/qca/tl_mr3020.dts         |  68 ++++++++++++++++
 arch/mips/configs/tl-mr3020-dt-raw_defconfig |  85 ++++++++++++++++++++
 include/dt-bindings/clock/ar933x-clk.h       |  22 ++++++
 7 files changed, 307 insertions(+), 7 deletions(-)
 create mode 100644 arch/mips/boot/dts/qca/ar9331.dtsi
 create mode 100644 arch/mips/boot/dts/qca/tl_mr3020.dts
 create mode 100644 arch/mips/configs/tl-mr3020-dt-raw_defconfig
 create mode 100644 include/dt-bindings/clock/ar933x-clk.h

Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org

-- 
2.6.2

[RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Antony Pavlov]

At the moment ar933x of-enabled drivers use use clock names
(e.g. "uart" or "ahb") to get clk descriptor.
On the other hand Documentation/devicetree/bindings/clock/clock-bindings.txt
states that the 'clocks' property is required for passing clk
to clock consumers.

This commit prepares ar933x clk code for using 'clocks' property
in the clock consumers code.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/ath79/clock.c                | 20 +++++++++++++-------
 include/dt-bindings/clock/ar933x-clk.h | 22 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index eb5117c..4c20813 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -156,6 +156,10 @@ static void __init ar913x_clocks_init(void)
 	clk_add_alias("uart", NULL, "ahb", NULL);
 }
 
+#include <dt-bindings/clock/ar933x-clk.h>
+
+static struct clk *ar933x_clks[AR933X_CLK_END];
+
 static void __init ar933x_clocks_init(void)
 {
 	unsigned long ref_rate;
@@ -167,6 +171,9 @@ static void __init ar933x_clocks_init(void)
 	u32 freq;
 	u32 t;
 
+	clk_data.clks = ar933x_clks;
+	clk_data.clk_num = AR933X_CLK_END;
+
 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 		ref_rate = (40 * 1000 * 1000);
@@ -209,13 +216,12 @@ static void __init ar933x_clocks_init(void)
 		ahb_rate = freq / t;
 	}
 
-	ath79_add_sys_clkdev("ref", ref_rate);
-	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
-	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
-	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
-
-	clk_add_alias("wdt", NULL, "ahb", NULL);
-	clk_add_alias("uart", NULL, "ref", NULL);
+	ar933x_clks[AR933X_CLK_REF] = ath79_add_sys_clkdev("ref", ref_rate);
+	ar933x_clks[AR933X_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	ar933x_clks[AR933X_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	ar933x_clks[AR933X_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+	ar933x_clks[AR933X_CLK_WDT] = ath79_add_sys_clkdev("wdt", ahb_rate);
+	ar933x_clks[AR933X_CLK_UART] = ath79_add_sys_clkdev("uart", ref_rate);
 }
 
 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
diff --git a/include/dt-bindings/clock/ar933x-clk.h b/include/dt-bindings/clock/ar933x-clk.h
new file mode 100644
index 0000000..ed9e5d5
--- /dev/null
+++ b/include/dt-bindings/clock/ar933x-clk.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_AR933X_CLK_H
+#define __DT_BINDINGS_AR933X_CLK_H
+
+#define AR933X_CLK_REF		0
+#define AR933X_CLK_CPU		1
+#define AR933X_CLK_DDR		2
+#define AR933X_CLK_AHB		3
+#define AR933X_CLK_WDT		4
+#define AR933X_CLK_UART		5
+
+#define AR933X_CLK_END		6
+
+#endif /* __DT_BINDINGS_AR933X_CLK_H */
-- 
2.6.2

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[RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Antony Pavlov]

At the moment ar933x of-enabled drivers use use clock names
(e.g. "uart" or "ahb") to get clk descriptor.
On the other hand Documentation/devicetree/bindings/clock/clock-bindings.txt
states that the 'clocks' property is required for passing clk
to clock consumers.

This commit prepares ar933x clk code for using 'clocks' property
in the clock consumers code.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/ath79/clock.c                | 20 +++++++++++++-------
 include/dt-bindings/clock/ar933x-clk.h | 22 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index eb5117c..4c20813 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -156,6 +156,10 @@ static void __init ar913x_clocks_init(void)
 	clk_add_alias("uart", NULL, "ahb", NULL);
 }
 
+#include <dt-bindings/clock/ar933x-clk.h>
+
+static struct clk *ar933x_clks[AR933X_CLK_END];
+
 static void __init ar933x_clocks_init(void)
 {
 	unsigned long ref_rate;
@@ -167,6 +171,9 @@ static void __init ar933x_clocks_init(void)
 	u32 freq;
 	u32 t;
 
+	clk_data.clks = ar933x_clks;
+	clk_data.clk_num = AR933X_CLK_END;
+
 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 		ref_rate = (40 * 1000 * 1000);
@@ -209,13 +216,12 @@ static void __init ar933x_clocks_init(void)
 		ahb_rate = freq / t;
 	}
 
-	ath79_add_sys_clkdev("ref", ref_rate);
-	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
-	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
-	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
-
-	clk_add_alias("wdt", NULL, "ahb", NULL);
-	clk_add_alias("uart", NULL, "ref", NULL);
+	ar933x_clks[AR933X_CLK_REF] = ath79_add_sys_clkdev("ref", ref_rate);
+	ar933x_clks[AR933X_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
+	ar933x_clks[AR933X_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
+	ar933x_clks[AR933X_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+	ar933x_clks[AR933X_CLK_WDT] = ath79_add_sys_clkdev("wdt", ahb_rate);
+	ar933x_clks[AR933X_CLK_UART] = ath79_add_sys_clkdev("uart", ref_rate);
 }
 
 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
diff --git a/include/dt-bindings/clock/ar933x-clk.h b/include/dt-bindings/clock/ar933x-clk.h
new file mode 100644
index 0000000..ed9e5d5
--- /dev/null
+++ b/include/dt-bindings/clock/ar933x-clk.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_AR933X_CLK_H
+#define __DT_BINDINGS_AR933X_CLK_H
+
+#define AR933X_CLK_REF		0
+#define AR933X_CLK_CPU		1
+#define AR933X_CLK_DDR		2
+#define AR933X_CLK_AHB		3
+#define AR933X_CLK_WDT		4
+#define AR933X_CLK_UART		5
+
+#define AR933X_CLK_END		6
+
+#endif /* __DT_BINDINGS_AR933X_CLK_H */
-- 
2.6.2

[RFC 2/4] MIPS: dts: qca: introduces AR9331 devicetree

[Antony Pavlov]

This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Access Points and Routers.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/ar9331.dtsi | 113 +++++++++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 0000000..49513b0
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi
@@ -0,0 +1,113 @@
+#include <dt-bindings/clock/ar933x-clk.h>
+
+/ {
+	compatible = "qca,ar9331";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			ddr_ctrl: memory-controller@18000000 {
+				compatible = "qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x14>;
+
+				interrupts = <3>;
+
+				clocks = <&pll AR933X_CLK_UART>;
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar7100-gpio";
+				reg = <0x18040000 0x34>;
+				interrupts = <2>;
+
+				ngpios = <30>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9330-pll";
+				reg = <0x18050000 0x20>;
+
+				#clock-cells = <1>;
+			};
+
+			miscintc: interrupt-controller@18060010 {
+				compatible = "qca,ar7240-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi";
+				reg = <0x1f000000 0x10>;
+
+				clocks = <&pll AR933X_CLK_AHB>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
2.6.2

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[RFC 2/4] MIPS: dts: qca: introduces AR9331 devicetree

[Antony Pavlov]

This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Access Points and Routers.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/boot/dts/qca/ar9331.dtsi | 113 +++++++++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 0000000..49513b0
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi
@@ -0,0 +1,113 @@
+#include <dt-bindings/clock/ar933x-clk.h>
+
+/ {
+	compatible = "qca,ar9331";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			ddr_ctrl: memory-controller@18000000 {
+				compatible = "qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x14>;
+
+				interrupts = <3>;
+
+				clocks = <&pll AR933X_CLK_UART>;
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar7100-gpio";
+				reg = <0x18040000 0x34>;
+				interrupts = <2>;
+
+				ngpios = <30>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9330-pll";
+				reg = <0x18050000 0x20>;
+
+				#clock-cells = <1>;
+			};
+
+			miscintc: interrupt-controller@18060010 {
+				compatible = "qca,ar7240-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi";
+				reg = <0x1f000000 0x10>;
+
+				clocks = <&pll AR933X_CLK_AHB>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
2.6.2

[RFC 3/4] MIPS: ath79: add initial support for TP-LINK MR3020

[Antony Pavlov]

Currently only the UART, SPI-flash and LEDs are supported.

Links:

  * http://www.tp-link.com/en/products/details/?model=TL-MR3020
  * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
  * https://wikidevi.com/wiki/TP-LINK_TL-MR3020

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/ath79/Kconfig              |  5 +++
 arch/mips/boot/dts/qca/Makefile      |  1 +
 arch/mips/boot/dts/qca/tl_mr3020.dts | 68 ++++++++++++++++++++++++++++++++++++
 3 files changed, 74 insertions(+)

diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 13c04cf..bbd7a1f 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -81,6 +81,11 @@ choice
 		bool "TL-WR1043ND Version 1"
 		select BUILTIN_DTB
 		select SOC_AR913X
+
+	config DTB_TL_MR3020
+		bool "TL-MR3020"
+		select BUILTIN_DTB
+		select SOC_AR933X
 endchoice
 
 endmenu
diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 2d61455d..8c96d67 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
 
 # Select a DTB to build in the kernel
 obj-$(CONFIG_DTB_TL_WR1043ND_V1)	+= ar9132_tl_wr1043nd_v1.dtb.o
+obj-$(CONFIG_DTB_TL_MR3020)		+= tl_mr3020.dtb.o
 
 # Force kbuild to make empty built-in.o if necessary
 obj-				+= dummy.o
diff --git a/arch/mips/boot/dts/qca/tl_mr3020.dts b/arch/mips/boot/dts/qca/tl_mr3020.dts
new file mode 100644
index 0000000..571989b
--- /dev/null
+++ b/arch/mips/boot/dts/qca/tl_mr3020.dts
@@ -0,0 +1,68 @@
+/dts-v1/;
+
+#include "ar9331.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "TP-Link TL-MR3020";
+	compatible = "tplink,tl-mr3020";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "tp-link:green:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "tp-link:green:lan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wps {
+			label = "tp-link:green:wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led3g {
+			label = "tp-link:green:3g";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Spansion S25FL032PIF SPI flash */
+	spiflash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "m25p80";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.6.2

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[RFC 3/4] MIPS: ath79: add initial support for TP-LINK MR3020

[Antony Pavlov]

Currently only the UART, SPI-flash and LEDs are supported.

Links:

  * http://www.tp-link.com/en/products/details/?model=TL-MR3020
  * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
  * https://wikidevi.com/wiki/TP-LINK_TL-MR3020

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/ath79/Kconfig              |  5 +++
 arch/mips/boot/dts/qca/Makefile      |  1 +
 arch/mips/boot/dts/qca/tl_mr3020.dts | 68 ++++++++++++++++++++++++++++++++++++
 3 files changed, 74 insertions(+)

diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 13c04cf..bbd7a1f 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -81,6 +81,11 @@ choice
 		bool "TL-WR1043ND Version 1"
 		select BUILTIN_DTB
 		select SOC_AR913X
+
+	config DTB_TL_MR3020
+		bool "TL-MR3020"
+		select BUILTIN_DTB
+		select SOC_AR933X
 endchoice
 
 endmenu
diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 2d61455d..8c96d67 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
 
 # Select a DTB to build in the kernel
 obj-$(CONFIG_DTB_TL_WR1043ND_V1)	+= ar9132_tl_wr1043nd_v1.dtb.o
+obj-$(CONFIG_DTB_TL_MR3020)		+= tl_mr3020.dtb.o
 
 # Force kbuild to make empty built-in.o if necessary
 obj-				+= dummy.o
diff --git a/arch/mips/boot/dts/qca/tl_mr3020.dts b/arch/mips/boot/dts/qca/tl_mr3020.dts
new file mode 100644
index 0000000..571989b
--- /dev/null
+++ b/arch/mips/boot/dts/qca/tl_mr3020.dts
@@ -0,0 +1,68 @@
+/dts-v1/;
+
+#include "ar9331.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "TP-Link TL-MR3020";
+	compatible = "tplink,tl-mr3020";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "tp-link:green:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "tp-link:green:lan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wps {
+			label = "tp-link:green:wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led3g {
+			label = "tp-link:green:3g";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Spansion S25FL032PIF SPI flash */
+	spiflash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "m25p80";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.6.2

[RFC 4/4] WIP: MIPS: add tl-mr3020-dt-raw_defconfig

[Antony Pavlov]

The tl-mr3020-dt-raw_defconfig conf file is used
to demonstrate devicetree-enabled linux kernel
runs on TP-LINK MR3020 board with u-boot_mod bootloader.

Here is a small instruction:

1. download rootfs.mipsI.cpio image into your linux kernel
   source root dir.

    $ wget https://github.com/frantony/linux/raw/c95a5953e3dd96ad304de515f79acb555e0bc24e/rootfs.mipsI.cpio

2. you have to disable fw_getenv() function because
devicetree-enabled kernel will hangs if started
from u-boot_mod:

    > --- a/arch/mips/fw/lib/cmdline.c
    > +++ b/arch/mips/fw/lib/cmdline.c
    > @@ -51,6 +51,8 @@ char *fw_getenv(char *envname)
    > {
    >        char *result = NULL;
    >
    > +       return result;
    > +

2. compile vmlinux.bin kernel image, e.g.

    $ make ARCH=mips tl-mr3020-dt-raw_defconfig
    $ make ARCH=mips CROSS_COMPILE=<your cross compiler> vmlinux.bin

3. put the vmlinux.bin to root directory of your tftp-server

4. connect to u-boot_mod console

5. download vmlinux.bin into RAM and run it:

   uboot> setenv serverip 192.168.1.2; setenv ipaddr 192.168.1.22
   uboot> tftpboot 0x80060000 vmlinux.bin; go 0x80060000

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/configs/tl-mr3020-dt-raw_defconfig | 85 ++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/arch/mips/configs/tl-mr3020-dt-raw_defconfig b/arch/mips/configs/tl-mr3020-dt-raw_defconfig
new file mode 100644
index 0000000..00cf775
--- /dev/null
+++ b/arch/mips/configs/tl-mr3020-dt-raw_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ATH79=y
+CONFIG_DTB_TL_MR3020=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="rootfs.mipsI.cpio"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_NETDEVICES=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_ATH79=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="init=/bin/sh machtype=DTB console=ttyATH0 root=/dev/ram"
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_CRC_ITU_T=y
-- 
2.6.2

Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Alban]

On Mon, 18 Jan 2016 02:56:24 +0300
Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> At the moment ar933x of-enabled drivers use use clock names
> (e.g. "uart" or "ahb") to get clk descriptor.
> On the other hand
> Documentation/devicetree/bindings/clock/clock-bindings.txt states
> that the 'clocks' property is required for passing clk to clock
> consumers.

This patch is not need, you should set the clock-names property in
the relevant device nodes instead.

Alban
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Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Alban]

On Mon, 18 Jan 2016 02:56:24 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> At the moment ar933x of-enabled drivers use use clock names
> (e.g. "uart" or "ahb") to get clk descriptor.
> On the other hand
> Documentation/devicetree/bindings/clock/clock-bindings.txt states
> that the 'clocks' property is required for passing clk to clock
> consumers.

This patch is not need, you should set the clock-names property in
the relevant device nodes instead.

Alban

Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Antony Pavlov]

On Mon, 18 Jan 2016 20:57:25 +0100
Alban <albeu-GANU6spQydw@public.gmane.org> wrote:

> On Mon, 18 Jan 2016 02:56:24 +0300
> Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> 
> > At the moment ar933x of-enabled drivers use use clock names
> > (e.g. "uart" or "ahb") to get clk descriptor.
> > On the other hand
> > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > that the 'clocks' property is required for passing clk to clock
> > consumers.
> 
> This patch is not need, you should set the clock-names property in
> the relevant device nodes instead.

This patch is needed for AR9331!

In ar933x_clocks_init() we have

        ath79_add_sys_clkdev("ref", ref_rate);
        clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
        clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
        clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

        clk_add_alias("wdt", NULL, "ahb", NULL);
        clk_add_alias("uart", NULL, "ref", NULL);

"uart" is an alias for "ref". But "ref" is not visible via device tree!

I see this error message on ar933x-uart start:
 
     ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)

 
-- 
Best regards,
  Antony Pavlov
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Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Antony Pavlov]

On Mon, 18 Jan 2016 20:57:25 +0100
Alban <albeu@free.fr> wrote:

> On Mon, 18 Jan 2016 02:56:24 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> > At the moment ar933x of-enabled drivers use use clock names
> > (e.g. "uart" or "ahb") to get clk descriptor.
> > On the other hand
> > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > that the 'clocks' property is required for passing clk to clock
> > consumers.
> 
> This patch is not need, you should set the clock-names property in
> the relevant device nodes instead.

This patch is needed for AR9331!

In ar933x_clocks_init() we have

        ath79_add_sys_clkdev("ref", ref_rate);
        clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
        clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
        clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

        clk_add_alias("wdt", NULL, "ahb", NULL);
        clk_add_alias("uart", NULL, "ref", NULL);

"uart" is an alias for "ref". But "ref" is not visible via device tree!

I see this error message on ar933x-uart start:
 
     ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)

 
-- 
Best regards,
  Antony Pavlov

Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Alban]

On Thu, 21 Jan 2016 03:12:15 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> On Mon, 18 Jan 2016 20:57:25 +0100
> Alban <albeu@free.fr> wrote:
> 
> > On Mon, 18 Jan 2016 02:56:24 +0300
> > Antony Pavlov <antonynpavlov@gmail.com> wrote:
> > 
> > > At the moment ar933x of-enabled drivers use use clock names
> > > (e.g. "uart" or "ahb") to get clk descriptor.
> > > On the other hand
> > > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > > that the 'clocks' property is required for passing clk to clock
> > > consumers.
> > 
> > This patch is not need, you should set the clock-names property in
> > the relevant device nodes instead.
> 
> This patch is needed for AR9331!
> 
> In ar933x_clocks_init() we have
> 
>         ath79_add_sys_clkdev("ref", ref_rate);
>         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
>         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
>         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
> 
>         clk_add_alias("wdt", NULL, "ahb", NULL);
>         clk_add_alias("uart", NULL, "ref", NULL);
> 
> "uart" is an alias for "ref". But "ref" is not visible via device tree!
> 
> I see this error message on ar933x-uart start:
>  
>      ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)

The ref clock should be defined in the board DTS, I now see that it is
missing in yours. What you need to do is to define the clock-names
property in the Soc DTS, that allow the names lookup to work. Then in
the board DTS you can define the clock property to connect it to the
proper parent. 

I'm also working on supporting the QCA9558 and the clock tree is similar.
See https://github.com/AlbanBedel/linux/commit/d6c8f8adfce08972c6
as example.

Alban

Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Antony Pavlov]

On Thu, 21 Jan 2016 09:12:17 +0100
Alban <albeu-GANU6spQydw@public.gmane.org> wrote:

> On Thu, 21 Jan 2016 03:12:15 +0300
> Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> 
> > On Mon, 18 Jan 2016 20:57:25 +0100
> > Alban <albeu-GANU6spQydw@public.gmane.org> wrote:
> > 
> > > On Mon, 18 Jan 2016 02:56:24 +0300
> > > Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > > 
> > > > At the moment ar933x of-enabled drivers use use clock names
> > > > (e.g. "uart" or "ahb") to get clk descriptor.
> > > > On the other hand
> > > > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > > > that the 'clocks' property is required for passing clk to clock
> > > > consumers.
> > > 
> > > This patch is not need, you should set the clock-names property in
> > > the relevant device nodes instead.
> > 
> > This patch is needed for AR9331!
> > 
> > In ar933x_clocks_init() we have
> > 
> >         ath79_add_sys_clkdev("ref", ref_rate);
> >         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
> >         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
> >         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
> > 
> >         clk_add_alias("wdt", NULL, "ahb", NULL);
> >         clk_add_alias("uart", NULL, "ref", NULL);
> > 
> > "uart" is an alias for "ref". But "ref" is not visible via device tree!
> > 
> > I see this error message on ar933x-uart start:
> >  
> >      ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)
> 
> The ref clock should be defined in the board DTS, I now see that it is
> missing in yours. What you need to do is to define the clock-names
> property in the Soc DTS, that allow the names lookup to work. Then in
> the board DTS you can define the clock property to connect it to the
> proper parent. 
> 
> I'm also working on supporting the QCA9558 and the clock tree is similar.
> See https://github.com/AlbanBedel/linux/commit/d6c8f8adfce08972c6
> as example.

Current ath79 clock.c code does not read ref clock from devicetree!
So you can set any clock rate value in board DTS but it will has no effect
on the real clk calculation.

A more reasonable solution is used for CI20 board.
In arch/mips/boot/dts/ingenic/jz4780.dtsi we have

	ext: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

...

	cgu: jz4780-cgu@10000000 {
		compatible = "ingenic,jz4780-cgu";
		reg = <0x10000000 0x100>;

		clocks = <&ext>, <&rtc>;
		clock-names = "ext", "rtc";

		#clock-cells = <1>;
	};


In arch/mips/boot/dts/ingenic/ci20.dts we have

&ext {
	clock-frequency = <48000000>;
};

At last drivers/clk/ingenic/jz4780-cgu.c registers this "ext" clock
as a parent of most other subordianate clocks. So there is no magic
frequency constants in drivers/clk/ingenic!

In arch/mips/ath79/clocks.c we have a very different situation:
the reference clock frequences are already hardcoded in C-code so there is
no need to mention them in devicetree files.

-- 
Best regards,
  Antony Pavlov
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Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Antony Pavlov]

On Thu, 21 Jan 2016 09:12:17 +0100
Alban <albeu@free.fr> wrote:

> On Thu, 21 Jan 2016 03:12:15 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> > On Mon, 18 Jan 2016 20:57:25 +0100
> > Alban <albeu@free.fr> wrote:
> > 
> > > On Mon, 18 Jan 2016 02:56:24 +0300
> > > Antony Pavlov <antonynpavlov@gmail.com> wrote:
> > > 
> > > > At the moment ar933x of-enabled drivers use use clock names
> > > > (e.g. "uart" or "ahb") to get clk descriptor.
> > > > On the other hand
> > > > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > > > that the 'clocks' property is required for passing clk to clock
> > > > consumers.
> > > 
> > > This patch is not need, you should set the clock-names property in
> > > the relevant device nodes instead.
> > 
> > This patch is needed for AR9331!
> > 
> > In ar933x_clocks_init() we have
> > 
> >         ath79_add_sys_clkdev("ref", ref_rate);
> >         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
> >         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
> >         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
> > 
> >         clk_add_alias("wdt", NULL, "ahb", NULL);
> >         clk_add_alias("uart", NULL, "ref", NULL);
> > 
> > "uart" is an alias for "ref". But "ref" is not visible via device tree!
> > 
> > I see this error message on ar933x-uart start:
> >  
> >      ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)
> 
> The ref clock should be defined in the board DTS, I now see that it is
> missing in yours. What you need to do is to define the clock-names
> property in the Soc DTS, that allow the names lookup to work. Then in
> the board DTS you can define the clock property to connect it to the
> proper parent. 
> 
> I'm also working on supporting the QCA9558 and the clock tree is similar.
> See https://github.com/AlbanBedel/linux/commit/d6c8f8adfce08972c6
> as example.

Current ath79 clock.c code does not read ref clock from devicetree!
So you can set any clock rate value in board DTS but it will has no effect
on the real clk calculation.

A more reasonable solution is used for CI20 board.
In arch/mips/boot/dts/ingenic/jz4780.dtsi we have

	ext: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

...

	cgu: jz4780-cgu@10000000 {
		compatible = "ingenic,jz4780-cgu";
		reg = <0x10000000 0x100>;

		clocks = <&ext>, <&rtc>;
		clock-names = "ext", "rtc";

		#clock-cells = <1>;
	};


In arch/mips/boot/dts/ingenic/ci20.dts we have

&ext {
	clock-frequency = <48000000>;
};

At last drivers/clk/ingenic/jz4780-cgu.c registers this "ext" clock
as a parent of most other subordianate clocks. So there is no magic
frequency constants in drivers/clk/ingenic!

In arch/mips/ath79/clocks.c we have a very different situation:
the reference clock frequences are already hardcoded in C-code so there is
no need to mention them in devicetree files.

-- 
Best regards,
  Antony Pavlov

Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Alban]

On Thu, 21 Jan 2016 13:17:11 +0300
Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> On Thu, 21 Jan 2016 09:12:17 +0100
> Alban <albeu-GANU6spQydw@public.gmane.org> wrote:
> 
> > On Thu, 21 Jan 2016 03:12:15 +0300
> > Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > 
> > > On Mon, 18 Jan 2016 20:57:25 +0100
> > > Alban <albeu-GANU6spQydw@public.gmane.org> wrote:
> > > 
> > > > On Mon, 18 Jan 2016 02:56:24 +0300
> > > > Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > > > 
> > > > > At the moment ar933x of-enabled drivers use use clock names
> > > > > (e.g. "uart" or "ahb") to get clk descriptor.
> > > > > On the other hand
> > > > > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > > > > that the 'clocks' property is required for passing clk to clock
> > > > > consumers.
> > > > 
> > > > This patch is not need, you should set the clock-names property in
> > > > the relevant device nodes instead.
> > > 
> > > This patch is needed for AR9331!
> > > 
> > > In ar933x_clocks_init() we have
> > > 
> > >         ath79_add_sys_clkdev("ref", ref_rate);
> > >         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
> > >         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
> > >         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
> > > 
> > >         clk_add_alias("wdt", NULL, "ahb", NULL);
> > >         clk_add_alias("uart", NULL, "ref", NULL);
> > > 
> > > "uart" is an alias for "ref". But "ref" is not visible via device tree!
> > > 
> > > I see this error message on ar933x-uart start:
> > >  
> > >      ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)
> > 
> > The ref clock should be defined in the board DTS, I now see that it is
> > missing in yours. What you need to do is to define the clock-names
> > property in the Soc DTS, that allow the names lookup to work. Then in
> > the board DTS you can define the clock property to connect it to the
> > proper parent. 
> > 
> > I'm also working on supporting the QCA9558 and the clock tree is similar.
> > See https://github.com/AlbanBedel/linux/commit/d6c8f8adfce08972c6
> > as example.
> 
> Current ath79 clock.c code does not read ref clock from devicetree!
> So you can set any clock rate value in board DTS but it will has no effect
> on the real clk calculation.

Yes, the ath79 clock is broken in this respect, however the uart driver
isn't and it will use the clock it receive. The fixed oscillator works
fine on QCA9558 which also use the ref clock for the uart.

> A more reasonable solution is used for CI20 board.
> In arch/mips/boot/dts/ingenic/jz4780.dtsi we have
> 
> 	ext: ext {
> 		compatible = "fixed-clock";
> 		#clock-cells = <0>;
> 	};
> 
> ...
> 
> 	cgu: jz4780-cgu@10000000 {
> 		compatible = "ingenic,jz4780-cgu";
> 		reg = <0x10000000 0x100>;
> 
> 		clocks = <&ext>, <&rtc>;
> 		clock-names = "ext", "rtc";
> 
> 		#clock-cells = <1>;
> 	};
> 
> 
> In arch/mips/boot/dts/ingenic/ci20.dts we have
> 
> &ext {
> 	clock-frequency = <48000000>;
> };
> 
> At last drivers/clk/ingenic/jz4780-cgu.c registers this "ext" clock
> as a parent of most other subordianate clocks. So there is no magic
> frequency constants in drivers/clk/ingenic!
> 
> In arch/mips/ath79/clocks.c we have a very different situation:
> the reference clock frequences are already hardcoded in C-code so there is
> no need to mention them in devicetree files.

No, we need to fix the code to only use the hard coded values for the
legacy platforms.

Alban
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Re: [RFC 1/4] WIP: MIPS: ath79: make ar933x clks more devicetree-friendly

[Alban]

On Thu, 21 Jan 2016 13:17:11 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> On Thu, 21 Jan 2016 09:12:17 +0100
> Alban <albeu@free.fr> wrote:
> 
> > On Thu, 21 Jan 2016 03:12:15 +0300
> > Antony Pavlov <antonynpavlov@gmail.com> wrote:
> > 
> > > On Mon, 18 Jan 2016 20:57:25 +0100
> > > Alban <albeu@free.fr> wrote:
> > > 
> > > > On Mon, 18 Jan 2016 02:56:24 +0300
> > > > Antony Pavlov <antonynpavlov@gmail.com> wrote:
> > > > 
> > > > > At the moment ar933x of-enabled drivers use use clock names
> > > > > (e.g. "uart" or "ahb") to get clk descriptor.
> > > > > On the other hand
> > > > > Documentation/devicetree/bindings/clock/clock-bindings.txt states
> > > > > that the 'clocks' property is required for passing clk to clock
> > > > > consumers.
> > > > 
> > > > This patch is not need, you should set the clock-names property in
> > > > the relevant device nodes instead.
> > > 
> > > This patch is needed for AR9331!
> > > 
> > > In ar933x_clocks_init() we have
> > > 
> > >         ath79_add_sys_clkdev("ref", ref_rate);
> > >         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
> > >         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
> > >         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
> > > 
> > >         clk_add_alias("wdt", NULL, "ahb", NULL);
> > >         clk_add_alias("uart", NULL, "ref", NULL);
> > > 
> > > "uart" is an alias for "ref". But "ref" is not visible via device tree!
> > > 
> > > I see this error message on ar933x-uart start:
> > >  
> > >      ERROR: could not get clock /ahb/apb/uart@18020000:uart(0)
> > 
> > The ref clock should be defined in the board DTS, I now see that it is
> > missing in yours. What you need to do is to define the clock-names
> > property in the Soc DTS, that allow the names lookup to work. Then in
> > the board DTS you can define the clock property to connect it to the
> > proper parent. 
> > 
> > I'm also working on supporting the QCA9558 and the clock tree is similar.
> > See https://github.com/AlbanBedel/linux/commit/d6c8f8adfce08972c6
> > as example.
> 
> Current ath79 clock.c code does not read ref clock from devicetree!
> So you can set any clock rate value in board DTS but it will has no effect
> on the real clk calculation.

Yes, the ath79 clock is broken in this respect, however the uart driver
isn't and it will use the clock it receive. The fixed oscillator works
fine on QCA9558 which also use the ref clock for the uart.

> A more reasonable solution is used for CI20 board.
> In arch/mips/boot/dts/ingenic/jz4780.dtsi we have
> 
> 	ext: ext {
> 		compatible = "fixed-clock";
> 		#clock-cells = <0>;
> 	};
> 
> ...
> 
> 	cgu: jz4780-cgu@10000000 {
> 		compatible = "ingenic,jz4780-cgu";
> 		reg = <0x10000000 0x100>;
> 
> 		clocks = <&ext>, <&rtc>;
> 		clock-names = "ext", "rtc";
> 
> 		#clock-cells = <1>;
> 	};
> 
> 
> In arch/mips/boot/dts/ingenic/ci20.dts we have
> 
> &ext {
> 	clock-frequency = <48000000>;
> };
> 
> At last drivers/clk/ingenic/jz4780-cgu.c registers this "ext" clock
> as a parent of most other subordianate clocks. So there is no magic
> frequency constants in drivers/clk/ingenic!
> 
> In arch/mips/ath79/clocks.c we have a very different situation:
> the reference clock frequences are already hardcoded in C-code so there is
> no need to mention them in devicetree files.

No, we need to fix the code to only use the hard coded values for the
legacy platforms.

Alban