From: John Garry <john.garry@huawei.com> To: <JBottomley@odin.com>, <martin.petersen@oracle.com>, <robh+dt@kernel.org>, <pawel.moll@arm.com>, <mark.rutland@arm.com>, <ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org> Cc: <linuxarm@huawei.com>, <zhangfei.gao@linaro.org>, <xuwei5@hisilicon.com>, <john.garry2@mail.dcu.ie>, <linux-scsi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <arnd@arndb.de>, <devicetree@vger.kernel.org>, John Garry <john.garry@huawei.com> Subject: [RESEND PATCH v2 15/23] hisi_sas: add v2 SATA interrupt handler Date: Tue, 26 Jan 2016 02:47:15 +0800 [thread overview] Message-ID: <1453747643-61875-16-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1453747643-61875-1-git-send-email-john.garry@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 100 +++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 5af2069..c4a887c 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -861,6 +861,86 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) return IRQ_HANDLED; } +static irqreturn_t sata_int_v2_hw(int irq_no, void *p) +{ + struct hisi_sas_phy *phy = p; + struct hisi_hba *hisi_hba = phy->hisi_hba; + struct asd_sas_phy *sas_phy = &phy->sas_phy; + struct device *dev = &hisi_hba->pdev->dev; + struct hisi_sas_initial_fis *initial_fis; + struct dev_to_host_fis *fis; + u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; + irqreturn_t res = IRQ_HANDLED; + u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; + int phy_no; + + phy_no = sas_phy->id; + initial_fis = &hisi_hba->initial_fis[phy_no]; + fis = &initial_fis->fis; + + ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk | 1 << phy_no); + + ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1); + ent_tmp = ent_int; + ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); + if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { + dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); + hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk); + res = IRQ_NONE; + goto end; + } + + if (unlikely(phy_no == 8)) { + u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); + + port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> + PORT_STATE_PHY8_PORT_NUM_OFF; + link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> + PORT_STATE_PHY8_CONN_RATE_OFF; + } else { + port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); + port_id = (port_id >> (4 * phy_no)) & 0xf; + link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); + link_rate = (link_rate >> (phy_no * 4)) & 0xf; + } + + if (port_id == 0xf) { + dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); + res = IRQ_NONE; + goto end; + } + + sas_phy->linkrate = link_rate; + hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, + HARD_PHY_LINKRATE); + phy->maximum_linkrate = hard_phy_linkrate & 0xf; + phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; + + sas_phy->oob_mode = SATA_OOB_MODE; + /* Make up some unique SAS address */ + attached_sas_addr[0] = 0x50; + attached_sas_addr[7] = phy_no; + memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); + memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); + dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); + phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); + phy->port_id = port_id; + phy->phy_type |= PORT_TYPE_SATA; + phy->phy_attached = 1; + phy->identify.device_type = SAS_SATA_DEV; + phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); + phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; + queue_work(hisi_hba->wq, &phy->phyup_ws); + +end: + hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk); + + return res; +} + static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { int_phy_updown_v2_hw, int_chnl_int_v2_hw, @@ -900,6 +980,26 @@ static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) } } + for (i = 0; i < hisi_hba->n_phy; i++) { + struct hisi_sas_phy *phy = &hisi_hba->phy[i]; + int idx = i + 72; /* First SATA interrupt is irq72 */ + + irq = irq_map[idx]; + if (!irq) { + dev_err(dev, "irq init: fail map phy interrupt %d\n", + idx); + return -ENOENT; + } + + rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, + DRV_NAME " sata", phy); + if (rc) { + dev_err(dev, "irq init: could not request " + "sata interrupt %d, rc=%d\n", + irq, rc); + return -ENOENT; + } + } return 0; } -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> To: JBottomley-wo1vFcy6AUs@public.gmane.org, martin.petersen-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org Cc: linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, john.garry2-s/0ZXS5h9803lw97EnAbAg@public.gmane.org, linux-scsi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Subject: [RESEND PATCH v2 15/23] hisi_sas: add v2 SATA interrupt handler Date: Tue, 26 Jan 2016 02:47:15 +0800 [thread overview] Message-ID: <1453747643-61875-16-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1453747643-61875-1-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 100 +++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 5af2069..c4a887c 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -861,6 +861,86 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) return IRQ_HANDLED; } +static irqreturn_t sata_int_v2_hw(int irq_no, void *p) +{ + struct hisi_sas_phy *phy = p; + struct hisi_hba *hisi_hba = phy->hisi_hba; + struct asd_sas_phy *sas_phy = &phy->sas_phy; + struct device *dev = &hisi_hba->pdev->dev; + struct hisi_sas_initial_fis *initial_fis; + struct dev_to_host_fis *fis; + u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; + irqreturn_t res = IRQ_HANDLED; + u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; + int phy_no; + + phy_no = sas_phy->id; + initial_fis = &hisi_hba->initial_fis[phy_no]; + fis = &initial_fis->fis; + + ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk | 1 << phy_no); + + ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1); + ent_tmp = ent_int; + ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); + if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { + dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); + hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk); + res = IRQ_NONE; + goto end; + } + + if (unlikely(phy_no == 8)) { + u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); + + port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> + PORT_STATE_PHY8_PORT_NUM_OFF; + link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> + PORT_STATE_PHY8_CONN_RATE_OFF; + } else { + port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); + port_id = (port_id >> (4 * phy_no)) & 0xf; + link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); + link_rate = (link_rate >> (phy_no * 4)) & 0xf; + } + + if (port_id == 0xf) { + dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); + res = IRQ_NONE; + goto end; + } + + sas_phy->linkrate = link_rate; + hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, + HARD_PHY_LINKRATE); + phy->maximum_linkrate = hard_phy_linkrate & 0xf; + phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; + + sas_phy->oob_mode = SATA_OOB_MODE; + /* Make up some unique SAS address */ + attached_sas_addr[0] = 0x50; + attached_sas_addr[7] = phy_no; + memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); + memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); + dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); + phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); + phy->port_id = port_id; + phy->phy_type |= PORT_TYPE_SATA; + phy->phy_attached = 1; + phy->identify.device_type = SAS_SATA_DEV; + phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); + phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; + queue_work(hisi_hba->wq, &phy->phyup_ws); + +end: + hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk); + + return res; +} + static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { int_phy_updown_v2_hw, int_chnl_int_v2_hw, @@ -900,6 +980,26 @@ static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) } } + for (i = 0; i < hisi_hba->n_phy; i++) { + struct hisi_sas_phy *phy = &hisi_hba->phy[i]; + int idx = i + 72; /* First SATA interrupt is irq72 */ + + irq = irq_map[idx]; + if (!irq) { + dev_err(dev, "irq init: fail map phy interrupt %d\n", + idx); + return -ENOENT; + } + + rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, + DRV_NAME " sata", phy); + if (rc) { + dev_err(dev, "irq init: could not request " + "sata interrupt %d, rc=%d\n", + irq, rc); + return -ENOENT; + } + } return 0; } -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2016-01-25 18:42 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-01-25 18:47 [RESEND PATCH v2 00/23] HiSilicon SAS v2 hw support John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 02/23] hisi_sas: relocate DEV_IS_EXPANDER John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 03/23] hisi_sas: set max commands as configurable John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 04/23] hisi_sas: reduce max itct entries John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 05/23] hisi_sas: add hisi_sas_err_record_v1 John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 06/23] hisi_sas: rename some fields in hisi_sas_itct John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 07/23] hisi_sas: add bare v2 hw driver John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 08/23] hisi_sas: add v2 register definitions John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 09/23] hisi_sas: add v2 hw init John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 10/23] hisi_sas: add init_id_frame_v2_hw() John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 11/23] hisi_sas: add v2 phy init code John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 12/23] hisi_sas: add v2 int init and phy up handler John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 13/23] hisi_sas: add v2 phy down handler John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 14/23] hisi_sas: add v2 channel interrupt handler John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` John Garry [this message] 2016-01-25 18:47 ` [RESEND PATCH v2 15/23] hisi_sas: add v2 SATA " John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 16/23] hisi_sas: add v2 cq " John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 17/23] hisi_sas: add v2 path to send ssp frame John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 18/23] hisi_sas: add v2 code to send smp command John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 19/23] hisi_sas: add v2 code for itct setup and free John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 20/23] hisi_sas: add v2 path to send ATA command John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 21/23] hisi_sas: add v2 slot error handler John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 22/23] hisi_sas: add v2 tmf functions John Garry 2016-01-25 18:47 ` John Garry 2016-01-25 18:47 ` [RESEND PATCH v2 23/23] hisi_sas: update driver version to 1.1 John Garry 2016-01-25 18:47 ` John Garry 2016-02-02 2:12 ` [RESEND PATCH v2 00/23] HiSilicon SAS v2 hw support Martin K. Petersen 2016-02-02 2:12 ` Martin K. Petersen
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