[U-Boot] [PATCH][v2] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471

[U-Boot] [PATCH][v2] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471

[Ashish Kumar]

 * 829520: Code bounded by indirect conditional branch might corrupt instruction stream,
    Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor

 * 833471: VMSR FPSCR functional failure or deadlock
    Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
 v2: Incorporated review comments

 arch/arm/cpu/armv8/start.S                        |   19 +++++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |    4 ++++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 2ee60d6..67b166c 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -168,6 +168,25 @@ apply_a57_core_errata:
 	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_833471
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* FPSCR write flush.
+	 * Note that in some cases where a flush is unnecessary this
+	    could impact performance. */
+	orr	x0, x0, #1 << 38
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_829520
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable Indirect Predictor bit will prevent this erratum
+	    from occurring
+	 * Note that in some cases where a flush is unnecessary this
+	    could impact performance. */
+	orr	x0, x0, #1 << 4
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_833069
 	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
 	/* Disable Enable Invalidates of BTB bit */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..9267082 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -118,6 +118,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008585
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 #define CONFIG_SYS_FSL_ERRATUM_A009635
+/* ARM A57 CORE ERRATA */
+#define CONFIG_ARM_ERRATA_833471
+#define CONFIG_ARM_ERRATA_829520
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
-- 
1.7.6.GIT

[U-Boot] [PATCH][v2] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471

[york sun]

On 01/27/2016 04:39 AM, Ashish Kumar wrote:
>  * 829520: Code bounded by indirect conditional branch might corrupt instruction stream,
>     Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor
> 

For future patches, please wrap back before 72th characters.


>  * 833471: VMSR FPSCR functional failure or deadlock
>     Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush
> 
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---
>  v2: Incorporated review comments
> 
>  arch/arm/cpu/armv8/start.S                        |   19 +++++++++++++++++++
>  arch/arm/include/asm/arch-fsl-layerscape/config.h |    4 ++++
>  2 files changed, 23 insertions(+), 0 deletions(-)

Slightly revised subject and commit message.
Applied to u-boot-fsl-qoriq master branch. Awaiting upstream.

Thanks.

York