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* [PATCH] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
@ 2016-01-27 12:24 ` Alexander Kochetkov
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Kochetkov @ 2016-01-27 12:24 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel,
	Alexander Kochetkov

Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
---
 drivers/clk/rockchip/clk-rk3188.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index fe728f8..50e3eee 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -691,10 +691,10 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
-	COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
+	COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(7), 0,
 			RK2928_CLKGATE_CON(0), 10, GFLAGS),
-	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
+	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
 
 	GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
@ 2016-01-27 12:24 ` Alexander Kochetkov
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Kochetkov @ 2016-01-27 12:24 UTC (permalink / raw)
  To: linux-arm-kernel

Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
---
 drivers/clk/rockchip/clk-rk3188.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index fe728f8..50e3eee 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -691,10 +691,10 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
-	COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
+	COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(7), 0,
 			RK2928_CLKGATE_CON(0), 10, GFLAGS),
-	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
+	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
 
 	GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
  2016-01-27 12:24 ` Alexander Kochetkov
@ 2016-01-28 17:01   ` Heiko Stübner
  -1 siblings, 0 replies; 8+ messages in thread
From: Heiko Stübner @ 2016-01-28 17:01 UTC (permalink / raw)
  To: Alexander Kochetkov
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel

Hi Alexander,

Am Mittwoch, 27. Januar 2016, 15:24:29 schrieb Alexander Kochetkov:
> Allow sclk_i2s0 and i2s0_frac to change their parents rate as
> that the upstream dividers are purely there to feed sclk_i2s0
> 
> Tested on radxarock-lite.
> 
> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>

doesn't apply due to the fractional divider change going into 4.5

please respin on top of 4.5-rc1 (or my clock-branch for 4.6 [0],
but should be the same in that regard).


Thanks
Heiko

[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.6-clk/next

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
@ 2016-01-28 17:01   ` Heiko Stübner
  0 siblings, 0 replies; 8+ messages in thread
From: Heiko Stübner @ 2016-01-28 17:01 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Alexander,

Am Mittwoch, 27. Januar 2016, 15:24:29 schrieb Alexander Kochetkov:
> Allow sclk_i2s0 and i2s0_frac to change their parents rate as
> that the upstream dividers are purely there to feed sclk_i2s0
> 
> Tested on radxarock-lite.
> 
> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>

doesn't apply due to the fractional divider change going into 4.5

please respin on top of 4.5-rc1 (or my clock-branch for 4.6 [0],
but should be the same in that regard).


Thanks
Heiko

[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.6-clk/next

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH v2] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
  2016-01-27 12:24 ` Alexander Kochetkov
@ 2016-01-29  7:58   ` Alexander Kochetkov
  -1 siblings, 0 replies; 8+ messages in thread
From: Alexander Kochetkov @ 2016-01-29  7:58 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel,
	Alexander Kochetkov

Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>

Changes in v2:
Rebased on top of 4.5-rc1 of branch[1]

[1] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.6-clk/next

---
 drivers/clk/rockchip/clk-rk3188.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index cc1d09d..629c65d 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -666,7 +666,7 @@ PNAME(mux_hsicphy_p)		= { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
 				    "gpll", "cpll" };
 
 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
-	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
+	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
@@ -722,7 +722,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
-	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
+	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(7), 0,
 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
 			&rk3188_i2s0_fracmux),
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH v2] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
@ 2016-01-29  7:58   ` Alexander Kochetkov
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Kochetkov @ 2016-01-29  7:58 UTC (permalink / raw)
  To: linux-arm-kernel

Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>

Changes in v2:
Rebased on top of 4.5-rc1 of branch[1]

[1] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.6-clk/next

---
 drivers/clk/rockchip/clk-rk3188.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index cc1d09d..629c65d 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -666,7 +666,7 @@ PNAME(mux_hsicphy_p)		= { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
 				    "gpll", "cpll" };
 
 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
-	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
+	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
@@ -722,7 +722,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
-	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
+	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(7), 0,
 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
 			&rk3188_i2s0_fracmux),
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH v2] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
  2016-01-29  7:58   ` Alexander Kochetkov
@ 2016-01-29  9:21     ` Heiko Stuebner
  -1 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2016-01-29  9:21 UTC (permalink / raw)
  To: Alexander Kochetkov
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel

Hi Alexander,

Am Freitag, 29. Januar 2016, 10:58:02 schrieb Alexander Kochetkov:
> Allow sclk_i2s0 and i2s0_frac to change their parents rate as
> that the upstream dividers are purely there to feed sclk_i2s0
> 
> Tested on radxarock-lite.
> 
> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
> 
> Changes in v2:
> Rebased on top of 4.5-rc1 of branch[1]
> 
> [1]
> https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log
> /?h=v4.6-clk/next

please put these comments (changes in vY, etc) in the "comment section" 
below the "---" in future patches.

I've removed these lines after the Signed-off here and applied the patch to 
my clk branch for 4.6 now.


Thanks
Heiko

> 
> ---
>  drivers/clk/rockchip/clk-rk3188.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3188.c
> b/drivers/clk/rockchip/clk-rk3188.c index cc1d09d..629c65d 100644
> --- a/drivers/clk/rockchip/clk-rk3188.c
> +++ b/drivers/clk/rockchip/clk-rk3188.c
> @@ -666,7 +666,7 @@ PNAME(mux_hsicphy_p)		= { "sclk_otgphy0_480m",
> "sclk_otgphy1_480m", "gpll", "cpll" };
> 
>  static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
> -	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
> +	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
>  			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
> 
>  static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
> @@ -722,7 +722,7 @@ static struct rockchip_clk_branch
> rk3188_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "i2s0_pre",
> "i2s_src", 0,
>  			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
>  			RK2928_CLKGATE_CON(0), 9, GFLAGS),
> -	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
> +	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
>  			RK2928_CLKSEL_CON(7), 0,
>  			RK2928_CLKGATE_CON(0), 10, GFLAGS,
>  			&rk3188_i2s0_fracmux),

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH v2] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
@ 2016-01-29  9:21     ` Heiko Stuebner
  0 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2016-01-29  9:21 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Alexander,

Am Freitag, 29. Januar 2016, 10:58:02 schrieb Alexander Kochetkov:
> Allow sclk_i2s0 and i2s0_frac to change their parents rate as
> that the upstream dividers are purely there to feed sclk_i2s0
> 
> Tested on radxarock-lite.
> 
> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
> 
> Changes in v2:
> Rebased on top of 4.5-rc1 of branch[1]
> 
> [1]
> https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log
> /?h=v4.6-clk/next

please put these comments (changes in vY, etc) in the "comment section" 
below the "---" in future patches.

I've removed these lines after the Signed-off here and applied the patch to 
my clk branch for 4.6 now.


Thanks
Heiko

> 
> ---
>  drivers/clk/rockchip/clk-rk3188.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3188.c
> b/drivers/clk/rockchip/clk-rk3188.c index cc1d09d..629c65d 100644
> --- a/drivers/clk/rockchip/clk-rk3188.c
> +++ b/drivers/clk/rockchip/clk-rk3188.c
> @@ -666,7 +666,7 @@ PNAME(mux_hsicphy_p)		= { "sclk_otgphy0_480m",
> "sclk_otgphy1_480m", "gpll", "cpll" };
> 
>  static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
> -	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
> +	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
>  			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
> 
>  static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
> @@ -722,7 +722,7 @@ static struct rockchip_clk_branch
> rk3188_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "i2s0_pre",
> "i2s_src", 0,
>  			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
>  			RK2928_CLKGATE_CON(0), 9, GFLAGS),
> -	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
> +	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
>  			RK2928_CLKSEL_CON(7), 0,
>  			RK2928_CLKGATE_CON(0), 10, GFLAGS,
>  			&rk3188_i2s0_fracmux),

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-01-29  9:21 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-27 12:24 [PATCH] clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188 Alexander Kochetkov
2016-01-27 12:24 ` Alexander Kochetkov
2016-01-28 17:01 ` Heiko Stübner
2016-01-28 17:01   ` Heiko Stübner
2016-01-29  7:58 ` [PATCH v2] " Alexander Kochetkov
2016-01-29  7:58   ` Alexander Kochetkov
2016-01-29  9:21   ` Heiko Stuebner
2016-01-29  9:21     ` Heiko Stuebner

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