* [U-Boot] [PATCH v1 0/2] Add back P2020DS @ 2016-01-30 22:03 York Sun 2016-01-30 22:03 ` [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" York Sun 2016-01-30 22:03 ` [U-Boot] [PATCH v1 2/2] powerpc: p2020ds: Update DDR speed tables York Sun 0 siblings, 2 replies; 13+ messages in thread From: York Sun @ 2016-01-30 22:03 UTC (permalink / raw) To: u-boot Recently Freescale (now NXP) received order to make more P2020DS. It's better have to U-Boot support than digging out old releases. Changes in v1: Add back P2020DS, using generic board structure. Initial patch to adjust DDR speed tables. York Sun (2): Revert "powerpc: mpc85xx: remove P2020DS board support" powerpc: p2020ds: Update DDR speed tables arch/powerpc/cpu/mpc85xx/Kconfig | 4 + board/freescale/p2020ds/Kconfig | 12 + board/freescale/p2020ds/MAINTAINERS | 10 + board/freescale/p2020ds/Makefile | 12 + board/freescale/p2020ds/ddr.c | 151 +++++++ board/freescale/p2020ds/law.c | 20 + board/freescale/p2020ds/p2020ds.c | 261 ++++++++++++ board/freescale/p2020ds/tlb.c | 91 +++++ configs/P2020DS_36BIT_defconfig | 9 + configs/P2020DS_DDR2_defconfig | 9 + configs/P2020DS_SDCARD_defconfig | 9 + configs/P2020DS_SPIFLASH_defconfig | 9 + configs/P2020DS_defconfig | 8 + doc/README.scrapyard | 1 - include/configs/P2020DS.h | 755 +++++++++++++++++++++++++++++++++++ 15 files changed, 1360 insertions(+), 1 deletion(-) create mode 100644 board/freescale/p2020ds/Kconfig create mode 100644 board/freescale/p2020ds/MAINTAINERS create mode 100644 board/freescale/p2020ds/Makefile create mode 100644 board/freescale/p2020ds/ddr.c create mode 100644 board/freescale/p2020ds/law.c create mode 100644 board/freescale/p2020ds/p2020ds.c create mode 100644 board/freescale/p2020ds/tlb.c create mode 100644 configs/P2020DS_36BIT_defconfig create mode 100644 configs/P2020DS_DDR2_defconfig create mode 100644 configs/P2020DS_SDCARD_defconfig create mode 100644 configs/P2020DS_SPIFLASH_defconfig create mode 100644 configs/P2020DS_defconfig create mode 100644 include/configs/P2020DS.h -- 1.7.9.5 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-01-30 22:03 [U-Boot] [PATCH v1 0/2] Add back P2020DS York Sun @ 2016-01-30 22:03 ` York Sun 2016-01-31 14:19 ` Bin Meng 2016-01-30 22:03 ` [U-Boot] [PATCH v1 2/2] powerpc: p2020ds: Update DDR speed tables York Sun 1 sibling, 1 reply; 13+ messages in thread From: York Sun @ 2016-01-30 22:03 UTC (permalink / raw) To: u-boot This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc. Align with changes since P2020DS was removed, including adding these macros to defconfig CONFIG_SYS_NS16550 CONFIG_CMD_NET CONFIG_NETDEVICES CONFIG_E1000 CONFIG_CMD_DHCP Remove macros and include from board header file, including CONFIG_E1000 CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_SYS_NS16550 config_cmd_default.h CONFIG_CMD_ELF CONFIG_CMD_SETEXPR CONFIG_CMD_NET Fixed checkpatch errors of exceedding 80 characters, etc. Signed-off-by: York Sun <york.sun@nxp.com> --- Changes in v1: Add back P2020DS, using generic board structure. arch/powerpc/cpu/mpc85xx/Kconfig | 4 + board/freescale/p2020ds/Kconfig | 12 + board/freescale/p2020ds/MAINTAINERS | 10 + board/freescale/p2020ds/Makefile | 12 + board/freescale/p2020ds/ddr.c | 128 ++++++ board/freescale/p2020ds/law.c | 20 + board/freescale/p2020ds/p2020ds.c | 261 ++++++++++++ board/freescale/p2020ds/tlb.c | 91 +++++ configs/P2020DS_36BIT_defconfig | 9 + configs/P2020DS_DDR2_defconfig | 9 + configs/P2020DS_SDCARD_defconfig | 9 + configs/P2020DS_SPIFLASH_defconfig | 9 + configs/P2020DS_defconfig | 8 + doc/README.scrapyard | 1 - include/configs/P2020DS.h | 755 +++++++++++++++++++++++++++++++++++ 15 files changed, 1337 insertions(+), 1 deletion(-) create mode 100644 board/freescale/p2020ds/Kconfig create mode 100644 board/freescale/p2020ds/MAINTAINERS create mode 100644 board/freescale/p2020ds/Makefile create mode 100644 board/freescale/p2020ds/ddr.c create mode 100644 board/freescale/p2020ds/law.c create mode 100644 board/freescale/p2020ds/p2020ds.c create mode 100644 board/freescale/p2020ds/tlb.c create mode 100644 configs/P2020DS_36BIT_defconfig create mode 100644 configs/P2020DS_DDR2_defconfig create mode 100644 configs/P2020DS_SDCARD_defconfig create mode 100644 configs/P2020DS_SPIFLASH_defconfig create mode 100644 configs/P2020DS_defconfig create mode 100644 include/configs/P2020DS.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0b89157..b35edfb 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -94,6 +94,9 @@ config TARGET_P1_P2_RDB_PC config TARGET_P1_TWR bool "Support p1_twr" +config TARGET_P2020DS + bool "Support P2020DS" + config TARGET_P2041RDB bool "Support P2041RDB" @@ -174,6 +177,7 @@ source "board/freescale/p1022ds/Kconfig" source "board/freescale/p1023rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" source "board/freescale/p1_twr/Kconfig" +source "board/freescale/p2020ds/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" source "board/freescale/t102xqds/Kconfig" diff --git a/board/freescale/p2020ds/Kconfig b/board/freescale/p2020ds/Kconfig new file mode 100644 index 0000000..e527ec9 --- /dev/null +++ b/board/freescale/p2020ds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2020DS + +config SYS_BOARD + default "p2020ds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "P2020DS" + +endif diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS new file mode 100644 index 0000000..1af28b9 --- /dev/null +++ b/board/freescale/p2020ds/MAINTAINERS @@ -0,0 +1,10 @@ +P2020DS BOARD +M: York Sun <york.sun@nxp.com> +S: Maintained +F: board/freescale/p2020ds/ +F: include/configs/P2020DS.h +F: configs/P2020DS_defconfig +F: configs/P2020DS_36BIT_defconfig +F: configs/P2020DS_DDR2_defconfig +F: configs/P2020DS_SDCARD_defconfig +F: configs/P2020DS_SPIFLASH_defconfig diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile new file mode 100644 index 0000000..ee00806 --- /dev/null +++ b/board/freescale/p2020ds/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p2020ds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c new file mode 100644 index 0000000..22aff48 --- /dev/null +++ b/board/freescale/p2020ds/ddr.c @@ -0,0 +1,128 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> + +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + * + * ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ +static const struct board_specific_parameters dimm0[] = { + /* + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| + */ +#ifdef CONFIG_SYS_FSL_DDR2 + {2, 549, 4, 0x1f, 2, 0}, + {2, 680, 4, 0x1f, 3, 0}, + {2, 850, 4, 0x1f, 4, 0}, + {1, 549, 4, 0x1f, 2, 0}, + {1, 680, 4, 0x1f, 3, 0}, + {1, 850, 4, 0x1f, 4, 0}, +#else + {2, 850, 6, 0x1f, 4, 0}, + {1, 850, 4, 0x1f, 4, 0}, +#endif + {} +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + int i; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + + pbsp = dimm0; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } + +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + popts->wrlvl_en = 1; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x8; + /* Rtt and Rtt_WR override */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_120_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ +} diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c new file mode 100644 index 0000000..9cd4da9 --- /dev/null +++ b/board/freescale/p2020ds/law.c @@ -0,0 +1,20 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c new file mode 100644 index 0000000..d68dfd0 --- /dev/null +++ b/board/freescale/p2020ds/p2020ds.c @@ -0,0 +1,261 @@ +/* + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <fsl_ddr_sdram.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <netdev.h> + +#include "../common/ngpixis.h" +#include "../common/sgmii_riser.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ +#ifdef CONFIG_MMC + ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); +#endif + + return 0; +} + +int checkboard(void) +{ + u8 sw; + + printf("Board: P2020DS Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + /* The lower two bits are the actual vbank number */ + printf("vBank: %d\n", sw & 3); + else + puts("Promjet\n"); + + return 0; +} + +#if !defined(CONFIG_DDR_SPD) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + uint d_init; + + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; + ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; + ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; + ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; + ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; + ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; + + if (!strcmp("performance", getenv("perf_mode"))) { + /* Performance Mode Values */ + + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; + } else { + /* Stable Mode Values */ + + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + + /* ECC will be assumed in stable mode */ + ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; + ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; + ddr->err_sbe = CONFIG_SYS_DDR_SBE; + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; + } + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) + udelay(1000); + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +#endif + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; +} + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_init(tsec_info, num); +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + + FT_FSL_PCI_SETUP; + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif + + return 0; +} +#endif diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c new file mode 100644 index 0000000..53b189a --- /dev/null +++ b/board/freescale/p2020ds/tlb.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_256K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/P2020DS_36BIT_defconfig b/configs/P2020DS_36BIT_defconfig new file mode 100644 index 0000000..13f6429 --- /dev/null +++ b/configs/P2020DS_36BIT_defconfig @@ -0,0 +1,9 @@ +CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2020DS=y +CONFIG_SYS_NS16550=y +CONFIG_CMD_NET=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_CMD_DHCP=y diff --git a/configs/P2020DS_DDR2_defconfig b/configs/P2020DS_DDR2_defconfig new file mode 100644 index 0000000..33bf336 --- /dev/null +++ b/configs/P2020DS_DDR2_defconfig @@ -0,0 +1,9 @@ +CONFIG_SYS_EXTRA_OPTIONS="DDR2" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2020DS=y +CONFIG_SYS_NS16550=y +CONFIG_CMD_NET=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_CMD_DHCP=y diff --git a/configs/P2020DS_SDCARD_defconfig b/configs/P2020DS_SDCARD_defconfig new file mode 100644 index 0000000..39e7a44 --- /dev/null +++ b/configs/P2020DS_SDCARD_defconfig @@ -0,0 +1,9 @@ +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2020DS=y +CONFIG_SYS_NS16550=y +CONFIG_CMD_NET=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_CMD_DHCP=y diff --git a/configs/P2020DS_SPIFLASH_defconfig b/configs/P2020DS_SPIFLASH_defconfig new file mode 100644 index 0000000..3f76529 --- /dev/null +++ b/configs/P2020DS_SPIFLASH_defconfig @@ -0,0 +1,9 @@ +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2020DS=y +CONFIG_SYS_NS16550=y +CONFIG_CMD_NET=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_CMD_DHCP=y diff --git a/configs/P2020DS_defconfig b/configs/P2020DS_defconfig new file mode 100644 index 0000000..550fe0b --- /dev/null +++ b/configs/P2020DS_defconfig @@ -0,0 +1,8 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P2020DS=y +CONFIG_SYS_NS16550=y +CONFIG_CMD_NET=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_CMD_DHCP=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index b7cf62d..7b3e192 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -129,7 +129,6 @@ PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner Total5200 powerpc mpc5xxx ad734f7d 2015-01-23 CATcenter powerpc ppc4xx 5344cc1a 2015-01-23 PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it> -P2020DS powerpc mpc85xx 168dcc6c 2015-01-23 P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu> P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com> P2010RDB powerpc mpc85xx 743d4815 2015-01-23 diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h new file mode 100644 index 0000000..e631d76 --- /dev/null +++ b/include/configs/P2020DS.h @@ -0,0 +1,755 @@ +/* + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * p2020ds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_DISPLAY_BOARDINFO + +#include "../board/freescale/common/ics307_clk.h" + +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_P2020 1 +#define CONFIG_P2020DS 1 +#define CONFIG_MP 1 /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L2 Cache + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_DDR2 +#define CONFIG_SYS_FSL_DDR2 +#else +#define CONFIG_SYS_FSL_DDR3 1 +#endif + +/* ECC will be enabled based on perf_mode environment variable */ +/* #define CONFIG_DDR_ECC */ + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ + +/* Default settings for "stable" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330804 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 +#define CONFIG_SYS_DDR_MODE_1 0x00421422 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x61800100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 +/* Type = DDR3: ECC enabled, No Interleaving */ +#define CONFIG_SYS_DDR_CONTROL 0xE7000000 +#define CONFIG_SYS_DDR_CONTROL2 0x24400011 +#define CONFIG_SYS_DDR_CDR1 0x00040000 +#define CONFIG_SYS_DDR_CDR2 0x00000000 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00010000 + +/* Settings that differ for "performance" mode */ +/* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F +/* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce +/* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ +#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 + +/* + * The following set of values were tested for DDR2 + * with a DDR3 to DDR2 interposer + * +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 +#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 +#define CONFIG_SYS_DDR_MODE_1 0x00480432 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x06180100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 +#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC3008000 +#define CONFIG_SYS_DDR_CONTROL2 0x04400010 + * + */ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 + +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#ifdef CONFIG_FSL_NGPIXIS +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x20 +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size used in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* for malloc */ + +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ + CONFIG_SYS_NAND_BASE + 0x40000, \ + CONFIG_SYS_NAND_BASE + 0x80000,\ + CONFIG_SYS_NAND_BASE + 0xC0000} +#define CONFIG_SYS_MAX_NAND_DEVICE 4 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base addr */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base addr */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR4_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#define CONFIG_SYS_BR5_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM + +#define CONFIG_SYS_BR6_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 1" +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "ULI" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_PCI) + +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + +/* SRIO1 uses the same window as PCIE2 mem window */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +/* SRIO2 uses the same window as PCIE1 mem window */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA +#define CONFIG_SATA_ULI5288 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE \ + (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE +#endif /* SCSI */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1b + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 */ +#endif + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif +#endif + +/* + * SDHC/MMC + */ +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_IPADDR 192.168.1.254 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "perf_mode=performance\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=ulpi\0" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ + "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2020ds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "othbootargs=cache-sram-size=0x10000\0" \ + "fdtfile=p2020ds/p2020ds.dtb\0" \ + "bdev=sda3\0" \ + "partition=scsi 0:0\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load $partition $loadaddr $bootfile;" \ + "ext2load $partition $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-01-30 22:03 ` [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" York Sun @ 2016-01-31 14:19 ` Bin Meng 2016-01-31 15:40 ` Simon Glass 2016-02-01 17:37 ` york sun 0 siblings, 2 replies; 13+ messages in thread From: Bin Meng @ 2016-01-31 14:19 UTC (permalink / raw) To: u-boot Hi York, On Sun, Jan 31, 2016 at 6:03 AM, York Sun <york.sun@nxp.com> wrote: > This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc. > Align with changes since P2020DS was removed, including adding > these macros to defconfig > > CONFIG_SYS_NS16550 > CONFIG_CMD_NET > CONFIG_NETDEVICES > CONFIG_E1000 > CONFIG_CMD_DHCP > > Remove macros and include from board header file, including > CONFIG_E1000 > CONFIG_MTD_NAND_VERIFY_WRITE > CONFIG_SYS_NS16550 > config_cmd_default.h > CONFIG_CMD_ELF > CONFIG_CMD_SETEXPR > CONFIG_CMD_NET > While we bring this board back, I believe we should add driver model support this this board as well, at least NS16550. > Fixed checkpatch errors of exceedding 80 characters, etc. > > Signed-off-by: York Sun <york.sun@nxp.com> > > --- > > Changes in v1: > Add back P2020DS, using generic board structure. > > arch/powerpc/cpu/mpc85xx/Kconfig | 4 + > board/freescale/p2020ds/Kconfig | 12 + > board/freescale/p2020ds/MAINTAINERS | 10 + > board/freescale/p2020ds/Makefile | 12 + > board/freescale/p2020ds/ddr.c | 128 ++++++ > board/freescale/p2020ds/law.c | 20 + > board/freescale/p2020ds/p2020ds.c | 261 ++++++++++++ > board/freescale/p2020ds/tlb.c | 91 +++++ > configs/P2020DS_36BIT_defconfig | 9 + > configs/P2020DS_DDR2_defconfig | 9 + > configs/P2020DS_SDCARD_defconfig | 9 + > configs/P2020DS_SPIFLASH_defconfig | 9 + > configs/P2020DS_defconfig | 8 + > doc/README.scrapyard | 1 - > include/configs/P2020DS.h | 755 +++++++++++++++++++++++++++++++++++ > 15 files changed, 1337 insertions(+), 1 deletion(-) > create mode 100644 board/freescale/p2020ds/Kconfig > create mode 100644 board/freescale/p2020ds/MAINTAINERS > create mode 100644 board/freescale/p2020ds/Makefile > create mode 100644 board/freescale/p2020ds/ddr.c > create mode 100644 board/freescale/p2020ds/law.c > create mode 100644 board/freescale/p2020ds/p2020ds.c > create mode 100644 board/freescale/p2020ds/tlb.c > create mode 100644 configs/P2020DS_36BIT_defconfig > create mode 100644 configs/P2020DS_DDR2_defconfig > create mode 100644 configs/P2020DS_SDCARD_defconfig > create mode 100644 configs/P2020DS_SPIFLASH_defconfig > create mode 100644 configs/P2020DS_defconfig > create mode 100644 include/configs/P2020DS.h > > diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig > index 0b89157..b35edfb 100644 > --- a/arch/powerpc/cpu/mpc85xx/Kconfig > +++ b/arch/powerpc/cpu/mpc85xx/Kconfig > @@ -94,6 +94,9 @@ config TARGET_P1_P2_RDB_PC > config TARGET_P1_TWR > bool "Support p1_twr" > > +config TARGET_P2020DS > + bool "Support P2020DS" > + > config TARGET_P2041RDB > bool "Support P2041RDB" > > @@ -174,6 +177,7 @@ source "board/freescale/p1022ds/Kconfig" > source "board/freescale/p1023rdb/Kconfig" > source "board/freescale/p1_p2_rdb_pc/Kconfig" > source "board/freescale/p1_twr/Kconfig" > +source "board/freescale/p2020ds/Kconfig" > source "board/freescale/p2041rdb/Kconfig" > source "board/freescale/qemu-ppce500/Kconfig" > source "board/freescale/t102xqds/Kconfig" > diff --git a/board/freescale/p2020ds/Kconfig b/board/freescale/p2020ds/Kconfig > new file mode 100644 > index 0000000..e527ec9 > --- /dev/null > +++ b/board/freescale/p2020ds/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_P2020DS > + > +config SYS_BOARD > + default "p2020ds" > + > +config SYS_VENDOR > + default "freescale" > + > +config SYS_CONFIG_NAME > + default "P2020DS" > + > +endif > diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS > new file mode 100644 > index 0000000..1af28b9 > --- /dev/null > +++ b/board/freescale/p2020ds/MAINTAINERS > @@ -0,0 +1,10 @@ > +P2020DS BOARD > +M: York Sun <york.sun@nxp.com> > +S: Maintained > +F: board/freescale/p2020ds/ > +F: include/configs/P2020DS.h > +F: configs/P2020DS_defconfig > +F: configs/P2020DS_36BIT_defconfig > +F: configs/P2020DS_DDR2_defconfig > +F: configs/P2020DS_SDCARD_defconfig > +F: configs/P2020DS_SPIFLASH_defconfig > diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile > new file mode 100644 > index 0000000..ee00806 > --- /dev/null > +++ b/board/freescale/p2020ds/Makefile > @@ -0,0 +1,12 @@ > +# > +# Copyright 2007-2009 Freescale Semiconductor, Inc. > +# (C) Copyright 2001-2006 > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += p2020ds.o > +obj-y += ddr.o > +obj-y += law.o > +obj-y += tlb.o > diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c > new file mode 100644 > index 0000000..22aff48 > --- /dev/null > +++ b/board/freescale/p2020ds/ddr.c > @@ -0,0 +1,128 @@ > +/* > + * Copyright 2008-2009 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * Version 2 as published by the Free Software Foundation. > + */ > + > +#include <common.h> > + > +#include <fsl_ddr_sdram.h> > +#include <fsl_ddr_dimm_params.h> > + > +struct board_specific_parameters { > + u32 n_ranks; > + u32 datarate_mhz_high; > + u32 clk_adjust; > + u32 cpo; > + u32 write_data_delay; > + u32 force_2t; > +}; > + > + > +/* > + * This table contains all valid speeds we want to override with board > + * specific parameters. datarate_mhz_high values need to be in ascending order > + * for each n_ranks group. > + * > + * ranges for parameters: > + * wr_data_delay = 0-6 > + * clk adjust = 0-8 > + * cpo 2-0x1E (30) > + */ > +static const struct board_specific_parameters dimm0[] = { > + /* > + * memory controller 0 > + * num| hi| clk| cpo|wrdata|2T > + * ranks| mhz|adjst| | delay| > + */ > +#ifdef CONFIG_SYS_FSL_DDR2 > + {2, 549, 4, 0x1f, 2, 0}, > + {2, 680, 4, 0x1f, 3, 0}, > + {2, 850, 4, 0x1f, 4, 0}, > + {1, 549, 4, 0x1f, 2, 0}, > + {1, 680, 4, 0x1f, 3, 0}, > + {1, 850, 4, 0x1f, 4, 0}, > +#else > + {2, 850, 6, 0x1f, 4, 0}, > + {1, 850, 4, 0x1f, 4, 0}, > +#endif > + {} > +}; > + > +void fsl_ddr_board_options(memctl_options_t *popts, > + dimm_params_t *pdimm, > + unsigned int ctrl_num) > +{ > + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; > + ulong ddr_freq; > + int i; > + > + if (ctrl_num) { > + printf("Wrong parameter for controller number %d", ctrl_num); > + return; > + } > + if (!pdimm->n_ranks) > + return; > + > + /* > + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in > + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If > + * there are two dimms in the controller, set odt_rd_cfg to 3 and > + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. > + */ > + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { > + popts->cs_local_opts[i].odt_rd_cfg = 0; > + popts->cs_local_opts[i].odt_wr_cfg = 1; > + } > + > + pbsp = dimm0; > + > + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr > + * freqency and n_banks specified in board_specific_parameters table. > + */ > + ddr_freq = get_ddr_freq(0) / 1000000; > + while (pbsp->datarate_mhz_high) { > + if (pbsp->n_ranks == pdimm->n_ranks) { > + if (ddr_freq <= pbsp->datarate_mhz_high) { > + popts->clk_adjust = pbsp->clk_adjust; > + popts->cpo_override = pbsp->cpo; > + popts->write_data_delay = > + pbsp->write_data_delay; > + popts->twot_en = pbsp->force_2t; > + goto found; > + } > + pbsp_highest = pbsp; > + } > + pbsp++; > + } > + > + if (pbsp_highest) { > + printf("Error: board specific timing not found for data rate %lu MT/s!\n" > + "Trying to use the highest speed (%u) parameters\n", > + ddr_freq, pbsp_highest->datarate_mhz_high); > + popts->clk_adjust = pbsp_highest->clk_adjust; > + popts->cpo_override = pbsp_highest->cpo; > + popts->write_data_delay = pbsp_highest->write_data_delay; > + popts->twot_en = pbsp_highest->force_2t; > + } else { > + panic("DIMM is not supported by this board"); > + } > + > +found: > + /* > + * Factors to consider for half-strength driver enable: > + * - number of DIMMs installed > + */ > + popts->half_strength_driver_enable = 0; > + popts->wrlvl_en = 1; > + /* Write leveling override */ > + popts->wrlvl_override = 1; > + popts->wrlvl_sample = 0xa; > + popts->wrlvl_start = 0x8; > + /* Rtt and Rtt_WR override */ > + popts->rtt_override = 1; > + popts->rtt_override_value = DDR3_RTT_120_OHM; > + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ > +} > diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c > new file mode 100644 > index 0000000..9cd4da9 > --- /dev/null > +++ b/board/freescale/p2020ds/law.c > @@ -0,0 +1,20 @@ > +/* > + * Copyright 2008-2010 Freescale Semiconductor, Inc. > + * > + * (C) Copyright 2000 > + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/fsl_law.h> > +#include <asm/mmu.h> > + > +struct law_entry law_table[] = { > + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), > + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), > + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), > +}; > + > +int num_law_entries = ARRAY_SIZE(law_table); > diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c > new file mode 100644 > index 0000000..d68dfd0 > --- /dev/null > +++ b/board/freescale/p2020ds/p2020ds.c > @@ -0,0 +1,261 @@ > +/* > + * Copyright 2007-2012 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <command.h> > +#include <pci.h> > +#include <asm/processor.h> > +#include <asm/mmu.h> > +#include <asm/cache.h> > +#include <asm/immap_85xx.h> > +#include <asm/fsl_pci.h> > +#include <fsl_ddr_sdram.h> > +#include <asm/io.h> > +#include <asm/fsl_serdes.h> > +#include <miiphy.h> > +#include <libfdt.h> > +#include <fdt_support.h> > +#include <fsl_mdio.h> > +#include <tsec.h> > +#include <asm/fsl_law.h> > +#include <netdev.h> > + > +#include "../common/ngpixis.h" > +#include "../common/sgmii_riser.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int board_early_init_f(void) > +{ > +#ifdef CONFIG_MMC > + ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); > + > + setbits_be32(&gur->pmuxcr, > + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); > +#endif > + > + return 0; > +} > + > +int checkboard(void) > +{ > + u8 sw; > + > + printf("Board: P2020DS Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", > + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); > + > + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); > + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; > + > + if (sw < 0x8) > + /* The lower two bits are the actual vbank number */ > + printf("vBank: %d\n", sw & 3); > + else > + puts("Promjet\n"); > + > + return 0; > +} > + > +#if !defined(CONFIG_DDR_SPD) > +/* > + * Fixed sdram init -- doesn't use serial presence detect. > + */ > + > +phys_size_t fixed_sdram(void) > +{ > + struct ccsr_ddr __iomem *ddr = > + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; > + uint d_init; > + > + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; > + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; > + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; > + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; > + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; > + ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; > + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; > + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; > + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; > + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; > + ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; > + ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; > + ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; > + ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; > + ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; > + > + if (!strcmp("performance", getenv("perf_mode"))) { > + /* Performance Mode Values */ > + > + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; > + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; > + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; > + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; > + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; > + > + asm("sync;isync"); > + > + udelay(500); > + > + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; > + } else { > + /* Stable Mode Values */ > + > + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; > + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; > + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; > + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; > + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; > + > + /* ECC will be assumed in stable mode */ > + ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; > + ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; > + ddr->err_sbe = CONFIG_SYS_DDR_SBE; > + > + asm("sync;isync"); > + > + udelay(500); > + > + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; > + } > + > +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) > + d_init = 1; > + debug("DDR - 1st controller: memory initializing\n"); > + /* > + * Poll until memory is initialized. > + * 512 Meg at 400 might hit this 200 times or so. > + */ > + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) > + udelay(1000); > + debug("DDR: memory initialized\n\n"); > + asm("sync; isync"); > + udelay(500); > +#endif > + > + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, > + CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, > + LAW_TRGT_IF_DDR) < 0) { > + printf("ERROR setting Local Access Windows for DDR\n"); > + return 0; > + }; > + > + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; > +} > + > +#endif > + > +#ifdef CONFIG_PCI > +void pci_init_board(void) > +{ > + fsl_pcie_init_board(0); > +} > +#endif > + > +int board_early_init_r(void) > +{ > + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; > + int flash_esel = find_tlb_idx((void *)flashbase, 1); > + > + /* > + * Remap Boot flash + PROMJET region to caching-inhibited > + * so that flash can be erased properly. > + */ > + > + /* Flush d-cache and invalidate i-cache of any FLASH data */ > + flush_dcache(); > + invalidate_icache(); > + > + if (flash_esel == -1) { > + /* very unlikely unless something is messed up */ > + puts("Error: Could not find TLB for FLASH BASE\n"); > + flash_esel = 2; /* give our best effort to continue */ > + } else { > + /* invalidate existing TLB entry for flash + promjet */ > + disable_tlb(flash_esel); > + } > + > + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, flash_esel, BOOKE_PAGESZ_256M, 1); > + > + return 0; > +} > + > +#ifdef CONFIG_TSEC_ENET This should be fixed as in this patch http://patchwork.ozlabs.org/patch/566334/ > +int board_eth_init(bd_t *bis) > +{ > + struct fsl_pq_mdio_info mdio_info; > + struct tsec_info_struct tsec_info[4]; > + int num = 0; > + > +#ifdef CONFIG_TSEC1 > + SET_STD_TSEC_INFO(tsec_info[num], 1); > + num++; > +#endif > +#ifdef CONFIG_TSEC2 > + SET_STD_TSEC_INFO(tsec_info[num], 2); > + if (is_serdes_configured(SGMII_TSEC2)) { > + puts("eTSEC2 is in sgmii mode.\n"); > + tsec_info[num].flags |= TSEC_SGMII; > + } > + num++; > +#endif > +#ifdef CONFIG_TSEC3 > + SET_STD_TSEC_INFO(tsec_info[num], 3); > + if (is_serdes_configured(SGMII_TSEC3)) { > + puts("eTSEC3 is in sgmii mode.\n"); > + tsec_info[num].flags |= TSEC_SGMII; > +} > + num++; > +#endif > + > + if (!num) { > + printf("No TSECs initialized\n"); > + > + return 0; > + } > + > +#ifdef CONFIG_FSL_SGMII_RISER > + fsl_sgmii_riser_init(tsec_info, num); > +#endif > + > + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; > + mdio_info.name = DEFAULT_MII_NAME; > + > + fsl_pq_mdio_init(bis, &mdio_info); > + > + tsec_eth_init(bis, tsec_info, num); > + > + return pci_eth_init(bis); > +} > +#endif > + > +#if defined(CONFIG_OF_BOARD_SETUP) > +int ft_board_setup(void *blob, bd_t *bd) > +{ > + phys_addr_t base; > + phys_size_t size; > + > + ft_cpu_setup(blob, bd); > + > + base = getenv_bootm_low(); > + size = getenv_bootm_size(); > + > + fdt_fixup_memory(blob, (u64)base, (u64)size); > + > +#ifdef CONFIG_HAS_FSL_DR_USB > + fdt_fixup_dr_usb(blob, bd); > +#endif > + > + FT_FSL_PCI_SETUP; > + > +#ifdef CONFIG_FSL_SGMII_RISER > + fsl_sgmii_riser_fdt_fixup(blob); > +#endif > + > + return 0; > +} > +#endif > diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c > new file mode 100644 > index 0000000..53b189a > --- /dev/null > +++ b/board/freescale/p2020ds/tlb.c > @@ -0,0 +1,91 @@ > +/* > + * Copyright 2008-2011 Freescale Semiconductor, Inc. > + * > + * (C) Copyright 2000 > + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/mmu.h> > + > +struct fsl_e_tlb_entry tlb_table[] = { > + /* TLB 0 - for temp stack in cache */ > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, > + CONFIG_SYS_INIT_RAM_ADDR_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + > + /* TLB 1 */ > + /* *I*** - Covers boot page */ > + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 0, BOOKE_PAGESZ_4K, 1), > + > + /* *I*G* - CCSRBAR */ > + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 1, BOOKE_PAGESZ_1M, 1), > + > + /* W**G* - Flash/promjet, localbus */ > + /* This will be changed to *I*G* after relocation to RAM. */ > + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, > + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, > + 0, 2, BOOKE_PAGESZ_256M, 1), > + > + /* *I*G* - PCI */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 3, BOOKE_PAGESZ_1G, 1), > + > + /* *I*G* - PCI */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, > + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 4, BOOKE_PAGESZ_256M, 1), > + > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, > + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 5, BOOKE_PAGESZ_256M, 1), > + > + /* *I*G* - PCI I/O */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 6, BOOKE_PAGESZ_256K, 1), > + > + /* *I*G - NAND */ > + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 7, BOOKE_PAGESZ_1M, 1), > + > + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 8, BOOKE_PAGESZ_4K, 1), > + > +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) > + /* *I*G - L2SRAM */ > + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 9, BOOKE_PAGESZ_256K, 1), > + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, > + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 10, BOOKE_PAGESZ_256K, 1), > +#endif > +}; > + > +int num_tlb_entries = ARRAY_SIZE(tlb_table); > diff --git a/configs/P2020DS_36BIT_defconfig b/configs/P2020DS_36BIT_defconfig > new file mode 100644 > index 0000000..13f6429 > --- /dev/null > +++ b/configs/P2020DS_36BIT_defconfig > @@ -0,0 +1,9 @@ > +CONFIG_SYS_EXTRA_OPTIONS="36BIT" > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_P2020DS=y > +CONFIG_SYS_NS16550=y > +CONFIG_CMD_NET=y > +CONFIG_NETDEVICES=y > +CONFIG_E1000=y > +CONFIG_CMD_DHCP=y > diff --git a/configs/P2020DS_DDR2_defconfig b/configs/P2020DS_DDR2_defconfig > new file mode 100644 > index 0000000..33bf336 > --- /dev/null > +++ b/configs/P2020DS_DDR2_defconfig > @@ -0,0 +1,9 @@ > +CONFIG_SYS_EXTRA_OPTIONS="DDR2" > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_P2020DS=y > +CONFIG_SYS_NS16550=y > +CONFIG_CMD_NET=y > +CONFIG_NETDEVICES=y > +CONFIG_E1000=y > +CONFIG_CMD_DHCP=y > diff --git a/configs/P2020DS_SDCARD_defconfig b/configs/P2020DS_SDCARD_defconfig > new file mode 100644 > index 0000000..39e7a44 > --- /dev/null > +++ b/configs/P2020DS_SDCARD_defconfig > @@ -0,0 +1,9 @@ > +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_P2020DS=y > +CONFIG_SYS_NS16550=y > +CONFIG_CMD_NET=y > +CONFIG_NETDEVICES=y > +CONFIG_E1000=y > +CONFIG_CMD_DHCP=y > diff --git a/configs/P2020DS_SPIFLASH_defconfig b/configs/P2020DS_SPIFLASH_defconfig > new file mode 100644 > index 0000000..3f76529 > --- /dev/null > +++ b/configs/P2020DS_SPIFLASH_defconfig > @@ -0,0 +1,9 @@ > +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_P2020DS=y > +CONFIG_SYS_NS16550=y > +CONFIG_CMD_NET=y > +CONFIG_NETDEVICES=y > +CONFIG_E1000=y > +CONFIG_CMD_DHCP=y > diff --git a/configs/P2020DS_defconfig b/configs/P2020DS_defconfig > new file mode 100644 > index 0000000..550fe0b > --- /dev/null > +++ b/configs/P2020DS_defconfig > @@ -0,0 +1,8 @@ > +CONFIG_PPC=y > +CONFIG_MPC85xx=y > +CONFIG_TARGET_P2020DS=y > +CONFIG_SYS_NS16550=y > +CONFIG_CMD_NET=y > +CONFIG_NETDEVICES=y > +CONFIG_E1000=y > +CONFIG_CMD_DHCP=y > diff --git a/doc/README.scrapyard b/doc/README.scrapyard > index b7cf62d..7b3e192 100644 > --- a/doc/README.scrapyard > +++ b/doc/README.scrapyard > @@ -129,7 +129,6 @@ PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner > Total5200 powerpc mpc5xxx ad734f7d 2015-01-23 > CATcenter powerpc ppc4xx 5344cc1a 2015-01-23 > PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it> > -P2020DS powerpc mpc85xx 168dcc6c 2015-01-23 > P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu> > P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com> > P2010RDB powerpc mpc85xx 743d4815 2015-01-23 > diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h > new file mode 100644 > index 0000000..e631d76 > --- /dev/null > +++ b/include/configs/P2020DS.h > @@ -0,0 +1,755 @@ > +/* > + * Copyright 2007-2012 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/* > + * p2020ds board configuration file > + * > + */ > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#define CONFIG_DISPLAY_BOARDINFO > + > +#include "../board/freescale/common/ics307_clk.h" > + > +#ifdef CONFIG_36BIT > +#define CONFIG_PHYS_64BIT > +#endif > + > +#ifdef CONFIG_SDCARD > +#define CONFIG_SYS_RAMBOOT > +#define CONFIG_SYS_EXTRA_ENV_RELOC > +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 > +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc > +#endif > + > +#ifdef CONFIG_SPIFLASH > +#define CONFIG_SYS_RAMBOOT > +#define CONFIG_SYS_EXTRA_ENV_RELOC > +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 > +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc > +#endif > + > +/* High Level Configuration Options */ > +#define CONFIG_BOOKE 1 /* BOOKE */ > +#define CONFIG_E500 1 /* BOOKE e500 family */ > +#define CONFIG_P2020 1 > +#define CONFIG_P2020DS 1 > +#define CONFIG_MP 1 /* support multiple processors */ > + > +#ifndef CONFIG_SYS_TEXT_BASE > +#define CONFIG_SYS_TEXT_BASE 0xeff40000 > +#endif > + > +#ifndef CONFIG_RESET_VECTOR_ADDRESS > +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc > +#endif > + > +#define CONFIG_SYS_SRIO > +#define CONFIG_SRIO1 /* SRIO port 1 */ > +#define CONFIG_SRIO2 /* SRIO port 2 */ > + > +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ > +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ > +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ > +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ > +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ > +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ > +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ > +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ > +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ > + > +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ > + > +#define CONFIG_TSEC_ENET /* tsec ethernet support */ > +#define CONFIG_ENV_OVERWRITE > + > +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ > +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ > +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ > + > +/* > + * These can be toggled for performance analysis, otherwise use default. > + */ > +#define CONFIG_L2_CACHE /* toggle L2 cache */ > +#define CONFIG_BTB /* toggle branch predition */ > + > +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ > + > +#define CONFIG_ENABLE_36BIT_PHYS 1 > + > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_ADDR_MAP 1 > +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ > +#endif > + > +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ > +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ > +#define CONFIG_SYS_MEMTEST_END 0x00400000 > +#define CONFIG_PANIC_HANG /* do not reset board on panic */ > + > +/* > + * Config the L2 Cache > + */ > +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull > +#else > +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR > +#endif > +#define CONFIG_SYS_L2_SIZE (512 << 10) > +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) > + > +#define CONFIG_SYS_CCSRBAR 0xffe00000 > +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR > + > +/* DDR Setup */ > +#define CONFIG_VERY_BIG_RAM > +#ifdef CONFIG_DDR2 > +#define CONFIG_SYS_FSL_DDR2 > +#else > +#define CONFIG_SYS_FSL_DDR3 1 > +#endif > + > +/* ECC will be enabled based on perf_mode environment variable */ > +/* #define CONFIG_DDR_ECC */ > + > +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER > +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef > + > +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 > +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE > + > +#define CONFIG_NUM_DDR_CONTROLLERS 1 > +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 > +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 > + > +/* I2C addresses of SPD EEPROMs */ > +#define CONFIG_DDR_SPD > +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ > +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ > + > +/* These are used when DDR doesn't use SPD. */ > +#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ > + > +/* Default settings for "stable" mode */ > +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F > +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 > +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 > +#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 > +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 > +#define CONFIG_SYS_DDR_TIMING_0 0x00330804 > +#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 > +#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 > +#define CONFIG_SYS_DDR_MODE_1 0x00421422 > +#define CONFIG_SYS_DDR_MODE_2 0x00000000 > +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 > +#define CONFIG_SYS_DDR_INTERVAL 0x61800100 > +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef > +#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 > +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 > +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 > +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 > +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 > +/* Type = DDR3: ECC enabled, No Interleaving */ > +#define CONFIG_SYS_DDR_CONTROL 0xE7000000 > +#define CONFIG_SYS_DDR_CONTROL2 0x24400011 > +#define CONFIG_SYS_DDR_CDR1 0x00040000 > +#define CONFIG_SYS_DDR_CDR2 0x00000000 > + > +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d > +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 > +#define CONFIG_SYS_DDR_SBE 0x00010000 > + > +/* Settings that differ for "performance" mode */ > +/* Interleaving Enabled */ > +#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F > +/* Interleaving Enabled */ > +#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 > +#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 > +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 > +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce > +/* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ > +#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 > + > +/* > + * The following set of values were tested for DDR2 > + * with a DDR3 to DDR2 interposer > + * > +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 > +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 > +#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 > +#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 > +#define CONFIG_SYS_DDR_MODE_1 0x00480432 > +#define CONFIG_SYS_DDR_MODE_2 0x00000000 > +#define CONFIG_SYS_DDR_INTERVAL 0x06180100 > +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef > +#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 > +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 > +#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 > +#define CONFIG_SYS_DDR_CONTROL 0xC3008000 > +#define CONFIG_SYS_DDR_CONTROL2 0x04400010 > + * > + */ > + > +/* > + * Memory map > + * > + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable > + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable > + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable > + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable > + * > + * Localbus cacheable (TBD) > + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable > + * > + * Localbus non-cacheable > + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable > + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable > + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable > + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 > + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 > + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable > + */ > + > +/* > + * Local Bus Definitions > + */ > +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of 128M */ > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull > +#else > +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE > +#endif > + > +#define CONFIG_FLASH_BR_PRELIM \ > + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) > +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 > + > +#define CONFIG_SYS_BR1_PRELIM \ > + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) > +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 > + > +#define CONFIG_SYS_FLASH_BANKS_LIST \ > + {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} > +#define CONFIG_SYS_FLASH_QUIET_TEST > +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ > + > +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ > +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ > +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ > +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ > + > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ > + > +#define CONFIG_FLASH_CFI_DRIVER > +#define CONFIG_SYS_FLASH_CFI > +#define CONFIG_SYS_FLASH_EMPTY_INFO > +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 > + > +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ > + > +#define CONFIG_HWCONFIG /* enable hwconfig */ > +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ > + > +#ifdef CONFIG_FSL_NGPIXIS > +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ > +#ifdef CONFIG_PHYS_64BIT > +#define PIXIS_BASE_PHYS 0xfffdf0000ull > +#else > +#define PIXIS_BASE_PHYS PIXIS_BASE > +#endif > + > +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) > +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but 4k mapped */ > + > +#define PIXIS_LBMAP_SWITCH 7 > +#define PIXIS_LBMAP_MASK 0xf0 > +#define PIXIS_LBMAP_SHIFT 4 > +#define PIXIS_LBMAP_ALTBANK 0x20 > +#endif > + > +#define CONFIG_SYS_INIT_RAM_LOCK 1 > +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR > +/* The assembler doesn't like typecast */ > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ > + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ > + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) > +#else > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS > +#endif > +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size used in RAM */ > + > +#define CONFIG_SYS_GBL_DATA_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET > + > +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) > +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* for malloc */ > + > +#define CONFIG_SYS_NAND_BASE 0xffa00000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull > +#else > +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE > +#endif > +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ > + CONFIG_SYS_NAND_BASE + 0x40000, \ > + CONFIG_SYS_NAND_BASE + 0x80000,\ > + CONFIG_SYS_NAND_BASE + 0xC0000} > +#define CONFIG_SYS_MAX_NAND_DEVICE 4 > +#define CONFIG_CMD_NAND 1 > +#define CONFIG_NAND_FSL_ELBC 1 > +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) > + > +/* NAND flash config */ > +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ > + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ > + | BR_PS_8 /* Port Size = 8bit */ \ > + | BR_MS_FCM /* MSEL = FCM */ \ > + | BR_V) /* valid */ > +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ > + | OR_FCM_PGS /* Large Page*/ \ > + | OR_FCM_CSCT \ > + | OR_FCM_CST \ > + | OR_FCM_CHT \ > + | OR_FCM_SCY_1 \ > + | OR_FCM_TRLX \ > + | OR_FCM_EHTR) > + > +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base addr */ > +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ > +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base addr */ > +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ > + > +#define CONFIG_SYS_BR4_PRELIM \ > + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ > + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ > + | BR_PS_8 /* Port Size = 8bit */ \ > + | BR_MS_FCM /* MSEL = FCM */ \ > + | BR_V) /* valid */ > +#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM > +#define CONFIG_SYS_BR5_PRELIM \ > + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ > + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ > + | BR_PS_8 /* Port Size = 8bit */ \ > + | BR_MS_FCM /* MSEL = FCM */ \ > + | BR_V) /* valid */ > +#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM > + > +#define CONFIG_SYS_BR6_PRELIM \ > + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ > + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ > + | BR_PS_8 /* Port Size = 8bit */ \ > + | BR_MS_FCM /* MSEL = FCM */ \ > + | BR_V) /* valid */ > +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM > + > +/* Serial Port - controlled on board with jumper J8 > + * open - index 2 > + * shorted - index 1 > + */ > +#define CONFIG_CONS_INDEX 1 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE 1 > +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) > + > +#define CONFIG_SYS_BAUDRATE_TABLE \ > + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} > + > +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) > +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) > + > +/* Use the HUSH parser */ > +#define CONFIG_SYS_HUSH_PARSER > + > +/* > + * Pass open firmware flat tree > + */ > +#define CONFIG_OF_LIBFDT 1 > +#define CONFIG_OF_BOARD_SETUP 1 > +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 > + > +/* I2C */ > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_FSL > +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 > +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 > +#define CONFIG_SYS_FSL_I2C_SPEED 400000 > +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F > +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 > +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 > +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } > + > +/* > + * I2C2 EEPROM > + */ > +#define CONFIG_ID_EEPROM > +#ifdef CONFIG_ID_EEPROM > +#define CONFIG_SYS_I2C_EEPROM_NXID > +#endif > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 > +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 > +#define CONFIG_SYS_EEPROM_BUS_NUM 0 > + > +/* > + * eSPI - Enhanced SPI > + */ > +#define CONFIG_FSL_ESPI > + > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_SPANSION > + > +#define CONFIG_CMD_SF > +#define CONFIG_SF_DEFAULT_SPEED 10000000 > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 > + > +/* > + * General PCI > + * Memory space is mapped 1-1, but I/O space must start from 0. > + */ > + > +/* controller 3, Slot 1, tgtid 3, Base address b000 */ > +#define CONFIG_SYS_PCIE3_NAME "Slot 1" > +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull > +#else > +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 > +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 > +#endif > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 > +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull > +#else > +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 > +#endif > +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ > + > +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ > +#define CONFIG_SYS_PCIE2_NAME "ULI" > +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull > +#else > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 > +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 > +#endif > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 > +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull > +#else > +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 > +#endif > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > + > +/* controller 1, Slot 2, tgtid 1, Base address a000 */ > +#define CONFIG_SYS_PCIE1_NAME "Slot 2" > +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull > +#else > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 > +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 > +#endif > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 > +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull > +#else > +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 > +#endif > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > + > +#if defined(CONFIG_PCI) > + > +/*PCIE video card used*/ > +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT > + > +/* video */ > +#undef CONFIG_VIDEO > + > +#if defined(CONFIG_VIDEO) > +#define CONFIG_BIOSEMU > +#define CONFIG_CFB_CONSOLE > +#define CONFIG_VIDEO_SW_CURSOR > +#define CONFIG_VGA_AS_SINGLE_DEVICE > +#define CONFIG_ATI_RADEON_FB > +#define CONFIG_VIDEO_LOGO > +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET > +#endif > + > +/* SRIO1 uses the same window as PCIE2 mem window */ > +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull > +#else > +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 > +#endif > +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ > + > +/* SRIO2 uses the same window as PCIE1 mem window */ > +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull > +#else > +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 > +#endif > +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ > + > +#define CONFIG_PCI_PNP /* do pci plug-and-play */ > +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ > +#define CONFIG_DOS_PARTITION > +#define CONFIG_SCSI_AHCI > + > +#ifdef CONFIG_SCSI_AHCI > +#define CONFIG_LIBATA > +#define CONFIG_SATA_ULI5288 > +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 > +#define CONFIG_SYS_SCSI_MAX_LUN 1 > +#define CONFIG_SYS_SCSI_MAX_DEVICE \ > + (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) > +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE > +#endif /* SCSI */ > + > +#endif /* CONFIG_PCI */ > + > + > +#if defined(CONFIG_TSEC_ENET) > + > +#define CONFIG_MII 1 /* MII PHY management */ > +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ > +#define CONFIG_TSEC1 1 > +#define CONFIG_TSEC1_NAME "eTSEC1" > +#define CONFIG_TSEC2 1 > +#define CONFIG_TSEC2_NAME "eTSEC2" > +#define CONFIG_TSEC3 1 > +#define CONFIG_TSEC3_NAME "eTSEC3" > + > +#define CONFIG_FSL_SGMII_RISER 1 > +#define SGMII_RISER_PHY_OFFSET 0x1b > + > +#ifdef CONFIG_FSL_SGMII_RISER > +#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 */ > +#endif > + > +#define TSEC1_PHY_ADDR 0 > +#define TSEC2_PHY_ADDR 1 > +#define TSEC3_PHY_ADDR 2 > + > +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) > +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) > +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) > + > +#define TSEC1_PHYIDX 0 > +#define TSEC2_PHYIDX 0 > +#define TSEC3_PHYIDX 0 > + > +#define CONFIG_ETHPRIME "eTSEC1" > + > +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ > +#endif /* CONFIG_TSEC_ENET */ > + > +/* > + * Environment > + */ > +#if defined(CONFIG_SDCARD) > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_FSL_FIXED_MMC_LOCATION > +#define CONFIG_ENV_SIZE 0x2000 > +#define CONFIG_SYS_MMC_ENV_DEV 0 > +#elif defined(CONFIG_SPIFLASH) > +#define CONFIG_ENV_IS_IN_SPI_FLASH > +#define CONFIG_ENV_SPI_BUS 0 > +#define CONFIG_ENV_SPI_CS 0 > +#define CONFIG_ENV_SPI_MAX_HZ 10000000 > +#define CONFIG_ENV_SPI_MODE 0 > +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ > +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ > +#define CONFIG_ENV_SECT_SIZE 0x10000 > +#else > +#define CONFIG_ENV_IS_IN_FLASH 1 > +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) > +#define CONFIG_ENV_SIZE 0x2000 > +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ > +#endif > + > +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ > +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ > + > +/* > + * Command line configuration. > + */ > +#define CONFIG_CMD_IRQ > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_I2C > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_IRQ > +#define CONFIG_CMD_REGINFO > + > +#if defined(CONFIG_PCI) > +#define CONFIG_CMD_PCI > +#define CONFIG_CMD_SCSI > +#define CONFIG_CMD_EXT2 > +#endif > + > +/* > + * USB > + */ > +#define CONFIG_HAS_FSL_DR_USB > +#ifdef CONFIG_HAS_FSL_DR_USB > +#define CONFIG_USB_EHCI > + > +#ifdef CONFIG_USB_EHCI > +#define CONFIG_CMD_USB > +#define CONFIG_USB_STORAGE > +#define CONFIG_USB_EHCI_FSL > +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET > +#endif > +#endif > + > +/* > + * SDHC/MMC > + */ > +#define CONFIG_MMC > + > +#ifdef CONFIG_MMC > +#define CONFIG_FSL_ESDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#endif > + > +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > +#define CONFIG_DOS_PARTITION > +#endif > + > +/* > + * Miscellaneous configurable options > + */ > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ > +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ > +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ > +#if defined(CONFIG_CMD_KGDB) > +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ > +#else > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > +#endif > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer size */ > + > +/* > + * For booting Linux, the board info and command line data > + * have to be in the first 64 MB of memory, since this is > + * the maximum mapped by the Linux kernel during initialization. > + */ > +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ > +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ > + > +#if defined(CONFIG_CMD_KGDB) > +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ > +#endif > + > +/* > + * Environment Configuration > + */ > + > +/* The mac addresses for all ethernet interface */ > +#if defined(CONFIG_TSEC_ENET) > +#define CONFIG_HAS_ETH0 > +#define CONFIG_HAS_ETH1 > +#define CONFIG_HAS_ETH2 > +#endif > + > +#define CONFIG_IPADDR 192.168.1.254 > + > +#define CONFIG_HOSTNAME unknown > +#define CONFIG_ROOTPATH "/opt/nfsroot" > +#define CONFIG_BOOTFILE "uImage" > +#define CONFIG_UBOOTPATH u-boot.bin > + > +#define CONFIG_SERVERIP 192.168.1.1 > +#define CONFIG_GATEWAYIP 192.168.1.1 > +#define CONFIG_NETMASK 255.255.255.0 > + > +/* default location for tftp and bootm */ > +#define CONFIG_LOADADDR 1000000 > + > +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ > + > +#define CONFIG_BAUDRATE 115200 > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "perf_mode=performance\0" \ > + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ > + "usb1:dr_mode=host,phy_type=ulpi\0" \ > + "netdev=eth0\0" \ > + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ > + "tftpflash=tftpboot $loadaddr $uboot; " \ > + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ > + "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ > + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ > + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ > + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ > + "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ > + "console=$consoledev,$baudrate $othbootargs;" \ > + "tftp $loadaddr $bootfile;" \ > + "tftp $fdtaddr $fdtfile;" \ > + "bootm $loadaddr - $fdtaddr" \ > + "consoledev=ttyS0\0" \ > + "ramdiskaddr=2000000\0" \ > + "ramdiskfile=p2020ds/ramdisk.uboot\0" \ > + "fdtaddr=c00000\0" \ > + "othbootargs=cache-sram-size=0x10000\0" \ > + "fdtfile=p2020ds/p2020ds.dtb\0" \ > + "bdev=sda3\0" \ > + "partition=scsi 0:0\0" > + > +#define CONFIG_HDBOOT \ > + "setenv bootargs root=/dev/$bdev rw " \ > + "console=$consoledev,$baudrate $othbootargs;" \ > + "ext2load $partition $loadaddr $bootfile;" \ > + "ext2load $partition $fdtaddr $fdtfile;" \ > + "bootm $loadaddr - $fdtaddr" > + > +#define CONFIG_NFSBOOTCOMMAND \ > + "setenv bootargs root=/dev/nfs rw " \ > + "nfsroot=$serverip:$rootpath " \ > + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ > + "console=$consoledev,$baudrate $othbootargs;" \ > + "tftp $loadaddr $bootfile;" \ > + "tftp $fdtaddr $fdtfile;" \ > + "bootm $loadaddr - $fdtaddr" > + > +#define CONFIG_RAMBOOTCOMMAND \ > + "setenv bootargs root=/dev/ram rw " \ > + "console=$consoledev,$baudrate $othbootargs;" \ > + "tftp $ramdiskaddr $ramdiskfile;" \ > + "tftp $loadaddr $bootfile;" \ > + "tftp $fdtaddr $fdtfile;" \ > + "bootm $loadaddr $ramdiskaddr $fdtaddr" > + > +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT > + > +#endif /* __CONFIG_H */ > -- Regards, Bin ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-01-31 14:19 ` Bin Meng @ 2016-01-31 15:40 ` Simon Glass 2016-02-01 19:37 ` york sun 2016-02-01 17:37 ` york sun 1 sibling, 1 reply; 13+ messages in thread From: Simon Glass @ 2016-01-31 15:40 UTC (permalink / raw) To: u-boot Hi, On 31 January 2016 at 07:19, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi York, > > On Sun, Jan 31, 2016 at 6:03 AM, York Sun <york.sun@nxp.com> wrote: >> This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc. >> Align with changes since P2020DS was removed, including adding >> these macros to defconfig >> >> CONFIG_SYS_NS16550 >> CONFIG_CMD_NET >> CONFIG_NETDEVICES >> CONFIG_E1000 >> CONFIG_CMD_DHCP >> >> Remove macros and include from board header file, including >> CONFIG_E1000 >> CONFIG_MTD_NAND_VERIFY_WRITE >> CONFIG_SYS_NS16550 >> config_cmd_default.h >> CONFIG_CMD_ELF >> CONFIG_CMD_SETEXPR >> CONFIG_CMD_NET >> > > While we bring this board back, I believe we should add driver model > support this this board as well, at least NS16550. Yes, since today is the day we are supposed to have all serial drivers converted over. Other things that could perhaps be converted, and would give PPC a better start on driver model: i2c, mmc, usb, Ethernet, PCI :-) > >> Fixed checkpatch errors of exceedding 80 characters, etc. >> >> Signed-off-by: York Sun <york.sun@nxp.com> >> >> --- >> >> Changes in v1: >> Add back P2020DS, using generic board structure. >> [snip] Regards, Simon ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-01-31 15:40 ` Simon Glass @ 2016-02-01 19:37 ` york sun 2016-02-02 0:05 ` Simon Glass 0 siblings, 1 reply; 13+ messages in thread From: york sun @ 2016-02-01 19:37 UTC (permalink / raw) To: u-boot On 01/31/2016 07:40 AM, Simon Glass wrote: > Hi, > > On 31 January 2016 at 07:19, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi York, >> >> On Sun, Jan 31, 2016 at 6:03 AM, York Sun <york.sun@nxp.com> wrote: >>> This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc. >>> Align with changes since P2020DS was removed, including adding >>> these macros to defconfig >>> >>> CONFIG_SYS_NS16550 >>> CONFIG_CMD_NET >>> CONFIG_NETDEVICES >>> CONFIG_E1000 >>> CONFIG_CMD_DHCP >>> >>> Remove macros and include from board header file, including >>> CONFIG_E1000 >>> CONFIG_MTD_NAND_VERIFY_WRITE >>> CONFIG_SYS_NS16550 >>> config_cmd_default.h >>> CONFIG_CMD_ELF >>> CONFIG_CMD_SETEXPR >>> CONFIG_CMD_NET >>> >> >> While we bring this board back, I believe we should add driver model >> support this this board as well, at least NS16550. > > Yes, since today is the day we are supposed to have all serial drivers > converted over. > > Other things that could perhaps be converted, and would give PPC a > better start on driver model: i2c, mmc, usb, Ethernet, PCI :-) > I will take this chance to convert P2020DS to use DM. Need some guidance here. For NS16550, it needs the clock. To keep it simple, let's presume platform data is used. My trouble is the clock is not unknown at compiling time. It needs to be updated by checking the board/soc configuration after power up. The clock is only available after get_clocks() is called in init_sequance. Is there a way I can update the clocks before the driver is initialized? York ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-02-01 19:37 ` york sun @ 2016-02-02 0:05 ` Simon Glass 2016-02-02 3:11 ` york sun 0 siblings, 1 reply; 13+ messages in thread From: Simon Glass @ 2016-02-02 0:05 UTC (permalink / raw) To: u-boot Hi York, On 1 February 2016 at 12:37, york sun <york.sun@nxp.com> wrote: > On 01/31/2016 07:40 AM, Simon Glass wrote: >> Hi, >> >> On 31 January 2016 at 07:19, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi York, >>> >>> On Sun, Jan 31, 2016 at 6:03 AM, York Sun <york.sun@nxp.com> wrote: >>>> This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc. >>>> Align with changes since P2020DS was removed, including adding >>>> these macros to defconfig >>>> >>>> CONFIG_SYS_NS16550 >>>> CONFIG_CMD_NET >>>> CONFIG_NETDEVICES >>>> CONFIG_E1000 >>>> CONFIG_CMD_DHCP >>>> >>>> Remove macros and include from board header file, including >>>> CONFIG_E1000 >>>> CONFIG_MTD_NAND_VERIFY_WRITE >>>> CONFIG_SYS_NS16550 >>>> config_cmd_default.h >>>> CONFIG_CMD_ELF >>>> CONFIG_CMD_SETEXPR >>>> CONFIG_CMD_NET >>>> >>> >>> While we bring this board back, I believe we should add driver model >>> support this this board as well, at least NS16550. >> >> Yes, since today is the day we are supposed to have all serial drivers >> converted over. >> >> Other things that could perhaps be converted, and would give PPC a >> better start on driver model: i2c, mmc, usb, Ethernet, PCI :-) >> > > I will take this chance to convert P2020DS to use DM. Need some guidance here. > For NS16550, it needs the clock. To keep it simple, let's presume platform data > is used. My trouble is the clock is not unknown at compiling time. It needs to > be updated by checking the board/soc configuration after power up. The clock is > only available after get_clocks() is called in init_sequance. Is there a way I > can update the clocks before the driver is initialized? > > York See this commit: 858530a8 dm: tegra: Enable driver model for serial It sets up its own clock. Regards, Simon ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-02-02 0:05 ` Simon Glass @ 2016-02-02 3:11 ` york sun 2016-02-02 3:19 ` Bin Meng 0 siblings, 1 reply; 13+ messages in thread From: york sun @ 2016-02-02 3:11 UTC (permalink / raw) To: u-boot On 02/01/2016 04:05 PM, Simon Glass wrote: <snip> >> >> I will take this chance to convert P2020DS to use DM. Need some guidance here. >> For NS16550, it needs the clock. To keep it simple, let's presume platform data >> is used. My trouble is the clock is not unknown at compiling time. It needs to >> be updated by checking the board/soc configuration after power up. The clock is >> only available after get_clocks() is called in init_sequance. Is there a way I >> can update the clocks before the driver is initialized? >> >> York > > See this commit: > > 858530a8 dm: tegra: Enable driver model for serial > > It sets up its own clock. Simon, Thanks for the pointer. I actually noticed this commit but it adds some confusion to me. Take your code as an example U_BOOT_DRIVER(serial_ns16550) = { .name = "serial_tegra20", .id = UCLASS_SERIAL, .of_match = tegra_serial_ids, .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, }; The name "serial_ns16550" is not directly used anywhere. So I guess you didn't have to name it as "serial_ns16550", right? One step forward, if I want to create a new driver, say "fsl_ns16550", I will have to use ofdata_to_platdata to fill in plat->clock. But for majority powerpc SoCs, we don't use device tree. We may start to use device tree on new products. But it is probably not a good idea to force every platform to change. Is there another way to update plat->clock? York ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-02-02 3:11 ` york sun @ 2016-02-02 3:19 ` Bin Meng 2016-02-02 3:31 ` york sun 0 siblings, 1 reply; 13+ messages in thread From: Bin Meng @ 2016-02-02 3:19 UTC (permalink / raw) To: u-boot Hi York, On Tue, Feb 2, 2016 at 11:11 AM, york sun <york.sun@nxp.com> wrote: > On 02/01/2016 04:05 PM, Simon Glass wrote: > <snip> >>> >>> I will take this chance to convert P2020DS to use DM. Need some guidance here. >>> For NS16550, it needs the clock. To keep it simple, let's presume platform data >>> is used. My trouble is the clock is not unknown at compiling time. It needs to >>> be updated by checking the board/soc configuration after power up. The clock is >>> only available after get_clocks() is called in init_sequance. Is there a way I >>> can update the clocks before the driver is initialized? >>> >>> York >> >> See this commit: >> >> 858530a8 dm: tegra: Enable driver model for serial >> >> It sets up its own clock. > > Simon, > > Thanks for the pointer. I actually noticed this commit but it adds some > confusion to me. Take your code as an example > > U_BOOT_DRIVER(serial_ns16550) = { > .name = "serial_tegra20", > .id = UCLASS_SERIAL, > .of_match = tegra_serial_ids, > .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, > .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), > .priv_auto_alloc_size = sizeof(struct NS16550), > .probe = ns16550_serial_probe, > .ops = &ns16550_serial_ops, > }; > > The name "serial_ns16550" is not directly used anywhere. So I guess you didn't > have to name it as "serial_ns16550", right? > The commit Simon gave was an old one. Now all ns16550 driver has been unified into one. > One step forward, if I want to create a new driver, say "fsl_ns16550", I will > have to use ofdata_to_platdata to fill in plat->clock. But for majority powerpc > SoCs, we don't use device tree. We may start to use device tree on new products. > But it is probably not a good idea to force every platform to change. > Please do not create a new driver for FSL chipset. Does FSL have any plan to continue maintaining all these PowerPC SoCs in U-Boot? If yes, I believe the intention is to bring driver model and device tree to these boards. > Is there another way to update plat->clock? > You can define CONFIG_SYS_NS16550_CLK to a routine that gets the correct clock freq at runtime: eg: get_serial_clock() Regards, Bin ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-02-02 3:19 ` Bin Meng @ 2016-02-02 3:31 ` york sun 2016-02-02 3:42 ` Bin Meng 0 siblings, 1 reply; 13+ messages in thread From: york sun @ 2016-02-02 3:31 UTC (permalink / raw) To: u-boot On 02/01/2016 07:19 PM, Bin Meng wrote: > Hi York, > > On Tue, Feb 2, 2016 at 11:11 AM, york sun <york.sun@nxp.com> wrote: >> On 02/01/2016 04:05 PM, Simon Glass wrote: >> <snip> >>>> >>>> I will take this chance to convert P2020DS to use DM. Need some guidance here. >>>> For NS16550, it needs the clock. To keep it simple, let's presume platform data >>>> is used. My trouble is the clock is not unknown at compiling time. It needs to >>>> be updated by checking the board/soc configuration after power up. The clock is >>>> only available after get_clocks() is called in init_sequance. Is there a way I >>>> can update the clocks before the driver is initialized? >>>> >>>> York >>> >>> See this commit: >>> >>> 858530a8 dm: tegra: Enable driver model for serial >>> >>> It sets up its own clock. >> >> Simon, >> >> Thanks for the pointer. I actually noticed this commit but it adds some >> confusion to me. Take your code as an example >> >> U_BOOT_DRIVER(serial_ns16550) = { >> .name = "serial_tegra20", >> .id = UCLASS_SERIAL, >> .of_match = tegra_serial_ids, >> .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, >> .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), >> .priv_auto_alloc_size = sizeof(struct NS16550), >> .probe = ns16550_serial_probe, >> .ops = &ns16550_serial_ops, >> }; >> >> The name "serial_ns16550" is not directly used anywhere. So I guess you didn't >> have to name it as "serial_ns16550", right? >> > > The commit Simon gave was an old one. Now all ns16550 driver has been > unified into one. > >> One step forward, if I want to create a new driver, say "fsl_ns16550", I will >> have to use ofdata_to_platdata to fill in plat->clock. But for majority powerpc >> SoCs, we don't use device tree. We may start to use device tree on new products. >> But it is probably not a good idea to force every platform to change. >> > > Please do not create a new driver for FSL chipset. Does FSL have any That's a relief. I don't want to create a new driver just for the clock. > plan to continue maintaining all these PowerPC SoCs in U-Boot? If yes, > I believe the intention is to bring driver model and device tree to > these boards. I'd rather to add the device tree step by step, not all at once. And probably leave some legacy boards behind. > >> Is there another way to update plat->clock? >> > > You can define CONFIG_SYS_NS16550_CLK to a routine that gets the > correct clock freq at runtime: eg: get_serial_clock() Please explain in detail. I want to go down this path. For non-device tree platforms (for the time being), doesn't U_BOOT_DEVICES evaluate the platdata at compiling time? How can I use a routine as the clock for ns16550_platdata? It is pretty simple for fixed clock, as I am looking at an example arch/arm/cpu/armv7/am33xx/board.c. York ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-02-02 3:31 ` york sun @ 2016-02-02 3:42 ` Bin Meng 2016-02-02 6:16 ` york sun 0 siblings, 1 reply; 13+ messages in thread From: Bin Meng @ 2016-02-02 3:42 UTC (permalink / raw) To: u-boot Hi York, On Tue, Feb 2, 2016 at 11:31 AM, york sun <york.sun@nxp.com> wrote: > On 02/01/2016 07:19 PM, Bin Meng wrote: >> Hi York, >> >> On Tue, Feb 2, 2016 at 11:11 AM, york sun <york.sun@nxp.com> wrote: >>> On 02/01/2016 04:05 PM, Simon Glass wrote: >>> <snip> >>>>> >>>>> I will take this chance to convert P2020DS to use DM. Need some guidance here. >>>>> For NS16550, it needs the clock. To keep it simple, let's presume platform data >>>>> is used. My trouble is the clock is not unknown at compiling time. It needs to >>>>> be updated by checking the board/soc configuration after power up. The clock is >>>>> only available after get_clocks() is called in init_sequance. Is there a way I >>>>> can update the clocks before the driver is initialized? >>>>> >>>>> York >>>> >>>> See this commit: >>>> >>>> 858530a8 dm: tegra: Enable driver model for serial >>>> >>>> It sets up its own clock. >>> >>> Simon, >>> >>> Thanks for the pointer. I actually noticed this commit but it adds some >>> confusion to me. Take your code as an example >>> >>> U_BOOT_DRIVER(serial_ns16550) = { >>> .name = "serial_tegra20", >>> .id = UCLASS_SERIAL, >>> .of_match = tegra_serial_ids, >>> .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, >>> .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), >>> .priv_auto_alloc_size = sizeof(struct NS16550), >>> .probe = ns16550_serial_probe, >>> .ops = &ns16550_serial_ops, >>> }; >>> >>> The name "serial_ns16550" is not directly used anywhere. So I guess you didn't >>> have to name it as "serial_ns16550", right? >>> >> >> The commit Simon gave was an old one. Now all ns16550 driver has been >> unified into one. >> >>> One step forward, if I want to create a new driver, say "fsl_ns16550", I will >>> have to use ofdata_to_platdata to fill in plat->clock. But for majority powerpc >>> SoCs, we don't use device tree. We may start to use device tree on new products. >>> But it is probably not a good idea to force every platform to change. >>> >> >> Please do not create a new driver for FSL chipset. Does FSL have any > > That's a relief. I don't want to create a new driver just for the clock. > >> plan to continue maintaining all these PowerPC SoCs in U-Boot? If yes, >> I believe the intention is to bring driver model and device tree to >> these boards. > > I'd rather to add the device tree step by step, not all at once. And probably > leave some legacy boards behind. > Agreed. We can add device tree and driver model drivers to these PowerPC boards step by step as long as they are maintained. There is no need to add them in a bunch. It's easy to convert these PowerPC boards to driver model, given they share some of the IPs in the new LayerScape ARM SoCs. >> >>> Is there another way to update plat->clock? >>> >> >> You can define CONFIG_SYS_NS16550_CLK to a routine that gets the >> correct clock freq at runtime: eg: get_serial_clock() > > Please explain in detail. I want to go down this path. For non-device tree > platforms (for the time being), doesn't U_BOOT_DEVICES evaluate the platdata at > compiling time? How can I use a routine as the clock for ns16550_platdata? > It is pretty simple for fixed clock, as I am looking at an example > arch/arm/cpu/armv7/am33xx/board.c. > We should add device tree to these platforms. The non-device tree (U_BOOT_DEVICES) was mainly for some SPL boards which does not have enough RAM before memory is initialized. I think you may refer to this patch: http://patchwork.ozlabs.org/patch/561853/ Regards, Bin ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-02-02 3:42 ` Bin Meng @ 2016-02-02 6:16 ` york sun 0 siblings, 0 replies; 13+ messages in thread From: york sun @ 2016-02-02 6:16 UTC (permalink / raw) To: u-boot On 02/01/2016 07:42 PM, Bin Meng wrote: <snip> Bin, > We should add device tree to these platforms. The non-device tree > (U_BOOT_DEVICES) was mainly for some SPL boards which does not have > enough RAM before memory is initialized. I think you may refer to this > patch: http://patchwork.ozlabs.org/patch/561853/ I looked into ls1021atwr earlier, ns16550 driver takes default value CONFIG_SYS_NS16550_CLK when the device tree doesn't have the clock-frequency node. It is a smart solution for device-tree enabled platforms. Even I believe we want to go with device tree for new boards, I don't believe driver model has to be used with device tree. We have many boards with sd/spi/nand boot options, including the P2020DS I am trying to bring back. York ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" 2016-01-31 14:19 ` Bin Meng 2016-01-31 15:40 ` Simon Glass @ 2016-02-01 17:37 ` york sun 1 sibling, 0 replies; 13+ messages in thread From: york sun @ 2016-02-01 17:37 UTC (permalink / raw) To: u-boot On 01/31/2016 06:19 AM, Bin Meng wrote: > Hi York, > > On Sun, Jan 31, 2016 at 6:03 AM, York Sun <york.sun@nxp.com> wrote: >> This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc. >> Align with changes since P2020DS was removed, including adding >> these macros to defconfig >> >> CONFIG_SYS_NS16550 >> CONFIG_CMD_NET >> CONFIG_NETDEVICES >> CONFIG_E1000 >> CONFIG_CMD_DHCP >> >> Remove macros and include from board header file, including >> CONFIG_E1000 >> CONFIG_MTD_NAND_VERIFY_WRITE >> CONFIG_SYS_NS16550 >> config_cmd_default.h >> CONFIG_CMD_ELF >> CONFIG_CMD_SETEXPR >> CONFIG_CMD_NET >> > > While we bring this board back, I believe we should add driver model > support this this board as well, at least NS16550. Thanks for the reminder. Let me work on it. <snip> >> + >> +#ifdef CONFIG_TSEC_ENET > > This should be fixed as in this patch http://patchwork.ozlabs.org/patch/566334/ > Thanks for catching this. York ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v1 2/2] powerpc: p2020ds: Update DDR speed tables 2016-01-30 22:03 [U-Boot] [PATCH v1 0/2] Add back P2020DS York Sun 2016-01-30 22:03 ` [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" York Sun @ 2016-01-30 22:03 ` York Sun 1 sibling, 0 replies; 13+ messages in thread From: York Sun @ 2016-01-30 22:03 UTC (permalink / raw) To: u-boot As old DIMMs are EOL, new DIMMs need some adjustment to the speed table. It is necessary to separate UDIMM and RDIMM for DDR3. Verified on iDIMM M3CN-2GSF3C09-G. Signed-off-by: York Sun <york.sun@nxp.com> --- Changes in v1: Initial patch to adjust DDR speed tables. board/freescale/p2020ds/ddr.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 22aff48..f7e58ef 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -31,7 +31,27 @@ struct board_specific_parameters { * clk adjust = 0-8 * cpo 2-0x1E (30) */ -static const struct board_specific_parameters dimm0[] = { +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| + */ +#ifdef CONFIG_SYS_FSL_DDR2 + {2, 549, 4, 0x1f, 2, 0}, + {2, 680, 4, 0x1f, 3, 0}, + {2, 850, 4, 0x1f, 4, 0}, + {1, 549, 4, 0x1f, 2, 0}, + {1, 680, 4, 0x1f, 3, 0}, + {1, 850, 4, 0x1f, 4, 0}, +#else + {2, 850, 4, 0x1f, 4, 0}, + {1, 850, 4, 0x1f, 4, 0}, +#endif + {} +}; + +static const struct board_specific_parameters rdimm0[] = { /* * memory controller 0 * num| hi| clk| cpo|wrdata|2T @@ -77,7 +97,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = 1; } - pbsp = dimm0; + if (popts->registered_dimm_en) + pbsp = rdimm0; + else + pbsp = udimm0; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-02-02 6:16 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-01-30 22:03 [U-Boot] [PATCH v1 0/2] Add back P2020DS York Sun 2016-01-30 22:03 ` [U-Boot] [PATCH v1 1/2] Revert "powerpc: mpc85xx: remove P2020DS board support" York Sun 2016-01-31 14:19 ` Bin Meng 2016-01-31 15:40 ` Simon Glass 2016-02-01 19:37 ` york sun 2016-02-02 0:05 ` Simon Glass 2016-02-02 3:11 ` york sun 2016-02-02 3:19 ` Bin Meng 2016-02-02 3:31 ` york sun 2016-02-02 3:42 ` Bin Meng 2016-02-02 6:16 ` york sun 2016-02-01 17:37 ` york sun 2016-01-30 22:03 ` [U-Boot] [PATCH v1 2/2] powerpc: p2020ds: Update DDR speed tables York Sun
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