[PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

The NAND Flash controller for SAMA5D2 has small differences that make it
impossible to use the existing driver for SAMA5D3. This patchset uses the
device tree's compatible string to get those differences, and the code is
slightly modified to handle them.

Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0

See previous revisions to apply on the Atmel Linux 4.1 branch.

Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
existing SAMA5D2 board with NAND Flash memory (yet).

V3 -> V2:
- Rebase on linux-mtd-next
- Skip patches already in the tree

V2 -> V1:
- Rebase on v4.4
- Use of_device_get_match_data
- Split message cleanup
- Reword a small part of the atmel_nand device tree binding
- Use 'caps' for all private data structures

RFC -> V1:
- Split the support of 32-bit ECC on SAMA5D2 in two commits
- Fix the missing ECC strength configuration code

Romain Izard (5):
  mtd: atmel_nand: Support variable RB_EDGE interrupts
  dt-bindings: atmel_nand: Reword the documenation
  mtd: atmel_nand: Support PMECC on SAMA5D2
  mtd: atmel_nand: Support 32-bit ECC strength
  ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

 .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
 arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
 drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
 drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
 drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
 5 files changed, 131 insertions(+), 27 deletions(-)

-- 
2.5.0

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[PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

The NAND Flash controller for SAMA5D2 has small differences that make it
impossible to use the existing driver for SAMA5D3. This patchset uses the
device tree's compatible string to get those differences, and the code is
slightly modified to handle them.

Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0

See previous revisions to apply on the Atmel Linux 4.1 branch.

Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
existing SAMA5D2 board with NAND Flash memory (yet).

V3 -> V2:
- Rebase on linux-mtd-next
- Skip patches already in the tree

V2 -> V1:
- Rebase on v4.4
- Use of_device_get_match_data
- Split message cleanup
- Reword a small part of the atmel_nand device tree binding
- Use 'caps' for all private data structures

RFC -> V1:
- Split the support of 32-bit ECC on SAMA5D2 in two commits
- Fix the missing ECC strength configuration code

Romain Izard (5):
  mtd: atmel_nand: Support variable RB_EDGE interrupts
  dt-bindings: atmel_nand: Reword the documenation
  mtd: atmel_nand: Support PMECC on SAMA5D2
  mtd: atmel_nand: Support 32-bit ECC strength
  ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

 .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
 arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
 drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
 drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
 drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
 5 files changed, 131 insertions(+), 27 deletions(-)

-- 
2.5.0

[PATCH v3 1/5] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Romain Izard]

The NFC controller used to accelerate the NAND transfers on SAMA5 chips
can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.

Use the controller's compatible string to select the correct bit.

For the binding:
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Reviewed-by: Wenyou Yang <Wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
v3: constify atmel_nand_nfc_caps structures
v2: use of_device_get_match_data

    rename struct atmel_nand_nfc_priv as atmel_nand_nfc_caps
    rename member rb_edge as rb_mask
    do not create defines for unused status bits

 .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-
 drivers/mtd/nand/atmel_nand.c                      | 35 +++++++++++++++++-----
 drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
 3 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 7d4c8eb775a5..89b0db9801b0 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -34,7 +34,7 @@ Optional properties:
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
   - Required properties:
-    - compatible : "atmel,sama5d3-nfc".
+    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
     - reg : should specify the address and size used for NFC command registers,
             NFC registers and NFC Sram. NFC Sram address and size can be absent
             if don't want to use it.
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index affe7a7e9ad7..600c77cb70ef 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -67,6 +67,10 @@ struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
 };
 
+struct atmel_nand_nfc_caps {
+	uint32_t rb_mask;
+};
+
 /* oob layout for large page size
  * bad block info is on bytes 0 and 1
  * the bytes have to be consecutives to avoid
@@ -111,6 +115,7 @@ struct atmel_nfc {
 	/* Point to the sram bank which include readed data via NFC */
 	void			*data_in_sram;
 	bool			will_write_sram;
+	const struct atmel_nand_nfc_caps *caps;
 };
 static struct atmel_nfc	nand_nfc;
 
@@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
 		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
 		ret = IRQ_HANDLED;
 	}
-	if (pending & NFC_SR_RB_EDGE) {
+	if (pending & host->nfc->caps->rb_mask) {
 		complete(&host->nfc->comp_ready);
-		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
+		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->caps->rb_mask);
 		ret = IRQ_HANDLED;
 	}
 	if (pending & NFC_SR_CMD_DONE) {
@@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		init_completion(&host->nfc->comp_xfer_done);
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->caps->rb_mask)
 		init_completion(&host->nfc->comp_ready);
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		comp[index++] = &host->nfc->comp_xfer_done;
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->caps->rb_mask)
 		comp[index++] = &host->nfc->comp_ready;
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
 		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
 				mask & status);
 
-	return status & NFC_SR_RB_EDGE;
+	return status & host->nfc->caps->rb_mask;
 }
 
 static void nfc_select_chip(struct mtd_info *mtd, int chip)
@@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 		}
 		/* fall through */
 	default:
-		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
-		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
+		nfc_prepare_interrupt(host, host->nfc->caps->rb_mask);
+		nfc_wait_interrupt(host, host->nfc->caps->rb_mask);
 	}
 }
 
@@ -2352,6 +2357,11 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
 		}
 	}
 
+	nfc->caps = (const struct atmel_nand_nfc_caps *)
+		of_device_get_match_data(&pdev->dev);
+	if (NULL == nfc->caps)
+		return -ENODEV;
+
 	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
 	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
 
@@ -2380,8 +2390,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct atmel_nand_nfc_caps sama5d3_nfc_caps = {
+	.rb_mask = NFC_SR_RB_EDGE0,
+};
+
+static const struct atmel_nand_nfc_caps sama5d4_nfc_caps = {
+	.rb_mask = NFC_SR_RB_EDGE3,
+};
+
 static const struct of_device_id atmel_nand_nfc_match[] = {
-	{ .compatible = "atmel,sama5d3-nfc" },
+	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_caps },
+	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_caps },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
index 4d5d26221a7e..0bbc1fa97dba 100644
--- a/drivers/mtd/nand/atmel_nand_nfc.h
+++ b/drivers/mtd/nand/atmel_nand_nfc.h
@@ -42,7 +42,8 @@
 #define		NFC_SR_UNDEF		(1 << 21)
 #define		NFC_SR_AWB		(1 << 22)
 #define		NFC_SR_ASE		(1 << 23)
-#define		NFC_SR_RB_EDGE		(1 << 24)
+#define		NFC_SR_RB_EDGE0		(1 << 24)
+#define		NFC_SR_RB_EDGE3		(1 << 27)
 
 #define ATMEL_HSMC_NFC_IER	0x0c
 #define ATMEL_HSMC_NFC_IDR	0x10
-- 
2.5.0

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[PATCH v3 1/5] mtd: atmel_nand: Support variable RB_EDGE interrupts

[Romain Izard]

The NFC controller used to accelerate the NAND transfers on SAMA5 chips
can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.

Use the controller's compatible string to select the correct bit.

For the binding:
Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Wenyou Yang <Wenyou.yang@atmel.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
v3: constify atmel_nand_nfc_caps structures
v2: use of_device_get_match_data

    rename struct atmel_nand_nfc_priv as atmel_nand_nfc_caps
    rename member rb_edge as rb_mask
    do not create defines for unused status bits

 .../devicetree/bindings/mtd/atmel-nand.txt         |  2 +-
 drivers/mtd/nand/atmel_nand.c                      | 35 +++++++++++++++++-----
 drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
 3 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 7d4c8eb775a5..89b0db9801b0 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -34,7 +34,7 @@ Optional properties:
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
   - Required properties:
-    - compatible : "atmel,sama5d3-nfc".
+    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
     - reg : should specify the address and size used for NFC command registers,
             NFC registers and NFC Sram. NFC Sram address and size can be absent
             if don't want to use it.
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index affe7a7e9ad7..600c77cb70ef 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -67,6 +67,10 @@ struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
 };
 
+struct atmel_nand_nfc_caps {
+	uint32_t rb_mask;
+};
+
 /* oob layout for large page size
  * bad block info is on bytes 0 and 1
  * the bytes have to be consecutives to avoid
@@ -111,6 +115,7 @@ struct atmel_nfc {
 	/* Point to the sram bank which include readed data via NFC */
 	void			*data_in_sram;
 	bool			will_write_sram;
+	const struct atmel_nand_nfc_caps *caps;
 };
 static struct atmel_nfc	nand_nfc;
 
@@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
 		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
 		ret = IRQ_HANDLED;
 	}
-	if (pending & NFC_SR_RB_EDGE) {
+	if (pending & host->nfc->caps->rb_mask) {
 		complete(&host->nfc->comp_ready);
-		nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
+		nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->caps->rb_mask);
 		ret = IRQ_HANDLED;
 	}
 	if (pending & NFC_SR_CMD_DONE) {
@@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		init_completion(&host->nfc->comp_xfer_done);
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->caps->rb_mask)
 		init_completion(&host->nfc->comp_ready);
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
 	if (flag & NFC_SR_XFR_DONE)
 		comp[index++] = &host->nfc->comp_xfer_done;
 
-	if (flag & NFC_SR_RB_EDGE)
+	if (flag & host->nfc->caps->rb_mask)
 		comp[index++] = &host->nfc->comp_ready;
 
 	if (flag & NFC_SR_CMD_DONE)
@@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
 		dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
 				mask & status);
 
-	return status & NFC_SR_RB_EDGE;
+	return status & host->nfc->caps->rb_mask;
 }
 
 static void nfc_select_chip(struct mtd_info *mtd, int chip)
@@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
 		}
 		/* fall through */
 	default:
-		nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
-		nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
+		nfc_prepare_interrupt(host, host->nfc->caps->rb_mask);
+		nfc_wait_interrupt(host, host->nfc->caps->rb_mask);
 	}
 }
 
@@ -2352,6 +2357,11 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
 		}
 	}
 
+	nfc->caps = (const struct atmel_nand_nfc_caps *)
+		of_device_get_match_data(&pdev->dev);
+	if (NULL == nfc->caps)
+		return -ENODEV;
+
 	nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
 	nfc_readl(nfc->hsmc_regs, SR);	/* clear the NFC_SR */
 
@@ -2380,8 +2390,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct atmel_nand_nfc_caps sama5d3_nfc_caps = {
+	.rb_mask = NFC_SR_RB_EDGE0,
+};
+
+static const struct atmel_nand_nfc_caps sama5d4_nfc_caps = {
+	.rb_mask = NFC_SR_RB_EDGE3,
+};
+
 static const struct of_device_id atmel_nand_nfc_match[] = {
-	{ .compatible = "atmel,sama5d3-nfc" },
+	{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_caps },
+	{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_caps },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
index 4d5d26221a7e..0bbc1fa97dba 100644
--- a/drivers/mtd/nand/atmel_nand_nfc.h
+++ b/drivers/mtd/nand/atmel_nand_nfc.h
@@ -42,7 +42,8 @@
 #define		NFC_SR_UNDEF		(1 << 21)
 #define		NFC_SR_AWB		(1 << 22)
 #define		NFC_SR_ASE		(1 << 23)
-#define		NFC_SR_RB_EDGE		(1 << 24)
+#define		NFC_SR_RB_EDGE0		(1 << 24)
+#define		NFC_SR_RB_EDGE3		(1 << 27)
 
 #define ATMEL_HSMC_NFC_IER	0x0c
 #define ATMEL_HSMC_NFC_IDR	0x10
-- 
2.5.0

[PATCH v3 2/5] dt-bindings: atmel_nand: Reword the documenation

[Romain Izard]

Do not mention which chips supporting the PMECC controller, as it a
duplicate of the information in the chips' device trees.

Use common terms when describing the sub-node for the NAND Flash
controller.

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
v3: no change
v2: new

 .../devicetree/bindings/mtd/atmel-nand.txt         | 23 +++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 89b0db9801b0..e68ab404d912 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -21,8 +21,8 @@ Optional properties:
 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
-- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
-  Only supported by at91sam9x5 or later sam9 product.
+- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
+  capable of BCH encoding and decoding, on devices where it is present.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
   Controller. Supported values are: 2, 4, 8, 12, 24.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
@@ -32,15 +32,16 @@ Optional properties:
   sector size 1024. If not specified, driver will build the table in runtime.
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
-- Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
-  - Required properties:
-    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
-    - reg : should specify the address and size used for NFC command registers,
-            NFC registers and NFC Sram. NFC Sram address and size can be absent
-            if don't want to use it.
-    - clocks: phandle to the peripheral clock
-  - Optional properties:
-    - atmel,write-by-sram: boolean to enable NFC write by sram.
+
+Nand Flash Controller(NFC) is an optional sub-node
+Required properties:
+- compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
+- reg : should specify the address and size used for NFC command registers,
+        NFC registers and NFC SRAM. NFC SRAM address and size can be absent
+        if don't want to use it.
+- clocks: phandle to the peripheral clock
+Optional properties:
+- atmel,write-by-sram: boolean to enable NFC write by SRAM.
 
 Examples:
 nand0: nand@40000000,0 {
-- 
2.5.0

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[PATCH v3 2/5] dt-bindings: atmel_nand: Reword the documenation

[Romain Izard]

Do not mention which chips supporting the PMECC controller, as it a
duplicate of the information in the chips' device trees.

Use common terms when describing the sub-node for the NAND Flash
controller.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
v3: no change
v2: new

 .../devicetree/bindings/mtd/atmel-nand.txt         | 23 +++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 89b0db9801b0..e68ab404d912 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -21,8 +21,8 @@ Optional properties:
 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
-- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
-  Only supported by at91sam9x5 or later sam9 product.
+- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
+  capable of BCH encoding and decoding, on devices where it is present.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
   Controller. Supported values are: 2, 4, 8, 12, 24.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
@@ -32,15 +32,16 @@ Optional properties:
   sector size 1024. If not specified, driver will build the table in runtime.
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
-- Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
-  - Required properties:
-    - compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
-    - reg : should specify the address and size used for NFC command registers,
-            NFC registers and NFC Sram. NFC Sram address and size can be absent
-            if don't want to use it.
-    - clocks: phandle to the peripheral clock
-  - Optional properties:
-    - atmel,write-by-sram: boolean to enable NFC write by sram.
+
+Nand Flash Controller(NFC) is an optional sub-node
+Required properties:
+- compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
+- reg : should specify the address and size used for NFC command registers,
+        NFC registers and NFC SRAM. NFC SRAM address and size can be absent
+        if don't want to use it.
+- clocks: phandle to the peripheral clock
+Optional properties:
+- atmel,write-by-sram: boolean to enable NFC write by SRAM.
 
 Examples:
 nand0: nand@40000000,0 {
-- 
2.5.0

[PATCH v3 3/5] mtd: atmel_nand: Support PMECC on SAMA5D2

[Romain Izard]

Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
controller that can correct 32 bits in each sector. This controller is
not 100% compatible with the previous revision that corrected a maximum
of 24 bits by sector, as some register addresses overlap.

Using information from the device tree, we can configure the driver to
work with both versions.

For the binding:
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
v3: rebase on linux-mtd-next
    constify the atmel_nand_caps structure
v2: split rewording of the binding into its own patch

 .../devicetree/bindings/mtd/atmel-nand.txt         |  5 ++++-
 drivers/mtd/nand/atmel_nand.c                      | 23 +++++++++++++++++++++-
 drivers/mtd/nand/atmel_nand_ecc.h                  |  8 ++++++--
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index e68ab404d912..e1887b7d7e53 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,7 +1,10 @@
 Atmel NAND flash
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand".
+- compatible: The possible values are:
+	"atmel,at91rm9200-nand"
+	"atmel,sama5d2-nand"
+	"atmel,sama5d4-nand"
 - reg : should specify localbus address and size used for the chip,
 	and hardware ECC controller if available.
 	If the hardware ECC is PMECC, it should contain address and size for
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 600c77cb70ef..00fa71045805 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -65,6 +65,7 @@ module_param(on_flash_bbt, int, 0);
 
 struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
+	uint8_t pmecc_max_correction;
 };
 
 struct atmel_nand_nfc_caps {
@@ -145,6 +146,7 @@ struct atmel_nand_host {
 	int			pmecc_cw_len;	/* Length of codeword */
 
 	void __iomem		*pmerrloc_base;
+	void __iomem		*pmerrloc_el_base;
 	void __iomem		*pmecc_rom_base;
 
 	/* lookup table for alpha_to and index_of */
@@ -818,7 +820,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 	sector_size = host->pmecc_sector_size;
 
 	while (err_nbr) {
-		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
+		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
 		byte_pos = tmp / 8;
 		bit_pos  = tmp % 8;
 
@@ -1210,6 +1212,8 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		err_no = PTR_ERR(host->pmerrloc_base);
 		goto err;
 	}
+	host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
+		(host->caps->pmecc_max_correction + 1) * 4;
 
 	if (!host->has_no_lookup_table) {
 		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
@@ -2307,17 +2311,34 @@ static int atmel_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+/*
+ * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
+ * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
+ * devices from the SAM9 family that have those.
+ */
 static const struct atmel_nand_caps at91rm9200_caps = {
 	.pmecc_correct_erase_page = false,
+	.pmecc_max_correction = 24,
 };
 
 static const struct atmel_nand_caps sama5d4_caps = {
 	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 24,
+};
+
+/*
+ * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
+ * as the increased correction strength requires more registers.
+ */
+static const struct atmel_nand_caps sama5d2_caps = {
+	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 32,
 };
 
 static const struct of_device_id atmel_nand_dt_ids[] = {
 	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
 	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
+	{ .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index 668e7358f19b..ec964c43c932 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -108,7 +108,11 @@
 #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
 #define		PMERRLOC_CALC_DONE		(1 << 0)
 #define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
-#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
+
+/*
+ * The ATMEL_PMERRLOC_ELx register location depends from the number of
+ * bits corrected by the PMECC controller. Do not use it.
+ */
 
 /* Register access macros for PMECC */
 #define pmecc_readl_relaxed(addr, reg) \
@@ -136,7 +140,7 @@
 	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
 
 #define pmerrloc_readl_el_relaxed(addr, n) \
-	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
+	readl_relaxed((addr) + ((n) * 4))
 
 /* Galois field dimension */
 #define PMECC_GF_DIMENSION_13			13
-- 
2.5.0

--
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[PATCH v3 3/5] mtd: atmel_nand: Support PMECC on SAMA5D2

[Romain Izard]

Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
controller that can correct 32 bits in each sector. This controller is
not 100% compatible with the previous revision that corrected a maximum
of 24 bits by sector, as some register addresses overlap.

Using information from the device tree, we can configure the driver to
work with both versions.

For the binding:
Acked-by: Rob Herring <robh@kernel.org>

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
v3: rebase on linux-mtd-next
    constify the atmel_nand_caps structure
v2: split rewording of the binding into its own patch

 .../devicetree/bindings/mtd/atmel-nand.txt         |  5 ++++-
 drivers/mtd/nand/atmel_nand.c                      | 23 +++++++++++++++++++++-
 drivers/mtd/nand/atmel_nand_ecc.h                  |  8 ++++++--
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index e68ab404d912..e1887b7d7e53 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -1,7 +1,10 @@
 Atmel NAND flash
 
 Required properties:
-- compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand".
+- compatible: The possible values are:
+	"atmel,at91rm9200-nand"
+	"atmel,sama5d2-nand"
+	"atmel,sama5d4-nand"
 - reg : should specify localbus address and size used for the chip,
 	and hardware ECC controller if available.
 	If the hardware ECC is PMECC, it should contain address and size for
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 600c77cb70ef..00fa71045805 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -65,6 +65,7 @@ module_param(on_flash_bbt, int, 0);
 
 struct atmel_nand_caps {
 	bool pmecc_correct_erase_page;
+	uint8_t pmecc_max_correction;
 };
 
 struct atmel_nand_nfc_caps {
@@ -145,6 +146,7 @@ struct atmel_nand_host {
 	int			pmecc_cw_len;	/* Length of codeword */
 
 	void __iomem		*pmerrloc_base;
+	void __iomem		*pmerrloc_el_base;
 	void __iomem		*pmecc_rom_base;
 
 	/* lookup table for alpha_to and index_of */
@@ -818,7 +820,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 	sector_size = host->pmecc_sector_size;
 
 	while (err_nbr) {
-		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
+		tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
 		byte_pos = tmp / 8;
 		bit_pos  = tmp % 8;
 
@@ -1210,6 +1212,8 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
 		err_no = PTR_ERR(host->pmerrloc_base);
 		goto err;
 	}
+	host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
+		(host->caps->pmecc_max_correction + 1) * 4;
 
 	if (!host->has_no_lookup_table) {
 		regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
@@ -2307,17 +2311,34 @@ static int atmel_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+/*
+ * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
+ * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
+ * devices from the SAM9 family that have those.
+ */
 static const struct atmel_nand_caps at91rm9200_caps = {
 	.pmecc_correct_erase_page = false,
+	.pmecc_max_correction = 24,
 };
 
 static const struct atmel_nand_caps sama5d4_caps = {
 	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 24,
+};
+
+/*
+ * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
+ * as the increased correction strength requires more registers.
+ */
+static const struct atmel_nand_caps sama5d2_caps = {
+	.pmecc_correct_erase_page = true,
+	.pmecc_max_correction = 32,
 };
 
 static const struct of_device_id atmel_nand_dt_ids[] = {
 	{ .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
 	{ .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
+	{ .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index 668e7358f19b..ec964c43c932 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -108,7 +108,11 @@
 #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
 #define		PMERRLOC_CALC_DONE		(1 << 0)
 #define ATMEL_PMERRLOC_SIGMAx		0x028	/* Error location SIGMA x */
-#define ATMEL_PMERRLOC_ELx		0x08c	/* Error location x */
+
+/*
+ * The ATMEL_PMERRLOC_ELx register location depends from the number of
+ * bits corrected by the PMECC controller. Do not use it.
+ */
 
 /* Register access macros for PMECC */
 #define pmecc_readl_relaxed(addr, reg) \
@@ -136,7 +140,7 @@
 	readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
 
 #define pmerrloc_readl_el_relaxed(addr, n) \
-	readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
+	readl_relaxed((addr) + ((n) * 4))
 
 /* Galois field dimension */
 #define PMECC_GF_DIMENSION_13			13
-- 
2.5.0

[PATCH v3 4/5] mtd: atmel_nand: Support 32-bit ECC strength

[Romain Izard]

As the SAMA5D2 controller supports the 32-bit ECC strength, accept it
as a valid setting when required by the device tree or the NAND
parameter page.

Then configure the controller to use this new setting.

For the binding:
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
v3: No change
v2: Split message rewording and binding rewording into their own patches

 Documentation/devicetree/bindings/mtd/atmel-nand.txt |  3 ++-
 drivers/mtd/nand/atmel_nand.c                        | 19 +++++++++++++++++--
 drivers/mtd/nand/atmel_nand_ecc.h                    |  1 +
 3 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index e1887b7d7e53..d53aba98fbc9 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -27,7 +27,8 @@ Optional properties:
 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
   capable of BCH encoding and decoding, on devices where it is present.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
-  Controller. Supported values are: 2, 4, 8, 12, 24.
+  Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
+  is "atmel,sama5d2-nand", 32 is also valid.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
   are: 512, 1024.
 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 00fa71045805..aaad1b98dd0d 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -475,6 +475,7 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  *                8-bits                13-bytes                 14-bytes
  *               12-bits                20-bytes                 21-bytes
  *               24-bits                39-bytes                 42-bytes
+ *               32-bits                52-bytes                 56-bytes
  */
 static int pmecc_get_ecc_bytes(int cap, int sector_size)
 {
@@ -1024,6 +1025,9 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
 	case 24:
 		val = PMECC_CFG_BCH_ERR24;
 		break;
+	case 32:
+		val = PMECC_CFG_BCH_ERR32;
+		break;
 	}
 
 	if (host->pmecc_sector_size == 512)
@@ -1085,6 +1089,9 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 
 	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
 	if (host->pmecc_corr_cap == 0) {
+		if (*cap > host->caps->pmecc_max_correction)
+			return -EINVAL;
+
 		/* use the most fitable ecc bits (the near bigger one ) */
 		if (*cap <= 2)
 			host->pmecc_corr_cap = 2;
@@ -1096,6 +1103,8 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 			host->pmecc_corr_cap = 12;
 		else if (*cap <= 24)
 			host->pmecc_corr_cap = 24;
+		else if (*cap <= 32)
+			host->pmecc_corr_cap = 32;
 		else
 			return -EINVAL;
 	}
@@ -1554,8 +1563,14 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * them from NAND ONFI parameters.
 	 */
 	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
-		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
-				(val != 24)) {
+		if (val > host->caps->pmecc_max_correction) {
+			dev_err(host->dev,
+				"Required ECC strength too high: %u max %u\n",
+				val, host->caps->pmecc_max_correction);
+			return -EINVAL;
+		}
+		if ((val != 2)  && (val != 4)  && (val != 8) &&
+		    (val != 12) && (val != 24) && (val != 32)) {
 			dev_err(host->dev,
 				"Required ECC strength not supported: %u\n",
 				val);
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index ec964c43c932..834d694487bd 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -43,6 +43,7 @@
 #define		PMECC_CFG_BCH_ERR8		(2 << 0)
 #define		PMECC_CFG_BCH_ERR12		(3 << 0)
 #define		PMECC_CFG_BCH_ERR24		(4 << 0)
+#define		PMECC_CFG_BCH_ERR32		(5 << 0)
 
 #define		PMECC_CFG_SECTOR512		(0 << 4)
 #define		PMECC_CFG_SECTOR1024		(1 << 4)
-- 
2.5.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH v3 4/5] mtd: atmel_nand: Support 32-bit ECC strength

[Romain Izard]

As the SAMA5D2 controller supports the 32-bit ECC strength, accept it
as a valid setting when required by the device tree or the NAND
parameter page.

Then configure the controller to use this new setting.

For the binding:
Acked-by: Rob Herring <robh@kernel.org>

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
v3: No change
v2: Split message rewording and binding rewording into their own patches

 Documentation/devicetree/bindings/mtd/atmel-nand.txt |  3 ++-
 drivers/mtd/nand/atmel_nand.c                        | 19 +++++++++++++++++--
 drivers/mtd/nand/atmel_nand_ecc.h                    |  1 +
 3 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index e1887b7d7e53..d53aba98fbc9 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -27,7 +27,8 @@ Optional properties:
 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
   capable of BCH encoding and decoding, on devices where it is present.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
-  Controller. Supported values are: 2, 4, 8, 12, 24.
+  Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
+  is "atmel,sama5d2-nand", 32 is also valid.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
   are: 512, 1024.
 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 00fa71045805..aaad1b98dd0d 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -475,6 +475,7 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  *                8-bits                13-bytes                 14-bytes
  *               12-bits                20-bytes                 21-bytes
  *               24-bits                39-bytes                 42-bytes
+ *               32-bits                52-bytes                 56-bytes
  */
 static int pmecc_get_ecc_bytes(int cap, int sector_size)
 {
@@ -1024,6 +1025,9 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
 	case 24:
 		val = PMECC_CFG_BCH_ERR24;
 		break;
+	case 32:
+		val = PMECC_CFG_BCH_ERR32;
+		break;
 	}
 
 	if (host->pmecc_sector_size == 512)
@@ -1085,6 +1089,9 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 
 	/* If device tree doesn't specify, use NAND's minimum ECC parameters */
 	if (host->pmecc_corr_cap == 0) {
+		if (*cap > host->caps->pmecc_max_correction)
+			return -EINVAL;
+
 		/* use the most fitable ecc bits (the near bigger one ) */
 		if (*cap <= 2)
 			host->pmecc_corr_cap = 2;
@@ -1096,6 +1103,8 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 			host->pmecc_corr_cap = 12;
 		else if (*cap <= 24)
 			host->pmecc_corr_cap = 24;
+		else if (*cap <= 32)
+			host->pmecc_corr_cap = 32;
 		else
 			return -EINVAL;
 	}
@@ -1554,8 +1563,14 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
 	 * them from NAND ONFI parameters.
 	 */
 	if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
-		if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
-				(val != 24)) {
+		if (val > host->caps->pmecc_max_correction) {
+			dev_err(host->dev,
+				"Required ECC strength too high: %u max %u\n",
+				val, host->caps->pmecc_max_correction);
+			return -EINVAL;
+		}
+		if ((val != 2)  && (val != 4)  && (val != 8) &&
+		    (val != 12) && (val != 24) && (val != 32)) {
 			dev_err(host->dev,
 				"Required ECC strength not supported: %u\n",
 				val);
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index ec964c43c932..834d694487bd 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -43,6 +43,7 @@
 #define		PMECC_CFG_BCH_ERR8		(2 << 0)
 #define		PMECC_CFG_BCH_ERR12		(3 << 0)
 #define		PMECC_CFG_BCH_ERR24		(4 << 0)
+#define		PMECC_CFG_BCH_ERR32		(5 << 0)
 
 #define		PMECC_CFG_SECTOR512		(0 << 4)
 #define		PMECC_CFG_SECTOR1024		(1 << 4)
-- 
2.5.0

[PATCH v3 5/5] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Romain Izard]

Both nodes are required to access NAND Flash memory. Additional
settings will be necessary at the board level to use it.

Signed-off-by: Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
v3: No change
v2: Fix device address, hexadecimal with minuscules

 arch/arm/boot/dts/sama5d2.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 3f750f6170f2..484bd8ea6602 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -263,6 +263,44 @@
 			cache-level = <2>;
 		};
 
+		nand0: nand@80000000 {
+			compatible = "atmel,sama5d2-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = < /* EBI CS3 */
+				0x80000000 0x08000000
+				/* SMC PMECC regs */
+				0xf8014070 0x00000490
+				/* SMC PMECC Error Location regs */
+				0xf8014500 0x00000200
+				/* ROM Galois tables */
+				0x00040000 0x00018000
+				>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			atmel,nand-has-dma;
+			atmel,has-pmecc;
+			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
+			status = "disabled";
+
+			nfc@c0000000 {
+				compatible = "atmel,sama5d4-nfc";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = < /* NFC Command Registers */
+					0xc0000000 0x08000000
+					/* NFC HSMC regs */
+					0xf8014000 0x00000070
+					/* NFC SRAM banks */
+					0x00100000 0x00100000
+					>;
+				clocks = <&hsmc_clk>;
+				atmel,write-by-sram;
+			};
+		};
+
 		sdmmc0: sdio-host@a0000000 {
 			compatible = "atmel,sama5d2-sdhci";
 			reg = <0xa0000000 0x300>;
-- 
2.5.0

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[PATCH v3 5/5] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes

[Romain Izard]

Both nodes are required to access NAND Flash memory. Additional
settings will be necessary at the board level to use it.

Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
v3: No change
v2: Fix device address, hexadecimal with minuscules

 arch/arm/boot/dts/sama5d2.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 3f750f6170f2..484bd8ea6602 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -263,6 +263,44 @@
 			cache-level = <2>;
 		};
 
+		nand0: nand@80000000 {
+			compatible = "atmel,sama5d2-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = < /* EBI CS3 */
+				0x80000000 0x08000000
+				/* SMC PMECC regs */
+				0xf8014070 0x00000490
+				/* SMC PMECC Error Location regs */
+				0xf8014500 0x00000200
+				/* ROM Galois tables */
+				0x00040000 0x00018000
+				>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			atmel,nand-has-dma;
+			atmel,has-pmecc;
+			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
+			status = "disabled";
+
+			nfc@c0000000 {
+				compatible = "atmel,sama5d4-nfc";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = < /* NFC Command Registers */
+					0xc0000000 0x08000000
+					/* NFC HSMC regs */
+					0xf8014000 0x00000070
+					/* NFC SRAM banks */
+					0x00100000 0x00100000
+					>;
+				clocks = <&hsmc_clk>;
+				atmel,write-by-sram;
+			};
+		};
+
 		sdmmc0: sdio-host@a0000000 {
 			compatible = "atmel,sama5d2-sdhci";
 			reg = <0xa0000000 0x300>;
-- 
2.5.0

Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Yang, Wenyou]

Hi Romain,

On 2016/2/1 18:25, Romain Izard wrote:
> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
>
> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
>
> See previous revisions to apply on the Atmel Linux 4.1 branch.
>
> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
> existing SAMA5D2 board with NAND Flash memory (yet).

Tested it on the SAMA5D2 board, with device: 8-bit ECC 
(MT29F4G08ABAEAWP-IT:E) and 24-bit ECC (MT29F64G08CBAAAWP-Z:A).

For all series,  you can add,

Tested-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

>
> V3 -> V2:
> - Rebase on linux-mtd-next
> - Skip patches already in the tree
>
> V2 -> V1:
> - Rebase on v4.4
> - Use of_device_get_match_data
> - Split message cleanup
> - Reword a small part of the atmel_nand device tree binding
> - Use 'caps' for all private data structures
>
> RFC -> V1:
> - Split the support of 32-bit ECC on SAMA5D2 in two commits
> - Fix the missing ECC strength configuration code
>
> Romain Izard (5):
>    mtd: atmel_nand: Support variable RB_EDGE interrupts
>    dt-bindings: atmel_nand: Reword the documenation
>    mtd: atmel_nand: Support PMECC on SAMA5D2
>    mtd: atmel_nand: Support 32-bit ECC strength
>    ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
>
>   .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
>   arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
>   drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
>   drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>   drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
>   5 files changed, 131 insertions(+), 27 deletions(-)
>
Best Regards,
Wenyou Yang
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Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Yang, Wenyou]

Hi Romain,

On 2016/2/1 18:25, Romain Izard wrote:
> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
>
> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
>
> See previous revisions to apply on the Atmel Linux 4.1 branch.
>
> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
> existing SAMA5D2 board with NAND Flash memory (yet).

Tested it on the SAMA5D2 board, with device: 8-bit ECC 
(MT29F4G08ABAEAWP-IT:E) and 24-bit ECC (MT29F64G08CBAAAWP-Z:A).

For all series,  you can add,

Tested-by: Wenyou Yang <wenyou.yang@atmel.com>

>
> V3 -> V2:
> - Rebase on linux-mtd-next
> - Skip patches already in the tree
>
> V2 -> V1:
> - Rebase on v4.4
> - Use of_device_get_match_data
> - Split message cleanup
> - Reword a small part of the atmel_nand device tree binding
> - Use 'caps' for all private data structures
>
> RFC -> V1:
> - Split the support of 32-bit ECC on SAMA5D2 in two commits
> - Fix the missing ECC strength configuration code
>
> Romain Izard (5):
>    mtd: atmel_nand: Support variable RB_EDGE interrupts
>    dt-bindings: atmel_nand: Reword the documenation
>    mtd: atmel_nand: Support PMECC on SAMA5D2
>    mtd: atmel_nand: Support 32-bit ECC strength
>    ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
>
>   .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
>   arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
>   drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
>   drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>   drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
>   5 files changed, 131 insertions(+), 27 deletions(-)
>
Best Regards,
Wenyou Yang

Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Boris Brezillon]

Hi Romain,

Just a remark that is not directly related to your work: when people
take the time to review your work, try to keep them in Cc of the
following versions of your patchset.

On Mon,  1 Feb 2016 11:25:55 +0100
Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
> 
> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
> 
> See previous revisions to apply on the Atmel Linux 4.1 branch.
> 
> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
> existing SAMA5D2 board with NAND Flash memory (yet).

Overall, it looks good to me (even if I don't fully agree on how you
decided to define NFC_SR_RB_EDGEX values :-P, but that's just a
nitpick).

Reviewed-by: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

> 
> V3 -> V2:
> - Rebase on linux-mtd-next
> - Skip patches already in the tree
> 
> V2 -> V1:
> - Rebase on v4.4
> - Use of_device_get_match_data
> - Split message cleanup
> - Reword a small part of the atmel_nand device tree binding
> - Use 'caps' for all private data structures
> 
> RFC -> V1:
> - Split the support of 32-bit ECC on SAMA5D2 in two commits
> - Fix the missing ECC strength configuration code
> 
> Romain Izard (5):
>   mtd: atmel_nand: Support variable RB_EDGE interrupts
>   dt-bindings: atmel_nand: Reword the documenation
>   mtd: atmel_nand: Support PMECC on SAMA5D2
>   mtd: atmel_nand: Support 32-bit ECC strength
>   ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
>  arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
>  drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
>  5 files changed, 131 insertions(+), 27 deletions(-)
> 



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Boris Brezillon]

Hi Romain,

Just a remark that is not directly related to your work: when people
take the time to review your work, try to keep them in Cc of the
following versions of your patchset.

On Mon,  1 Feb 2016 11:25:55 +0100
Romain Izard <romain.izard.pro@gmail.com> wrote:

> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
> 
> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
> 
> See previous revisions to apply on the Atmel Linux 4.1 branch.
> 
> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
> existing SAMA5D2 board with NAND Flash memory (yet).

Overall, it looks good to me (even if I don't fully agree on how you
decided to define NFC_SR_RB_EDGEX values :-P, but that's just a
nitpick).

Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>

> 
> V3 -> V2:
> - Rebase on linux-mtd-next
> - Skip patches already in the tree
> 
> V2 -> V1:
> - Rebase on v4.4
> - Use of_device_get_match_data
> - Split message cleanup
> - Reword a small part of the atmel_nand device tree binding
> - Use 'caps' for all private data structures
> 
> RFC -> V1:
> - Split the support of 32-bit ECC on SAMA5D2 in two commits
> - Fix the missing ECC strength configuration code
> 
> Romain Izard (5):
>   mtd: atmel_nand: Support variable RB_EDGE interrupts
>   dt-bindings: atmel_nand: Reword the documenation
>   mtd: atmel_nand: Support PMECC on SAMA5D2
>   mtd: atmel_nand: Support 32-bit ECC strength
>   ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
>  arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
>  drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
>  5 files changed, 131 insertions(+), 27 deletions(-)
> 



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

Hi Boris,

2016-02-04 14:33 GMT+01:00 Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>:
> Hi Romain,
>
> Just a remark that is not directly related to your work: when people
> take the time to review your work, try to keep them in Cc of the
> following versions of your patchset.
>
OK. I'll keep it in mind for my next submission.

> On Mon,  1 Feb 2016 11:25:55 +0100
> Romain Izard <romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
>> The NAND Flash controller for SAMA5D2 has small differences that make it
>> impossible to use the existing driver for SAMA5D3. This patchset uses the
>> device tree's compatible string to get those differences, and the code is
>> slightly modified to handle them.
>>
>> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
>>
>> See previous revisions to apply on the Atmel Linux 4.1 branch.
>>
>> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
>> existing SAMA5D2 board with NAND Flash memory (yet).
>
> Overall, it looks good to me (even if I don't fully agree on how you
> decided to define NFC_SR_RB_EDGEX values :-P, but that's just a
> nitpick).
>
> Reviewed-by: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>

Thanks for your review.

Best regards,
-- 
Romain Izard
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Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

Hi Boris,

2016-02-04 14:33 GMT+01:00 Boris Brezillon <boris.brezillon@free-electrons.com>:
> Hi Romain,
>
> Just a remark that is not directly related to your work: when people
> take the time to review your work, try to keep them in Cc of the
> following versions of your patchset.
>
OK. I'll keep it in mind for my next submission.

> On Mon,  1 Feb 2016 11:25:55 +0100
> Romain Izard <romain.izard.pro@gmail.com> wrote:
>
>> The NAND Flash controller for SAMA5D2 has small differences that make it
>> impossible to use the existing driver for SAMA5D3. This patchset uses the
>> device tree's compatible string to get those differences, and the code is
>> slightly modified to handle them.
>>
>> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
>>
>> See previous revisions to apply on the Atmel Linux 4.1 branch.
>>
>> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
>> existing SAMA5D2 board with NAND Flash memory (yet).
>
> Overall, it looks good to me (even if I don't fully agree on how you
> decided to define NFC_SR_RB_EDGEX values :-P, but that's just a
> nitpick).
>
> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
>

Thanks for your review.

Best regards,
-- 
Romain Izard

Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 01/02/2016 11:25, Romain Izard a écrit :
> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
> 
> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
> 
> See previous revisions to apply on the Atmel Linux 4.1 branch.
> 
> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
> existing SAMA5D2 board with NAND Flash memory (yet).

Brian,

Hi, do we need to resend this series with all the tags collected (aka
ping ;-)) ?

Bye,


> V3 -> V2:
> - Rebase on linux-mtd-next
> - Skip patches already in the tree
> 
> V2 -> V1:
> - Rebase on v4.4
> - Use of_device_get_match_data
> - Split message cleanup
> - Reword a small part of the atmel_nand device tree binding
> - Use 'caps' for all private data structures
> 
> RFC -> V1:
> - Split the support of 32-bit ECC on SAMA5D2 in two commits
> - Fix the missing ECC strength configuration code
> 
> Romain Izard (5):
>   mtd: atmel_nand: Support variable RB_EDGE interrupts
>   dt-bindings: atmel_nand: Reword the documenation
>   mtd: atmel_nand: Support PMECC on SAMA5D2
>   mtd: atmel_nand: Support 32-bit ECC strength
>   ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
>  arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
>  drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
>  5 files changed, 131 insertions(+), 27 deletions(-)
> 


-- 
Nicolas Ferre
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Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 01/02/2016 11:25, Romain Izard a écrit :
> The NAND Flash controller for SAMA5D2 has small differences that make it
> impossible to use the existing driver for SAMA5D3. This patchset uses the
> device tree's compatible string to get those differences, and the code is
> slightly modified to handle them.
> 
> Base on linux-mtd-next, commit 15c0be7bec002f9a529dd0966d0db96dde176fd0
> 
> See previous revisions to apply on the Atmel Linux 4.1 branch.
> 
> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there is no
> existing SAMA5D2 board with NAND Flash memory (yet).

Brian,

Hi, do we need to resend this series with all the tags collected (aka
ping ;-)) ?

Bye,


> V3 -> V2:
> - Rebase on linux-mtd-next
> - Skip patches already in the tree
> 
> V2 -> V1:
> - Rebase on v4.4
> - Use of_device_get_match_data
> - Split message cleanup
> - Reword a small part of the atmel_nand device tree binding
> - Use 'caps' for all private data structures
> 
> RFC -> V1:
> - Split the support of 32-bit ECC on SAMA5D2 in two commits
> - Fix the missing ECC strength configuration code
> 
> Romain Izard (5):
>   mtd: atmel_nand: Support variable RB_EDGE interrupts
>   dt-bindings: atmel_nand: Reword the documenation
>   mtd: atmel_nand: Support PMECC on SAMA5D2
>   mtd: atmel_nand: Support 32-bit ECC strength
>   ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes
> 
>  .../devicetree/bindings/mtd/atmel-nand.txt         | 31 +++++----
>  arch/arm/boot/dts/sama5d2.dtsi                     | 38 +++++++++++
>  drivers/mtd/nand/atmel_nand.c                      | 77 ++++++++++++++++++----
>  drivers/mtd/nand/atmel_nand_ecc.h                  |  9 ++-
>  drivers/mtd/nand/atmel_nand_nfc.h                  |  3 +-
>  5 files changed, 131 insertions(+), 27 deletions(-)
> 


-- 
Nicolas Ferre

Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

Hi Nicolas,

2016-03-01 11:27 GMT+01:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
> Le 01/02/2016 11:25, Romain Izard a écrit :
>> The NAND Flash controller for SAMA5D2 has small differences that make
>> it impossible to use the existing driver for SAMA5D3. This patchset
>> uses the device tree's compatible string to get those differences,
>> and the code is slightly modified to handle them.
>>
>> Base on linux-mtd-next, commit
>> 15c0be7bec002f9a529dd0966d0db96dde176fd0
>>
>> See previous revisions to apply on the Atmel Linux 4.1 branch.
>>
>> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there
>> is no existing SAMA5D2 board with NAND Flash memory (yet).
>
> Brian,
>
> Hi, do we need to resend this series with all the tags collected (aka
> ping ;-)) ?
>

A v4 has already been sent, and Brian has picked patches 1-4, as seen
in: http://article.gmane.org/gmane.linux.drivers.devicetree/155864/

For patch #5, it is the update for the sama5d2.dtsi to describe the
NAND controller. Perhaps you can take it on your tree for 4.6, it
won't change anything until a board needs it, either Atmel's SAMA5D2 PTC
or another one.

Best regards,
-- 
Romain Izard
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Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Romain Izard]

Hi Nicolas,

2016-03-01 11:27 GMT+01:00 Nicolas Ferre <nicolas.ferre@atmel.com>:
> Le 01/02/2016 11:25, Romain Izard a écrit :
>> The NAND Flash controller for SAMA5D2 has small differences that make
>> it impossible to use the existing driver for SAMA5D3. This patchset
>> uses the device tree's compatible string to get those differences,
>> and the code is slightly modified to handle them.
>>
>> Base on linux-mtd-next, commit
>> 15c0be7bec002f9a529dd0966d0db96dde176fd0
>>
>> See previous revisions to apply on the Atmel Linux 4.1 branch.
>>
>> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there
>> is no existing SAMA5D2 board with NAND Flash memory (yet).
>
> Brian,
>
> Hi, do we need to resend this series with all the tags collected (aka
> ping ;-)) ?
>

A v4 has already been sent, and Brian has picked patches 1-4, as seen
in: http://article.gmane.org/gmane.linux.drivers.devicetree/155864/

For patch #5, it is the update for the sama5d2.dtsi to describe the
NAND controller. Perhaps you can take it on your tree for 4.6, it
won't change anything until a board needs it, either Atmel's SAMA5D2 PTC
or another one.

Best regards,
-- 
Romain Izard

Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 01/03/2016 12:29, Romain Izard a écrit :
> Hi Nicolas,
> 
> 2016-03-01 11:27 GMT+01:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
>> Le 01/02/2016 11:25, Romain Izard a écrit :
>>> The NAND Flash controller for SAMA5D2 has small differences that make
>>> it impossible to use the existing driver for SAMA5D3. This patchset
>>> uses the device tree's compatible string to get those differences,
>>> and the code is slightly modified to handle them.
>>>
>>> Base on linux-mtd-next, commit
>>> 15c0be7bec002f9a529dd0966d0db96dde176fd0
>>>
>>> See previous revisions to apply on the Atmel Linux 4.1 branch.
>>>
>>> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there
>>> is no existing SAMA5D2 board with NAND Flash memory (yet).
>>
>> Brian,
>>
>> Hi, do we need to resend this series with all the tags collected (aka
>> ping ;-)) ?
>>
> 
> A v4 has already been sent, and Brian has picked patches 1-4, as seen
> in: http://article.gmane.org/gmane.linux.drivers.devicetree/155864/

Ok, I forget it and it was in another mailbox on my side: sorry for the
noise...

> For patch #5, it is the update for the sama5d2.dtsi to describe the
> NAND controller. Perhaps you can take it on your tree for 4.6, it
> won't change anything until a board needs it, either Atmel's SAMA5D2 PTC
> or another one.

Absolutely. As I am collecting this material, it makes perfect sense to
add it to our at91-4.6-dt branch.

Thanks for the help Romain!

Bye,
-- 
Nicolas Ferre
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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Re: [PATCH v3 0/5] mtd: atmel_nand: Add support for NAND Flash on SAMA5D2

[Nicolas Ferre]

Le 01/03/2016 12:29, Romain Izard a écrit :
> Hi Nicolas,
> 
> 2016-03-01 11:27 GMT+01:00 Nicolas Ferre <nicolas.ferre@atmel.com>:
>> Le 01/02/2016 11:25, Romain Izard a écrit :
>>> The NAND Flash controller for SAMA5D2 has small differences that make
>>> it impossible to use the existing driver for SAMA5D3. This patchset
>>> uses the device tree's compatible string to get those differences,
>>> and the code is slightly modified to handle them.
>>>
>>> Base on linux-mtd-next, commit
>>> 15c0be7bec002f9a529dd0966d0db96dde176fd0
>>>
>>> See previous revisions to apply on the Atmel Linux 4.1 branch.
>>>
>>> Compile tested for sama5_defconfig, and tested on SAMA5D3xek as there
>>> is no existing SAMA5D2 board with NAND Flash memory (yet).
>>
>> Brian,
>>
>> Hi, do we need to resend this series with all the tags collected (aka
>> ping ;-)) ?
>>
> 
> A v4 has already been sent, and Brian has picked patches 1-4, as seen
> in: http://article.gmane.org/gmane.linux.drivers.devicetree/155864/

Ok, I forget it and it was in another mailbox on my side: sorry for the
noise...

> For patch #5, it is the update for the sama5d2.dtsi to describe the
> NAND controller. Perhaps you can take it on your tree for 4.6, it
> won't change anything until a board needs it, either Atmel's SAMA5D2 PTC
> or another one.

Absolutely. As I am collecting this material, it makes perfect sense to
add it to our at91-4.6-dt branch.

Thanks for the help Romain!

Bye,
-- 
Nicolas Ferre