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From: Paul Burton <paul.burton@imgtec.com>
To: <linux-mips@linux-mips.org>
Cc: "Bharat Kumar Gogada" <bharatku@xilinx.com>,
	"Michal Simek" <michal.simek@xilinx.com>,
	"Ravikiran Gummaluri" <rgummal@xilinx.com>,
	"Paul Burton" <paul.burton@imgtec.com>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	"Jiang Liu" <jiang.liu@linux.intel.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Grygorii Strashko" <grygorii.strashko@ti.com>,
	"Russell Joyce" <russell.joyce@york.ac.uk>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/6] PCI: xilinx: Fix INTX irq dispatch
Date: Thu, 4 Feb 2016 16:10:12 +0000	[thread overview]
Message-ID: <1454602213-967-6-git-send-email-paul.burton@imgtec.com> (raw)
In-Reply-To: <1454602213-967-1-git-send-email-paul.burton@imgtec.com>

The IRQ domain for INTX interrupts has 4 entries, numbered 0 to 3. This
matches what the hardware reports from the interrupt FIFO exactly, but
xilinx_pcie_intr_handler was adding 1 to that value to convert to the
range 1 to 4. Stop adding 1, such that all of INTA through to INTD fall
within the range of the IRQ domain.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver")

---

Changes in v3:
- Split out from Boston patchset.

Changes in v2:
- Add Fixes tag.

 drivers/pci/host/pcie-xilinx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 6c5a503..8013e83 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -451,8 +451,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 			irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
 				XILINX_PCIE_RPIFR2_MSG_DATA;
 		} else {
-			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
-				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+			val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+				XILINX_PCIE_RPIFR1_INTR_SHIFT;
 			irq = irq_find_mapping(port->irq_domain, val);
 		}
 
-- 
2.7.0

WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com>
To: linux-mips@linux-mips.org
Cc: "Bharat Kumar Gogada" <bharatku@xilinx.com>,
	"Michal Simek" <michal.simek@xilinx.com>,
	"Ravikiran Gummaluri" <rgummal@xilinx.com>,
	"Paul Burton" <paul.burton@imgtec.com>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	"Jiang Liu" <jiang.liu@linux.intel.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Grygorii Strashko" <grygorii.strashko@ti.com>,
	"Russell Joyce" <russell.joyce@york.ac.uk>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/6] PCI: xilinx: Fix INTX irq dispatch
Date: Thu, 4 Feb 2016 16:10:12 +0000	[thread overview]
Message-ID: <1454602213-967-6-git-send-email-paul.burton@imgtec.com> (raw)
Message-ID: <20160204161012.W7D8evC3HW4HKQFQp14CIjOCIFUJ_pAjKRY1RhP_FDI@z> (raw)
In-Reply-To: <1454602213-967-1-git-send-email-paul.burton@imgtec.com>

The IRQ domain for INTX interrupts has 4 entries, numbered 0 to 3. This
matches what the hardware reports from the interrupt FIFO exactly, but
xilinx_pcie_intr_handler was adding 1 to that value to convert to the
range 1 to 4. Stop adding 1, such that all of INTA through to INTD fall
within the range of the IRQ domain.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver")

---

Changes in v3:
- Split out from Boston patchset.

Changes in v2:
- Add Fixes tag.

 drivers/pci/host/pcie-xilinx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 6c5a503..8013e83 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -451,8 +451,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 			irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
 				XILINX_PCIE_RPIFR2_MSG_DATA;
 		} else {
-			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
-				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+			val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+				XILINX_PCIE_RPIFR1_INTR_SHIFT;
 			irq = irq_find_mapping(port->irq_domain, val);
 		}
 
-- 
2.7.0

WARNING: multiple messages have this Message-ID (diff)
From: paul.burton@imgtec.com (Paul Burton)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/6] PCI: xilinx: Fix INTX irq dispatch
Date: Thu, 4 Feb 2016 16:10:12 +0000	[thread overview]
Message-ID: <1454602213-967-6-git-send-email-paul.burton@imgtec.com> (raw)
In-Reply-To: <1454602213-967-1-git-send-email-paul.burton@imgtec.com>

The IRQ domain for INTX interrupts has 4 entries, numbered 0 to 3. This
matches what the hardware reports from the interrupt FIFO exactly, but
xilinx_pcie_intr_handler was adding 1 to that value to convert to the
range 1 to 4. Stop adding 1, such that all of INTA through to INTD fall
within the range of the IRQ domain.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver")

---

Changes in v3:
- Split out from Boston patchset.

Changes in v2:
- Add Fixes tag.

 drivers/pci/host/pcie-xilinx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 6c5a503..8013e83 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -451,8 +451,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
 			irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
 				XILINX_PCIE_RPIFR2_MSG_DATA;
 		} else {
-			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
-				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+			val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+				XILINX_PCIE_RPIFR1_INTR_SHIFT;
 			irq = irq_find_mapping(port->irq_domain, val);
 		}
 
-- 
2.7.0

  parent reply	other threads:[~2016-02-04 16:12 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-04 16:10 [PATCH v3 0/6] Xilinx AXI PCIe Host Bridge driver fixes Paul Burton
2016-02-04 16:10 ` Paul Burton
2016-02-04 16:10 ` Paul Burton
2016-02-04 16:10 ` [PATCH v3 1/6] PCI: xilinx: Keep references to both IRQ domains Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10 ` [PATCH v3 2/6] PCI: xilinx: Unify INTx & MSI interrupt FIFO decode Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-11  5:42   ` Bharat Kumar Gogada
2016-02-11  5:42     ` Bharat Kumar Gogada
2016-02-11  5:42     ` Bharat Kumar Gogada
2016-02-11  5:50     ` Bharat Kumar Gogada
2016-02-11  5:50       ` Bharat Kumar Gogada
2016-02-11  5:50       ` Bharat Kumar Gogada
2016-02-04 16:10 ` [PATCH v3 3/6] PCI: xilinx: Always clear interrupt decode register Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10 ` [PATCH v3 4/6] PCI: xilinx: Clear interrupt FIFO during probe Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-11  6:20   ` Bharat Kumar Gogada
2016-02-11  6:20     ` Bharat Kumar Gogada
2016-02-11  6:20     ` Bharat Kumar Gogada
2016-02-04 16:10 ` Paul Burton [this message]
2016-02-04 16:10   ` [PATCH v3 5/6] PCI: xilinx: Fix INTX irq dispatch Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 16:10 ` [PATCH v3 6/6] PCI: xilinx: Allow build on MIPS platforms Paul Burton
2016-02-04 16:10   ` Paul Burton
2016-02-04 17:46   ` Rob Herring
2016-02-04 17:53     ` Paul Burton
2016-02-25 15:43       ` Bjorn Helgaas
2016-02-26  7:49         ` Michal Simek
2016-02-25 15:59 ` [PATCH v3 0/6] Xilinx AXI PCIe Host Bridge driver fixes Bjorn Helgaas
2016-02-25 15:59   ` Bjorn Helgaas

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