* [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows
@ 2016-02-10 3:41 Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 1/4] tcg: Implement indirect memory registers Richard Henderson
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Richard Henderson @ 2016-02-10 3:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
The bulk of the original patch set has been reviewed and
comitted. But the actual end result is still outstanding.
r~
Richard Henderson (4):
tcg: Implement indirect memory registers
tcg: Allocate indirect_base temporaries in a different order
target-sparc: Tidy global register initialization
target-sparc: Use global registers for the register window
target-sparc/translate.c | 196 ++++++++++++++++++++++-------------------------
tcg/tcg.c | 136 ++++++++++++++++++++++----------
tcg/tcg.h | 2 +
3 files changed, 191 insertions(+), 143 deletions(-)
--
2.5.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v3 1/4] tcg: Implement indirect memory registers
2016-02-10 3:41 [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Richard Henderson
@ 2016-02-10 3:41 ` Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 2/4] tcg: Allocate indirect_base temporaries in a different order Richard Henderson
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2016-02-10 3:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
That is, global_mem registers whose base is another global_mem
register, rather than a fixed register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 95 ++++++++++++++++++++++++++++++++++++++++++++-------------------
tcg/tcg.h | 2 ++
2 files changed, 68 insertions(+), 29 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0317c9e..9f6d363 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -506,17 +506,23 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
TCGContext *s = &tcg_ctx;
TCGTemp *base_ts = &s->temps[GET_TCGV_PTR(base)];
TCGTemp *ts = tcg_global_alloc(s);
- int bigendian = 0;
+ int indirect_reg = 0, bigendian = 0;
#ifdef HOST_WORDS_BIGENDIAN
bigendian = 1;
#endif
+ if (!base_ts->fixed_reg) {
+ indirect_reg = 1;
+ base_ts->indirect_base = 1;
+ }
+
if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
TCGTemp *ts2 = tcg_global_alloc(s);
char buf[64];
ts->base_type = TCG_TYPE_I64;
ts->type = TCG_TYPE_I32;
+ ts->indirect_reg = indirect_reg;
ts->mem_allocated = 1;
ts->mem_base = base_ts;
ts->mem_offset = offset + bigendian * 4;
@@ -527,6 +533,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
tcg_debug_assert(ts2 == ts + 1);
ts2->base_type = TCG_TYPE_I64;
ts2->type = TCG_TYPE_I32;
+ ts2->indirect_reg = indirect_reg;
ts2->mem_allocated = 1;
ts2->mem_base = base_ts;
ts2->mem_offset = offset + (1 - bigendian) * 4;
@@ -536,6 +543,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
} else {
ts->base_type = type;
ts->type = type;
+ ts->indirect_reg = indirect_reg;
ts->mem_allocated = 1;
ts->mem_base = base_ts;
ts->mem_offset = offset;
@@ -1652,8 +1660,10 @@ static void temp_allocate_frame(TCGContext *s, int temp)
s->current_frame_offset += sizeof(tcg_target_long);
}
+static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet);
+
/* sync register 'reg' by saving it to the corresponding temporary */
-static inline void tcg_reg_sync(TCGContext *s, TCGReg reg)
+static void tcg_reg_sync(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs)
{
TCGTemp *ts = s->reg_to_temp[reg];
@@ -1661,6 +1671,11 @@ static inline void tcg_reg_sync(TCGContext *s, TCGReg reg)
if (!ts->mem_coherent && !ts->fixed_reg) {
if (!ts->mem_allocated) {
temp_allocate_frame(s, temp_idx(s, ts));
+ } else if (ts->indirect_reg) {
+ tcg_regset_set_reg(allocated_regs, ts->reg);
+ temp_load(s, ts->mem_base,
+ tcg_target_available_regs[TCG_TYPE_PTR],
+ allocated_regs);
}
tcg_out_st(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset);
}
@@ -1668,25 +1683,26 @@ static inline void tcg_reg_sync(TCGContext *s, TCGReg reg)
}
/* free register 'reg' by spilling the corresponding temporary if necessary */
-static void tcg_reg_free(TCGContext *s, TCGReg reg)
+static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs)
{
TCGTemp *ts = s->reg_to_temp[reg];
if (ts != NULL) {
- tcg_reg_sync(s, reg);
+ tcg_reg_sync(s, reg, allocated_regs);
ts->val_type = TEMP_VAL_MEM;
s->reg_to_temp[reg] = NULL;
}
}
/* Allocate a register belonging to reg1 & ~reg2 */
-static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
+static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs,
+ TCGRegSet allocated_regs)
{
int i;
TCGReg reg;
TCGRegSet reg_ct;
- tcg_regset_andnot(reg_ct, reg1, reg2);
+ tcg_regset_andnot(reg_ct, desired_regs, allocated_regs);
/* first try free registers */
for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
@@ -1699,7 +1715,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
reg = tcg_target_reg_alloc_order[i];
if (tcg_regset_test_reg(reg_ct, reg)) {
- tcg_reg_free(s, reg);
+ tcg_reg_free(s, reg, allocated_regs);
return reg;
}
}
@@ -1724,6 +1740,12 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
break;
case TEMP_VAL_MEM:
reg = tcg_reg_alloc(s, desired_regs, allocated_regs);
+ if (ts->indirect_reg) {
+ tcg_regset_set_reg(allocated_regs, reg);
+ temp_load(s, ts->mem_base,
+ tcg_target_available_regs[TCG_TYPE_PTR],
+ allocated_regs);
+ }
tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset);
ts->mem_coherent = 1;
break;
@@ -1761,7 +1783,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs)
temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs);
/* fallthrough */
case TEMP_VAL_REG:
- tcg_reg_sync(s, ts->reg);
+ tcg_reg_sync(s, ts->reg, allocated_regs);
break;
case TEMP_VAL_DEAD:
case TEMP_VAL_MEM:
@@ -1777,13 +1799,16 @@ static inline void temp_save(TCGContext *s, TCGTemp *ts,
TCGRegSet allocated_regs)
{
#ifdef USE_LIVENESS_ANALYSIS
- /* The liveness analysis already ensures that globals are back
- in memory. Keep an assert for safety. */
- tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg);
-#else
+ /* ??? Liveness does not yet incorporate indirect bases. */
+ if (!ts->indirect_base) {
+ /* The liveness analysis already ensures that globals are back
+ in memory. Keep an assert for safety. */
+ tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg);
+ return;
+ }
+#endif
temp_sync(s, ts, allocated_regs);
temp_dead(s, ts);
-#endif
}
/* save globals to their canonical location and assume they can be
@@ -1808,12 +1833,15 @@ static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
for (i = 0; i < s->nb_globals; i++) {
TCGTemp *ts = &s->temps[i];
#ifdef USE_LIVENESS_ANALYSIS
- tcg_debug_assert(ts->val_type != TEMP_VAL_REG
- || ts->fixed_reg
- || ts->mem_coherent);
-#else
- temp_sync(s, ts, allocated_regs);
+ /* ??? Liveness does not yet incorporate indirect bases. */
+ if (!ts->indirect_base) {
+ tcg_debug_assert(ts->val_type != TEMP_VAL_REG
+ || ts->fixed_reg
+ || ts->mem_coherent);
+ continue;
+ }
#endif
+ temp_sync(s, ts, allocated_regs);
}
}
@@ -1829,12 +1857,15 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
temp_save(s, ts, allocated_regs);
} else {
#ifdef USE_LIVENESS_ANALYSIS
- /* The liveness analysis already ensures that temps are dead.
- Keep an assert for safety. */
- assert(ts->val_type == TEMP_VAL_DEAD);
-#else
- temp_dead(s, ts);
+ /* ??? Liveness does not yet incorporate indirect bases. */
+ if (!ts->indirect_base) {
+ /* The liveness analysis already ensures that temps are dead.
+ Keep an assert for safety. */
+ assert(ts->val_type == TEMP_VAL_DEAD);
+ continue;
+ }
#endif
+ temp_dead(s, ts);
}
}
@@ -1907,6 +1938,12 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
if (!ots->mem_allocated) {
temp_allocate_frame(s, args[0]);
}
+ if (ots->indirect_reg) {
+ tcg_regset_set_reg(allocated_regs, ts->reg);
+ temp_load(s, ots->mem_base,
+ tcg_target_available_regs[TCG_TYPE_PTR],
+ allocated_regs);
+ }
tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset);
if (IS_DEAD_ARG(1)) {
temp_dead(s, ts);
@@ -1947,7 +1984,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
ots->mem_coherent = 0;
s->reg_to_temp[ots->reg] = ots;
if (NEED_SYNC_ARG(0)) {
- tcg_reg_sync(s, ots->reg);
+ tcg_reg_sync(s, ots->reg, allocated_regs);
}
}
}
@@ -2047,7 +2084,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* XXX: permit generic clobber register list ? */
for (i = 0; i < TCG_TARGET_NB_REGS; i++) {
if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) {
- tcg_reg_free(s, i);
+ tcg_reg_free(s, i, allocated_regs);
}
}
}
@@ -2104,7 +2141,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
tcg_out_mov(s, ts->type, ts->reg, reg);
}
if (NEED_SYNC_ARG(i)) {
- tcg_reg_sync(s, reg);
+ tcg_reg_sync(s, reg, allocated_regs);
}
if (IS_DEAD_ARG(i)) {
temp_dead(s, ts);
@@ -2175,7 +2212,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
if (arg != TCG_CALL_DUMMY_ARG) {
ts = &s->temps[arg];
reg = tcg_target_call_iarg_regs[i];
- tcg_reg_free(s, reg);
+ tcg_reg_free(s, reg, allocated_regs);
if (ts->val_type == TEMP_VAL_REG) {
if (ts->reg != reg) {
@@ -2203,7 +2240,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
/* clobber call registers */
for (i = 0; i < TCG_TARGET_NB_REGS; i++) {
if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) {
- tcg_reg_free(s, i);
+ tcg_reg_free(s, i, allocated_regs);
}
}
@@ -2239,7 +2276,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
ts->mem_coherent = 0;
s->reg_to_temp[reg] = ts;
if (NEED_SYNC_ARG(i)) {
- tcg_reg_sync(s, reg);
+ tcg_reg_sync(s, reg, allocated_regs);
}
if (IS_DEAD_ARG(i)) {
temp_dead(s, ts);
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 83da5fb..d181694 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -453,6 +453,8 @@ typedef struct TCGTemp {
TCGType base_type:8;
TCGType type:8;
unsigned int fixed_reg:1;
+ unsigned int indirect_reg:1;
+ unsigned int indirect_base:1;
unsigned int mem_coherent:1;
unsigned int mem_allocated:1;
unsigned int temp_local:1; /* If true, the temp is saved across
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v3 2/4] tcg: Allocate indirect_base temporaries in a different order
2016-02-10 3:41 [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 1/4] tcg: Implement indirect memory registers Richard Henderson
@ 2016-02-10 3:41 ` Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 3/4] target-sparc: Tidy global register initialization Richard Henderson
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2016-02-10 3:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Since we've not got liveness analysis for indirect bases,
placing them at the end of the call-saved registers makes
it more likely that it'll stay live.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 43 ++++++++++++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 9f6d363..b2e31a2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -318,6 +318,8 @@ static const TCGHelperInfo all_helpers[] = {
#include "exec/helper-tcg.h"
};
+static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)];
+
void tcg_context_init(TCGContext *s)
{
int op, total_args, n, i;
@@ -360,6 +362,21 @@ void tcg_context_init(TCGContext *s)
}
tcg_target_init(s);
+
+ /* Reverse the order of the saved registers, assuming they're all at
+ the start of tcg_target_reg_alloc_order. */
+ for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) {
+ int r = tcg_target_reg_alloc_order[n];
+ if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) {
+ break;
+ }
+ }
+ for (i = 0; i < n; ++i) {
+ indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i];
+ }
+ for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) {
+ indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i];
+ }
}
void tcg_prologue_init(TCGContext *s)
@@ -1696,24 +1713,26 @@ static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs)
/* Allocate a register belonging to reg1 & ~reg2 */
static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs,
- TCGRegSet allocated_regs)
+ TCGRegSet allocated_regs, bool rev)
{
- int i;
+ int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order);
+ const int *order;
TCGReg reg;
TCGRegSet reg_ct;
tcg_regset_andnot(reg_ct, desired_regs, allocated_regs);
+ order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;
/* first try free registers */
- for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
- reg = tcg_target_reg_alloc_order[i];
+ for(i = 0; i < n; i++) {
+ reg = order[i];
if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL)
return reg;
}
/* XXX: do better spill choice */
- for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
- reg = tcg_target_reg_alloc_order[i];
+ for(i = 0; i < n; i++) {
+ reg = order[i];
if (tcg_regset_test_reg(reg_ct, reg)) {
tcg_reg_free(s, reg, allocated_regs);
return reg;
@@ -1734,12 +1753,12 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
case TEMP_VAL_REG:
return;
case TEMP_VAL_CONST:
- reg = tcg_reg_alloc(s, desired_regs, allocated_regs);
+ reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base);
tcg_out_movi(s, ts->type, reg, ts->val);
ts->mem_coherent = 0;
break;
case TEMP_VAL_MEM:
- reg = tcg_reg_alloc(s, desired_regs, allocated_regs);
+ reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base);
if (ts->indirect_reg) {
tcg_regset_set_reg(allocated_regs, reg);
temp_load(s, ts->mem_base,
@@ -1976,7 +1995,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
input one. */
tcg_regset_set_reg(allocated_regs, ts->reg);
ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
- allocated_regs);
+ allocated_regs, ots->indirect_base);
}
tcg_out_mov(s, otype, ots->reg, ts->reg);
}
@@ -2061,7 +2080,8 @@ static void tcg_reg_alloc_op(TCGContext *s,
allocate_in_reg:
/* allocate a new register matching the constraint
and move the temporary register into it */
- reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
+ reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs,
+ ts->indirect_base);
tcg_out_mov(s, ts->type, reg, ts->reg);
}
new_args[i] = reg;
@@ -2110,7 +2130,8 @@ static void tcg_reg_alloc_op(TCGContext *s,
tcg_regset_test_reg(arg_ct->u.regs, reg)) {
goto oarg_end;
}
- reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
+ reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs,
+ ts->indirect_base);
}
tcg_regset_set_reg(allocated_regs, reg);
/* if a fixed register is used, then a move will be done afterwards */
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v3 3/4] target-sparc: Tidy global register initialization
2016-02-10 3:41 [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 1/4] tcg: Implement indirect memory registers Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 2/4] tcg: Allocate indirect_base temporaries in a different order Richard Henderson
@ 2016-02-10 3:41 ` Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 4/4] target-sparc: Use global registers for the register window Richard Henderson
2016-02-12 22:14 ` [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Mark Cave-Ayland
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2016-02-10 3:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Create tables for the various global registers that need allocation.
Remove one level of indirection from gregnames and fregnames.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 157 +++++++++++++++++++++--------------------------
1 file changed, 70 insertions(+), 87 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 536c4b5..4be56dd 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5329,106 +5329,89 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
void gen_intermediate_code_init(CPUSPARCState *env)
{
- unsigned int i;
static int inited;
- static const char * const gregnames[8] = {
- NULL, // g0 not used
- "g1",
- "g2",
- "g3",
- "g4",
- "g5",
- "g6",
- "g7",
+ static const char gregnames[8][4] = {
+ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
};
- static const char * const fregnames[32] = {
+ static const char fregnames[32][4] = {
"f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
"f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
};
- /* init various static tables */
- if (!inited) {
- inited = 1;
-
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
- offsetof(CPUSPARCState, regwptr),
- "regwptr");
+ static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
#ifdef TARGET_SPARC64
- cpu_xcc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUSPARCState, xcc),
- "xcc");
- cpu_asi = tcg_global_mem_new_i32(cpu_env, offsetof(CPUSPARCState, asi),
- "asi");
- cpu_fprs = tcg_global_mem_new_i32(cpu_env,
- offsetof(CPUSPARCState, fprs),
- "fprs");
- cpu_gsr = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, gsr),
- "gsr");
- cpu_tick_cmpr = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, tick_cmpr),
- "tick_cmpr");
- cpu_stick_cmpr = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, stick_cmpr),
- "stick_cmpr");
- cpu_hstick_cmpr = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, hstick_cmpr),
- "hstick_cmpr");
- cpu_hintp = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, hintp),
- "hintp");
- cpu_htba = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, htba),
- "htba");
- cpu_hver = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, hver),
- "hver");
- cpu_ssr = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, ssr), "ssr");
- cpu_ver = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, version), "ver");
- cpu_softint = tcg_global_mem_new_i32(cpu_env,
- offsetof(CPUSPARCState, softint),
- "softint");
+ { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
+ { &cpu_asi, offsetof(CPUSPARCState, asi), "asi" },
+ { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
+ { &cpu_softint, offsetof(CPUSPARCState, softint), "softint" },
#else
- cpu_wim = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, wim),
- "wim");
+ { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
+#endif
+ { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
+ { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
+ };
+
+ static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
+#ifdef TARGET_SPARC64
+ { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
+ { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
+ { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
+ { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
+ "hstick_cmpr" },
+ { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
+ { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
+ { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
+ { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
+ { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
#endif
- cpu_cond = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, cond),
- "cond");
- cpu_cc_src = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, cc_src),
- "cc_src");
- cpu_cc_src2 = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, cc_src2),
- "cc_src2");
- cpu_cc_dst = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, cc_dst),
- "cc_dst");
- cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
- offsetof(CPUSPARCState, cc_op),
- "cc_op");
- cpu_psr = tcg_global_mem_new_i32(cpu_env, offsetof(CPUSPARCState, psr),
- "psr");
- cpu_fsr = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, fsr),
- "fsr");
- cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, pc),
- "pc");
- cpu_npc = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, npc),
- "npc");
- cpu_y = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, y), "y");
+ { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
+ { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
+ { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
+ { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
+ { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
+ { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
+ { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
+ { &cpu_y, offsetof(CPUSPARCState, y), "y" },
#ifndef CONFIG_USER_ONLY
- cpu_tbr = tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, tbr),
- "tbr");
+ { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
#endif
- for (i = 1; i < 8; i++) {
- cpu_gregs[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, gregs[i]),
- gregnames[i]);
- }
- for (i = 0; i < TARGET_DPREGS; i++) {
- cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
- offsetof(CPUSPARCState, fpr[i]),
- fregnames[i]);
- }
+ };
+
+ unsigned int i;
+
+ /* init various static tables */
+ if (inited) {
+ return;
+ }
+ inited = 1;
+
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+
+ cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
+ offsetof(CPUSPARCState, regwptr),
+ "regwptr");
+
+ for (i = 0; i < ARRAY_SIZE(r32); ++i) {
+ *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
+ *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
+ }
+
+ TCGV_UNUSED(cpu_gregs[0]);
+ for (i = 1; i < 8; ++i) {
+ cpu_gregs[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUSPARCState, gregs[i]),
+ gregnames[i]);
+ }
+
+ for (i = 0; i < TARGET_DPREGS; i++) {
+ cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
+ offsetof(CPUSPARCState, fpr[i]),
+ fregnames[i]);
}
}
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v3 4/4] target-sparc: Use global registers for the register window
2016-02-10 3:41 [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Richard Henderson
` (2 preceding siblings ...)
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 3/4] target-sparc: Tidy global register initialization Richard Henderson
@ 2016-02-10 3:41 ` Richard Henderson
2016-02-12 22:14 ` [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Mark Cave-Ayland
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2016-02-10 3:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Via indirection off cpu_regwptr.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 49 ++++++++++++++++++++++++++----------------------
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4be56dd..66008f7 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -43,7 +43,8 @@ static TCGv_ptr cpu_env, cpu_regwptr;
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
static TCGv_i32 cpu_cc_op;
static TCGv_i32 cpu_psr;
-static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
+static TCGv cpu_fsr, cpu_pc, cpu_npc;
+static TCGv cpu_regs[32];
static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
@@ -273,36 +274,31 @@ static inline void gen_address_mask(DisasContext *dc, TCGv addr)
static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
{
- if (reg == 0 || reg >= 8) {
+ if (reg > 0) {
+ assert(reg < 32);
+ return cpu_regs[reg];
+ } else {
TCGv t = get_temp_tl(dc);
- if (reg == 0) {
- tcg_gen_movi_tl(t, 0);
- } else {
- tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
- }
+ tcg_gen_movi_tl(t, 0);
return t;
- } else {
- return cpu_gregs[reg];
}
}
static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
{
if (reg > 0) {
- if (reg < 8) {
- tcg_gen_mov_tl(cpu_gregs[reg], v);
- } else {
- tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
- }
+ assert(reg < 32);
+ tcg_gen_mov_tl(cpu_regs[reg], v);
}
}
static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
{
- if (reg == 0 || reg >= 8) {
- return get_temp_tl(dc);
+ if (reg > 0) {
+ assert(reg < 32);
+ return cpu_regs[reg];
} else {
- return cpu_gregs[reg];
+ return get_temp_tl(dc);
}
}
@@ -5330,8 +5326,11 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
void gen_intermediate_code_init(CPUSPARCState *env)
{
static int inited;
- static const char gregnames[8][4] = {
+ static const char gregnames[32][4] = {
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
+ "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+ "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
};
static const char fregnames[32][4] = {
"f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
@@ -5401,11 +5400,17 @@ void gen_intermediate_code_init(CPUSPARCState *env)
*rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
}
- TCGV_UNUSED(cpu_gregs[0]);
+ TCGV_UNUSED(cpu_regs[0]);
for (i = 1; i < 8; ++i) {
- cpu_gregs[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUSPARCState, gregs[i]),
- gregnames[i]);
+ cpu_regs[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUSPARCState, gregs[i]),
+ gregnames[i]);
+ }
+
+ for (i = 8; i < 32; ++i) {
+ cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
+ (i - 8) * sizeof(target_ulong),
+ gregnames[i]);
}
for (i = 0; i < TARGET_DPREGS; i++) {
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows
2016-02-10 3:41 [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Richard Henderson
` (3 preceding siblings ...)
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 4/4] target-sparc: Use global registers for the register window Richard Henderson
@ 2016-02-12 22:14 ` Mark Cave-Ayland
4 siblings, 0 replies; 6+ messages in thread
From: Mark Cave-Ayland @ 2016-02-12 22:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: aurelien
On 10/02/16 03:41, Richard Henderson wrote:
> The bulk of the original patch set has been reviewed and
> comitted. But the actual end result is still outstanding.
>
>
> r~
>
>
> Richard Henderson (4):
> tcg: Implement indirect memory registers
> tcg: Allocate indirect_base temporaries in a different order
> target-sparc: Tidy global register initialization
> target-sparc: Use global registers for the register window
>
> target-sparc/translate.c | 196 ++++++++++++++++++++++-------------------------
> tcg/tcg.c | 136 ++++++++++++++++++++++----------
> tcg/tcg.h | 2 +
> 3 files changed, 191 insertions(+), 143 deletions(-)
Looks good here booting all of my SPARC32 and SPARC64 images into
userspace, so:
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
ATB,
Mark.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-02-12 22:15 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-10 3:41 [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 1/4] tcg: Implement indirect memory registers Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 2/4] tcg: Allocate indirect_base temporaries in a different order Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 3/4] target-sparc: Tidy global register initialization Richard Henderson
2016-02-10 3:41 ` [Qemu-devel] [PATCH v3 4/4] target-sparc: Use global registers for the register window Richard Henderson
2016-02-12 22:14 ` [Qemu-devel] [PATCH v3 0/4] tcg: Improve sparc register windows Mark Cave-Ayland
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