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From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Simon Horman <horms@verge.net.au>, Magnus Damm <magnus.damm@gmail.com>
Cc: Dirk Behme <dirk.behme@de.bosch.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH v3 5/7] ARM: dts: r8a7794: Add L2 cache-controller node
Date: Mon, 15 Feb 2016 21:38:33 +0100	[thread overview]
Message-ID: <1455568715-20880-6-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1455568715-20880-1-git-send-email-geert+renesas@glider.be>

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index df0861e84a4b81eb..21a02df3609b24aa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu@1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

WARNING: multiple messages have this Message-ID (diff)
From: geert+renesas@glider.be (Geert Uytterhoeven)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/7] ARM: dts: r8a7794: Add L2 cache-controller node
Date: Mon, 15 Feb 2016 21:38:33 +0100	[thread overview]
Message-ID: <1455568715-20880-6-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1455568715-20880-1-git-send-email-geert+renesas@glider.be>

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index df0861e84a4b81eb..21a02df3609b24aa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu at 1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

  parent reply	other threads:[~2016-02-15 20:38 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-15 20:38 [PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes Geert Uytterhoeven
2016-02-15 20:38 ` Geert Uytterhoeven
2016-02-15 20:38 ` Geert Uytterhoeven
     [not found] ` <1455568715-20880-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2016-02-15 20:38   ` [PATCH v3 1/7] ARM: dts: r8a73a4: Add " Geert Uytterhoeven
2016-02-15 20:38     ` Geert Uytterhoeven
2016-02-15 20:38     ` Geert Uytterhoeven
2016-02-15 20:38   ` [PATCH v3 4/7] ARM: dts: r8a7793: Add L2 cache-controller node Geert Uytterhoeven
2016-02-15 20:38     ` Geert Uytterhoeven
2016-02-15 20:38     ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 2/7] ARM: dts: r8a7790: Add L2 cache-controller nodes Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 3/7] ARM: dts: r8a7791: Add L2 cache-controller node Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-15 20:38 ` Geert Uytterhoeven [this message]
2016-02-15 20:38   ` [PATCH v3 5/7] ARM: dts: r8a7794: " Geert Uytterhoeven
2016-02-15 20:38 ` [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
2016-02-16  6:40   ` Dirk Behme
2016-02-16  6:40     ` Dirk Behme
2016-02-16  6:40     ` Dirk Behme
2016-02-16  9:43     ` Sudeep Holla
2016-02-16  9:43       ` Sudeep Holla
2016-02-16  9:55       ` Dirk Behme
2016-02-16  9:55         ` Dirk Behme
2016-02-16  9:55         ` Dirk Behme
2016-02-15 20:38 ` [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node Geert Uytterhoeven
2016-02-15 20:38   ` Geert Uytterhoeven
     [not found]   ` <1455568715-20880-8-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2016-02-16  6:44     ` Dirk Behme
2016-02-16  6:44       ` Dirk Behme
2016-02-16  6:44       ` Dirk Behme
2016-02-16  7:12       ` Geert Uytterhoeven
2016-02-16  7:12         ` Geert Uytterhoeven
     [not found]         ` <CAMuHMdX=Kgb-i+QpP=yNO2e6nw7sXuCutXPoK0U9NwK-OyANFA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-16  7:33           ` Dirk Behme
2016-02-16  7:33             ` Dirk Behme
2016-02-16  7:33             ` Dirk Behme
2016-02-16  9:46           ` Sudeep Holla
2016-02-16  9:46             ` Sudeep Holla
2016-02-16  9:46             ` Sudeep Holla
2016-02-17  5:53 ` [PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes Simon Horman
2016-02-17  5:53   ` Simon Horman

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