* [PATCH 0/3] i40e: enable extended tag
@ 2015-12-21 2:38 Helin Zhang
2015-12-21 2:38 ` [PATCH 1/3] " Helin Zhang
` (3 more replies)
0 siblings, 4 replies; 32+ messages in thread
From: Helin Zhang @ 2015-12-21 2:38 UTC (permalink / raw)
To: dev
'extended tag' is important for XL710 performance, while might not be neccessary
for other NICs. It adds the enabling 'extended tag' into i40e PMD specifically,
then the sys files of 'extended_tag' and 'max_read_request_size', and all of their
relavant operations are removed as they are not neccessary for all devices.
In addition, documentations are updated at the same time.
Helin Zhang (3):
i40e: enable extended tag
eal: remove pci config of extended tag
igb_uio: remove sys files for setting pci config space
config/common_linuxapp | 7 --
doc/guides/linux_gsg/enable_func.rst | 22 ------
doc/guides/rel_notes/deprecation.rst | 3 +
doc/guides/rel_notes/release_2_3.rst | 11 +++
drivers/net/i40e/i40e_ethdev.c | 67 +++++++++++++++++-
lib/librte_eal/common/eal_common_pci.c | 7 --
lib/librte_eal/common/include/rte_pci.h | 4 +-
lib/librte_eal/linuxapp/eal/eal_pci.c | 90 ++-----------------------
lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 108 ------------------------------
9 files changed, 87 insertions(+), 232 deletions(-)
--
1.9.3
^ permalink raw reply [flat|nested] 32+ messages in thread* [PATCH 1/3] i40e: enable extended tag 2015-12-21 2:38 [PATCH 0/3] i40e: enable extended tag Helin Zhang @ 2015-12-21 2:38 ` Helin Zhang 2016-01-22 1:34 ` Wu, Jingjing 2016-01-22 10:26 ` Thomas Monjalon 2015-12-21 2:38 ` [PATCH 2/3] eal: remove pci config of " Helin Zhang ` (2 subsequent siblings) 3 siblings, 2 replies; 32+ messages in thread From: Helin Zhang @ 2015-12-21 2:38 UTC (permalink / raw) To: dev PCIe feature of 'Extended Tag' is important for 40G performance. It adds its enabling during each port initialization, to ensure the high performance. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- doc/guides/rel_notes/release_2_3.rst | 5 +++ drivers/net/i40e/i40e_ethdev.c | 67 ++++++++++++++++++++++++++++++++++-- 2 files changed, 69 insertions(+), 3 deletions(-) diff --git a/doc/guides/rel_notes/release_2_3.rst b/doc/guides/rel_notes/release_2_3.rst index 99de186..efd258b 100644 --- a/doc/guides/rel_notes/release_2_3.rst +++ b/doc/guides/rel_notes/release_2_3.rst @@ -4,6 +4,11 @@ DPDK Release 2.3 New Features ------------ +* **i40e: Enabled extended tag.** + + It enabled extended tag by checking and writing corresponding PCI config + space bytes, to boost the performance. + Resolved Issues --------------- diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index bf6220d..973aca8 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -273,6 +273,17 @@ #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL +/* PCI offset for querying capability */ +#define PCI_DEV_CAP_REG 0xA4 +/* PCI offset for enabling/disabling Extended Tag */ +#define PCI_DEV_CTRL_REG 0xA8 +/* Bit mask of Extended Tag capability */ +#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 +/* Bit shift of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 +/* Bit mask of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) + static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev); static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -386,7 +397,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info); static void i40e_configure_registers(struct i40e_hw *hw); -static void i40e_hw_init(struct i40e_hw *hw); +static void i40e_hw_init(struct rte_eth_dev *dev); static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); static int i40e_mirror_rule_set(struct rte_eth_dev *dev, struct rte_eth_mirror_conf *mirror_conf, @@ -765,7 +776,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) i40e_clear_hw(hw); /* Initialize the hardware */ - i40e_hw_init(hw); + i40e_hw_init(dev); /* Reset here to make sure all is clean for each PF */ ret = i40e_pf_reset(hw); @@ -7262,13 +7273,63 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, } /* + * Check and enable Extended Tag. + * Enabling Extended Tag is important for 40G performance. + */ +static int +i40e_enable_extended_tag(struct rte_eth_dev *dev) +{ + uint32_t buf = 0; + int ret; + + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CAP_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CAP_REG); + return -1; + } + if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { + PMD_DRV_LOG(ERR, "Does not support Extended Tag"); + return -1; + } + + buf = 0; + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return -1; + } + if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { + PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); + return 0; + } + buf |= PCI_DEV_CTRL_EXT_TAG_MASK; + ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return -1; + } + + return 0; +} + +/* * As some registers wouldn't be reset unless a global hardware reset, * hardware initialization is needed to put those registers into an * expected initial state. */ static void -i40e_hw_init(struct i40e_hw *hw) +i40e_hw_init(struct rte_eth_dev *dev) { + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + i40e_enable_extended_tag(dev); + /* clear the PF Queue Filter control register */ I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH 1/3] i40e: enable extended tag 2015-12-21 2:38 ` [PATCH 1/3] " Helin Zhang @ 2016-01-22 1:34 ` Wu, Jingjing 2016-01-22 10:26 ` Thomas Monjalon 1 sibling, 0 replies; 32+ messages in thread From: Wu, Jingjing @ 2016-01-22 1:34 UTC (permalink / raw) To: Zhang, Helin, dev Hi > */ > static void > -i40e_hw_init(struct i40e_hw *hw) > +i40e_hw_init(struct rte_eth_dev *dev) > { > + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > + i40e_enable_extended_tag(dev); If the function i40e_enable_extended_tag is only used here without Checking the return value, why not define it as void? Thanks Jingjing > + > /* clear the PF Queue Filter control register */ > I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); > > -- > 1.9.3 ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/3] i40e: enable extended tag 2015-12-21 2:38 ` [PATCH 1/3] " Helin Zhang 2016-01-22 1:34 ` Wu, Jingjing @ 2016-01-22 10:26 ` Thomas Monjalon 2016-01-24 3:25 ` Zhang, Helin 1 sibling, 1 reply; 32+ messages in thread From: Thomas Monjalon @ 2016-01-22 10:26 UTC (permalink / raw) To: Helin Zhang; +Cc: dev 2015-12-21 10:38, Helin Zhang: > PCIe feature of 'Extended Tag' is important for 40G performance. > It adds its enabling during each port initialization, to ensure > the high performance. If it's so important, why the values are not documented? Please start to fill a file doc/guides/nics/i40e.rst to explain how the device works. Thanks ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/3] i40e: enable extended tag 2016-01-22 10:26 ` Thomas Monjalon @ 2016-01-24 3:25 ` Zhang, Helin 2016-01-25 9:16 ` Thomas Monjalon 0 siblings, 1 reply; 32+ messages in thread From: Zhang, Helin @ 2016-01-24 3:25 UTC (permalink / raw) To: Thomas Monjalon; +Cc: dev Hi Thomas It has already been mentioned in getting started guide for a long time. Are you suggesting to move into i40e specifically? Thanks! Regards, Helin -----Original Message----- From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] Sent: Friday, January 22, 2016 6:27 PM To: Zhang, Helin <helin.zhang@intel.com> Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH 1/3] i40e: enable extended tag 2015-12-21 10:38, Helin Zhang: > PCIe feature of 'Extended Tag' is important for 40G performance. > It adds its enabling during each port initialization, to ensure the > high performance. If it's so important, why the values are not documented? Please start to fill a file doc/guides/nics/i40e.rst to explain how the device works. Thanks ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/3] i40e: enable extended tag 2016-01-24 3:25 ` Zhang, Helin @ 2016-01-25 9:16 ` Thomas Monjalon 2016-01-26 0:29 ` Zhang, Helin 0 siblings, 1 reply; 32+ messages in thread From: Thomas Monjalon @ 2016-01-25 9:16 UTC (permalink / raw) To: Zhang, Helin; +Cc: dev > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > > 2015-12-21 10:38, Helin Zhang: > > > PCIe feature of 'Extended Tag' is important for 40G performance. > > > It adds its enabling during each port initialization, to ensure the > > > high performance. > > > > If it's so important, why the values are not documented? > > Please start to fill a file doc/guides/nics/i40e.rst to explain how the > > device works. Thanks > > It has already been mentioned in getting started guide for a long time. > Are you suggesting to move into i40e specifically? Thanks! Yes you're right. I had forgotten that: http://dpdk.org/doc/guides-2.2/linux_gsg/enable_func.html#enabling-extended-tag-and-setting-max-read-request-size Yes, it would be better moved into an i40e doc. And maybe max_read_request_size may be commented to give advices on values. Thanks ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/3] i40e: enable extended tag 2016-01-25 9:16 ` Thomas Monjalon @ 2016-01-26 0:29 ` Zhang, Helin 0 siblings, 0 replies; 32+ messages in thread From: Zhang, Helin @ 2016-01-26 0:29 UTC (permalink / raw) To: Thomas Monjalon; +Cc: dev > -----Original Message----- > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > Sent: Monday, January 25, 2016 5:17 PM > To: Zhang, Helin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH 1/3] i40e: enable extended tag > > > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > > > 2015-12-21 10:38, Helin Zhang: > > > > PCIe feature of 'Extended Tag' is important for 40G performance. > > > > It adds its enabling during each port initialization, to ensure > > > > the high performance. > > > > > > If it's so important, why the values are not documented? > > > Please start to fill a file doc/guides/nics/i40e.rst to explain how > > > the device works. Thanks > > > > It has already been mentioned in getting started guide for a long time. > > Are you suggesting to move into i40e specifically? Thanks! > > Yes you're right. I had forgotten that: > http://dpdk.org/doc/guides-2.2/linux_gsg/enable_func.html#enabling- > extended-tag-and-setting-max-read-request-size > > Yes, it would be better moved into an i40e doc. > And maybe max_read_request_size may be commented to give advices on > values. > Thanks OK. Good idea, and I will move that soon later. Thanks! Regards, Helin ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/3] eal: remove pci config of extended tag 2015-12-21 2:38 [PATCH 0/3] i40e: enable extended tag Helin Zhang 2015-12-21 2:38 ` [PATCH 1/3] " Helin Zhang @ 2015-12-21 2:38 ` Helin Zhang 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2015-12-21 2:38 ` [PATCH 3/3] igb_uio: remove sys files for setting pci config space Helin Zhang 2016-02-22 6:31 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 3 siblings, 1 reply; 32+ messages in thread From: Helin Zhang @ 2015-12-21 2:38 UTC (permalink / raw) To: dev Remove pci configuration of 'extended tag' and 'max read request size', as they are not required by all devices and it lets PMD to configure them if neccessary. In addition, 'pci_config_space_set()' is deprecated. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- config/common_linuxapp | 7 --- lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 4 +- lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++------------------------------ 4 files changed, 9 insertions(+), 99 deletions(-) diff --git a/config/common_linuxapp b/config/common_linuxapp index 74bc515..f52baf9 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -115,13 +115,6 @@ CONFIG_RTE_MALLOC_DEBUG=n CONFIG_RTE_EAL_PMD_PATH="" # -# Special configurations in PCI Config Space for high performance -# -CONFIG_RTE_PCI_CONFIG=n -CONFIG_RTE_PCI_EXTENDED_TAG="" -CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0 - -# # Compile Environment Abstraction Layer for linux # CONFIG_RTE_LIBRTE_EAL_LINUXAPP=y diff --git a/lib/librte_eal/common/eal_common_pci.c b/lib/librte_eal/common/eal_common_pci.c index dcfe947..63d0829 100644 --- a/lib/librte_eal/common/eal_common_pci.c +++ b/lib/librte_eal/common/eal_common_pci.c @@ -180,13 +180,6 @@ rte_eal_pci_probe_one_driver(struct rte_pci_driver *dr, struct rte_pci_device *d } if (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) { -#ifdef RTE_PCI_CONFIG - /* - * Set PCIe config space for high performance. - * Return value can be ignored. - */ - pci_config_space_set(dev); -#endif /* map resources for devices that use igb_uio */ ret = pci_map_device(dev); if (ret != 0) diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 334c12e..8201fe8 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -489,12 +489,14 @@ int rte_eal_pci_write_config(const struct rte_pci_device *device, #ifdef RTE_PCI_CONFIG /** * Set special config space registers for performance purpose. + * It is deprecated, as all configurations have been moved into + * each PMDs respectively. * * @param dev * A pointer to a rte_pci_device structure describing the device * to use */ -void pci_config_space_set(struct rte_pci_device *dev); +void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; #endif /* RTE_PCI_CONFIG */ #ifdef __cplusplus diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c b/lib/librte_eal/linuxapp/eal/eal_pci.c index bc5b5be..11de652 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci.c @@ -482,92 +482,14 @@ error: } #ifdef RTE_PCI_CONFIG -static int -pci_config_extended_tag(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ]; - FILE *f; - - /* not configured, let it as is */ - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) != 0 && - strncmp(RTE_PCI_EXTENDED_TAG, "off", 3) != 0) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "extended_tag", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) == 0) { - /* enable Extended Tag*/ - if (strncmp(buf, "on", 2) != 0) { - fseek(f, 0, SEEK_SET); - fputs("on", f); - } - } else { - /* disable Extended Tag */ - if (strncmp(buf, "off", 3) != 0) { - fseek(f, 0, SEEK_SET); - fputs("off", f); - } - } - fclose(f); - - return 0; -} - -static int -pci_config_max_read_request_size(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ], param[BUFSIZ]; - FILE *f; - /* size can be 128, 256, 512, 1024, 2048, 4096 */ - uint32_t max_size = RTE_PCI_MAX_READ_REQUEST_SIZE; - - /* not configured, let it as is */ - if (!max_size) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "max_read_request_size", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - snprintf(param, sizeof(param), "%d", max_size); - - /* check if the size to be set is the same as current */ - if (strcmp(buf, param) == 0) { - fclose(f); - return 0; - } - fseek(f, 0, SEEK_SET); - fputs(param, f); - fclose(f); - - return 0; -} - +/* + * It is deprecated, all its configurations have been moved into + * each PMD respectively. + */ void -pci_config_space_set(struct rte_pci_device *dev) +pci_config_space_set(__rte_unused struct rte_pci_device *dev) { - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return; - - /* configure extended tag */ - pci_config_extended_tag(dev); - - /* configure max read request size */ - pci_config_max_read_request_size(dev); + RTE_LOG(DEBUG, EAL, "Nothing here, as it is deprecated\n"); } #endif -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 0/3] enable extended tag for i40e 2015-12-21 2:38 ` [PATCH 2/3] eal: remove pci config of " Helin Zhang @ 2016-02-22 3:59 ` Helin Zhang 2016-02-22 3:59 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang ` (4 more replies) 0 siblings, 5 replies; 32+ messages in thread From: Helin Zhang @ 2016-02-22 3:59 UTC (permalink / raw) To: dev; +Cc: zhe.tag It enables 'extended tag' for i40e devices only during its port initialization, which is key for 40G performance. It also deprecates the similar in igb_uio, and eal lib. v2: - Changed the type of return value of i40e_enable_extended_tag() to 'void'. - Fixed the compile warnings. - Kept the sys files as they were, and added ABI change announcement for them. - Moved high performance part of i40e from 'GSG' to a new for .nics'. Helin Zhang (3): i40e: enable extended tag eal: remove pci config of extended tag igb_uio: deprecate sys files config/common_linuxapp | 1 + doc/guides/linux_gsg/enable_func.rst | 47 ---------------- doc/guides/nics/i40e.rst | 76 ++++++++++++++++++++++++++ doc/guides/rel_notes/deprecation.rst | 6 +++ doc/guides/rel_notes/release_16_04.rst | 6 +++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++-- lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 2 + lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++---------------------------- lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 72 +++---------------------- 10 files changed, 167 insertions(+), 205 deletions(-) create mode 100644 doc/guides/nics/i40e.rst -- 1.9.3 ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 1/3] i40e: enable extended tag 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang @ 2016-02-22 3:59 ` Helin Zhang 2016-02-23 10:44 ` Bruce Richardson 2016-02-22 3:59 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang ` (3 subsequent siblings) 4 siblings, 1 reply; 32+ messages in thread From: Helin Zhang @ 2016-02-22 3:59 UTC (permalink / raw) To: dev; +Cc: zhe.tag PCIe feature of 'Extended Tag' is important for 40G performance. It adds its enabling during each port initialization, to ensure the high performance. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- doc/guides/rel_notes/release_16_04.rst | 6 ++++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 3 deletions(-) v2: - Changed the type of return value of i40e_enable_extended_tag() to 'void'. diff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst index 5786f74..bed5779 100644 --- a/doc/guides/rel_notes/release_16_04.rst +++ b/doc/guides/rel_notes/release_16_04.rst @@ -46,6 +46,12 @@ This section should contain new features added in this release. Sample format: * **Added vhost-user live migration support.** +* **i40e: Enabled extended tag.** + + It enabled extended tag by checking and writing corresponding PCI config + space bytes, to boost the performance. In the meanwhile, it deprecated the + legacy way via reading/writing sysfile supported by kernel module of igb_uio. + Resolved Issues --------------- diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ef24122..7e68c61 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -273,6 +273,17 @@ #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL +/* PCI offset for querying capability */ +#define PCI_DEV_CAP_REG 0xA4 +/* PCI offset for enabling/disabling Extended Tag */ +#define PCI_DEV_CTRL_REG 0xA8 +/* Bit mask of Extended Tag capability */ +#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 +/* Bit shift of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 +/* Bit mask of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) + static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev); static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -386,7 +397,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info); static void i40e_configure_registers(struct i40e_hw *hw); -static void i40e_hw_init(struct i40e_hw *hw); +static void i40e_hw_init(struct rte_eth_dev *dev); static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); static int i40e_mirror_rule_set(struct rte_eth_dev *dev, struct rte_eth_mirror_conf *mirror_conf, @@ -765,7 +776,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) i40e_clear_hw(hw); /* Initialize the hardware */ - i40e_hw_init(hw); + i40e_hw_init(dev); /* Reset here to make sure all is clean for each PF */ ret = i40e_pf_reset(hw); @@ -7262,13 +7273,61 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, } /* + * Check and enable Extended Tag. + * Enabling Extended Tag is important for 40G performance. + */ +static void +i40e_enable_extended_tag(struct rte_eth_dev *dev) +{ + uint32_t buf = 0; + int ret; + + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CAP_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CAP_REG); + return; + } + if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { + PMD_DRV_LOG(ERR, "Does not support Extended Tag"); + return; + } + + buf = 0; + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } + if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { + PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); + return; + } + buf |= PCI_DEV_CTRL_EXT_TAG_MASK; + ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } +} + +/* * As some registers wouldn't be reset unless a global hardware reset, * hardware initialization is needed to put those registers into an * expected initial state. */ static void -i40e_hw_init(struct i40e_hw *hw) +i40e_hw_init(struct rte_eth_dev *dev) { + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + i40e_enable_extended_tag(dev); + /* clear the PF Queue Filter control register */ I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/3] i40e: enable extended tag 2016-02-22 3:59 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang @ 2016-02-23 10:44 ` Bruce Richardson 2016-02-24 0:39 ` Zhang, Helin 0 siblings, 1 reply; 32+ messages in thread From: Bruce Richardson @ 2016-02-23 10:44 UTC (permalink / raw) To: Helin Zhang; +Cc: dev, zhe.tag On Mon, Feb 22, 2016 at 11:59:43AM +0800, Helin Zhang wrote: > PCIe feature of 'Extended Tag' is important for 40G performance. > It adds its enabling during each port initialization, to ensure > the high performance. > > Signed-off-by: Helin Zhang <helin.zhang@intel.com> > --- > doc/guides/rel_notes/release_16_04.rst | 6 ++++ > drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++++++++++++++-- > 2 files changed, 68 insertions(+), 3 deletions(-) > > v2: > - Changed the type of return value of i40e_enable_extended_tag() to 'void'. > > diff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst > index 5786f74..bed5779 100644 > --- a/doc/guides/rel_notes/release_16_04.rst > +++ b/doc/guides/rel_notes/release_16_04.rst > @@ -46,6 +46,12 @@ This section should contain new features added in this release. Sample format: > > * **Added vhost-user live migration support.** > > +* **i40e: Enabled extended tag.** > + > + It enabled extended tag by checking and writing corresponding PCI config > + space bytes, to boost the performance. In the meanwhile, it deprecated the > + legacy way via reading/writing sysfile supported by kernel module of igb_uio. > + Hi Helin, does this really need to go into the release notes? Is it a user-visible change that affects the user experience in any way? /Bruce ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/3] i40e: enable extended tag 2016-02-23 10:44 ` Bruce Richardson @ 2016-02-24 0:39 ` Zhang, Helin 0 siblings, 0 replies; 32+ messages in thread From: Zhang, Helin @ 2016-02-24 0:39 UTC (permalink / raw) To: Richardson, Bruce; +Cc: dev, zhe.tag > -----Original Message----- > From: Richardson, Bruce > Sent: Tuesday, February 23, 2016 6:45 PM > To: Zhang, Helin <helin.zhang@intel.com> > Cc: dev@dpdk.org; zhe.tag@intel.com > Subject: Re: [dpdk-dev] [PATCH v2 1/3] i40e: enable extended tag > > On Mon, Feb 22, 2016 at 11:59:43AM +0800, Helin Zhang wrote: > > PCIe feature of 'Extended Tag' is important for 40G performance. > > It adds its enabling during each port initialization, to ensure the > > high performance. > > > > Signed-off-by: Helin Zhang <helin.zhang@intel.com> > > --- > > doc/guides/rel_notes/release_16_04.rst | 6 ++++ > > drivers/net/i40e/i40e_ethdev.c | 65 > ++++++++++++++++++++++++++++++++-- > > 2 files changed, 68 insertions(+), 3 deletions(-) > > > > v2: > > - Changed the type of return value of i40e_enable_extended_tag() to 'void'. > > > > diff --git a/doc/guides/rel_notes/release_16_04.rst > > b/doc/guides/rel_notes/release_16_04.rst > > index 5786f74..bed5779 100644 > > --- a/doc/guides/rel_notes/release_16_04.rst > > +++ b/doc/guides/rel_notes/release_16_04.rst > > @@ -46,6 +46,12 @@ This section should contain new features added in this > release. Sample format: > > > > * **Added vhost-user live migration support.** > > > > +* **i40e: Enabled extended tag.** > > + > > + It enabled extended tag by checking and writing corresponding PCI > > + config space bytes, to boost the performance. In the meanwhile, it > > + deprecated the legacy way via reading/writing sysfile supported by kernel > module of igb_uio. > > + > > Hi Helin, > > does this really need to go into the release notes? Is it a user-visible change that > affects the user experience in any way? Previously we enable it in eal via igb_uio sys file (by default, it is disabled), which was deprecated now, and will be removed from next release. All now added into i40e PMD init only. Yes, user might see the performance boost without doing anything, which is different from previous version of DPDK. I think it should be mentioned somewhere. Any better idea? Thanks, Helin > > /Bruce ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 2/3] eal: remove pci config of extended tag 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2016-02-22 3:59 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang @ 2016-02-22 3:59 ` Helin Zhang 2016-03-08 17:05 ` Thomas Monjalon 2016-02-22 3:59 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang ` (2 subsequent siblings) 4 siblings, 1 reply; 32+ messages in thread From: Helin Zhang @ 2016-02-22 3:59 UTC (permalink / raw) To: dev; +Cc: zhe.tag Remove pci configuration of 'extended tag' and 'max read request size', as they are not required by all devices and it lets PMD to configure them if neccessary. In addition, 'pci_config_space_set()' is deprecated. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- config/common_linuxapp | 1 + lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 4 +- lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++------------------------------ 4 files changed, 10 insertions(+), 92 deletions(-) v2: - Fixed the compile warnings. diff --git a/config/common_linuxapp b/config/common_linuxapp index f1638db..a74cbab 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -110,6 +110,7 @@ CONFIG_RTE_EAL_PMD_PATH="" # # Special configurations in PCI Config Space for high performance +# They are all deprecated, and will be removed later. # CONFIG_RTE_PCI_CONFIG=n CONFIG_RTE_PCI_EXTENDED_TAG="" diff --git a/lib/librte_eal/common/eal_common_pci.c b/lib/librte_eal/common/eal_common_pci.c index 96d5113..366fb46 100644 --- a/lib/librte_eal/common/eal_common_pci.c +++ b/lib/librte_eal/common/eal_common_pci.c @@ -180,13 +180,6 @@ rte_eal_pci_probe_one_driver(struct rte_pci_driver *dr, struct rte_pci_device *d } if (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) { -#ifdef RTE_PCI_CONFIG - /* - * Set PCIe config space for high performance. - * Return value can be ignored. - */ - pci_config_space_set(dev); -#endif /* map resources for devices that use igb_uio */ ret = rte_eal_pci_map_device(dev); if (ret != 0) diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 067e084..189d509 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -580,12 +580,14 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, #ifdef RTE_PCI_CONFIG /** * Set special config space registers for performance purpose. + * It is deprecated, as all configurations have been moved into + * each PMDs respectively. * * @param dev * A pointer to a rte_pci_device structure describing the device * to use */ -void pci_config_space_set(struct rte_pci_device *dev); +void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; #endif /* RTE_PCI_CONFIG */ #ifdef __cplusplus diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c b/lib/librte_eal/linuxapp/eal/eal_pci.c index 4346973..4c45452 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci.c @@ -482,92 +482,14 @@ error: } #ifdef RTE_PCI_CONFIG -static int -pci_config_extended_tag(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ]; - FILE *f; - - /* not configured, let it as is */ - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) != 0 && - strncmp(RTE_PCI_EXTENDED_TAG, "off", 3) != 0) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "extended_tag", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) == 0) { - /* enable Extended Tag*/ - if (strncmp(buf, "on", 2) != 0) { - fseek(f, 0, SEEK_SET); - fputs("on", f); - } - } else { - /* disable Extended Tag */ - if (strncmp(buf, "off", 3) != 0) { - fseek(f, 0, SEEK_SET); - fputs("off", f); - } - } - fclose(f); - - return 0; -} - -static int -pci_config_max_read_request_size(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ], param[BUFSIZ]; - FILE *f; - /* size can be 128, 256, 512, 1024, 2048, 4096 */ - uint32_t max_size = RTE_PCI_MAX_READ_REQUEST_SIZE; - - /* not configured, let it as is */ - if (!max_size) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "max_read_request_size", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - snprintf(param, sizeof(param), "%d", max_size); - - /* check if the size to be set is the same as current */ - if (strcmp(buf, param) == 0) { - fclose(f); - return 0; - } - fseek(f, 0, SEEK_SET); - fputs(param, f); - fclose(f); - - return 0; -} - +/* + * It is deprecated, all its configurations have been moved into + * each PMD respectively. + */ void -pci_config_space_set(struct rte_pci_device *dev) +pci_config_space_set(__rte_unused struct rte_pci_device *dev) { - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return; - - /* configure extended tag */ - pci_config_extended_tag(dev); - - /* configure max read request size */ - pci_config_max_read_request_size(dev); + RTE_LOG(DEBUG, EAL, "Nothing here, as it is deprecated\n"); } #endif -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/3] eal: remove pci config of extended tag 2016-02-22 3:59 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang @ 2016-03-08 17:05 ` Thomas Monjalon 0 siblings, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 17:05 UTC (permalink / raw) To: Helin Zhang; +Cc: dev, zhe.tag 2016-02-22 11:59, Helin Zhang: > --- a/lib/librte_eal/common/include/rte_pci.h > +++ b/lib/librte_eal/common/include/rte_pci.h > @@ -580,12 +580,14 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, > #ifdef RTE_PCI_CONFIG > /** > * Set special config space registers for performance purpose. > + * It is deprecated, as all configurations have been moved into > + * each PMDs respectively. > * > * @param dev > * A pointer to a rte_pci_device structure describing the device > * to use > */ > -void pci_config_space_set(struct rte_pci_device *dev); > +void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; There is a missing prototype error because #include <rte_common.h> is missing. ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 3/3] igb_uio: deprecate sys files 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2016-02-22 3:59 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang 2016-02-22 3:59 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang @ 2016-02-22 3:59 ` Helin Zhang 2016-03-08 17:48 ` Thomas Monjalon 2016-03-08 18:02 ` Thomas Monjalon 2016-02-22 5:52 ` [PATCH v2 0/3] enable extended tag for i40e Wu, Jingjing 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon 4 siblings, 2 replies; 32+ messages in thread From: Helin Zhang @ 2016-02-22 3:59 UTC (permalink / raw) To: dev; +Cc: zhe.tag It deprecated sys files of 'extended_tag' and 'max_read_request_size', and announced the planned ABI changes of them. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- doc/guides/linux_gsg/enable_func.rst | 47 ------------------- doc/guides/nics/i40e.rst | 76 +++++++++++++++++++++++++++++++ doc/guides/rel_notes/deprecation.rst | 6 +++ lib/librte_eal/common/include/rte_pci.h | 2 +- lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 72 ++++------------------------- 5 files changed, 91 insertions(+), 112 deletions(-) create mode 100644 doc/guides/nics/i40e.rst v2: - Kept the sys files as they were, and added ABI change announcement for them. - Moved high performance part of i40e from 'GSG' to a new for .nics'. diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst index c3fa6d3..f59f25c 100644 --- a/doc/guides/linux_gsg/enable_func.rst +++ b/doc/guides/linux_gsg/enable_func.rst @@ -176,50 +176,3 @@ Also, if ``INTEL_IOMMU_DEFAULT_ON`` is not set in the kernel, the ``intel_iommu= This ensures that the Intel IOMMU is being initialized as expected. Please note that while using ``iommu=pt`` is compulsory for ``igb_uio driver``, the ``vfio-pci`` driver can actually work with both ``iommu=pt`` and ``iommu=on``. - -High Performance of Small Packets on 40G NIC --------------------------------------------- - -As there might be firmware fixes for performance enhancement in latest version -of firmware image, the firmware update might be needed for getting high performance. -Check with the local Intel's Network Division application engineers for firmware updates. -The base driver to support firmware version of FVL3E will be integrated in the next -DPDK release, so currently the validated firmware version is 4.2.6. - -Enabling Extended Tag and Setting Max Read Request Size -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -PCI configurations of ``extended_tag`` and max _read_requ st_size have big impacts on performance of small packets on 40G NIC. -Enabling extended_tag and setting ``max_read_request_size`` to small size such as 128 bytes provide great helps to high performance of small packets. - -* These can be done in some BIOS implementations. - -* For other BIOS implementations, PCI configurations can be changed by using command of ``setpci``, or special configurations in DPDK config file of ``common_linux``. - - * Bits 7:5 at address of 0xA8 of each PCI device is used for setting the max_read_request_size, - and bit 8 of 0xA8 of each PCI device is used for enabling/disabling the extended_tag. - lspci and setpci can be used to read the values of 0xA8 and then write it back after being changed. - - * In config file of common_linux, below three configurations can be changed for the same purpose. - - ``CONFIG_RTE_PCI_CONFIG`` - - ``CONFIG_RTE_PCI_EXTENDED_TAG`` - - ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` - -Use 16 Bytes RX Descriptor Size -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -As i40e PMD supports both 16 and 32 bytes RX descriptor sizes, and 16 bytes size can provide helps to high performance of small packets. -Configuration of ``CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC`` in config files can be changed to use 16 bytes size RX descriptors. - -High Performance and per Packet Latency Tradeoff -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Due to the hardware design, the interrupt signal inside NIC is needed for per -packet descriptor write-back. The minimum interval of interrupts could be set -at compile time by ``CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL`` in configuration files. -Though there is a default configuration, the interval could be tuned by the -users with that configuration item depends on what the user cares about more, -performance or per packet latency. diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst new file mode 100644 index 0000000..b6f089f --- /dev/null +++ b/doc/guides/nics/i40e.rst @@ -0,0 +1,76 @@ +.. BSD LICENSE + Copyright(c) 2010-2016 Intel Corporation. All rights reserved. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +I40E Poll Mode Driver +===================== + +The I40E PMD (**librte_pmd_i40e**) provides poll mode driver support +for **Intel X710/XL710/X722** 10/40 Gbps family of adapters. + +High performance of small packets +--------------------------------- + +As there might be firmware fixes or enhancements for performance in newer +version of firmware images, firmware update might be necessary for getting +high performance. In addition, host driver version is also important for +DPDK VF performance if kernel PF driver is being used. Check with the local +Intel Network Division application engineers for helps on firmware upgrade +and kernel driver upgrade. Release 16.04 will be validated with NVM 5.xx. + +Extended Tag +~~~~~~~~~~~~ + +PCI configuration of ``extended_tag`` has big impact on small packet size +performance of 40G ports. Enabling ``extended_tag`` can help 40G port to +achieve the best performance, especially for small packet size. + +- Disabling/enabling ``extended_tag`` can be done in some BIOS implementations. +- If BIOS does not enable it, and does not support changing it, tools + (e.g. ``setpci`` on Linux) can be used to enable or disable ``extended_tag``. +- From release 16.04, ``extended_tag`` is enabled by default during port + initialization, users don't need to care about that anymore. + +Use 16 bytes RX descriptor size +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +As i40e PMD supports both 16 and 32 bytes RX descriptor sizes, and 16 bytes +size may help a bit for high performance of small packet size. Configuration +of ``CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC`` in config files can be changed +to use 16 bytes size RX descriptors. + +High performance and per packet latency tradeoff +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to the hardware design, the interrupt signal inside NIC is needed for per +packet descriptor write-back. The minimum interval of interrupts could be set +at compile time by ``CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL`` in configuration +files. Though there is a default configuration, the interval could be tuned by +the users with that configuration item depends on what the user cares about +more, performance or per packet latency. diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index e94d4a2..b7e0a4f 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -49,3 +49,9 @@ Deprecation Notices commands (such as RETA update in testpmd). This should impact CMDLINE_PARSE_RESULT_BUFSIZE, STR_TOKEN_SIZE and RDLINE_BUF_SIZE. It should be integrated in release 2.3. + +* ABI changes are planned for release 16.07. The eal function of + pci_config_space_set is deprecated in release 16.04, and will be removed + from 16.07. Macros of CONFIG_RTE_PCI_CONFIG, CONFIG_RTE_PCI_EXTENDED_TAG and + CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE will be removed. sysfile of extended_tag + and max_read_request_size created by kernel module igb_uio will be removed. diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 189d509..e4fb82d 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -587,7 +587,7 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, * A pointer to a rte_pci_device structure describing the device * to use */ -void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; +void pci_config_space_set(struct rte_pci_device *dev); #endif /* RTE_PCI_CONFIG */ #ifdef __cplusplus diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c index f5617d2..01b4ca6 100644 --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c @@ -40,15 +40,6 @@ #include "compat.h" -#ifdef RTE_PCI_CONFIG -#define PCI_SYS_FILE_BUF_SIZE 10 -#define PCI_DEV_CAP_REG 0xA4 -#define PCI_DEV_CTRL_REG 0xA8 -#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 -#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 -#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) -#endif - /** * A structure describing the private information for a uio device. */ @@ -94,19 +85,9 @@ store_max_vfs(struct device *dev, struct device_attribute *attr, static ssize_t show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf) { - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0; + dev_info(dev, "Deprecated\n"); - pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid"); - - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", - (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off"); + return 0; } static ssize_t @@ -115,36 +96,9 @@ store_extended_tag(struct device *dev, const char *buf, size_t count) { - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0, enable; - - if (strncmp(buf, "on", 2) == 0) - enable = 1; - else if (strncmp(buf, "off", 3) == 0) - enable = 0; - else - return -EINVAL; - - pci_cfg_access_lock(pci_dev); - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */ - pci_cfg_access_unlock(pci_dev); - return -EPERM; - } + dev_info(dev, "Deprecated\n"); - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - if (enable) - val |= PCI_DEV_CTRL_EXT_TAG_MASK; - else - val &= ~PCI_DEV_CTRL_EXT_TAG_MASK; - pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, val); - pci_cfg_access_unlock(pci_dev); - - return count; + return 0; } static ssize_t @@ -152,10 +106,9 @@ show_max_read_request_size(struct device *dev, struct device_attribute *attr, char *buf) { - struct pci_dev *pci_dev = to_pci_dev(dev); - int val = pcie_get_readrq(pci_dev); + dev_info(dev, "Deprecated\n"); - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val); + return 0; } static ssize_t @@ -164,18 +117,9 @@ store_max_read_request_size(struct device *dev, const char *buf, size_t count) { - struct pci_dev *pci_dev = to_pci_dev(dev); - unsigned long size = 0; - int ret; + dev_info(dev, "Deprecated\n"); - if (0 != kstrtoul(buf, 0, &size)) - return -EINVAL; - - ret = pcie_set_readrq(pci_dev, (int)size); - if (ret < 0) - return ret; - - return count; + return 0; } #endif -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/3] igb_uio: deprecate sys files 2016-02-22 3:59 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang @ 2016-03-08 17:48 ` Thomas Monjalon 2016-03-08 18:02 ` Thomas Monjalon 1 sibling, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 17:48 UTC (permalink / raw) To: Helin Zhang; +Cc: dev 2016-02-22 11:59, Helin Zhang: > --- /dev/null > +++ b/doc/guides/nics/i40e.rst This file is not included in the index. > --- a/lib/librte_eal/common/include/rte_pci.h > +++ b/lib/librte_eal/common/include/rte_pci.h > @@ -587,7 +587,7 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, > * A pointer to a rte_pci_device structure describing the device > * to use > */ > -void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; > +void pci_config_space_set(struct rte_pci_device *dev); Why the deprecated attribute is now removed? ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/3] igb_uio: deprecate sys files 2016-02-22 3:59 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang 2016-03-08 17:48 ` Thomas Monjalon @ 2016-03-08 18:02 ` Thomas Monjalon 1 sibling, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 18:02 UTC (permalink / raw) To: Helin Zhang; +Cc: dev 2016-02-22 11:59, Helin Zhang: > It deprecated sys files of 'extended_tag' and > 'max_read_request_size', and announced the planned ABI changes of > them. [...] > - Moved high performance part of i40e from 'GSG' to a new for .nics'. This change is not related to extended tag only. Let's move the docs after Jingjing have created i40e.rst. ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 0/3] enable extended tag for i40e 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang ` (2 preceding siblings ...) 2016-02-22 3:59 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang @ 2016-02-22 5:52 ` Wu, Jingjing 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon 4 siblings, 0 replies; 32+ messages in thread From: Wu, Jingjing @ 2016-02-22 5:52 UTC (permalink / raw) To: Zhang, Helin, dev; +Cc: zhe.tag > -----Original Message----- > From: Zhang, Helin > Sent: Monday, February 22, 2016 12:00 PM > To: dev@dpdk.org > Cc: thomas.monjalon@6wind.com; Wu, Jingjing; zhe.tag@intel.com; Zhang, > Helin > Subject: [PATCH v2 0/3] enable extended tag for i40e > > It enables 'extended tag' for i40e devices only during its port initialization, > which is key for 40G performance. It also deprecates the similar in igb_uio, > and eal lib. > > v2: > - Changed the type of return value of i40e_enable_extended_tag() to 'void'. > - Fixed the compile warnings. > - Kept the sys files as they were, and added ABI change announcement for > them. > - Moved high performance part of i40e from 'GSG' to a new for .nics'. > > Helin Zhang (3): > i40e: enable extended tag > eal: remove pci config of extended tag > igb_uio: deprecate sys files Agree to add a doc i40e.rst to record i40e specific stuff. I also sent a patch http://dpdk.org/dev/patchwork/patch/10173/, it will be great if they can be merged. :) Acked-by: Jingjing Wu <jingjing.wu@intel.com> > > -- > 1.9.3 ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 0/3] enable extended tag for i40e 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang ` (3 preceding siblings ...) 2016-02-22 5:52 ` [PATCH v2 0/3] enable extended tag for i40e Wu, Jingjing @ 2016-03-08 18:38 ` Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 1/3] i40e: enable extended tag Thomas Monjalon ` (3 more replies) 4 siblings, 4 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 18:38 UTC (permalink / raw) To: helin.zhang; +Cc: dev It enables 'extended tag' for i40e devices only during its port initialization, which is key for 40G performance. It also deprecates the similar in igb_uio, and eal lib. v3: - fix build with deprecated attribute - keep deprecated attribute - reword release notes a bit - revert doc move from v2 - better split the patches v2: - Changed the type of return value of i40e_enable_extended_tag() to 'void'. - Fixed the compile warnings. - Kept the sys files as they were, and added ABI change announcement for them. - Moved high performance part of i40e from 'GSG' to a new for .nics'. Helin Zhang (3): i40e: enable extended tag pci: remove config of extended tag igb_uio: deprecate extended tag config/common_base | 1 + doc/guides/linux_gsg/enable_func.rst | 27 ++++------ doc/guides/rel_notes/deprecation.rst | 7 +++ doc/guides/rel_notes/release_16_04.rst | 6 +++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++-- lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 5 +- lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++---------------------------- lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 72 +++---------------------- 9 files changed, 104 insertions(+), 176 deletions(-) -- 2.7.0 ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 1/3] i40e: enable extended tag 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon @ 2016-03-08 18:38 ` Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 2/3] pci: remove config of " Thomas Monjalon ` (2 subsequent siblings) 3 siblings, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 18:38 UTC (permalink / raw) To: helin.zhang; +Cc: dev From: Helin Zhang <helin.zhang@intel.com> PCIe feature of 'Extended Tag' is important for 40G performance. It adds its enabling during each port initialization, to ensure the high performance. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- doc/guides/linux_gsg/enable_func.rst | 3 ++ doc/guides/rel_notes/release_16_04.rst | 6 ++++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++++++++++++++-- 3 files changed, 71 insertions(+), 3 deletions(-) diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst index c3fa6d3..8cb3d79 100644 --- a/doc/guides/linux_gsg/enable_func.rst +++ b/doc/guides/linux_gsg/enable_func.rst @@ -208,6 +208,9 @@ Enabling extended_tag and setting ``max_read_request_size`` to small size such a ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` +* From release 16.04, ``extended_tag`` is enabled by default during port + initialization, users don't need to care about that anymore. + Use 16 Bytes RX Descriptor Size ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst index 24f15bf..96f144e 100644 --- a/doc/guides/rel_notes/release_16_04.rst +++ b/doc/guides/rel_notes/release_16_04.rst @@ -57,6 +57,12 @@ This section should contain new features added in this release. Sample format: * **Added vhost-user live migration support.** +* **Enabled PCI extended tag for i40e.** + + It enabled extended tag by checking and writing corresponding PCI config + space bytes, to boost the performance. In the meanwhile, it deprecated the + legacy way via reading/writing sysfile supported by kernel module igb_uio. + Resolved Issues --------------- diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ef24122..7e68c61 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -273,6 +273,17 @@ #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL +/* PCI offset for querying capability */ +#define PCI_DEV_CAP_REG 0xA4 +/* PCI offset for enabling/disabling Extended Tag */ +#define PCI_DEV_CTRL_REG 0xA8 +/* Bit mask of Extended Tag capability */ +#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 +/* Bit shift of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 +/* Bit mask of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) + static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev); static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -386,7 +397,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info); static void i40e_configure_registers(struct i40e_hw *hw); -static void i40e_hw_init(struct i40e_hw *hw); +static void i40e_hw_init(struct rte_eth_dev *dev); static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); static int i40e_mirror_rule_set(struct rte_eth_dev *dev, struct rte_eth_mirror_conf *mirror_conf, @@ -765,7 +776,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) i40e_clear_hw(hw); /* Initialize the hardware */ - i40e_hw_init(hw); + i40e_hw_init(dev); /* Reset here to make sure all is clean for each PF */ ret = i40e_pf_reset(hw); @@ -7262,13 +7273,61 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, } /* + * Check and enable Extended Tag. + * Enabling Extended Tag is important for 40G performance. + */ +static void +i40e_enable_extended_tag(struct rte_eth_dev *dev) +{ + uint32_t buf = 0; + int ret; + + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CAP_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CAP_REG); + return; + } + if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { + PMD_DRV_LOG(ERR, "Does not support Extended Tag"); + return; + } + + buf = 0; + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } + if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { + PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); + return; + } + buf |= PCI_DEV_CTRL_EXT_TAG_MASK; + ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } +} + +/* * As some registers wouldn't be reset unless a global hardware reset, * hardware initialization is needed to put those registers into an * expected initial state. */ static void -i40e_hw_init(struct i40e_hw *hw) +i40e_hw_init(struct rte_eth_dev *dev) { + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + i40e_enable_extended_tag(dev); + /* clear the PF Queue Filter control register */ I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); -- 2.7.0 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 2/3] pci: remove config of extended tag 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 1/3] i40e: enable extended tag Thomas Monjalon @ 2016-03-08 18:38 ` Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 3/3] igb_uio: deprecate " Thomas Monjalon 2016-03-08 18:41 ` [PATCH v3 0/3] enable extended tag for i40e Thomas Monjalon 3 siblings, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 18:38 UTC (permalink / raw) To: helin.zhang; +Cc: dev From: Helin Zhang <helin.zhang@intel.com> Remove pci configuration of 'extended tag' and 'max read request size', as they are not required by all devices and it lets PMD to configure them if necessary. In addition, 'pci_config_space_set()' is deprecated. Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com> --- config/common_base | 1 + doc/guides/rel_notes/deprecation.rst | 5 ++ lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 5 +- lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++------------------------------ 5 files changed, 16 insertions(+), 92 deletions(-) diff --git a/config/common_base b/config/common_base index 1af28c8..c73f71a 100644 --- a/config/common_base +++ b/config/common_base @@ -102,6 +102,7 @@ CONFIG_RTE_EAL_PMD_PATH="" # # Special configurations in PCI Config Space for high performance +# They are all deprecated, and will be removed later. # CONFIG_RTE_PCI_CONFIG=n CONFIG_RTE_PCI_EXTENDED_TAG="" diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index 9930b5a..9979982 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -8,6 +8,11 @@ API and ABI deprecation notices are to be posted here. Deprecation Notices ------------------- +* The EAL function pci_config_space_set is deprecated in release 16.04 + and will be removed from 16.07. + Macros CONFIG_RTE_PCI_CONFIG, CONFIG_RTE_PCI_EXTENDED_TAG and + CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE will be removed. + * The following fields have been deprecated in rte_eth_stats: ibadcrc, ibadlen, imcasts, fdirmatch, fdirmiss, tx_pause_xon, rx_pause_xon, tx_pause_xoff, rx_pause_xoff diff --git a/lib/librte_eal/common/eal_common_pci.c b/lib/librte_eal/common/eal_common_pci.c index 96d5113..366fb46 100644 --- a/lib/librte_eal/common/eal_common_pci.c +++ b/lib/librte_eal/common/eal_common_pci.c @@ -180,13 +180,6 @@ rte_eal_pci_probe_one_driver(struct rte_pci_driver *dr, struct rte_pci_device *d } if (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) { -#ifdef RTE_PCI_CONFIG - /* - * Set PCIe config space for high performance. - * Return value can be ignored. - */ - pci_config_space_set(dev); -#endif /* map resources for devices that use igb_uio */ ret = rte_eal_pci_map_device(dev); if (ret != 0) diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 067e084..e692094 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -578,14 +578,17 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset); #ifdef RTE_PCI_CONFIG +#include <rte_common.h> /** * Set special config space registers for performance purpose. + * It is deprecated, as all configurations have been moved into + * each PMDs respectively. * * @param dev * A pointer to a rte_pci_device structure describing the device * to use */ -void pci_config_space_set(struct rte_pci_device *dev); +void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; #endif /* RTE_PCI_CONFIG */ #ifdef __cplusplus diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c b/lib/librte_eal/linuxapp/eal/eal_pci.c index 4346973..4c45452 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci.c @@ -482,92 +482,14 @@ error: } #ifdef RTE_PCI_CONFIG -static int -pci_config_extended_tag(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ]; - FILE *f; - - /* not configured, let it as is */ - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) != 0 && - strncmp(RTE_PCI_EXTENDED_TAG, "off", 3) != 0) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "extended_tag", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) == 0) { - /* enable Extended Tag*/ - if (strncmp(buf, "on", 2) != 0) { - fseek(f, 0, SEEK_SET); - fputs("on", f); - } - } else { - /* disable Extended Tag */ - if (strncmp(buf, "off", 3) != 0) { - fseek(f, 0, SEEK_SET); - fputs("off", f); - } - } - fclose(f); - - return 0; -} - -static int -pci_config_max_read_request_size(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ], param[BUFSIZ]; - FILE *f; - /* size can be 128, 256, 512, 1024, 2048, 4096 */ - uint32_t max_size = RTE_PCI_MAX_READ_REQUEST_SIZE; - - /* not configured, let it as is */ - if (!max_size) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "max_read_request_size", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - snprintf(param, sizeof(param), "%d", max_size); - - /* check if the size to be set is the same as current */ - if (strcmp(buf, param) == 0) { - fclose(f); - return 0; - } - fseek(f, 0, SEEK_SET); - fputs(param, f); - fclose(f); - - return 0; -} - +/* + * It is deprecated, all its configurations have been moved into + * each PMD respectively. + */ void -pci_config_space_set(struct rte_pci_device *dev) +pci_config_space_set(__rte_unused struct rte_pci_device *dev) { - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return; - - /* configure extended tag */ - pci_config_extended_tag(dev); - - /* configure max read request size */ - pci_config_max_read_request_size(dev); + RTE_LOG(DEBUG, EAL, "Nothing here, as it is deprecated\n"); } #endif -- 2.7.0 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 3/3] igb_uio: deprecate extended tag 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 1/3] i40e: enable extended tag Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 2/3] pci: remove config of " Thomas Monjalon @ 2016-03-08 18:38 ` Thomas Monjalon 2016-03-08 18:41 ` [PATCH v3 0/3] enable extended tag for i40e Thomas Monjalon 3 siblings, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 18:38 UTC (permalink / raw) To: helin.zhang; +Cc: dev From: Helin Zhang <helin.zhang@intel.com> It deprecates sys files of 'extended_tag' and 'max_read_request_size' which was not documented. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- doc/guides/linux_gsg/enable_func.rst | 26 ++++------- doc/guides/rel_notes/deprecation.rst | 2 + lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 72 ++++--------------------------- 3 files changed, 18 insertions(+), 82 deletions(-) diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst index 8cb3d79..076770f 100644 --- a/doc/guides/linux_gsg/enable_func.rst +++ b/doc/guides/linux_gsg/enable_func.rst @@ -186,27 +186,17 @@ Check with the local Intel's Network Division application engineers for firmware The base driver to support firmware version of FVL3E will be integrated in the next DPDK release, so currently the validated firmware version is 4.2.6. -Enabling Extended Tag and Setting Max Read Request Size -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Enabling Extended Tag +~~~~~~~~~~~~~~~~~~~~~ -PCI configurations of ``extended_tag`` and max _read_requ st_size have big impacts on performance of small packets on 40G NIC. -Enabling extended_tag and setting ``max_read_request_size`` to small size such as 128 bytes provide great helps to high performance of small packets. +PCI configuration of ``extended_tag`` has big impact on small packet size +performance of 40G ports. Enabling ``extended_tag`` can help 40G port to +achieve the best performance, especially for small packet size. -* These can be done in some BIOS implementations. +* Disabling/enabling ``extended_tag`` can be done in some BIOS implementations. -* For other BIOS implementations, PCI configurations can be changed by using command of ``setpci``, or special configurations in DPDK config file of ``common_linux``. - - * Bits 7:5 at address of 0xA8 of each PCI device is used for setting the max_read_request_size, - and bit 8 of 0xA8 of each PCI device is used for enabling/disabling the extended_tag. - lspci and setpci can be used to read the values of 0xA8 and then write it back after being changed. - - * In config file of common_linux, below three configurations can be changed for the same purpose. - - ``CONFIG_RTE_PCI_CONFIG`` - - ``CONFIG_RTE_PCI_EXTENDED_TAG`` - - ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` +* If BIOS does not enable it, and does not support changing it, tools + (e.g. ``setpci`` on Linux) can be used to enable or disable ``extended_tag``. * From release 16.04, ``extended_tag`` is enabled by default during port initialization, users don't need to care about that anymore. diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index 9979982..5287811 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -12,6 +12,8 @@ Deprecation Notices and will be removed from 16.07. Macros CONFIG_RTE_PCI_CONFIG, CONFIG_RTE_PCI_EXTENDED_TAG and CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE will be removed. + The /sys entries extended_tag and max_read_request_size created by igb_uio + will be removed. * The following fields have been deprecated in rte_eth_stats: ibadcrc, ibadlen, imcasts, fdirmatch, fdirmiss, diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c index a3ad912..72b2692 100644 --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c @@ -40,15 +40,6 @@ #include "compat.h" -#ifdef RTE_PCI_CONFIG -#define PCI_SYS_FILE_BUF_SIZE 10 -#define PCI_DEV_CAP_REG 0xA4 -#define PCI_DEV_CTRL_REG 0xA8 -#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 -#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 -#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) -#endif - /** * A structure describing the private information for a uio device. */ @@ -94,19 +85,9 @@ store_max_vfs(struct device *dev, struct device_attribute *attr, static ssize_t show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf) { - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0; + dev_info(dev, "Deprecated\n"); - pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid"); - - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", - (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off"); + return 0; } static ssize_t @@ -115,36 +96,9 @@ store_extended_tag(struct device *dev, const char *buf, size_t count) { - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0, enable; - - if (strncmp(buf, "on", 2) == 0) - enable = 1; - else if (strncmp(buf, "off", 3) == 0) - enable = 0; - else - return -EINVAL; - - pci_cfg_access_lock(pci_dev); - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */ - pci_cfg_access_unlock(pci_dev); - return -EPERM; - } + dev_info(dev, "Deprecated\n"); - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - if (enable) - val |= PCI_DEV_CTRL_EXT_TAG_MASK; - else - val &= ~PCI_DEV_CTRL_EXT_TAG_MASK; - pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, val); - pci_cfg_access_unlock(pci_dev); - - return count; + return 0; } static ssize_t @@ -152,10 +106,9 @@ show_max_read_request_size(struct device *dev, struct device_attribute *attr, char *buf) { - struct pci_dev *pci_dev = to_pci_dev(dev); - int val = pcie_get_readrq(pci_dev); + dev_info(dev, "Deprecated\n"); - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val); + return 0; } static ssize_t @@ -164,18 +117,9 @@ store_max_read_request_size(struct device *dev, const char *buf, size_t count) { - struct pci_dev *pci_dev = to_pci_dev(dev); - unsigned long size = 0; - int ret; + dev_info(dev, "Deprecated\n"); - if (0 != kstrtoul(buf, 0, &size)) - return -EINVAL; - - ret = pcie_set_readrq(pci_dev, (int)size); - if (ret < 0) - return ret; - - return count; + return 0; } #endif -- 2.7.0 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 0/3] enable extended tag for i40e 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon ` (2 preceding siblings ...) 2016-03-08 18:38 ` [PATCH v3 3/3] igb_uio: deprecate " Thomas Monjalon @ 2016-03-08 18:41 ` Thomas Monjalon 2016-03-09 0:48 ` Zhang, Helin 3 siblings, 1 reply; 32+ messages in thread From: Thomas Monjalon @ 2016-03-08 18:41 UTC (permalink / raw) To: helin.zhang; +Cc: dev 2016-03-08 19:38, Thomas Monjalon: > It enables 'extended tag' for i40e devices only during its port > initialization, which is key for 40G performance. It also deprecates > the similar in igb_uio, and eal lib. > > v3: > - fix build with deprecated attribute > - keep deprecated attribute > - reword release notes a bit > - revert doc move from v2 > - better split the patches I've forgot the Acked-by: Jingjing Wu <jingjing.wu@intel.com> Helin, if you agree with this new revision, I'll apply it. ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 0/3] enable extended tag for i40e 2016-03-08 18:41 ` [PATCH v3 0/3] enable extended tag for i40e Thomas Monjalon @ 2016-03-09 0:48 ` Zhang, Helin 2016-03-09 0:50 ` Thomas Monjalon 2016-03-09 0:52 ` Thomas Monjalon 0 siblings, 2 replies; 32+ messages in thread From: Zhang, Helin @ 2016-03-09 0:48 UTC (permalink / raw) To: Thomas Monjalon; +Cc: dev > -----Original Message----- > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > Sent: Wednesday, March 9, 2016 2:41 AM > To: Zhang, Helin <helin.zhang@intel.com> > Cc: dev@dpdk.org > Subject: Re: [PATCH v3 0/3] enable extended tag for i40e > > 2016-03-08 19:38, Thomas Monjalon: > > It enables 'extended tag' for i40e devices only during its port > > initialization, which is key for 40G performance. It also deprecates > > the similar in igb_uio, and eal lib. > > > > v3: > > - fix build with deprecated attribute > > - keep deprecated attribute > > - reword release notes a bit > > - revert doc move from v2 > > - better split the patches > > I've forgot the Acked-by: Jingjing Wu <jingjing.wu@intel.com> > > Helin, if you agree with this new revision, I'll apply it. Thomas Yes, that's what I expected to be applied. Please apply it, thank you very much! Regards, Helin ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 0/3] enable extended tag for i40e 2016-03-09 0:48 ` Zhang, Helin @ 2016-03-09 0:50 ` Thomas Monjalon 2016-03-09 0:52 ` Thomas Monjalon 1 sibling, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-09 0:50 UTC (permalink / raw) To: Zhang, Helin; +Cc: dev 2016-03-09 00:48, Zhang, Helin: > > > -----Original Message----- > > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > > Sent: Wednesday, March 9, 2016 2:41 AM > > To: Zhang, Helin <helin.zhang@intel.com> > > Cc: dev@dpdk.org > > Subject: Re: [PATCH v3 0/3] enable extended tag for i40e > > > > 2016-03-08 19:38, Thomas Monjalon: > > > It enables 'extended tag' for i40e devices only during its port > > > initialization, which is key for 40G performance. It also deprecates > > > the similar in igb_uio, and eal lib. > > > > > > v3: > > > - fix build with deprecated attribute > > > - keep deprecated attribute > > > - reword release notes a bit > > > - revert doc move from v2 > > > - better split the patches > > > > I've forgot the Acked-by: Jingjing Wu <jingjing.wu@intel.com> > > > > Helin, if you agree with this new revision, I'll apply it. > > Thomas > > Yes, that's what I expected to be applied. Please apply it, thank you very much! Note that reworking these patches was an investment for future, to show how better split patches ;) ^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 0/3] enable extended tag for i40e 2016-03-09 0:48 ` Zhang, Helin 2016-03-09 0:50 ` Thomas Monjalon @ 2016-03-09 0:52 ` Thomas Monjalon 1 sibling, 0 replies; 32+ messages in thread From: Thomas Monjalon @ 2016-03-09 0:52 UTC (permalink / raw) To: Zhang, Helin; +Cc: dev 2016-03-09 00:48, Zhang, Helin: > > 2016-03-08 19:38, Thomas Monjalon: > > > It enables 'extended tag' for i40e devices only during its port > > > initialization, which is key for 40G performance. It also deprecates > > > the similar in igb_uio, and eal lib. > > > > > > v3: > > > - fix build with deprecated attribute > > > - keep deprecated attribute > > > - reword release notes a bit > > > - revert doc move from v2 > > > - better split the patches > > > > I've forgot the Acked-by: Jingjing Wu <jingjing.wu@intel.com> > > > > Helin, if you agree with this new revision, I'll apply it. > > Thomas > > Yes, that's what I expected to be applied. Please apply it, thank you very much! Applied, thanks ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 3/3] igb_uio: remove sys files for setting pci config space 2015-12-21 2:38 [PATCH 0/3] i40e: enable extended tag Helin Zhang 2015-12-21 2:38 ` [PATCH 1/3] " Helin Zhang 2015-12-21 2:38 ` [PATCH 2/3] eal: remove pci config of " Helin Zhang @ 2015-12-21 2:38 ` Helin Zhang 2015-12-21 18:57 ` Stephen Hemminger 2016-02-22 6:31 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 3 siblings, 1 reply; 32+ messages in thread From: Helin Zhang @ 2015-12-21 2:38 UTC (permalink / raw) To: dev Sys files of 'extended_tag' and 'max_read_request_size' are useless, as nobody will use them for setting pci config space. Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- doc/guides/linux_gsg/enable_func.rst | 22 ------ doc/guides/rel_notes/deprecation.rst | 3 + doc/guides/rel_notes/release_2_3.rst | 6 ++ lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 108 ------------------------------ 4 files changed, 9 insertions(+), 130 deletions(-) diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst index c3fa6d3..ec0e04d 100644 --- a/doc/guides/linux_gsg/enable_func.rst +++ b/doc/guides/linux_gsg/enable_func.rst @@ -186,28 +186,6 @@ Check with the local Intel's Network Division application engineers for firmware The base driver to support firmware version of FVL3E will be integrated in the next DPDK release, so currently the validated firmware version is 4.2.6. -Enabling Extended Tag and Setting Max Read Request Size -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -PCI configurations of ``extended_tag`` and max _read_requ st_size have big impacts on performance of small packets on 40G NIC. -Enabling extended_tag and setting ``max_read_request_size`` to small size such as 128 bytes provide great helps to high performance of small packets. - -* These can be done in some BIOS implementations. - -* For other BIOS implementations, PCI configurations can be changed by using command of ``setpci``, or special configurations in DPDK config file of ``common_linux``. - - * Bits 7:5 at address of 0xA8 of each PCI device is used for setting the max_read_request_size, - and bit 8 of 0xA8 of each PCI device is used for enabling/disabling the extended_tag. - lspci and setpci can be used to read the values of 0xA8 and then write it back after being changed. - - * In config file of common_linux, below three configurations can be changed for the same purpose. - - ``CONFIG_RTE_PCI_CONFIG`` - - ``CONFIG_RTE_PCI_EXTENDED_TAG`` - - ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` - Use 16 Bytes RX Descriptor Size ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index e94d4a2..7438f80 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -49,3 +49,6 @@ Deprecation Notices commands (such as RETA update in testpmd). This should impact CMDLINE_PARSE_RESULT_BUFSIZE, STR_TOKEN_SIZE and RDLINE_BUF_SIZE. It should be integrated in release 2.3. + +* The eal function of pci_config_space_set is deprecated in release 2.3, and + will be removed from 2.4. diff --git a/doc/guides/rel_notes/release_2_3.rst b/doc/guides/rel_notes/release_2_3.rst index efd258b..ed10d94 100644 --- a/doc/guides/rel_notes/release_2_3.rst +++ b/doc/guides/rel_notes/release_2_3.rst @@ -16,6 +16,12 @@ Resolved Issues EAL ~~~ +* **eal/linux: removed sys files for pci config space.** + + Removed sys files of 'extended_tag' and 'max_read_request_size' and + their relavant operations, as they shouldn't be done in eal for all + possible devices. + Drivers ~~~~~~~ diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c index f5617d2..054d053 100644 --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c @@ -40,15 +40,6 @@ #include "compat.h" -#ifdef RTE_PCI_CONFIG -#define PCI_SYS_FILE_BUF_SIZE 10 -#define PCI_DEV_CAP_REG 0xA4 -#define PCI_DEV_CTRL_REG 0xA8 -#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 -#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 -#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) -#endif - /** * A structure describing the private information for a uio device. */ @@ -90,109 +81,10 @@ store_max_vfs(struct device *dev, struct device_attribute *attr, return err ? err : count; } -#ifdef RTE_PCI_CONFIG -static ssize_t -show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0; - - pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid"); - - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", - (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off"); -} - -static ssize_t -store_extended_tag(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0, enable; - - if (strncmp(buf, "on", 2) == 0) - enable = 1; - else if (strncmp(buf, "off", 3) == 0) - enable = 0; - else - return -EINVAL; - - pci_cfg_access_lock(pci_dev); - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */ - pci_cfg_access_unlock(pci_dev); - return -EPERM; - } - - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - if (enable) - val |= PCI_DEV_CTRL_EXT_TAG_MASK; - else - val &= ~PCI_DEV_CTRL_EXT_TAG_MASK; - pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, val); - pci_cfg_access_unlock(pci_dev); - - return count; -} - -static ssize_t -show_max_read_request_size(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct pci_dev *pci_dev = to_pci_dev(dev); - int val = pcie_get_readrq(pci_dev); - - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val); -} - -static ssize_t -store_max_read_request_size(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - struct pci_dev *pci_dev = to_pci_dev(dev); - unsigned long size = 0; - int ret; - - if (0 != kstrtoul(buf, 0, &size)) - return -EINVAL; - - ret = pcie_set_readrq(pci_dev, (int)size); - if (ret < 0) - return ret; - - return count; -} -#endif - static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs); -#ifdef RTE_PCI_CONFIG -static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag, - store_extended_tag); -static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR, - show_max_read_request_size, store_max_read_request_size); -#endif static struct attribute *dev_attrs[] = { &dev_attr_max_vfs.attr, -#ifdef RTE_PCI_CONFIG - &dev_attr_extended_tag.attr, - &dev_attr_max_read_request_size.attr, -#endif NULL, }; -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH 3/3] igb_uio: remove sys files for setting pci config space 2015-12-21 2:38 ` [PATCH 3/3] igb_uio: remove sys files for setting pci config space Helin Zhang @ 2015-12-21 18:57 ` Stephen Hemminger 0 siblings, 0 replies; 32+ messages in thread From: Stephen Hemminger @ 2015-12-21 18:57 UTC (permalink / raw) To: Helin Zhang; +Cc: dev On Mon, 21 Dec 2015 10:38:06 +0800 Helin Zhang <helin.zhang@intel.com> wrote: > Sys files of 'extended_tag' and 'max_read_request_size' are > useless, as nobody will use them for setting pci config space. > > Signed-off-by: Helin Zhang <helin.zhang@intel.com> > --- > doc/guides/linux_gsg/enable_func.rst | 22 ------ > doc/guides/rel_notes/deprecation.rst | 3 + > doc/guides/rel_notes/release_2_3.rst | 6 ++ > lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 108 ------------------------------ > 4 files changed, 9 insertions(+), 130 deletions(-) > > diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst > index c3fa6d3..ec0e04d 100644 > --- a/doc/guides/linux_gsg/enable_func.rst > +++ b/doc/guides/linux_gsg/enable_func.rst > @@ -186,28 +186,6 @@ Check with the local Intel's Network Division application engineers for firmware > The base driver to support firmware version of FVL3E will be integrated in the next > DPDK release, so currently the validated firmware version is 4.2.6. > > -Enabling Extended Tag and Setting Max Read Request Size > -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > - > -PCI configurations of ``extended_tag`` and max _read_requ st_size have big impacts on performance of small packets on 40G NIC. > -Enabling extended_tag and setting ``max_read_request_size`` to small size such as 128 bytes provide great helps to high performance of small packets. > - > -* These can be done in some BIOS implementations. > - > -* For other BIOS implementations, PCI configurations can be changed by using command of ``setpci``, or special configurations in DPDK config file of ``common_linux``. > - > - * Bits 7:5 at address of 0xA8 of each PCI device is used for setting the max_read_request_size, > - and bit 8 of 0xA8 of each PCI device is used for enabling/disabling the extended_tag. > - lspci and setpci can be used to read the values of 0xA8 and then write it back after being changed. > - > - * In config file of common_linux, below three configurations can be changed for the same purpose. > - > - ``CONFIG_RTE_PCI_CONFIG`` > - > - ``CONFIG_RTE_PCI_EXTENDED_TAG`` > - > - ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` > - > Use 16 Bytes RX Descriptor Size > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst > index e94d4a2..7438f80 100644 > --- a/doc/guides/rel_notes/deprecation.rst > +++ b/doc/guides/rel_notes/deprecation.rst > @@ -49,3 +49,6 @@ Deprecation Notices > commands (such as RETA update in testpmd). This should impact > CMDLINE_PARSE_RESULT_BUFSIZE, STR_TOKEN_SIZE and RDLINE_BUF_SIZE. > It should be integrated in release 2.3. > + > +* The eal function of pci_config_space_set is deprecated in release 2.3, and > + will be removed from 2.4. > diff --git a/doc/guides/rel_notes/release_2_3.rst b/doc/guides/rel_notes/release_2_3.rst > index efd258b..ed10d94 100644 > --- a/doc/guides/rel_notes/release_2_3.rst > +++ b/doc/guides/rel_notes/release_2_3.rst > @@ -16,6 +16,12 @@ Resolved Issues > EAL > ~~~ > > +* **eal/linux: removed sys files for pci config space.** > + > + Removed sys files of 'extended_tag' and 'max_read_request_size' and > + their relavant operations, as they shouldn't be done in eal for all > + possible devices. > + > > Drivers > ~~~~~~~ > diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > index f5617d2..054d053 100644 > --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > @@ -40,15 +40,6 @@ > > #include "compat.h" > > -#ifdef RTE_PCI_CONFIG > -#define PCI_SYS_FILE_BUF_SIZE 10 > -#define PCI_DEV_CAP_REG 0xA4 > -#define PCI_DEV_CTRL_REG 0xA8 > -#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 > -#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 > -#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) > -#endif > - > /** > * A structure describing the private information for a uio device. > */ > @@ -90,109 +81,10 @@ store_max_vfs(struct device *dev, struct device_attribute *attr, > return err ? err : count; > } > > -#ifdef RTE_PCI_CONFIG > -static ssize_t > -show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf) > -{ > - struct pci_dev *pci_dev = to_pci_dev(dev); > - uint32_t val = 0; > - > - pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val); > - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ > - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid"); > - > - val = 0; > - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, > - PCI_DEV_CTRL_REG, &val); > - > - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", > - (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off"); > -} > - > -static ssize_t > -store_extended_tag(struct device *dev, > - struct device_attribute *attr, > - const char *buf, > - size_t count) > -{ > - struct pci_dev *pci_dev = to_pci_dev(dev); > - uint32_t val = 0, enable; > - > - if (strncmp(buf, "on", 2) == 0) > - enable = 1; > - else if (strncmp(buf, "off", 3) == 0) > - enable = 0; > - else > - return -EINVAL; > - > - pci_cfg_access_lock(pci_dev); > - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, > - PCI_DEV_CAP_REG, &val); > - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */ > - pci_cfg_access_unlock(pci_dev); > - return -EPERM; > - } > - > - val = 0; > - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, > - PCI_DEV_CTRL_REG, &val); > - if (enable) > - val |= PCI_DEV_CTRL_EXT_TAG_MASK; > - else > - val &= ~PCI_DEV_CTRL_EXT_TAG_MASK; > - pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn, > - PCI_DEV_CTRL_REG, val); > - pci_cfg_access_unlock(pci_dev); > - > - return count; > -} > - > -static ssize_t > -show_max_read_request_size(struct device *dev, > - struct device_attribute *attr, > - char *buf) > -{ > - struct pci_dev *pci_dev = to_pci_dev(dev); > - int val = pcie_get_readrq(pci_dev); > - > - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val); > -} > - > -static ssize_t > -store_max_read_request_size(struct device *dev, > - struct device_attribute *attr, > - const char *buf, > - size_t count) > -{ > - struct pci_dev *pci_dev = to_pci_dev(dev); > - unsigned long size = 0; > - int ret; > - > - if (0 != kstrtoul(buf, 0, &size)) > - return -EINVAL; > - > - ret = pcie_set_readrq(pci_dev, (int)size); > - if (ret < 0) > - return ret; > - > - return count; > -} > -#endif > - > static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs); > -#ifdef RTE_PCI_CONFIG > -static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag, > - store_extended_tag); > -static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR, > - show_max_read_request_size, store_max_read_request_size); > -#endif > > static struct attribute *dev_attrs[] = { > &dev_attr_max_vfs.attr, > -#ifdef RTE_PCI_CONFIG > - &dev_attr_extended_tag.attr, > - &dev_attr_max_read_request_size.attr, > -#endif > NULL, > }; > Agreed, the current way was a mess and it is always possible to change pci settings easier with setpci anyway. Acked-by: Stephen Hemminger <stephen.hemminger@networkplumber.org> ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 0/3] enable extended tag for i40e 2015-12-21 2:38 [PATCH 0/3] i40e: enable extended tag Helin Zhang ` (2 preceding siblings ...) 2015-12-21 2:38 ` [PATCH 3/3] igb_uio: remove sys files for setting pci config space Helin Zhang @ 2016-02-22 6:31 ` Helin Zhang 2016-02-22 6:31 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang ` (2 more replies) 3 siblings, 3 replies; 32+ messages in thread From: Helin Zhang @ 2016-02-22 6:31 UTC (permalink / raw) To: dev It enables 'extended tag' for i40e devices only during its port initialization, which is key for 40G performance. It also deprecates the similar in igb_uio, and eal lib. v2: - Changed the type of return value of i40e_enable_extended_tag() to 'void'. - Fixed the compile warnings. - Kept the sys files as they were, and added ABI change announcement for them. - Moved high performance part of i40e from 'GSG' to a new for .nics'. Helin Zhang (3): i40e: enable extended tag eal: remove pci config of extended tag igb_uio: deprecate sys files config/common_linuxapp | 1 + doc/guides/linux_gsg/enable_func.rst | 47 ---------------- doc/guides/nics/i40e.rst | 76 ++++++++++++++++++++++++++ doc/guides/rel_notes/deprecation.rst | 6 +++ doc/guides/rel_notes/release_16_04.rst | 6 +++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++-- lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 2 + lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++---------------------------- lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 72 +++---------------------- 10 files changed, 167 insertions(+), 205 deletions(-) create mode 100644 doc/guides/nics/i40e.rst -- 1.9.3 ^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 1/3] i40e: enable extended tag 2016-02-22 6:31 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang @ 2016-02-22 6:31 ` Helin Zhang 2016-02-22 6:31 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang 2016-02-22 6:31 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang 2 siblings, 0 replies; 32+ messages in thread From: Helin Zhang @ 2016-02-22 6:31 UTC (permalink / raw) To: dev PCIe feature of 'Extended Tag' is important for 40G performance. It adds its enabling during each port initialization, to ensure the high performance. Signed-off-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> --- doc/guides/rel_notes/release_16_04.rst | 6 ++++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 3 deletions(-) v2: - Changed the type of return value of i40e_enable_extended_tag() to 'void'. diff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst index 5786f74..bed5779 100644 --- a/doc/guides/rel_notes/release_16_04.rst +++ b/doc/guides/rel_notes/release_16_04.rst @@ -46,6 +46,12 @@ This section should contain new features added in this release. Sample format: * **Added vhost-user live migration support.** +* **i40e: Enabled extended tag.** + + It enabled extended tag by checking and writing corresponding PCI config + space bytes, to boost the performance. In the meanwhile, it deprecated the + legacy way via reading/writing sysfile supported by kernel module of igb_uio. + Resolved Issues --------------- diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ef24122..7e68c61 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -273,6 +273,17 @@ #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL +/* PCI offset for querying capability */ +#define PCI_DEV_CAP_REG 0xA4 +/* PCI offset for enabling/disabling Extended Tag */ +#define PCI_DEV_CTRL_REG 0xA8 +/* Bit mask of Extended Tag capability */ +#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 +/* Bit shift of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 +/* Bit mask of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) + static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev); static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -386,7 +397,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info); static void i40e_configure_registers(struct i40e_hw *hw); -static void i40e_hw_init(struct i40e_hw *hw); +static void i40e_hw_init(struct rte_eth_dev *dev); static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); static int i40e_mirror_rule_set(struct rte_eth_dev *dev, struct rte_eth_mirror_conf *mirror_conf, @@ -765,7 +776,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) i40e_clear_hw(hw); /* Initialize the hardware */ - i40e_hw_init(hw); + i40e_hw_init(dev); /* Reset here to make sure all is clean for each PF */ ret = i40e_pf_reset(hw); @@ -7262,13 +7273,61 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, } /* + * Check and enable Extended Tag. + * Enabling Extended Tag is important for 40G performance. + */ +static void +i40e_enable_extended_tag(struct rte_eth_dev *dev) +{ + uint32_t buf = 0; + int ret; + + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CAP_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CAP_REG); + return; + } + if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { + PMD_DRV_LOG(ERR, "Does not support Extended Tag"); + return; + } + + buf = 0; + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } + if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { + PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); + return; + } + buf |= PCI_DEV_CTRL_EXT_TAG_MASK; + ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } +} + +/* * As some registers wouldn't be reset unless a global hardware reset, * hardware initialization is needed to put those registers into an * expected initial state. */ static void -i40e_hw_init(struct i40e_hw *hw) +i40e_hw_init(struct rte_eth_dev *dev) { + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + i40e_enable_extended_tag(dev); + /* clear the PF Queue Filter control register */ I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 2/3] eal: remove pci config of extended tag 2016-02-22 6:31 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2016-02-22 6:31 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang @ 2016-02-22 6:31 ` Helin Zhang 2016-02-22 6:31 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang 2 siblings, 0 replies; 32+ messages in thread From: Helin Zhang @ 2016-02-22 6:31 UTC (permalink / raw) To: dev Remove pci configuration of 'extended tag' and 'max read request size', as they are not required by all devices and it lets PMD to configure them if neccessary. In addition, 'pci_config_space_set()' is deprecated. Signed-off-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> --- config/common_linuxapp | 1 + lib/librte_eal/common/eal_common_pci.c | 7 --- lib/librte_eal/common/include/rte_pci.h | 4 +- lib/librte_eal/linuxapp/eal/eal_pci.c | 90 +++------------------------------ 4 files changed, 10 insertions(+), 92 deletions(-) v2: - Fixed the compile warnings. diff --git a/config/common_linuxapp b/config/common_linuxapp index f1638db..a74cbab 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -110,6 +110,7 @@ CONFIG_RTE_EAL_PMD_PATH="" # # Special configurations in PCI Config Space for high performance +# They are all deprecated, and will be removed later. # CONFIG_RTE_PCI_CONFIG=n CONFIG_RTE_PCI_EXTENDED_TAG="" diff --git a/lib/librte_eal/common/eal_common_pci.c b/lib/librte_eal/common/eal_common_pci.c index 96d5113..366fb46 100644 --- a/lib/librte_eal/common/eal_common_pci.c +++ b/lib/librte_eal/common/eal_common_pci.c @@ -180,13 +180,6 @@ rte_eal_pci_probe_one_driver(struct rte_pci_driver *dr, struct rte_pci_device *d } if (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) { -#ifdef RTE_PCI_CONFIG - /* - * Set PCIe config space for high performance. - * Return value can be ignored. - */ - pci_config_space_set(dev); -#endif /* map resources for devices that use igb_uio */ ret = rte_eal_pci_map_device(dev); if (ret != 0) diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 067e084..189d509 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -580,12 +580,14 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, #ifdef RTE_PCI_CONFIG /** * Set special config space registers for performance purpose. + * It is deprecated, as all configurations have been moved into + * each PMDs respectively. * * @param dev * A pointer to a rte_pci_device structure describing the device * to use */ -void pci_config_space_set(struct rte_pci_device *dev); +void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; #endif /* RTE_PCI_CONFIG */ #ifdef __cplusplus diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c b/lib/librte_eal/linuxapp/eal/eal_pci.c index 4346973..4c45452 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci.c @@ -482,92 +482,14 @@ error: } #ifdef RTE_PCI_CONFIG -static int -pci_config_extended_tag(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ]; - FILE *f; - - /* not configured, let it as is */ - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) != 0 && - strncmp(RTE_PCI_EXTENDED_TAG, "off", 3) != 0) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "extended_tag", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - if (strncmp(RTE_PCI_EXTENDED_TAG, "on", 2) == 0) { - /* enable Extended Tag*/ - if (strncmp(buf, "on", 2) != 0) { - fseek(f, 0, SEEK_SET); - fputs("on", f); - } - } else { - /* disable Extended Tag */ - if (strncmp(buf, "off", 3) != 0) { - fseek(f, 0, SEEK_SET); - fputs("off", f); - } - } - fclose(f); - - return 0; -} - -static int -pci_config_max_read_request_size(struct rte_pci_device *dev) -{ - struct rte_pci_addr *loc = &dev->addr; - char filename[PATH_MAX]; - char buf[BUFSIZ], param[BUFSIZ]; - FILE *f; - /* size can be 128, 256, 512, 1024, 2048, 4096 */ - uint32_t max_size = RTE_PCI_MAX_READ_REQUEST_SIZE; - - /* not configured, let it as is */ - if (!max_size) - return 0; - - snprintf(filename, sizeof(filename), - SYSFS_PCI_DEVICES "/" PCI_PRI_FMT "/" "max_read_request_size", - loc->domain, loc->bus, loc->devid, loc->function); - f = fopen(filename, "rw+"); - if (!f) - return -1; - - fgets(buf, sizeof(buf), f); - snprintf(param, sizeof(param), "%d", max_size); - - /* check if the size to be set is the same as current */ - if (strcmp(buf, param) == 0) { - fclose(f); - return 0; - } - fseek(f, 0, SEEK_SET); - fputs(param, f); - fclose(f); - - return 0; -} - +/* + * It is deprecated, all its configurations have been moved into + * each PMD respectively. + */ void -pci_config_space_set(struct rte_pci_device *dev) +pci_config_space_set(__rte_unused struct rte_pci_device *dev) { - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return; - - /* configure extended tag */ - pci_config_extended_tag(dev); - - /* configure max read request size */ - pci_config_max_read_request_size(dev); + RTE_LOG(DEBUG, EAL, "Nothing here, as it is deprecated\n"); } #endif -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 3/3] igb_uio: deprecate sys files 2016-02-22 6:31 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2016-02-22 6:31 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang 2016-02-22 6:31 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang @ 2016-02-22 6:31 ` Helin Zhang 2 siblings, 0 replies; 32+ messages in thread From: Helin Zhang @ 2016-02-22 6:31 UTC (permalink / raw) To: dev It deprecated sys files of 'extended_tag' and 'max_read_request_size', and announced the planned ABI changes of them. Signed-off-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> --- doc/guides/linux_gsg/enable_func.rst | 47 ------------------- doc/guides/nics/i40e.rst | 76 +++++++++++++++++++++++++++++++ doc/guides/rel_notes/deprecation.rst | 6 +++ lib/librte_eal/common/include/rte_pci.h | 2 +- lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 72 ++++------------------------- 5 files changed, 91 insertions(+), 112 deletions(-) create mode 100644 doc/guides/nics/i40e.rst v2: - Kept the sys files as they were, and added ABI change announcement for them. - Moved high performance part of i40e from 'GSG' to a new for .nics'. diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst index c3fa6d3..f59f25c 100644 --- a/doc/guides/linux_gsg/enable_func.rst +++ b/doc/guides/linux_gsg/enable_func.rst @@ -176,50 +176,3 @@ Also, if ``INTEL_IOMMU_DEFAULT_ON`` is not set in the kernel, the ``intel_iommu= This ensures that the Intel IOMMU is being initialized as expected. Please note that while using ``iommu=pt`` is compulsory for ``igb_uio driver``, the ``vfio-pci`` driver can actually work with both ``iommu=pt`` and ``iommu=on``. - -High Performance of Small Packets on 40G NIC --------------------------------------------- - -As there might be firmware fixes for performance enhancement in latest version -of firmware image, the firmware update might be needed for getting high performance. -Check with the local Intel's Network Division application engineers for firmware updates. -The base driver to support firmware version of FVL3E will be integrated in the next -DPDK release, so currently the validated firmware version is 4.2.6. - -Enabling Extended Tag and Setting Max Read Request Size -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -PCI configurations of ``extended_tag`` and max _read_requ st_size have big impacts on performance of small packets on 40G NIC. -Enabling extended_tag and setting ``max_read_request_size`` to small size such as 128 bytes provide great helps to high performance of small packets. - -* These can be done in some BIOS implementations. - -* For other BIOS implementations, PCI configurations can be changed by using command of ``setpci``, or special configurations in DPDK config file of ``common_linux``. - - * Bits 7:5 at address of 0xA8 of each PCI device is used for setting the max_read_request_size, - and bit 8 of 0xA8 of each PCI device is used for enabling/disabling the extended_tag. - lspci and setpci can be used to read the values of 0xA8 and then write it back after being changed. - - * In config file of common_linux, below three configurations can be changed for the same purpose. - - ``CONFIG_RTE_PCI_CONFIG`` - - ``CONFIG_RTE_PCI_EXTENDED_TAG`` - - ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` - -Use 16 Bytes RX Descriptor Size -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -As i40e PMD supports both 16 and 32 bytes RX descriptor sizes, and 16 bytes size can provide helps to high performance of small packets. -Configuration of ``CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC`` in config files can be changed to use 16 bytes size RX descriptors. - -High Performance and per Packet Latency Tradeoff -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Due to the hardware design, the interrupt signal inside NIC is needed for per -packet descriptor write-back. The minimum interval of interrupts could be set -at compile time by ``CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL`` in configuration files. -Though there is a default configuration, the interval could be tuned by the -users with that configuration item depends on what the user cares about more, -performance or per packet latency. diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst new file mode 100644 index 0000000..b6f089f --- /dev/null +++ b/doc/guides/nics/i40e.rst @@ -0,0 +1,76 @@ +.. BSD LICENSE + Copyright(c) 2010-2016 Intel Corporation. All rights reserved. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +I40E Poll Mode Driver +===================== + +The I40E PMD (**librte_pmd_i40e**) provides poll mode driver support +for **Intel X710/XL710/X722** 10/40 Gbps family of adapters. + +High performance of small packets +--------------------------------- + +As there might be firmware fixes or enhancements for performance in newer +version of firmware images, firmware update might be necessary for getting +high performance. In addition, host driver version is also important for +DPDK VF performance if kernel PF driver is being used. Check with the local +Intel Network Division application engineers for helps on firmware upgrade +and kernel driver upgrade. Release 16.04 will be validated with NVM 5.xx. + +Extended Tag +~~~~~~~~~~~~ + +PCI configuration of ``extended_tag`` has big impact on small packet size +performance of 40G ports. Enabling ``extended_tag`` can help 40G port to +achieve the best performance, especially for small packet size. + +- Disabling/enabling ``extended_tag`` can be done in some BIOS implementations. +- If BIOS does not enable it, and does not support changing it, tools + (e.g. ``setpci`` on Linux) can be used to enable or disable ``extended_tag``. +- From release 16.04, ``extended_tag`` is enabled by default during port + initialization, users don't need to care about that anymore. + +Use 16 bytes RX descriptor size +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +As i40e PMD supports both 16 and 32 bytes RX descriptor sizes, and 16 bytes +size may help a bit for high performance of small packet size. Configuration +of ``CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC`` in config files can be changed +to use 16 bytes size RX descriptors. + +High performance and per packet latency tradeoff +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to the hardware design, the interrupt signal inside NIC is needed for per +packet descriptor write-back. The minimum interval of interrupts could be set +at compile time by ``CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL`` in configuration +files. Though there is a default configuration, the interval could be tuned by +the users with that configuration item depends on what the user cares about +more, performance or per packet latency. diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index e94d4a2..b7e0a4f 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -49,3 +49,9 @@ Deprecation Notices commands (such as RETA update in testpmd). This should impact CMDLINE_PARSE_RESULT_BUFSIZE, STR_TOKEN_SIZE and RDLINE_BUF_SIZE. It should be integrated in release 2.3. + +* ABI changes are planned for release 16.07. The eal function of + pci_config_space_set is deprecated in release 16.04, and will be removed + from 16.07. Macros of CONFIG_RTE_PCI_CONFIG, CONFIG_RTE_PCI_EXTENDED_TAG and + CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE will be removed. sysfile of extended_tag + and max_read_request_size created by kernel module igb_uio will be removed. diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 189d509..e4fb82d 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -587,7 +587,7 @@ void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, * A pointer to a rte_pci_device structure describing the device * to use */ -void pci_config_space_set(struct rte_pci_device *dev) __rte_deprecated; +void pci_config_space_set(struct rte_pci_device *dev); #endif /* RTE_PCI_CONFIG */ #ifdef __cplusplus diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c index f5617d2..01b4ca6 100644 --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c @@ -40,15 +40,6 @@ #include "compat.h" -#ifdef RTE_PCI_CONFIG -#define PCI_SYS_FILE_BUF_SIZE 10 -#define PCI_DEV_CAP_REG 0xA4 -#define PCI_DEV_CTRL_REG 0xA8 -#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 -#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 -#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) -#endif - /** * A structure describing the private information for a uio device. */ @@ -94,19 +85,9 @@ store_max_vfs(struct device *dev, struct device_attribute *attr, static ssize_t show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf) { - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0; + dev_info(dev, "Deprecated\n"); - pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid"); - - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", - (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off"); + return 0; } static ssize_t @@ -115,36 +96,9 @@ store_extended_tag(struct device *dev, const char *buf, size_t count) { - struct pci_dev *pci_dev = to_pci_dev(dev); - uint32_t val = 0, enable; - - if (strncmp(buf, "on", 2) == 0) - enable = 1; - else if (strncmp(buf, "off", 3) == 0) - enable = 0; - else - return -EINVAL; - - pci_cfg_access_lock(pci_dev); - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CAP_REG, &val); - if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */ - pci_cfg_access_unlock(pci_dev); - return -EPERM; - } + dev_info(dev, "Deprecated\n"); - val = 0; - pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, &val); - if (enable) - val |= PCI_DEV_CTRL_EXT_TAG_MASK; - else - val &= ~PCI_DEV_CTRL_EXT_TAG_MASK; - pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn, - PCI_DEV_CTRL_REG, val); - pci_cfg_access_unlock(pci_dev); - - return count; + return 0; } static ssize_t @@ -152,10 +106,9 @@ show_max_read_request_size(struct device *dev, struct device_attribute *attr, char *buf) { - struct pci_dev *pci_dev = to_pci_dev(dev); - int val = pcie_get_readrq(pci_dev); + dev_info(dev, "Deprecated\n"); - return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val); + return 0; } static ssize_t @@ -164,18 +117,9 @@ store_max_read_request_size(struct device *dev, const char *buf, size_t count) { - struct pci_dev *pci_dev = to_pci_dev(dev); - unsigned long size = 0; - int ret; + dev_info(dev, "Deprecated\n"); - if (0 != kstrtoul(buf, 0, &size)) - return -EINVAL; - - ret = pcie_set_readrq(pci_dev, (int)size); - if (ret < 0) - return ret; - - return count; + return 0; } #endif -- 1.9.3 ^ permalink raw reply related [flat|nested] 32+ messages in thread
end of thread, other threads:[~2016-03-09 0:54 UTC | newest] Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-12-21 2:38 [PATCH 0/3] i40e: enable extended tag Helin Zhang 2015-12-21 2:38 ` [PATCH 1/3] " Helin Zhang 2016-01-22 1:34 ` Wu, Jingjing 2016-01-22 10:26 ` Thomas Monjalon 2016-01-24 3:25 ` Zhang, Helin 2016-01-25 9:16 ` Thomas Monjalon 2016-01-26 0:29 ` Zhang, Helin 2015-12-21 2:38 ` [PATCH 2/3] eal: remove pci config of " Helin Zhang 2016-02-22 3:59 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2016-02-22 3:59 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang 2016-02-23 10:44 ` Bruce Richardson 2016-02-24 0:39 ` Zhang, Helin 2016-02-22 3:59 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang 2016-03-08 17:05 ` Thomas Monjalon 2016-02-22 3:59 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang 2016-03-08 17:48 ` Thomas Monjalon 2016-03-08 18:02 ` Thomas Monjalon 2016-02-22 5:52 ` [PATCH v2 0/3] enable extended tag for i40e Wu, Jingjing 2016-03-08 18:38 ` [PATCH v3 " Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 1/3] i40e: enable extended tag Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 2/3] pci: remove config of " Thomas Monjalon 2016-03-08 18:38 ` [PATCH v3 3/3] igb_uio: deprecate " Thomas Monjalon 2016-03-08 18:41 ` [PATCH v3 0/3] enable extended tag for i40e Thomas Monjalon 2016-03-09 0:48 ` Zhang, Helin 2016-03-09 0:50 ` Thomas Monjalon 2016-03-09 0:52 ` Thomas Monjalon 2015-12-21 2:38 ` [PATCH 3/3] igb_uio: remove sys files for setting pci config space Helin Zhang 2015-12-21 18:57 ` Stephen Hemminger 2016-02-22 6:31 ` [PATCH v2 0/3] enable extended tag for i40e Helin Zhang 2016-02-22 6:31 ` [PATCH v2 1/3] i40e: enable extended tag Helin Zhang 2016-02-22 6:31 ` [PATCH v2 2/3] eal: remove pci config of " Helin Zhang 2016-02-22 6:31 ` [PATCH v2 3/3] igb_uio: deprecate sys files Helin Zhang
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