From: <tthayer@opensource.altera.com>
To: <bp@alien8.de>, <dougthompson@xmission.com>,
<m.chehab@samsung.com>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<linux@arm.linux.org.uk>, <dinguyen@opensource.altera.com>,
<grant.likely@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <tthayer.linux@gmail.com>,
<tthayer@opensource.altera.com>
Subject: [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry
Date: Tue, 1 Mar 2016 10:38:21 -0600 [thread overview]
Message-ID: <1456850301-22066-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1456850301-22066-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index cce9e50..e83e973 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -599,6 +599,20 @@
reg = <0xffe00000 0x40000>;
};
+ eccmgr: eccmgr@ffd06090 {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc@ffd06000 {
+ compatible = "altr,socfpga-a10-l2-ecc";
+ reg = <0xffd06010 0x4>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: <tthayer@opensource.altera.com>
To: bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com,
tthayer@opensource.altera.com
Subject: [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry
Date: Tue, 1 Mar 2016 10:38:21 -0600 [thread overview]
Message-ID: <1456850301-22066-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1456850301-22066-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index cce9e50..e83e973 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -599,6 +599,20 @@
reg = <0xffe00000 0x40000>;
};
+ eccmgr: eccmgr@ffd06090 {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc@ffd06000 {
+ compatible = "altr,socfpga-a10-l2-ecc";
+ reg = <0xffd06010 0x4>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: tthayer@opensource.altera.com (tthayer at opensource.altera.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry
Date: Tue, 1 Mar 2016 10:38:21 -0600 [thread overview]
Message-ID: <1456850301-22066-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1456850301-22066-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index cce9e50..e83e973 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -599,6 +599,20 @@
reg = <0xffe00000 0x40000>;
};
+ eccmgr: eccmgr at ffd06090 {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc at ffd06000 {
+ compatible = "altr,socfpga-a10-l2-ecc";
+ reg = <0xffd06010 0x4>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
rst: rstmgr at ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
--
1.7.9.5
next prev parent reply other threads:[~2016-03-01 16:35 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 16:38 [PATCH 1/5] EDAC: Altera L2 Kconfig change from select to depends upon tthayer
2016-03-01 16:38 ` tthayer at opensource.altera.com
2016-03-01 16:38 ` tthayer
2016-03-01 16:38 ` [PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding tthayer
2016-03-01 16:38 ` tthayer at opensource.altera.com
2016-03-01 16:38 ` tthayer
2016-03-05 4:26 ` Rob Herring
2016-03-05 4:26 ` Rob Herring
2016-03-01 16:38 ` [PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer
2016-03-01 16:38 ` tthayer at opensource.altera.com
2016-03-01 16:38 ` tthayer
2016-03-04 10:38 ` Borislav Petkov
2016-03-04 10:38 ` Borislav Petkov
2016-03-04 15:42 ` Thor Thayer
2016-03-04 15:42 ` Thor Thayer
2016-03-04 15:42 ` Thor Thayer
2016-03-01 16:38 ` [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer
2016-03-01 16:38 ` tthayer at opensource.altera.com
2016-03-01 16:38 ` tthayer
2016-03-05 6:36 ` Dinh Nguyen
2016-03-05 6:36 ` Dinh Nguyen
2016-03-05 6:36 ` Dinh Nguyen
2016-03-01 16:38 ` tthayer [this message]
2016-03-01 16:38 ` [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry tthayer at opensource.altera.com
2016-03-01 16:38 ` tthayer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1456850301-22066-5-git-send-email-tthayer@opensource.altera.com \
--to=tthayer@opensource.altera.com \
--cc=bp@alien8.de \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@opensource.altera.com \
--cc=dougthompson@xmission.com \
--cc=galak@codeaurora.org \
--cc=grant.likely@linaro.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=m.chehab@samsung.com \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=tthayer.linux@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.