* [PATCH 0/7] drm/i915: Move some load time init steps earlier
@ 2016-03-09 15:31 Imre Deak
2016-03-09 15:31 ` [PATCH 1/7] drm/i915: Add comments marking the start of load time init phases Imre Deak
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
While working on the CDCLK init code I realized that the driver load time
dependencies between the different init steps are rather difficult to follow
and so it's not obvious where some new piece of initialization needs to be
added.
Also because some things are initialized too late, other steps depending on
these must be initialized in a non-logical place or even split into multiple
parts. One example is the CDCLK initialization which needs the display
callbacks to be set already, but those callbacks are setup only late, so the
CDCLK initialization must be done in two parts.
As a generic solution, I suggest that we define the following load
time init phases:
- state init not requiring device access
(i.e SW only, like initializing locks, allocating system memory, setting
up callbacks, device attributes)
- minimal HW setup to enable MMIO access to the device
- state init requiring device access w/o side effects
(i.e. read-only HW access, no interface registrations)
- state init causing device-wide side effects
(i.e any HW access, no interface registration)
- registering all interfaces
This patchset adds the corresponding comment markers for the first
two phases above and one common phase for the rest of the current
init steps. Later we could also add the last three init phases above
and restructure the code accordingly.
For now I only moved earlier a few obvious init steps that fit these
new phases.
I smoke tested this on GEN4, SNB, BXT.
Imre Deak (7):
drm/i915: Add comments marking the start of load time init phases
drm/i915: Move laod time PCH detect, DPIO, power domain SW init
earlier
drm/i915: Move load time IRQ SW init earlier
drm/i915: Move load time display/audio callback init earlier
drm/i915: Move load time clock gating callback init earlier
drm/i915: Move load time runtime device info init earlier
drm/i915: Move load time runtime PM get later
drivers/gpu/drm/i915/i915_dma.c | 33 ++++++++++------
drivers/gpu/drm/i915/i915_irq.c | 2 -
drivers/gpu/drm/i915/intel_audio.c | 12 +++---
drivers/gpu/drm/i915/intel_display.c | 77 ++++++++++++++++--------------------
drivers/gpu/drm/i915/intel_drv.h | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 65 +++++++++++++++---------------
6 files changed, 95 insertions(+), 98 deletions(-)
--
2.5.0
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/7] drm/i915: Add comments marking the start of load time init phases
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 15:31 ` [PATCH 2/7] drm/i915: Move laod time PCH detect, DPIO, power domain SW init earlier Imre Deak
` (7 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
To make it easier to get init time dependencies right during driver
loading, define the following init phases:
- state init not requiring device access
- minimal HW setup to enable MMIO access to the device
- state init requiring device access
In the future the 3rd phase could be fine-grained further for example:
- state init requiring device access w/o side effects
(i.e. read-only HW access, no interface registrations)
- state init causing device side effects
(i.e any HW access, no interface registration)
- registering all interfaces
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4aa3db6..d3dc4d4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -991,6 +991,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
int ret = 0;
uint32_t aperture_size;
+ /* Init phase: setup state not requiring accessing the device. */
info = (struct intel_device_info *) flags;
dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
@@ -1036,6 +1037,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
DRM_INFO("This is an early pre-production Haswell machine. "
"It may not be fully functional.\n");
+ /* Init phase: setup device MMIO */
if (i915_get_bridge_dev(dev)) {
ret = -EIO;
goto out_runtime_pm_put;
@@ -1050,6 +1052,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_uncore_init(dev);
+ /* Init phase: setup state requiring accessing the device. */
ret = i915_gem_gtt_init(dev);
if (ret)
goto out_uncore_fini;
--
2.5.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/7] drm/i915: Move laod time PCH detect, DPIO, power domain SW init earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
2016-03-09 15:31 ` [PATCH 1/7] drm/i915: Add comments marking the start of load time init phases Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 15:31 ` [PATCH 3/7] drm/i915: Move load time IRQ " Imre Deak
` (6 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
These are all SW only init steps, so we can move them earlier.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d3dc4d4..9269f1c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1021,7 +1021,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (ret < 0)
goto out_free_priv;
+ /* This must be called before any calls to HAS_PCH_* */
+ intel_detect_pch(dev);
+
intel_pm_setup(dev);
+ intel_init_dpio(dev_priv);
+ intel_power_domains_init(dev_priv);
intel_runtime_pm_get(dev_priv);
@@ -1047,9 +1052,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (ret < 0)
goto put_bridge;
- /* This must be called before any calls to HAS_PCH_* */
- intel_detect_pch(dev);
-
intel_uncore_init(dev);
/* Init phase: setup state requiring accessing the device. */
@@ -1127,16 +1129,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_device_info_runtime_init(dev);
- intel_init_dpio(dev_priv);
-
if (INTEL_INFO(dev)->num_pipes) {
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
goto out_gem_unload;
}
- intel_power_domains_init(dev_priv);
-
ret = i915_load_modeset_init(dev);
if (ret < 0) {
DRM_ERROR("failed to init modeset\n");
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/7] drm/i915: Move load time IRQ SW init earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
2016-03-09 15:31 ` [PATCH 1/7] drm/i915: Add comments marking the start of load time init phases Imre Deak
2016-03-09 15:31 ` [PATCH 2/7] drm/i915: Move laod time PCH detect, DPIO, power domain SW init earlier Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 15:31 ` [PATCH 4/7] drm/i915: Move load time display/audio callback " Imre Deak
` (5 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
Most of the IRQ init is setting up callbacks so move that part earlier.
Leave the pm_qos_add_request() call in place.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 5 ++++-
drivers/gpu/drm/i915/i915_irq.c | 2 --
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9269f1c..9b3ed00 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1027,6 +1027,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_pm_setup(dev);
intel_init_dpio(dev_priv);
intel_power_domains_init(dev_priv);
+ intel_irq_init(dev_priv);
intel_runtime_pm_get(dev_priv);
@@ -1103,7 +1104,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
aperture_size);
- intel_irq_init(dev_priv);
+ pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
+ PM_QOS_DEFAULT_VALUE);
+
intel_uncore_sanitize(dev);
intel_opregion_setup(dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 53e5104..8c7f730 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4564,8 +4564,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
i915_hangcheck_elapsed);
- pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
-
if (IS_GEN2(dev_priv)) {
dev->max_vblank_count = 0;
dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
--
2.5.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
` (2 preceding siblings ...)
2016-03-09 15:31 ` [PATCH 3/7] drm/i915: Move load time IRQ " Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 17:14 ` kbuild test robot
` (2 more replies)
2016-03-09 15:31 ` [PATCH 5/7] drm/i915: Move load time clock gating " Imre Deak
` (4 subsequent siblings)
8 siblings, 3 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
All of this is SW only initialization so we can move them earlier. Move
the mutex init where the rest of the locks are inited. While at it also
convert dev to dev_priv.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 3 ++
drivers/gpu/drm/i915/intel_audio.c | 12 +++---
drivers/gpu/drm/i915/intel_display.c | 77 ++++++++++++++++--------------------
drivers/gpu/drm/i915/intel_drv.h | 3 +-
4 files changed, 45 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9b3ed00..55b0c62 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1016,6 +1016,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
mutex_init(&dev_priv->modeset_restore_lock);
mutex_init(&dev_priv->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
+ mutex_init(&dev_priv->pps_mutex);
ret = i915_workqueues_init(dev_priv);
if (ret < 0)
@@ -1028,6 +1029,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_init_dpio(dev_priv);
intel_power_domains_init(dev_priv);
intel_irq_init(dev_priv);
+ intel_init_display_callbacks(dev_priv);
+ intel_init_audio_callbacks(dev_priv);
intel_runtime_pm_get(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 30f9214..1936752 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -567,20 +567,18 @@ void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
* intel_init_audio - Set up chip specific audio functions
* @dev: drm device
*/
-void intel_init_audio(struct drm_device *dev)
+void intel_init_audio_callbacks(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- if (IS_G4X(dev)) {
+ if (IS_G4X(dev_priv)) {
dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
- } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
+ } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..5170718 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15095,22 +15095,20 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
};
/* Set up chip specific display functions */
-static void intel_init_display(struct drm_device *dev)
+void intel_init_display_callbacks(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
+ if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
dev_priv->display.find_dpll = g4x_find_best_dpll;
- else if (IS_CHERRYVIEW(dev))
+ else if (IS_CHERRYVIEW(dev_priv))
dev_priv->display.find_dpll = chv_find_best_dpll;
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv))
dev_priv->display.find_dpll = vlv_find_best_dpll;
- else if (IS_PINEVIEW(dev))
+ else if (IS_PINEVIEW(dev_priv))
dev_priv->display.find_dpll = pnv_find_best_dpll;
else
dev_priv->display.find_dpll = i9xx_find_best_dpll;
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_INFO(dev_priv)->gen >= 9) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
skylake_get_initial_plane_config;
@@ -15118,7 +15116,7 @@ static void intel_init_display(struct drm_device *dev)
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
dev_priv->display.crtc_disable = haswell_crtc_disable;
- } else if (HAS_DDI(dev)) {
+ } else if (HAS_DDI(dev_priv)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
ironlake_get_initial_plane_config;
@@ -15126,7 +15124,7 @@ static void intel_init_display(struct drm_device *dev)
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
dev_priv->display.crtc_disable = haswell_crtc_disable;
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_initial_plane_config =
ironlake_get_initial_plane_config;
@@ -15134,7 +15132,7 @@ static void intel_init_display(struct drm_device *dev)
ironlake_crtc_compute_clock;
dev_priv->display.crtc_enable = ironlake_crtc_enable;
dev_priv->display.crtc_disable = ironlake_crtc_disable;
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
dev_priv->display.get_initial_plane_config =
i9xx_get_initial_plane_config;
@@ -15151,89 +15149,89 @@ static void intel_init_display(struct drm_device *dev)
}
/* Returns the core display clock speed */
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dev_priv->display.get_display_clock_speed =
skylake_get_display_clock_speed;
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
dev_priv->display.get_display_clock_speed =
broxton_get_display_clock_speed;
- else if (IS_BROADWELL(dev))
+ else if (IS_BROADWELL(dev_priv))
dev_priv->display.get_display_clock_speed =
broadwell_get_display_clock_speed;
- else if (IS_HASWELL(dev))
+ else if (IS_HASWELL(dev_priv))
dev_priv->display.get_display_clock_speed =
haswell_get_display_clock_speed;
- else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->display.get_display_clock_speed =
valleyview_get_display_clock_speed;
- else if (IS_GEN5(dev))
+ else if (IS_GEN5(dev_priv))
dev_priv->display.get_display_clock_speed =
ilk_get_display_clock_speed;
- else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
- IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+ else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
+ IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
dev_priv->display.get_display_clock_speed =
i945_get_display_clock_speed;
- else if (IS_GM45(dev))
+ else if (IS_GM45(dev_priv))
dev_priv->display.get_display_clock_speed =
gm45_get_display_clock_speed;
- else if (IS_CRESTLINE(dev))
+ else if (IS_CRESTLINE(dev_priv))
dev_priv->display.get_display_clock_speed =
i965gm_get_display_clock_speed;
- else if (IS_PINEVIEW(dev))
+ else if (IS_PINEVIEW(dev_priv))
dev_priv->display.get_display_clock_speed =
pnv_get_display_clock_speed;
- else if (IS_G33(dev) || IS_G4X(dev))
+ else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
dev_priv->display.get_display_clock_speed =
g33_get_display_clock_speed;
- else if (IS_I915G(dev))
+ else if (IS_I915G(dev_priv))
dev_priv->display.get_display_clock_speed =
i915_get_display_clock_speed;
- else if (IS_I945GM(dev) || IS_845G(dev))
+ else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
dev_priv->display.get_display_clock_speed =
i9xx_misc_get_display_clock_speed;
- else if (IS_I915GM(dev))
+ else if (IS_I915GM(dev_priv))
dev_priv->display.get_display_clock_speed =
i915gm_get_display_clock_speed;
- else if (IS_I865G(dev))
+ else if (IS_I865G(dev_priv))
dev_priv->display.get_display_clock_speed =
i865_get_display_clock_speed;
- else if (IS_I85X(dev))
+ else if (IS_I85X(dev_priv))
dev_priv->display.get_display_clock_speed =
i85x_get_display_clock_speed;
else { /* 830 */
- WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
+ WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
dev_priv->display.get_display_clock_speed =
i830_get_display_clock_speed;
}
- if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev_priv)) {
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
- } else if (IS_GEN6(dev)) {
+ } else if (IS_GEN6(dev_priv)) {
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
- } else if (IS_IVYBRIDGE(dev)) {
+ } else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
- } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
dev_priv->display.fdi_link_train = hsw_fdi_link_train;
- if (IS_BROADWELL(dev)) {
+ if (IS_BROADWELL(dev_priv)) {
dev_priv->display.modeset_commit_cdclk =
broadwell_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broadwell_modeset_calc_cdclk;
}
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.modeset_commit_cdclk =
valleyview_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
valleyview_modeset_calc_cdclk;
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
dev_priv->display.modeset_commit_cdclk =
broxton_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
broxton_modeset_calc_cdclk;
}
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev_priv)->gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
break;
@@ -15260,8 +15258,6 @@ static void intel_init_display(struct drm_device *dev)
/* Default just returns -ENODEV to indicate unsupported */
dev_priv->display.queue_flip = intel_default_queue_flip;
}
-
- mutex_init(&dev_priv->pps_mutex);
}
/*
@@ -15588,9 +15584,6 @@ void intel_modeset_init(struct drm_device *dev)
}
}
- intel_init_display(dev);
- intel_init_audio(dev);
-
if (IS_GEN2(dev)) {
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b2d66d..5264901 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1110,7 +1110,7 @@ u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
uint64_t fb_modifier, uint32_t pixel_format);
/* intel_audio.c */
-void intel_init_audio(struct drm_device *dev);
+void intel_init_audio_callbacks(struct drm_i915_private *dev_priv);
void intel_audio_codec_enable(struct intel_encoder *encoder);
void intel_audio_codec_disable(struct intel_encoder *encoder);
void i915_audio_component_init(struct drm_i915_private *dev_priv);
@@ -1118,6 +1118,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
/* intel_display.c */
extern const struct drm_plane_funcs intel_plane_funcs;
+void intel_init_display_callbacks(struct drm_i915_private *dev_priv);
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
bool intel_has_pending_fb_unpin(struct drm_device *dev);
void intel_mark_busy(struct drm_device *dev);
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
` (3 preceding siblings ...)
2016-03-09 15:31 ` [PATCH 4/7] drm/i915: Move load time display/audio callback " Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 15:57 ` Chris Wilson
2016-03-09 15:31 ` [PATCH 6/7] drm/i915: Move load time runtime device info " Imre Deak
` (3 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
Split out the part initing the clock gating callbacks and move it
earlier.
The rest of the callbacks in intel_init_pm() should be inited in the
same way, but atm some of the callbacks are set only conditionally, so
before doing this we need to make the setup unconditional and use
instead some flags.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 65 ++++++++++++++++++++--------------------
3 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 55b0c62..8cbe9ef 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1030,6 +1030,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_power_domains_init(dev_priv);
intel_irq_init(dev_priv);
intel_init_display_callbacks(dev_priv);
+ intel_init_clock_gating_callbacks(dev_priv);
intel_init_audio_callbacks(dev_priv);
intel_runtime_pm_get(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5264901..d3d31cc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1596,6 +1596,7 @@ void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_device *dev);
void intel_update_watermarks(struct drm_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
+void intel_init_clock_gating_callbacks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d7aef17..02d3598 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7107,6 +7107,38 @@ void intel_suspend_hw(struct drm_device *dev)
lpt_suspend_hw(dev);
}
+void intel_init_clock_gating_callbacks(struct drm_i915_private *dev_priv)
+{
+ if (IS_BROXTON(dev_priv))
+ dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ else if (IS_BROADWELL(dev_priv))
+ dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
+ else if (IS_CHERRYVIEW(dev_priv))
+ dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
+ else if (IS_HASWELL(dev_priv))
+ dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+ else if (IS_IVYBRIDGE(dev_priv))
+ dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+ else if (IS_VALLEYVIEW(dev_priv))
+ dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
+ else if (IS_GEN6(dev_priv))
+ dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+ else if (IS_GEN5(dev_priv))
+ dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
+ else if (IS_G4X(dev_priv))
+ dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ else if (IS_CRESTLINE(dev_priv))
+ dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+ else if (IS_BROADWATER(dev_priv))
+ dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+ else if (IS_GEN3(dev_priv))
+ dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
+ dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ else if (IS_GEN2(dev_priv))
+ dev_priv->display.init_clock_gating = i830_init_clock_gating;
+}
+
/* Set up chip specific power management-related functions */
void intel_init_pm(struct drm_device *dev)
{
@@ -7123,10 +7155,6 @@ void intel_init_pm(struct drm_device *dev)
/* For FIFO watermark updates */
if (INTEL_INFO(dev)->gen >= 9) {
skl_setup_wm_latency(dev);
-
- if (IS_BROXTON(dev))
- dev_priv->display.init_clock_gating =
- bxt_init_clock_gating;
dev_priv->display.update_wm = skl_update_wm;
} else if (HAS_PCH_SPLIT(dev)) {
ilk_setup_wm_latency(dev);
@@ -7146,29 +7174,12 @@ void intel_init_pm(struct drm_device *dev)
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
}
-
- if (IS_GEN5(dev))
- dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
- else if (IS_GEN6(dev))
- dev_priv->display.init_clock_gating = gen6_init_clock_gating;
- else if (IS_IVYBRIDGE(dev))
- dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
- else if (IS_HASWELL(dev))
- dev_priv->display.init_clock_gating = haswell_init_clock_gating;
- else if (INTEL_INFO(dev)->gen == 8)
- dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
} else if (IS_CHERRYVIEW(dev)) {
vlv_setup_wm_latency(dev);
-
dev_priv->display.update_wm = vlv_update_wm;
- dev_priv->display.init_clock_gating =
- cherryview_init_clock_gating;
} else if (IS_VALLEYVIEW(dev)) {
vlv_setup_wm_latency(dev);
-
dev_priv->display.update_wm = vlv_update_wm;
- dev_priv->display.init_clock_gating =
- valleyview_init_clock_gating;
} else if (IS_PINEVIEW(dev)) {
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
dev_priv->is_ddr3,
@@ -7184,20 +7195,13 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pineview_update_wm;
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
} else if (IS_G4X(dev)) {
dev_priv->display.update_wm = g4x_update_wm;
- dev_priv->display.init_clock_gating = g4x_init_clock_gating;
} else if (IS_GEN4(dev)) {
dev_priv->display.update_wm = i965_update_wm;
- if (IS_CRESTLINE(dev))
- dev_priv->display.init_clock_gating = crestline_init_clock_gating;
- else if (IS_BROADWATER(dev))
- dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
} else if (IS_GEN3(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
} else if (IS_GEN2(dev)) {
if (INTEL_INFO(dev)->num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
@@ -7206,11 +7210,6 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i830_get_fifo_size;
}
-
- if (IS_I85X(dev) || IS_I865G(dev))
- dev_priv->display.init_clock_gating = i85x_init_clock_gating;
- else
- dev_priv->display.init_clock_gating = i830_init_clock_gating;
} else {
DRM_ERROR("unexpected fall-through in intel_init_pm\n");
}
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 6/7] drm/i915: Move load time runtime device info init earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
` (4 preceding siblings ...)
2016-03-09 15:31 ` [PATCH 5/7] drm/i915: Move load time clock gating " Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 15:31 ` [PATCH 7/7] drm/i915: Move load time runtime PM get later Imre Deak
` (2 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
This init step accesses the device, but doesn't have any device
specific side effect. It also sets up some platform specific
attributes that may be required early, so move it earlier.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 8cbe9ef..76e5c69 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1060,6 +1060,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_uncore_init(dev);
/* Init phase: setup state requiring accessing the device. */
+ intel_device_info_runtime_init(dev);
+
ret = i915_gem_gtt_init(dev);
if (ret)
goto out_uncore_fini;
@@ -1134,8 +1136,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG_DRIVER("can't enable MSI");
}
- intel_device_info_runtime_init(dev);
-
if (INTEL_INFO(dev)->num_pipes) {
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 7/7] drm/i915: Move load time runtime PM get later
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
` (5 preceding siblings ...)
2016-03-09 15:31 ` [PATCH 6/7] drm/i915: Move load time runtime device info " Imre Deak
@ 2016-03-09 15:31 ` Imre Deak
2016-03-09 16:02 ` ✗ Fi.CI.BAT: warning for drm/i915: Move some load time init steps earlier Patchwork
2016-03-09 16:03 ` [PATCH 0/7] " Chris Wilson
8 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-09 15:31 UTC (permalink / raw)
To: intel-gfx
We require the device to be powered only before accessing it, so we can
move this call later.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 76e5c69..cbf42a9 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1032,9 +1032,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_init_display_callbacks(dev_priv);
intel_init_clock_gating_callbacks(dev_priv);
intel_init_audio_callbacks(dev_priv);
-
- intel_runtime_pm_get(dev_priv);
-
intel_display_crc_init(dev);
i915_dump_device_info(dev_priv);
@@ -1048,6 +1045,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
"It may not be fully functional.\n");
/* Init phase: setup device MMIO */
+ intel_runtime_pm_get(dev_priv);
+
if (i915_get_bridge_dev(dev)) {
ret = -EIO;
goto out_runtime_pm_put;
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier
2016-03-09 15:31 ` [PATCH 5/7] drm/i915: Move load time clock gating " Imre Deak
@ 2016-03-09 15:57 ` Chris Wilson
2016-03-09 16:01 ` Imre Deak
0 siblings, 1 reply; 20+ messages in thread
From: Chris Wilson @ 2016-03-09 15:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Mar 09, 2016 at 05:31:44PM +0200, Imre Deak wrote:
> Split out the part initing the clock gating callbacks and move it
> earlier.
>
> The rest of the callbacks in intel_init_pm() should be inited in the
> same way, but atm some of the callbacks are set only conditionally, so
> before doing this we need to make the setup unconditional and use
> instead some flags.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 65 ++++++++++++++++++++--------------------
> 3 files changed, 34 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 55b0c62..8cbe9ef 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1030,6 +1030,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> intel_power_domains_init(dev_priv);
> intel_irq_init(dev_priv);
> intel_init_display_callbacks(dev_priv);
> + intel_init_clock_gating_callbacks(dev_priv);
> intel_init_audio_callbacks(dev_priv);
>
> intel_runtime_pm_get(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5264901..d3d31cc 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1596,6 +1596,7 @@ void intel_suspend_hw(struct drm_device *dev);
> int ilk_wm_max_level(const struct drm_device *dev);
> void intel_update_watermarks(struct drm_crtc *crtc);
> void intel_init_pm(struct drm_device *dev);
> +void intel_init_clock_gating_callbacks(struct drm_i915_private *dev_priv);
> void intel_pm_setup(struct drm_device *dev);
> void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
> void intel_gpu_ips_teardown(void);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d7aef17..02d3598 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7107,6 +7107,38 @@ void intel_suspend_hw(struct drm_device *dev)
> lpt_suspend_hw(dev);
> }
>
> +void intel_init_clock_gating_callbacks(struct drm_i915_private *dev_priv)
> +{
> + if (IS_BROXTON(dev_priv))
> + dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> + else if (IS_BROADWELL(dev_priv))
> + dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
> + else if (IS_CHERRYVIEW(dev_priv))
> + dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
> + else if (IS_HASWELL(dev_priv))
> + dev_priv->display.init_clock_gating = haswell_init_clock_gating;
> + else if (IS_IVYBRIDGE(dev_priv))
> + dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
> + else if (IS_VALLEYVIEW(dev_priv))
> + dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
> + else if (IS_GEN6(dev_priv))
> + dev_priv->display.init_clock_gating = gen6_init_clock_gating;
> + else if (IS_GEN5(dev_priv))
> + dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
> + else if (IS_G4X(dev_priv))
> + dev_priv->display.init_clock_gating = g4x_init_clock_gating;
> + else if (IS_CRESTLINE(dev_priv))
> + dev_priv->display.init_clock_gating = crestline_init_clock_gating;
> + else if (IS_BROADWATER(dev_priv))
> + dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
> + else if (IS_GEN3(dev_priv))
> + dev_priv->display.init_clock_gating = gen3_init_clock_gating;
> + else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> + dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> + else if (IS_GEN2(dev_priv))
> + dev_priv->display.init_clock_gating = i830_init_clock_gating;
else
MISSING_CASE()
We definitely need a warning here in case we fall through and leave a
most unexpected NULL pointer.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier
2016-03-09 15:57 ` Chris Wilson
@ 2016-03-09 16:01 ` Imre Deak
2016-03-09 16:09 ` Chris Wilson
0 siblings, 1 reply; 20+ messages in thread
From: Imre Deak @ 2016-03-09 16:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-03-09 at 15:57 +0000, Chris Wilson wrote:
> On Wed, Mar 09, 2016 at 05:31:44PM +0200, Imre Deak wrote:
> > Split out the part initing the clock gating callbacks and move it
> > earlier.
> >
> > The rest of the callbacks in intel_init_pm() should be inited in
> > the
> > same way, but atm some of the callbacks are set only conditionally,
> > so
> > before doing this we need to make the setup unconditional and use
> > instead some flags.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 1 +
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 65 ++++++++++++++++++++------
> > --------------
> > 3 files changed, 34 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index 55b0c62..8cbe9ef 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1030,6 +1030,7 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned long flags)
> > intel_power_domains_init(dev_priv);
> > intel_irq_init(dev_priv);
> > intel_init_display_callbacks(dev_priv);
> > + intel_init_clock_gating_callbacks(dev_priv);
> > intel_init_audio_callbacks(dev_priv);
> >
> > intel_runtime_pm_get(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 5264901..d3d31cc 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1596,6 +1596,7 @@ void intel_suspend_hw(struct drm_device
> > *dev);
> > int ilk_wm_max_level(const struct drm_device *dev);
> > void intel_update_watermarks(struct drm_crtc *crtc);
> > void intel_init_pm(struct drm_device *dev);
> > +void intel_init_clock_gating_callbacks(struct drm_i915_private
> > *dev_priv);
> > void intel_pm_setup(struct drm_device *dev);
> > void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
> > void intel_gpu_ips_teardown(void);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index d7aef17..02d3598 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7107,6 +7107,38 @@ void intel_suspend_hw(struct drm_device
> > *dev)
> > lpt_suspend_hw(dev);
> > }
> >
> > +void intel_init_clock_gating_callbacks(struct drm_i915_private
> > *dev_priv)
> > +{
> > + if (IS_BROXTON(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > bxt_init_clock_gating;
> > + else if (IS_BROADWELL(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > broadwell_init_clock_gating;
> > + else if (IS_CHERRYVIEW(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > cherryview_init_clock_gating;
> > + else if (IS_HASWELL(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > haswell_init_clock_gating;
> > + else if (IS_IVYBRIDGE(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > ivybridge_init_clock_gating;
> > + else if (IS_VALLEYVIEW(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > valleyview_init_clock_gating;
> > + else if (IS_GEN6(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > gen6_init_clock_gating;
> > + else if (IS_GEN5(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > ironlake_init_clock_gating;
> > + else if (IS_G4X(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > g4x_init_clock_gating;
> > + else if (IS_CRESTLINE(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > crestline_init_clock_gating;
> > + else if (IS_BROADWATER(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > broadwater_init_clock_gating;
> > + else if (IS_GEN3(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > gen3_init_clock_gating;
> > + else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > i85x_init_clock_gating;
> > + else if (IS_GEN2(dev_priv))
> > + dev_priv->display.init_clock_gating =
> > i830_init_clock_gating;
>
> else
> MISSING_CASE()
>
> We definitely need a warning here in case we fall through and leave a
> most unexpected NULL pointer.
Ok, can add that. At least SKL doesn't have a callback, but I can check
for such platforms explicitly.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Move some load time init steps earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
` (6 preceding siblings ...)
2016-03-09 15:31 ` [PATCH 7/7] drm/i915: Move load time runtime PM get later Imre Deak
@ 2016-03-09 16:02 ` Patchwork
2016-03-09 16:03 ` [PATCH 0/7] " Chris Wilson
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2016-03-09 16:02 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move some load time init steps earlier
URL : https://patchwork.freedesktop.org/series/4277/
State : warning
== Summary ==
Series 4277v1 drm/i915: Move some load time init steps earlier
http://patchwork.freedesktop.org/api/1.0/series/4277/revisions/1/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
pass -> DMESG-WARN (hsw-brixbox)
dmesg-warn -> PASS (bdw-ultra)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (hsw-brixbox)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (bsw-nuc-2)
bdw-nuci7 total:193 pass:181 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:193 pass:172 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:193 pass:156 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:193 pass:158 dwarn:0 dfail:0 fail:0 skip:35
hsw-brixbox total:193 pass:170 dwarn:1 dfail:0 fail:0 skip:22
hsw-gt2 total:193 pass:175 dwarn:1 dfail:0 fail:0 skip:17
ilk-hp8440p total:193 pass:129 dwarn:1 dfail:0 fail:0 skip:63
skl-i5k-2 total:193 pass:170 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:193 pass:170 dwarn:0 dfail:0 fail:0 skip:23
snb-dellxps total:193 pass:158 dwarn:1 dfail:0 fail:0 skip:34
Results at /archive/results/CI_IGT_test/Patchwork_1551/
ab403b26610034afe0e0c97d960782bad98b97d0 drm-intel-nightly: 2016y-03m-09d-09h-25m-31s UTC integration manifest
31a9f0eb7255e6db7d2c2ead85c82a7a563d613c drm/i915: Move load time runtime PM get later
12441e34328cb74efd2171173917a228533346af drm/i915: Move load time runtime device info init earlier
e6a2f41a605493e196ec653a083fe45e41acde2b drm/i915: Move load time clock gating callback init earlier
bb85943be0fc41628f90163831ac4e734e6a1516 drm/i915: Move load time display/audio callback init earlier
23740b43760949edca1146662b0651e53c6e0a6c drm/i915: Move load time IRQ SW init earlier
d66e1cc5ce11b04c995d6cf4ea3ea1611b977758 drm/i915: Move laod time PCH detect, DPIO, power domain SW init earlier
ee9ef87a8f4084ed39e0674cf770fee37dbd9bac drm/i915: Add comments marking the start of load time init phases
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/7] drm/i915: Move some load time init steps earlier
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
` (7 preceding siblings ...)
2016-03-09 16:02 ` ✗ Fi.CI.BAT: warning for drm/i915: Move some load time init steps earlier Patchwork
@ 2016-03-09 16:03 ` Chris Wilson
2016-03-10 18:37 ` Imre Deak
2016-03-11 13:59 ` Jani Nikula
8 siblings, 2 replies; 20+ messages in thread
From: Chris Wilson @ 2016-03-09 16:03 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Mar 09, 2016 at 05:31:39PM +0200, Imre Deak wrote:
> While working on the CDCLK init code I realized that the driver load time
> dependencies between the different init steps are rather difficult to follow
> and so it's not obvious where some new piece of initialization needs to be
> added.
>
> Also because some things are initialized too late, other steps depending on
> these must be initialized in a non-logical place or even split into multiple
> parts. One example is the CDCLK initialization which needs the display
> callbacks to be set already, but those callbacks are setup only late, so the
> CDCLK initialization must be done in two parts.
>
> As a generic solution, I suggest that we define the following load
> time init phases:
> - state init not requiring device access
> (i.e SW only, like initializing locks, allocating system memory, setting
> up callbacks, device attributes)
> - minimal HW setup to enable MMIO access to the device
> - state init requiring device access w/o side effects
> (i.e. read-only HW access, no interface registrations)
> - state init causing device-wide side effects
> (i.e any HW access, no interface registration)
> - registering all interfaces
On paper sounds goods. The only complaint I have is that we have only
nomenclature for 2 phases: init and init_hw. To be compelling I want
consistent names for each init function so that we know at a glance what
phase we are in, and the expectations/limitations upon the function.
init_early() / setup()
init_mmio()
init_late()
init_hw()
> This patchset adds the corresponding comment markers for the first
> two phases above and one common phase for the rest of the current
> init steps. Later we could also add the last three init phases above
> and restructure the code accordingly.
>
> For now I only moved earlier a few obvious init steps that fit these
> new phases.
>
> I smoke tested this on GEN4, SNB, BXT.
>
> Imre Deak (7):
> drm/i915: Add comments marking the start of load time init phases
> drm/i915: Move laod time PCH detect, DPIO, power domain SW init
> earlier
> drm/i915: Move load time IRQ SW init earlier
> drm/i915: Move load time display/audio callback init earlier
> drm/i915: Move load time clock gating callback init earlier
> drm/i915: Move load time runtime device info init earlier
> drm/i915: Move load time runtime PM get later
Lgtm.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/7] drm/i915: Move load time clock gating callback init earlier
2016-03-09 16:01 ` Imre Deak
@ 2016-03-09 16:09 ` Chris Wilson
0 siblings, 0 replies; 20+ messages in thread
From: Chris Wilson @ 2016-03-09 16:09 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Mar 09, 2016 at 06:01:32PM +0200, Imre Deak wrote:
> > else
> > MISSING_CASE()
> >
> > We definitely need a warning here in case we fall through and leave a
> > most unexpected NULL pointer.
>
> Ok, can add that. At least SKL doesn't have a callback, but I can check
> for such platforms explicitly.
imo, set it to a nop_init_clock_gating as it is very much the exception
rather than the rule (and expect we'll find something to put in there
eventually!)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier
2016-03-09 15:31 ` [PATCH 4/7] drm/i915: Move load time display/audio callback " Imre Deak
@ 2016-03-09 17:14 ` kbuild test robot
2016-03-10 8:58 ` Ander Conselvan De Oliveira
2016-03-11 14:00 ` Jani Nikula
2 siblings, 0 replies; 20+ messages in thread
From: kbuild test robot @ 2016-03-09 17:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 15620 bytes --]
Hi Imre,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20160309]
[cannot apply to v4.5-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-Move-some-load-time-init-steps-earlier/20160309-233629
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
include/drm/drm_crtc.h:2144: warning: No description found for parameter 'allow_fb_modifiers'
include/drm/drm_dp_helper.h:749: warning: No description found for parameter 'i2c_nack_count'
include/drm/drm_dp_helper.h:749: warning: No description found for parameter 'i2c_defer_count'
drivers/gpu/drm/drm_dp_mst_topology.c:2364: warning: No description found for parameter 'connector'
include/drm/drm_dp_mst_helper.h:92: warning: No description found for parameter 'cached_edid'
include/drm/drm_dp_mst_helper.h:92: warning: No description found for parameter 'has_audio'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'max_dpcd_transaction_bytes'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'sink_count'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'total_slots'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'avail_slots'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'total_pbn'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'qlock'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'tx_msg_downq'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'tx_down_in_progress'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'payload_lock'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'proposed_vcpis'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'payloads'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'payload_mask'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'vcpi_mask'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'tx_waitq'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'work'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'tx_work'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'destroy_connector_list'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'destroy_connector_lock'
include/drm/drm_dp_mst_helper.h:466: warning: No description found for parameter 'destroy_connector_work'
drivers/gpu/drm/drm_dp_mst_topology.c:2364: warning: No description found for parameter 'connector'
drivers/gpu/drm/drm_irq.c:176: warning: No description found for parameter 'flags'
include/drm/drmP.h:168: warning: No description found for parameter 'fmt'
include/drm/drmP.h:184: warning: No description found for parameter 'fmt'
include/drm/drmP.h:202: warning: No description found for parameter 'fmt'
include/drm/drmP.h:247: warning: No description found for parameter 'dev'
include/drm/drmP.h:247: warning: No description found for parameter 'data'
include/drm/drmP.h:247: warning: No description found for parameter 'file_priv'
include/drm/drmP.h:280: warning: No description found for parameter 'ioctl'
include/drm/drmP.h:280: warning: No description found for parameter '_func'
include/drm/drmP.h:280: warning: No description found for parameter '_flags'
include/drm/drmP.h:362: warning: cannot understand function prototype: 'struct drm_lock_data '
include/drm/drmP.h:415: warning: cannot understand function prototype: 'struct drm_driver '
include/drm/drmP.h:672: warning: cannot understand function prototype: 'struct drm_info_list '
include/drm/drmP.h:682: warning: cannot understand function prototype: 'struct drm_info_node '
include/drm/drmP.h:692: warning: cannot understand function prototype: 'struct drm_minor '
include/drm/drmP.h:740: warning: cannot understand function prototype: 'struct drm_device '
drivers/gpu/drm/i915/intel_runtime_pm.c:2269: warning: No description found for parameter 'resume'
drivers/gpu/drm/i915/intel_runtime_pm.c:2269: warning: No description found for parameter 'resume'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'wedged'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'fmt'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'wedged'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'fmt'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'wedged'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'fmt'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'wedged'
drivers/gpu/drm/i915/i915_irq.c:2665: warning: No description found for parameter 'fmt'
drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:421: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:686: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'args'
drivers/gpu/drm/i915/i915_gem.c:767: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:1029: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:1245: warning: No description found for parameter 'rps'
drivers/gpu/drm/i915/i915_gem.c:1461: warning: No description found for parameter 'req'
drivers/gpu/drm/i915/i915_gem.c:1496: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:1496: warning: No description found for parameter 'readonly'
drivers/gpu/drm/i915/i915_gem.c:1619: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:1619: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:1619: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:1682: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:1682: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:1682: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:1727: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:1727: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:1727: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:2015: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:2015: warning: No description found for parameter 'size'
drivers/gpu/drm/i915/i915_gem.c:2015: warning: No description found for parameter 'tiling_mode'
drivers/gpu/drm/i915/i915_gem.c:2015: warning: No description found for parameter 'fenced'
drivers/gpu/drm/i915/i915_gem.c:2015: warning: Excess function parameter 'obj' description in 'i915_gem_get_gtt_alignment'
drivers/gpu/drm/i915/i915_gem.c:2914: warning: No description found for parameter 'ring'
drivers/gpu/drm/i915/i915_gem.c:3045: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:3095: warning: No description found for parameter 'dev'
drivers/gpu/drm/i915/i915_gem.c:3095: warning: No description found for parameter 'data'
drivers/gpu/drm/i915/i915_gem.c:3095: warning: No description found for parameter 'file'
drivers/gpu/drm/i915/i915_gem.c:3095: warning: Excess function parameter 'DRM_IOCTL_ARGS' description in 'i915_gem_wait_ioctl'
drivers/gpu/drm/i915/i915_gem.c:3467: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:3467: warning: No description found for parameter 'vm'
drivers/gpu/drm/i915/i915_gem.c:3467: warning: No description found for parameter 'ggtt_view'
drivers/gpu/drm/i915/i915_gem.c:3467: warning: No description found for parameter 'alignment'
drivers/gpu/drm/i915/i915_gem.c:3467: warning: No description found for parameter 'flags'
drivers/gpu/drm/i915/i915_gem.c:3722: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:3722: warning: No description found for parameter 'write'
drivers/gpu/drm/i915/i915_gem.c:3797: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:3797: warning: No description found for parameter 'cache_level'
drivers/gpu/drm/i915/i915_gem.c:4071: warning: No description found for parameter 'obj'
drivers/gpu/drm/i915/i915_gem.c:4071: warning: No description found for parameter 'write'
>> drivers/gpu/drm/i915/intel_audio.c:571: warning: No description found for parameter 'dev_priv'
>> drivers/gpu/drm/i915/intel_audio.c:571: warning: Excess function parameter 'dev' description in 'intel_init_audio_callbacks'
>> drivers/gpu/drm/i915/intel_audio.c:571: warning: No description found for parameter 'dev_priv'
>> drivers/gpu/drm/i915/intel_audio.c:571: warning: Excess function parameter 'dev' description in 'intel_init_audio_callbacks'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: No description found for parameter 'params'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'dev' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'file' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'ring' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'ctx' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'batch_obj' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'exec_start' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'dispatch_flags' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: No description found for parameter 'params'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'dev' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'file' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'ring' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'ctx' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'batch_obj' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'exec_start' description in 'intel_execlists_submission'
drivers/gpu/drm/i915/intel_lrc.c:948: warning: Excess function parameter 'dispatch_flags' description in 'intel_execlists_submission'
Warning: didn't use docs for i915_hotplug_interrupt_update
Warning: didn't use docs for ilk_update_display_irq
Warning: didn't use docs for ilk_update_gt_irq
Warning: didn't use docs for snb_update_pm_irq
Warning: didn't use docs for bdw_update_port_irq
Warning: didn't use docs for bdw_update_pipe_irq
Warning: didn't use docs for ibx_display_interrupt_update
Warning: didn't use docs for i915_enable_asle_pipestat
Warning: didn't use docs for ivybridge_parity_work
Warning: didn't use docs for i915_reset_and_wakeup
Warning: didn't use docs for i915_handle_error
Warning: didn't use docs for intel_irq_install
Warning: didn't use docs for intel_irq_uninstall
vim +/dev_priv +571 drivers/gpu/drm/i915/intel_audio.c
51e1d83c David Henningsson 2015-08-19 555 dev_priv->display.audio_codec_disable(intel_encoder);
51e1d83c David Henningsson 2015-08-19 556
cae666ce Takashi Iwai 2015-11-12 557 mutex_lock(&dev_priv->av_mutex);
cae666ce Takashi Iwai 2015-11-12 558 intel_dig_port->audio_connector = NULL;
9dfbffcf Takashi Iwai 2016-02-24 559 dev_priv->dig_port_map[port] = NULL;
cae666ce Takashi Iwai 2015-11-12 560 mutex_unlock(&dev_priv->av_mutex);
cae666ce Takashi Iwai 2015-11-12 561
51e1d83c David Henningsson 2015-08-19 562 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
f0675d4a David Henningsson 2015-09-03 563 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
7c10a2b5 Jani Nikula 2014-10-27 564 }
7c10a2b5 Jani Nikula 2014-10-27 565
7c10a2b5 Jani Nikula 2014-10-27 566 /**
7c10a2b5 Jani Nikula 2014-10-27 567 * intel_init_audio - Set up chip specific audio functions
7c10a2b5 Jani Nikula 2014-10-27 568 * @dev: drm device
7c10a2b5 Jani Nikula 2014-10-27 569 */
576177de Imre Deak 2016-03-09 570 void intel_init_audio_callbacks(struct drm_i915_private *dev_priv)
7c10a2b5 Jani Nikula 2014-10-27 @571 {
576177de Imre Deak 2016-03-09 572 if (IS_G4X(dev_priv)) {
69bfe1a9 Jani Nikula 2014-10-27 573 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
76d8d3e5 Jani Nikula 2014-10-27 574 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
576177de Imre Deak 2016-03-09 575 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
69bfe1a9 Jani Nikula 2014-10-27 576 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8 Jani Nikula 2014-10-27 577 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
576177de Imre Deak 2016-03-09 578 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
69bfe1a9 Jani Nikula 2014-10-27 579 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
:::::: The code at line 571 was first introduced by commit
:::::: 7c10a2b5876e014b3986d7e20b2a2894a757b138 drm/i915: add new intel audio file to group DP/HDMI audio
:::::: TO: Jani Nikula <jani.nikula@intel.com>
:::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 6229 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier
2016-03-09 15:31 ` [PATCH 4/7] drm/i915: Move load time display/audio callback " Imre Deak
2016-03-09 17:14 ` kbuild test robot
@ 2016-03-10 8:58 ` Ander Conselvan De Oliveira
2016-03-10 11:24 ` Imre Deak
2016-03-11 14:00 ` Jani Nikula
2 siblings, 1 reply; 20+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-03-10 8:58 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Wed, 2016-03-09 at 17:31 +0200, Imre Deak wrote:
> All of this is SW only initialization so we can move them earlier. Move
> the mutex init where the rest of the locks are inited. While at it also
> convert dev to dev_priv.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 ++
> drivers/gpu/drm/i915/intel_audio.c | 12 +++---
> drivers/gpu/drm/i915/intel_display.c | 77 ++++++++++++++++-------------------
> -
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> 4 files changed, 45 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 9b3ed00..55b0c62 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1016,6 +1016,7 @@ int i915_driver_load(struct drm_device *dev, unsigned
> long flags)
> mutex_init(&dev_priv->modeset_restore_lock);
> mutex_init(&dev_priv->av_mutex);
> mutex_init(&dev_priv->wm.wm_mutex);
> + mutex_init(&dev_priv->pps_mutex);
>
> ret = i915_workqueues_init(dev_priv);
> if (ret < 0)
> @@ -1028,6 +1029,8 @@ int i915_driver_load(struct drm_device *dev, unsigned
> long flags)
> intel_init_dpio(dev_priv);
> intel_power_domains_init(dev_priv);
> intel_irq_init(dev_priv);
> + intel_init_display_callbacks(dev_priv);
> + intel_init_audio_callbacks(dev_priv);
>
> intel_runtime_pm_get(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 30f9214..1936752 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -567,20 +567,18 @@ void intel_audio_codec_disable(struct intel_encoder
> *intel_encoder)
> * intel_init_audio - Set up chip specific audio functions
> * @dev: drm device
> */
> -void intel_init_audio(struct drm_device *dev)
> +void intel_init_audio_callbacks(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> dev_priv->display.audio_codec_enable =
> g4x_audio_codec_enable;
> dev_priv->display.audio_codec_disable =
> g4x_audio_codec_disable;
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.audio_codec_enable =
> ilk_audio_codec_enable;
> dev_priv->display.audio_codec_disable =
> ilk_audio_codec_disable;
> - } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
> + } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
> dev_priv->display.audio_codec_enable =
> hsw_audio_codec_enable;
> dev_priv->display.audio_codec_disable =
> hsw_audio_codec_disable;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> dev_priv->display.audio_codec_enable =
> ilk_audio_codec_enable;
> dev_priv->display.audio_codec_disable =
> ilk_audio_codec_disable;
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 62d36a7..5170718 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15095,22 +15095,20 @@ static const struct drm_mode_config_funcs
> intel_mode_funcs = {
> };
>
> /* Set up chip specific display functions */
> -static void intel_init_display(struct drm_device *dev)
> +void intel_init_display_callbacks(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
> + if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
> dev_priv->display.find_dpll = g4x_find_best_dpll;
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> dev_priv->display.find_dpll = chv_find_best_dpll;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
> dev_priv->display.find_dpll = vlv_find_best_dpll;
> - else if (IS_PINEVIEW(dev))
> + else if (IS_PINEVIEW(dev_priv))
> dev_priv->display.find_dpll = pnv_find_best_dpll;
> else
> dev_priv->display.find_dpll = i9xx_find_best_dpll;
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_INFO(dev_priv)->gen >= 9) {
> dev_priv->display.get_pipe_config = haswell_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> skylake_get_initial_plane_config;
> @@ -15118,7 +15116,7 @@ static void intel_init_display(struct drm_device *dev)
> haswell_crtc_compute_clock;
> dev_priv->display.crtc_enable = haswell_crtc_enable;
> dev_priv->display.crtc_disable = haswell_crtc_disable;
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> dev_priv->display.get_pipe_config = haswell_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> ironlake_get_initial_plane_config;
> @@ -15126,7 +15124,7 @@ static void intel_init_display(struct drm_device *dev)
> haswell_crtc_compute_clock;
> dev_priv->display.crtc_enable = haswell_crtc_enable;
> dev_priv->display.crtc_disable = haswell_crtc_disable;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> ironlake_get_initial_plane_config;
> @@ -15134,7 +15132,7 @@ static void intel_init_display(struct drm_device *dev)
> ironlake_crtc_compute_clock;
> dev_priv->display.crtc_enable = ironlake_crtc_enable;
> dev_priv->display.crtc_disable = ironlake_crtc_disable;
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> i9xx_get_initial_plane_config;
> @@ -15151,89 +15149,89 @@ static void intel_init_display(struct drm_device
> *dev)
> }
>
> /* Returns the core display clock speed */
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> dev_priv->display.get_display_clock_speed =
> broxton_get_display_clock_speed;
> - else if (IS_BROADWELL(dev))
> + else if (IS_BROADWELL(dev_priv))
> dev_priv->display.get_display_clock_speed =
> broadwell_get_display_clock_speed;
> - else if (IS_HASWELL(dev))
> + else if (IS_HASWELL(dev_priv))
> dev_priv->display.get_display_clock_speed =
> haswell_get_display_clock_speed;
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->display.get_display_clock_speed =
> valleyview_get_display_clock_speed;
> - else if (IS_GEN5(dev))
> + else if (IS_GEN5(dev_priv))
> dev_priv->display.get_display_clock_speed =
> ilk_get_display_clock_speed;
> - else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
> - IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> + else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
> + IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i945_get_display_clock_speed;
> - else if (IS_GM45(dev))
> + else if (IS_GM45(dev_priv))
> dev_priv->display.get_display_clock_speed =
> gm45_get_display_clock_speed;
> - else if (IS_CRESTLINE(dev))
> + else if (IS_CRESTLINE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i965gm_get_display_clock_speed;
> - else if (IS_PINEVIEW(dev))
> + else if (IS_PINEVIEW(dev_priv))
> dev_priv->display.get_display_clock_speed =
> pnv_get_display_clock_speed;
> - else if (IS_G33(dev) || IS_G4X(dev))
> + else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
> dev_priv->display.get_display_clock_speed =
> g33_get_display_clock_speed;
> - else if (IS_I915G(dev))
> + else if (IS_I915G(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i915_get_display_clock_speed;
> - else if (IS_I945GM(dev) || IS_845G(dev))
> + else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i9xx_misc_get_display_clock_speed;
> - else if (IS_I915GM(dev))
> + else if (IS_I915GM(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i915gm_get_display_clock_speed;
> - else if (IS_I865G(dev))
> + else if (IS_I865G(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i865_get_display_clock_speed;
> - else if (IS_I85X(dev))
> + else if (IS_I85X(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i85x_get_display_clock_speed;
> else { /* 830 */
> - WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz
> CDCLK\n");
> + WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz
> CDCLK\n");
> dev_priv->display.get_display_clock_speed =
> i830_get_display_clock_speed;
> }
>
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> - } else if (IS_GEN6(dev)) {
> + } else if (IS_GEN6(dev_priv)) {
> dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> - } else if (IS_IVYBRIDGE(dev)) {
> + } else if (IS_IVYBRIDGE(dev_priv)) {
> /* FIXME: detect B0+ stepping and use auto training */
> dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> - if (IS_BROADWELL(dev)) {
> + if (IS_BROADWELL(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> broadwell_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broadwell_modeset_calc_cdclk;
> }
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> valleyview_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> valleyview_modeset_calc_cdclk;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> }
Would it make sense to change these if ladders into a structs of function
pointers and point to those from struct intel_device_info? The HAS_PCH_SPLIT()
check could be a bit tricky, but those usually go as
if (HAS_DDI())
...
else if (HAS_PCH_SPLIT())
...,
so they usually mean ILK, SNB and IVB.
I'm not saying this should be part of this series, but just wanted to throw the
idea out there.
Ander
>
> - switch (INTEL_INFO(dev)->gen) {
> + switch (INTEL_INFO(dev_priv)->gen) {
> case 2:
> dev_priv->display.queue_flip = intel_gen2_queue_flip;
> break;
> @@ -15260,8 +15258,6 @@ static void intel_init_display(struct drm_device *dev)
> /* Default just returns -ENODEV to indicate unsupported */
> dev_priv->display.queue_flip = intel_default_queue_flip;
> }
> -
> - mutex_init(&dev_priv->pps_mutex);
> }
>
> /*
> @@ -15588,9 +15584,6 @@ void intel_modeset_init(struct drm_device *dev)
> }
> }
>
> - intel_init_display(dev);
> - intel_init_audio(dev);
> -
> if (IS_GEN2(dev)) {
> dev->mode_config.max_width = 2048;
> dev->mode_config.max_height = 2048;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 7b2d66d..5264901 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1110,7 +1110,7 @@ u32 intel_fb_stride_alignment(const struct
> drm_i915_private *dev_priv,
> uint64_t fb_modifier, uint32_t pixel_format);
>
> /* intel_audio.c */
> -void intel_init_audio(struct drm_device *dev);
> +void intel_init_audio_callbacks(struct drm_i915_private *dev_priv);
> void intel_audio_codec_enable(struct intel_encoder *encoder);
> void intel_audio_codec_disable(struct intel_encoder *encoder);
> void i915_audio_component_init(struct drm_i915_private *dev_priv);
> @@ -1118,6 +1118,7 @@ void i915_audio_component_cleanup(struct
> drm_i915_private *dev_priv);
>
> /* intel_display.c */
> extern const struct drm_plane_funcs intel_plane_funcs;
> +void intel_init_display_callbacks(struct drm_i915_private *dev_priv);
> unsigned int intel_rotation_info_size(const struct intel_rotation_info
> *rot_info);
> bool intel_has_pending_fb_unpin(struct drm_device *dev);
> void intel_mark_busy(struct drm_device *dev);
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier
2016-03-10 8:58 ` Ander Conselvan De Oliveira
@ 2016-03-10 11:24 ` Imre Deak
0 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-10 11:24 UTC (permalink / raw)
To: Ander Conselvan De Oliveira, intel-gfx
On to, 2016-03-10 at 10:58 +0200, Ander Conselvan De Oliveira wrote:
> On Wed, 2016-03-09 at 17:31 +0200, Imre Deak wrote:
> > All of this is SW only initialization so we can move them earlier.
> > Move
> > the mutex init where the rest of the locks are inited. While at it
> > also
> > convert dev to dev_priv.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 3 ++
> > drivers/gpu/drm/i915/intel_audio.c | 12 +++---
> > drivers/gpu/drm/i915/intel_display.c | 77 ++++++++++++++++------
> > -------------
> > -
> > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > 4 files changed, 45 insertions(+), 50 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index 9b3ed00..55b0c62 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1016,6 +1016,7 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned
> > long flags)
> > mutex_init(&dev_priv->modeset_restore_lock);
> > mutex_init(&dev_priv->av_mutex);
> > mutex_init(&dev_priv->wm.wm_mutex);
> > + mutex_init(&dev_priv->pps_mutex);
> >
> > ret = i915_workqueues_init(dev_priv);
> > if (ret < 0)
> > @@ -1028,6 +1029,8 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned
> > long flags)
> > intel_init_dpio(dev_priv);
> > intel_power_domains_init(dev_priv);
> > intel_irq_init(dev_priv);
> > + intel_init_display_callbacks(dev_priv);
> > + intel_init_audio_callbacks(dev_priv);
> >
> > intel_runtime_pm_get(dev_priv);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 30f9214..1936752 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -567,20 +567,18 @@ void intel_audio_codec_disable(struct
> > intel_encoder
> > *intel_encoder)
> > * intel_init_audio - Set up chip specific audio functions
> > * @dev: drm device
> > */
> > -void intel_init_audio(struct drm_device *dev)
> > +void intel_init_audio_callbacks(struct drm_i915_private *dev_priv)
> > {
> > - struct drm_i915_private *dev_priv = dev->dev_private;
> > -
> > - if (IS_G4X(dev)) {
> > + if (IS_G4X(dev_priv)) {
> > dev_priv->display.audio_codec_enable =
> > g4x_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > g4x_audio_codec_disable;
> > - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > + } else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.audio_codec_enable =
> > ilk_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > ilk_audio_codec_disable;
> > - } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
> > + } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)-
> > >gen >= 8) {
> > dev_priv->display.audio_codec_enable =
> > hsw_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > hsw_audio_codec_disable;
> > - } else if (HAS_PCH_SPLIT(dev)) {
> > + } else if (HAS_PCH_SPLIT(dev_priv)) {
> > dev_priv->display.audio_codec_enable =
> > ilk_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > ilk_audio_codec_disable;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 62d36a7..5170718 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15095,22 +15095,20 @@ static const struct drm_mode_config_funcs
> > intel_mode_funcs = {
> > };
> >
> > /* Set up chip specific display functions */
> > -static void intel_init_display(struct drm_device *dev)
> > +void intel_init_display_callbacks(struct drm_i915_private
> > *dev_priv)
> > {
> > - struct drm_i915_private *dev_priv = dev->dev_private;
> > -
> > - if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
> > + if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
> > dev_priv->display.find_dpll = g4x_find_best_dpll;
> > - else if (IS_CHERRYVIEW(dev))
> > + else if (IS_CHERRYVIEW(dev_priv))
> > dev_priv->display.find_dpll = chv_find_best_dpll;
> > - else if (IS_VALLEYVIEW(dev))
> > + else if (IS_VALLEYVIEW(dev_priv))
> > dev_priv->display.find_dpll = vlv_find_best_dpll;
> > - else if (IS_PINEVIEW(dev))
> > + else if (IS_PINEVIEW(dev_priv))
> > dev_priv->display.find_dpll = pnv_find_best_dpll;
> > else
> > dev_priv->display.find_dpll = i9xx_find_best_dpll;
> >
> > - if (INTEL_INFO(dev)->gen >= 9) {
> > + if (INTEL_INFO(dev_priv)->gen >= 9) {
> > dev_priv->display.get_pipe_config =
> > haswell_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > skylake_get_initial_plane_config;
> > @@ -15118,7 +15116,7 @@ static void intel_init_display(struct
> > drm_device *dev)
> > haswell_crtc_compute_clock;
> > dev_priv->display.crtc_enable =
> > haswell_crtc_enable;
> > dev_priv->display.crtc_disable =
> > haswell_crtc_disable;
> > - } else if (HAS_DDI(dev)) {
> > + } else if (HAS_DDI(dev_priv)) {
> > dev_priv->display.get_pipe_config =
> > haswell_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > ironlake_get_initial_plane_config;
> > @@ -15126,7 +15124,7 @@ static void intel_init_display(struct
> > drm_device *dev)
> > haswell_crtc_compute_clock;
> > dev_priv->display.crtc_enable =
> > haswell_crtc_enable;
> > dev_priv->display.crtc_disable =
> > haswell_crtc_disable;
> > - } else if (HAS_PCH_SPLIT(dev)) {
> > + } else if (HAS_PCH_SPLIT(dev_priv)) {
> > dev_priv->display.get_pipe_config =
> > ironlake_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > ironlake_get_initial_plane_config;
> > @@ -15134,7 +15132,7 @@ static void intel_init_display(struct
> > drm_device *dev)
> > ironlake_crtc_compute_clock;
> > dev_priv->display.crtc_enable =
> > ironlake_crtc_enable;
> > dev_priv->display.crtc_disable =
> > ironlake_crtc_disable;
> > - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > + } else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.get_pipe_config =
> > i9xx_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > i9xx_get_initial_plane_config;
> > @@ -15151,89 +15149,89 @@ static void intel_init_display(struct
> > drm_device
> > *dev)
> > }
> >
> > /* Returns the core display clock speed */
> > - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> > + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > skylake_get_display_clock_speed;
> > - else if (IS_BROXTON(dev))
> > + else if (IS_BROXTON(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > broxton_get_display_clock_speed;
> > - else if (IS_BROADWELL(dev))
> > + else if (IS_BROADWELL(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > broadwell_get_display_clock_speed;
> > - else if (IS_HASWELL(dev))
> > + else if (IS_HASWELL(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > haswell_get_display_clock_speed;
> > - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > + else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > valleyview_get_display_clock_speed;
> > - else if (IS_GEN5(dev))
> > + else if (IS_GEN5(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > ilk_get_display_clock_speed;
> > - else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
> > - IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> > + else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
> > + IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i945_get_display_clock_speed;
> > - else if (IS_GM45(dev))
> > + else if (IS_GM45(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > gm45_get_display_clock_speed;
> > - else if (IS_CRESTLINE(dev))
> > + else if (IS_CRESTLINE(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i965gm_get_display_clock_speed;
> > - else if (IS_PINEVIEW(dev))
> > + else if (IS_PINEVIEW(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > pnv_get_display_clock_speed;
> > - else if (IS_G33(dev) || IS_G4X(dev))
> > + else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > g33_get_display_clock_speed;
> > - else if (IS_I915G(dev))
> > + else if (IS_I915G(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i915_get_display_clock_speed;
> > - else if (IS_I945GM(dev) || IS_845G(dev))
> > + else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i9xx_misc_get_display_clock_speed;
> > - else if (IS_I915GM(dev))
> > + else if (IS_I915GM(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i915gm_get_display_clock_speed;
> > - else if (IS_I865G(dev))
> > + else if (IS_I865G(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i865_get_display_clock_speed;
> > - else if (IS_I85X(dev))
> > + else if (IS_I85X(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i85x_get_display_clock_speed;
> > else { /* 830 */
> > - WARN(!IS_I830(dev), "Unknown platform. Assuming
> > 133 MHz
> > CDCLK\n");
> > + WARN(!IS_I830(dev_priv), "Unknown platform.
> > Assuming 133 MHz
> > CDCLK\n");
> > dev_priv->display.get_display_clock_speed =
> > i830_get_display_clock_speed;
> > }
> >
> > - if (IS_GEN5(dev)) {
> > + if (IS_GEN5(dev_priv)) {
> > dev_priv->display.fdi_link_train =
> > ironlake_fdi_link_train;
> > - } else if (IS_GEN6(dev)) {
> > + } else if (IS_GEN6(dev_priv)) {
> > dev_priv->display.fdi_link_train =
> > gen6_fdi_link_train;
> > - } else if (IS_IVYBRIDGE(dev)) {
> > + } else if (IS_IVYBRIDGE(dev_priv)) {
> > /* FIXME: detect B0+ stepping and use auto
> > training */
> > dev_priv->display.fdi_link_train =
> > ivb_manual_fdi_link_train;
> > - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> > + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > {
> > dev_priv->display.fdi_link_train =
> > hsw_fdi_link_train;
> > - if (IS_BROADWELL(dev)) {
> > + if (IS_BROADWELL(dev_priv)) {
> > dev_priv->display.modeset_commit_cdclk =
> > broadwell_modeset_commit_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > broadwell_modeset_calc_cdclk;
> > }
> > - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > + } else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.modeset_commit_cdclk =
> > valleyview_modeset_commit_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > valleyview_modeset_calc_cdclk;
> > - } else if (IS_BROXTON(dev)) {
> > + } else if (IS_BROXTON(dev_priv)) {
> > dev_priv->display.modeset_commit_cdclk =
> > broxton_modeset_commit_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > broxton_modeset_calc_cdclk;
> > }
>
> Would it make sense to change these if ladders into a structs of function
> pointers and point to those from struct intel_device_info? The HAS_PCH_SPLIT()
> check could be a bit tricky, but those usually go as
>
> if (HAS_DDI())
> ...
> else if (HAS_PCH_SPLIT())
> ...,
>
> so they usually mean ILK, SNB and IVB.
Yes, a good idea, would clarify things.
> I'm not saying this should be part of this series, but just wanted to throw the
> idea out there.
I'm not sure yet how many variations of new function structs we need to
spawn depending on platform differences that you also mention (AFAICS
there are similar ones for older platforms too). We would also need to
remove first the conditional assignments to callbacks (see the next
patch). But I think after having all callback initializations collected
to one place, we'd have a better overview and could go for what you
suggested.
--Imre
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/7] drm/i915: Move some load time init steps earlier
2016-03-09 16:03 ` [PATCH 0/7] " Chris Wilson
@ 2016-03-10 18:37 ` Imre Deak
2016-03-11 13:59 ` Jani Nikula
1 sibling, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-10 18:37 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On ke, 2016-03-09 at 16:03 +0000, Chris Wilson wrote:
> On Wed, Mar 09, 2016 at 05:31:39PM +0200, Imre Deak wrote:
> > While working on the CDCLK init code I realized that the driver
> > load time
> > dependencies between the different init steps are rather difficult
> > to follow
> > and so it's not obvious where some new piece of initialization
> > needs to be
> > added.
> >
> > Also because some things are initialized too late, other steps
> > depending on
> > these must be initialized in a non-logical place or even split into
> > multiple
> > parts. One example is the CDCLK initialization which needs the
> > display
> > callbacks to be set already, but those callbacks are setup only
> > late, so the
> > CDCLK initialization must be done in two parts.
> >
> > As a generic solution, I suggest that we define the following load
> > time init phases:
> > - state init not requiring device access
> > (i.e SW only, like initializing locks, allocating system memory,
> > setting
> > up callbacks, device attributes)
> > - minimal HW setup to enable MMIO access to the device
> > - state init requiring device access w/o side effects
> > (i.e. read-only HW access, no interface registrations)
> > - state init causing device-wide side effects
> > (i.e any HW access, no interface registration)
> > - registering all interfaces
>
> On paper sounds goods. The only complaint I have is that we have only
> nomenclature for 2 phases: init and init_hw. To be compelling I want
> consistent names for each init function so that we know at a glance
> what
> phase we are in, and the expectations/limitations upon the function.
>
> init_early() / setup()
> init_mmio()
> init_late()
> init_hw()
Ok, I moved around the code according to the above:
https://github.com/ideak/linux/commits/driver_init_refactor
I left out the init_late() step but also added a registration step.
There are still some init steps - mostly on the modesetting path - that
will need to be moved into one of the above functions, but that can be
done later.
I can post this patchset after some more testing.
--Imre
> > This patchset adds the corresponding comment markers for the first
> > two phases above and one common phase for the rest of the current
> > init steps. Later we could also add the last three init phases
> > above
> > and restructure the code accordingly.
> >
> > For now I only moved earlier a few obvious init steps that fit
> > these
> > new phases.
> >
> > I smoke tested this on GEN4, SNB, BXT.
> >
> > Imre Deak (7):
> > drm/i915: Add comments marking the start of load time init phases
> > drm/i915: Move laod time PCH detect, DPIO, power domain SW init
> > earlier
> > drm/i915: Move load time IRQ SW init earlier
> > drm/i915: Move load time display/audio callback init earlier
> > drm/i915: Move load time clock gating callback init earlier
> > drm/i915: Move load time runtime device info init earlier
> > drm/i915: Move load time runtime PM get later
>
> Lgtm.
> -Chris
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/7] drm/i915: Move some load time init steps earlier
2016-03-09 16:03 ` [PATCH 0/7] " Chris Wilson
2016-03-10 18:37 ` Imre Deak
@ 2016-03-11 13:59 ` Jani Nikula
1 sibling, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2016-03-11 13:59 UTC (permalink / raw)
To: Chris Wilson, Imre Deak; +Cc: intel-gfx
On Wed, 09 Mar 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Wed, Mar 09, 2016 at 05:31:39PM +0200, Imre Deak wrote:
>> While working on the CDCLK init code I realized that the driver load time
>> dependencies between the different init steps are rather difficult to follow
>> and so it's not obvious where some new piece of initialization needs to be
>> added.
>>
>> Also because some things are initialized too late, other steps depending on
>> these must be initialized in a non-logical place or even split into multiple
>> parts. One example is the CDCLK initialization which needs the display
>> callbacks to be set already, but those callbacks are setup only late, so the
>> CDCLK initialization must be done in two parts.
>>
>> As a generic solution, I suggest that we define the following load
>> time init phases:
>> - state init not requiring device access
>> (i.e SW only, like initializing locks, allocating system memory, setting
>> up callbacks, device attributes)
>> - minimal HW setup to enable MMIO access to the device
>> - state init requiring device access w/o side effects
>> (i.e. read-only HW access, no interface registrations)
>> - state init causing device-wide side effects
>> (i.e any HW access, no interface registration)
>> - registering all interfaces
>
> On paper sounds goods. The only complaint I have is that we have only
> nomenclature for 2 phases: init and init_hw. To be compelling I want
> consistent names for each init function so that we know at a glance what
> phase we are in, and the expectations/limitations upon the function.
>
> init_early() / setup()
> init_mmio()
> init_late()
> init_hw()
Agreed.
>
>> This patchset adds the corresponding comment markers for the first
>> two phases above and one common phase for the rest of the current
>> init steps. Later we could also add the last three init phases above
>> and restructure the code accordingly.
>>
>> For now I only moved earlier a few obvious init steps that fit these
>> new phases.
>>
>> I smoke tested this on GEN4, SNB, BXT.
>>
>> Imre Deak (7):
>> drm/i915: Add comments marking the start of load time init phases
>> drm/i915: Move laod time PCH detect, DPIO, power domain SW init
>> earlier
>> drm/i915: Move load time IRQ SW init earlier
>> drm/i915: Move load time display/audio callback init earlier
>> drm/i915: Move load time clock gating callback init earlier
>> drm/i915: Move load time runtime device info init earlier
>> drm/i915: Move load time runtime PM get later
>
> Lgtm.
> -Chris
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier
2016-03-09 15:31 ` [PATCH 4/7] drm/i915: Move load time display/audio callback " Imre Deak
2016-03-09 17:14 ` kbuild test robot
2016-03-10 8:58 ` Ander Conselvan De Oliveira
@ 2016-03-11 14:00 ` Jani Nikula
2016-03-11 14:17 ` Imre Deak
2 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2016-03-11 14:00 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Wed, 09 Mar 2016, Imre Deak <imre.deak@intel.com> wrote:
> All of this is SW only initialization so we can move them earlier. Move
> the mutex init where the rest of the locks are inited. While at it also
> convert dev to dev_priv.
Bikeshedding on this patch and the next: I don't think the function
pointers are *callbacks* in any way. There's no "call back". Maybe
"hooks"?
BR,
Jani.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 ++
> drivers/gpu/drm/i915/intel_audio.c | 12 +++---
> drivers/gpu/drm/i915/intel_display.c | 77 ++++++++++++++++--------------------
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> 4 files changed, 45 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 9b3ed00..55b0c62 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1016,6 +1016,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> mutex_init(&dev_priv->modeset_restore_lock);
> mutex_init(&dev_priv->av_mutex);
> mutex_init(&dev_priv->wm.wm_mutex);
> + mutex_init(&dev_priv->pps_mutex);
>
> ret = i915_workqueues_init(dev_priv);
> if (ret < 0)
> @@ -1028,6 +1029,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> intel_init_dpio(dev_priv);
> intel_power_domains_init(dev_priv);
> intel_irq_init(dev_priv);
> + intel_init_display_callbacks(dev_priv);
> + intel_init_audio_callbacks(dev_priv);
>
> intel_runtime_pm_get(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 30f9214..1936752 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -567,20 +567,18 @@ void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
> * intel_init_audio - Set up chip specific audio functions
> * @dev: drm device
> */
> -void intel_init_audio(struct drm_device *dev)
> +void intel_init_audio_callbacks(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
> dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> - } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
> + } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
> dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
> dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 62d36a7..5170718 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15095,22 +15095,20 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
> };
>
> /* Set up chip specific display functions */
> -static void intel_init_display(struct drm_device *dev)
> +void intel_init_display_callbacks(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
> + if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
> dev_priv->display.find_dpll = g4x_find_best_dpll;
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> dev_priv->display.find_dpll = chv_find_best_dpll;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
> dev_priv->display.find_dpll = vlv_find_best_dpll;
> - else if (IS_PINEVIEW(dev))
> + else if (IS_PINEVIEW(dev_priv))
> dev_priv->display.find_dpll = pnv_find_best_dpll;
> else
> dev_priv->display.find_dpll = i9xx_find_best_dpll;
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_INFO(dev_priv)->gen >= 9) {
> dev_priv->display.get_pipe_config = haswell_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> skylake_get_initial_plane_config;
> @@ -15118,7 +15116,7 @@ static void intel_init_display(struct drm_device *dev)
> haswell_crtc_compute_clock;
> dev_priv->display.crtc_enable = haswell_crtc_enable;
> dev_priv->display.crtc_disable = haswell_crtc_disable;
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> dev_priv->display.get_pipe_config = haswell_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> ironlake_get_initial_plane_config;
> @@ -15126,7 +15124,7 @@ static void intel_init_display(struct drm_device *dev)
> haswell_crtc_compute_clock;
> dev_priv->display.crtc_enable = haswell_crtc_enable;
> dev_priv->display.crtc_disable = haswell_crtc_disable;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> ironlake_get_initial_plane_config;
> @@ -15134,7 +15132,7 @@ static void intel_init_display(struct drm_device *dev)
> ironlake_crtc_compute_clock;
> dev_priv->display.crtc_enable = ironlake_crtc_enable;
> dev_priv->display.crtc_disable = ironlake_crtc_disable;
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> i9xx_get_initial_plane_config;
> @@ -15151,89 +15149,89 @@ static void intel_init_display(struct drm_device *dev)
> }
>
> /* Returns the core display clock speed */
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> dev_priv->display.get_display_clock_speed =
> broxton_get_display_clock_speed;
> - else if (IS_BROADWELL(dev))
> + else if (IS_BROADWELL(dev_priv))
> dev_priv->display.get_display_clock_speed =
> broadwell_get_display_clock_speed;
> - else if (IS_HASWELL(dev))
> + else if (IS_HASWELL(dev_priv))
> dev_priv->display.get_display_clock_speed =
> haswell_get_display_clock_speed;
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->display.get_display_clock_speed =
> valleyview_get_display_clock_speed;
> - else if (IS_GEN5(dev))
> + else if (IS_GEN5(dev_priv))
> dev_priv->display.get_display_clock_speed =
> ilk_get_display_clock_speed;
> - else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
> - IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> + else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
> + IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i945_get_display_clock_speed;
> - else if (IS_GM45(dev))
> + else if (IS_GM45(dev_priv))
> dev_priv->display.get_display_clock_speed =
> gm45_get_display_clock_speed;
> - else if (IS_CRESTLINE(dev))
> + else if (IS_CRESTLINE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i965gm_get_display_clock_speed;
> - else if (IS_PINEVIEW(dev))
> + else if (IS_PINEVIEW(dev_priv))
> dev_priv->display.get_display_clock_speed =
> pnv_get_display_clock_speed;
> - else if (IS_G33(dev) || IS_G4X(dev))
> + else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
> dev_priv->display.get_display_clock_speed =
> g33_get_display_clock_speed;
> - else if (IS_I915G(dev))
> + else if (IS_I915G(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i915_get_display_clock_speed;
> - else if (IS_I945GM(dev) || IS_845G(dev))
> + else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i9xx_misc_get_display_clock_speed;
> - else if (IS_I915GM(dev))
> + else if (IS_I915GM(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i915gm_get_display_clock_speed;
> - else if (IS_I865G(dev))
> + else if (IS_I865G(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i865_get_display_clock_speed;
> - else if (IS_I85X(dev))
> + else if (IS_I85X(dev_priv))
> dev_priv->display.get_display_clock_speed =
> i85x_get_display_clock_speed;
> else { /* 830 */
> - WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
> + WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
> dev_priv->display.get_display_clock_speed =
> i830_get_display_clock_speed;
> }
>
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> - } else if (IS_GEN6(dev)) {
> + } else if (IS_GEN6(dev_priv)) {
> dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> - } else if (IS_IVYBRIDGE(dev)) {
> + } else if (IS_IVYBRIDGE(dev_priv)) {
> /* FIXME: detect B0+ stepping and use auto training */
> dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> - if (IS_BROADWELL(dev)) {
> + if (IS_BROADWELL(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> broadwell_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broadwell_modeset_calc_cdclk;
> }
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> valleyview_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> valleyview_modeset_calc_cdclk;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> broxton_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> broxton_modeset_calc_cdclk;
> }
>
> - switch (INTEL_INFO(dev)->gen) {
> + switch (INTEL_INFO(dev_priv)->gen) {
> case 2:
> dev_priv->display.queue_flip = intel_gen2_queue_flip;
> break;
> @@ -15260,8 +15258,6 @@ static void intel_init_display(struct drm_device *dev)
> /* Default just returns -ENODEV to indicate unsupported */
> dev_priv->display.queue_flip = intel_default_queue_flip;
> }
> -
> - mutex_init(&dev_priv->pps_mutex);
> }
>
> /*
> @@ -15588,9 +15584,6 @@ void intel_modeset_init(struct drm_device *dev)
> }
> }
>
> - intel_init_display(dev);
> - intel_init_audio(dev);
> -
> if (IS_GEN2(dev)) {
> dev->mode_config.max_width = 2048;
> dev->mode_config.max_height = 2048;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7b2d66d..5264901 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1110,7 +1110,7 @@ u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
> uint64_t fb_modifier, uint32_t pixel_format);
>
> /* intel_audio.c */
> -void intel_init_audio(struct drm_device *dev);
> +void intel_init_audio_callbacks(struct drm_i915_private *dev_priv);
> void intel_audio_codec_enable(struct intel_encoder *encoder);
> void intel_audio_codec_disable(struct intel_encoder *encoder);
> void i915_audio_component_init(struct drm_i915_private *dev_priv);
> @@ -1118,6 +1118,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
>
> /* intel_display.c */
> extern const struct drm_plane_funcs intel_plane_funcs;
> +void intel_init_display_callbacks(struct drm_i915_private *dev_priv);
> unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
> bool intel_has_pending_fb_unpin(struct drm_device *dev);
> void intel_mark_busy(struct drm_device *dev);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/7] drm/i915: Move load time display/audio callback init earlier
2016-03-11 14:00 ` Jani Nikula
@ 2016-03-11 14:17 ` Imre Deak
0 siblings, 0 replies; 20+ messages in thread
From: Imre Deak @ 2016-03-11 14:17 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On pe, 2016-03-11 at 16:00 +0200, Jani Nikula wrote:
> On Wed, 09 Mar 2016, Imre Deak <imre.deak@intel.com> wrote:
> > All of this is SW only initialization so we can move them earlier.
> > Move
> > the mutex init where the rest of the locks are inited. While at it
> > also
> > convert dev to dev_priv.
>
> Bikeshedding on this patch and the next: I don't think the function
> pointers are *callbacks* in any way. There's no "call back". Maybe
> "hooks"?
Yea, callback isn't a correct term here. I have no preference for an
alternative, I can rename it to hooks both here and the next patch.
--Imre
>
> BR,
> Jani.
>
>
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 3 ++
> > drivers/gpu/drm/i915/intel_audio.c | 12 +++---
> > drivers/gpu/drm/i915/intel_display.c | 77 ++++++++++++++++------
> > --------------
> > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > 4 files changed, 45 insertions(+), 50 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index 9b3ed00..55b0c62 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1016,6 +1016,7 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned long flags)
> > mutex_init(&dev_priv->modeset_restore_lock);
> > mutex_init(&dev_priv->av_mutex);
> > mutex_init(&dev_priv->wm.wm_mutex);
> > + mutex_init(&dev_priv->pps_mutex);
> >
> > ret = i915_workqueues_init(dev_priv);
> > if (ret < 0)
> > @@ -1028,6 +1029,8 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned long flags)
> > intel_init_dpio(dev_priv);
> > intel_power_domains_init(dev_priv);
> > intel_irq_init(dev_priv);
> > + intel_init_display_callbacks(dev_priv);
> > + intel_init_audio_callbacks(dev_priv);
> >
> > intel_runtime_pm_get(dev_priv);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 30f9214..1936752 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -567,20 +567,18 @@ void intel_audio_codec_disable(struct
> > intel_encoder *intel_encoder)
> > * intel_init_audio - Set up chip specific audio functions
> > * @dev: drm device
> > */
> > -void intel_init_audio(struct drm_device *dev)
> > +void intel_init_audio_callbacks(struct drm_i915_private *dev_priv)
> > {
> > - struct drm_i915_private *dev_priv = dev->dev_private;
> > -
> > - if (IS_G4X(dev)) {
> > + if (IS_G4X(dev_priv)) {
> > dev_priv->display.audio_codec_enable =
> > g4x_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > g4x_audio_codec_disable;
> > - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > + } else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.audio_codec_enable =
> > ilk_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > ilk_audio_codec_disable;
> > - } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
> > + } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)-
> > >gen >= 8) {
> > dev_priv->display.audio_codec_enable =
> > hsw_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > hsw_audio_codec_disable;
> > - } else if (HAS_PCH_SPLIT(dev)) {
> > + } else if (HAS_PCH_SPLIT(dev_priv)) {
> > dev_priv->display.audio_codec_enable =
> > ilk_audio_codec_enable;
> > dev_priv->display.audio_codec_disable =
> > ilk_audio_codec_disable;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 62d36a7..5170718 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15095,22 +15095,20 @@ static const struct drm_mode_config_funcs
> > intel_mode_funcs = {
> > };
> >
> > /* Set up chip specific display functions */
> > -static void intel_init_display(struct drm_device *dev)
> > +void intel_init_display_callbacks(struct drm_i915_private
> > *dev_priv)
> > {
> > - struct drm_i915_private *dev_priv = dev->dev_private;
> > -
> > - if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
> > + if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
> > dev_priv->display.find_dpll = g4x_find_best_dpll;
> > - else if (IS_CHERRYVIEW(dev))
> > + else if (IS_CHERRYVIEW(dev_priv))
> > dev_priv->display.find_dpll = chv_find_best_dpll;
> > - else if (IS_VALLEYVIEW(dev))
> > + else if (IS_VALLEYVIEW(dev_priv))
> > dev_priv->display.find_dpll = vlv_find_best_dpll;
> > - else if (IS_PINEVIEW(dev))
> > + else if (IS_PINEVIEW(dev_priv))
> > dev_priv->display.find_dpll = pnv_find_best_dpll;
> > else
> > dev_priv->display.find_dpll = i9xx_find_best_dpll;
> >
> > - if (INTEL_INFO(dev)->gen >= 9) {
> > + if (INTEL_INFO(dev_priv)->gen >= 9) {
> > dev_priv->display.get_pipe_config =
> > haswell_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > skylake_get_initial_plane_config;
> > @@ -15118,7 +15116,7 @@ static void intel_init_display(struct
> > drm_device *dev)
> > haswell_crtc_compute_clock;
> > dev_priv->display.crtc_enable =
> > haswell_crtc_enable;
> > dev_priv->display.crtc_disable =
> > haswell_crtc_disable;
> > - } else if (HAS_DDI(dev)) {
> > + } else if (HAS_DDI(dev_priv)) {
> > dev_priv->display.get_pipe_config =
> > haswell_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > ironlake_get_initial_plane_config;
> > @@ -15126,7 +15124,7 @@ static void intel_init_display(struct
> > drm_device *dev)
> > haswell_crtc_compute_clock;
> > dev_priv->display.crtc_enable =
> > haswell_crtc_enable;
> > dev_priv->display.crtc_disable =
> > haswell_crtc_disable;
> > - } else if (HAS_PCH_SPLIT(dev)) {
> > + } else if (HAS_PCH_SPLIT(dev_priv)) {
> > dev_priv->display.get_pipe_config =
> > ironlake_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > ironlake_get_initial_plane_config;
> > @@ -15134,7 +15132,7 @@ static void intel_init_display(struct
> > drm_device *dev)
> > ironlake_crtc_compute_clock;
> > dev_priv->display.crtc_enable =
> > ironlake_crtc_enable;
> > dev_priv->display.crtc_disable =
> > ironlake_crtc_disable;
> > - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > + } else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.get_pipe_config =
> > i9xx_get_pipe_config;
> > dev_priv->display.get_initial_plane_config =
> > i9xx_get_initial_plane_config;
> > @@ -15151,89 +15149,89 @@ static void intel_init_display(struct
> > drm_device *dev)
> > }
> >
> > /* Returns the core display clock speed */
> > - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> > + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > skylake_get_display_clock_speed;
> > - else if (IS_BROXTON(dev))
> > + else if (IS_BROXTON(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > broxton_get_display_clock_speed;
> > - else if (IS_BROADWELL(dev))
> > + else if (IS_BROADWELL(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > broadwell_get_display_clock_speed;
> > - else if (IS_HASWELL(dev))
> > + else if (IS_HASWELL(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > haswell_get_display_clock_speed;
> > - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > + else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > valleyview_get_display_clock_speed;
> > - else if (IS_GEN5(dev))
> > + else if (IS_GEN5(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > ilk_get_display_clock_speed;
> > - else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
> > - IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> > + else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
> > + IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i945_get_display_clock_speed;
> > - else if (IS_GM45(dev))
> > + else if (IS_GM45(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > gm45_get_display_clock_speed;
> > - else if (IS_CRESTLINE(dev))
> > + else if (IS_CRESTLINE(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i965gm_get_display_clock_speed;
> > - else if (IS_PINEVIEW(dev))
> > + else if (IS_PINEVIEW(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > pnv_get_display_clock_speed;
> > - else if (IS_G33(dev) || IS_G4X(dev))
> > + else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > g33_get_display_clock_speed;
> > - else if (IS_I915G(dev))
> > + else if (IS_I915G(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i915_get_display_clock_speed;
> > - else if (IS_I945GM(dev) || IS_845G(dev))
> > + else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i9xx_misc_get_display_clock_speed;
> > - else if (IS_I915GM(dev))
> > + else if (IS_I915GM(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i915gm_get_display_clock_speed;
> > - else if (IS_I865G(dev))
> > + else if (IS_I865G(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i865_get_display_clock_speed;
> > - else if (IS_I85X(dev))
> > + else if (IS_I85X(dev_priv))
> > dev_priv->display.get_display_clock_speed =
> > i85x_get_display_clock_speed;
> > else { /* 830 */
> > - WARN(!IS_I830(dev), "Unknown platform. Assuming
> > 133 MHz CDCLK\n");
> > + WARN(!IS_I830(dev_priv), "Unknown platform.
> > Assuming 133 MHz CDCLK\n");
> > dev_priv->display.get_display_clock_speed =
> > i830_get_display_clock_speed;
> > }
> >
> > - if (IS_GEN5(dev)) {
> > + if (IS_GEN5(dev_priv)) {
> > dev_priv->display.fdi_link_train =
> > ironlake_fdi_link_train;
> > - } else if (IS_GEN6(dev)) {
> > + } else if (IS_GEN6(dev_priv)) {
> > dev_priv->display.fdi_link_train =
> > gen6_fdi_link_train;
> > - } else if (IS_IVYBRIDGE(dev)) {
> > + } else if (IS_IVYBRIDGE(dev_priv)) {
> > /* FIXME: detect B0+ stepping and use auto
> > training */
> > dev_priv->display.fdi_link_train =
> > ivb_manual_fdi_link_train;
> > - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> > + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > {
> > dev_priv->display.fdi_link_train =
> > hsw_fdi_link_train;
> > - if (IS_BROADWELL(dev)) {
> > + if (IS_BROADWELL(dev_priv)) {
> > dev_priv->display.modeset_commit_cdclk =
> > broadwell_modeset_commit_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > broadwell_modeset_calc_cdclk;
> > }
> > - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > + } else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->display.modeset_commit_cdclk =
> > valleyview_modeset_commit_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > valleyview_modeset_calc_cdclk;
> > - } else if (IS_BROXTON(dev)) {
> > + } else if (IS_BROXTON(dev_priv)) {
> > dev_priv->display.modeset_commit_cdclk =
> > broxton_modeset_commit_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > broxton_modeset_calc_cdclk;
> > }
> >
> > - switch (INTEL_INFO(dev)->gen) {
> > + switch (INTEL_INFO(dev_priv)->gen) {
> > case 2:
> > dev_priv->display.queue_flip =
> > intel_gen2_queue_flip;
> > break;
> > @@ -15260,8 +15258,6 @@ static void intel_init_display(struct
> > drm_device *dev)
> > /* Default just returns -ENODEV to indicate
> > unsupported */
> > dev_priv->display.queue_flip =
> > intel_default_queue_flip;
> > }
> > -
> > - mutex_init(&dev_priv->pps_mutex);
> > }
> >
> > /*
> > @@ -15588,9 +15584,6 @@ void intel_modeset_init(struct drm_device
> > *dev)
> > }
> > }
> >
> > - intel_init_display(dev);
> > - intel_init_audio(dev);
> > -
> > if (IS_GEN2(dev)) {
> > dev->mode_config.max_width = 2048;
> > dev->mode_config.max_height = 2048;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 7b2d66d..5264901 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1110,7 +1110,7 @@ u32 intel_fb_stride_alignment(const struct
> > drm_i915_private *dev_priv,
> > uint64_t fb_modifier, uint32_t
> > pixel_format);
> >
> > /* intel_audio.c */
> > -void intel_init_audio(struct drm_device *dev);
> > +void intel_init_audio_callbacks(struct drm_i915_private
> > *dev_priv);
> > void intel_audio_codec_enable(struct intel_encoder *encoder);
> > void intel_audio_codec_disable(struct intel_encoder *encoder);
> > void i915_audio_component_init(struct drm_i915_private *dev_priv);
> > @@ -1118,6 +1118,7 @@ void i915_audio_component_cleanup(struct
> > drm_i915_private *dev_priv);
> >
> > /* intel_display.c */
> > extern const struct drm_plane_funcs intel_plane_funcs;
> > +void intel_init_display_callbacks(struct drm_i915_private
> > *dev_priv);
> > unsigned int intel_rotation_info_size(const struct
> > intel_rotation_info *rot_info);
> > bool intel_has_pending_fb_unpin(struct drm_device *dev);
> > void intel_mark_busy(struct drm_device *dev);
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2016-03-11 14:17 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-09 15:31 [PATCH 0/7] drm/i915: Move some load time init steps earlier Imre Deak
2016-03-09 15:31 ` [PATCH 1/7] drm/i915: Add comments marking the start of load time init phases Imre Deak
2016-03-09 15:31 ` [PATCH 2/7] drm/i915: Move laod time PCH detect, DPIO, power domain SW init earlier Imre Deak
2016-03-09 15:31 ` [PATCH 3/7] drm/i915: Move load time IRQ " Imre Deak
2016-03-09 15:31 ` [PATCH 4/7] drm/i915: Move load time display/audio callback " Imre Deak
2016-03-09 17:14 ` kbuild test robot
2016-03-10 8:58 ` Ander Conselvan De Oliveira
2016-03-10 11:24 ` Imre Deak
2016-03-11 14:00 ` Jani Nikula
2016-03-11 14:17 ` Imre Deak
2016-03-09 15:31 ` [PATCH 5/7] drm/i915: Move load time clock gating " Imre Deak
2016-03-09 15:57 ` Chris Wilson
2016-03-09 16:01 ` Imre Deak
2016-03-09 16:09 ` Chris Wilson
2016-03-09 15:31 ` [PATCH 6/7] drm/i915: Move load time runtime device info " Imre Deak
2016-03-09 15:31 ` [PATCH 7/7] drm/i915: Move load time runtime PM get later Imre Deak
2016-03-09 16:02 ` ✗ Fi.CI.BAT: warning for drm/i915: Move some load time init steps earlier Patchwork
2016-03-09 16:03 ` [PATCH 0/7] " Chris Wilson
2016-03-10 18:37 ` Imre Deak
2016-03-11 13:59 ` Jani Nikula
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