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From: "Michał Winiarski" <michal.winiarski@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
Date: Mon, 14 Mar 2016 19:24:56 +0100	[thread overview]
Message-ID: <1457979896-7967-1-git-send-email-michal.winiarski@intel.com> (raw)

On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6fcbf6b..8fabca5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1933,7 +1933,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
 	 * need a prior CS_STALL, which is emitted by the flush
 	 * following the batch.
 	 */
-	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
+	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
 	intel_logical_ring_emit(ringbuf,
 				(PIPE_CONTROL_GLOBAL_GTT_IVB |
 				 PIPE_CONTROL_CS_STALL |
@@ -1941,6 +1941,7 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
 	intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
 	intel_logical_ring_emit(ringbuf, 0);
 	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+	intel_logical_ring_emit(ringbuf, 0);
 	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
 	return intel_logical_ring_advance_and_submit(request);
 }
-- 
2.7.1

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             reply	other threads:[~2016-03-14 18:25 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-14 18:24 Michał Winiarski [this message]
2016-03-14 19:48 ` [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Chris Wilson
2016-03-15  7:32 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-03-15  9:20 ` [PATCH v2] " Michał Winiarski
2016-03-15 10:01   ` Chris Wilson
2016-03-15 17:52   ` [PATCH v3] " Michał Winiarski
2016-03-15 10:37 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2) Patchwork
2016-03-16  6:57 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3) Patchwork

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