From: Chris Wilson <chris@chris-wilson.co.uk>
To: "Michał Winiarski" <michal.winiarski@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
Date: Tue, 15 Mar 2016 10:01:22 +0000 [thread overview]
Message-ID: <20160315100121.GU14143@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1458033609-28865-1-git-send-email-michal.winiarski@intel.com>
On Tue, Mar 15, 2016 at 10:20:09AM +0100, Michał Winiarski wrote:
> On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.
But gen8/gen9 still respect 5 for a dword write instead of a qword write.
Please include an explanation of the impact.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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next prev parent reply other threads:[~2016-03-15 10:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-14 18:24 [PATCH] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Michał Winiarski
2016-03-14 19:48 ` Chris Wilson
2016-03-15 7:32 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-03-15 9:20 ` [PATCH v2] " Michał Winiarski
2016-03-15 10:01 ` Chris Wilson [this message]
2016-03-15 17:52 ` [PATCH v3] " Michał Winiarski
2016-03-15 10:37 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2) Patchwork
2016-03-16 6:57 ` ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev3) Patchwork
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