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From: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Subject: [PATCH 03/15] drm/i915: Fold intel_ironlake_limit() into clock computation function
Date: Mon, 21 Mar 2016 18:00:04 +0200	[thread overview]
Message-ID: <1458576016-30348-4-git-send-email-ander.conselvan.de.oliveira@intel.com> (raw)
In-Reply-To: <1458576016-30348-1-git-send-email-ander.conselvan.de.oliveira@intel.com>

The funcion intel_ironlake_limit() is only called by the crtc compute
clock path. By merging it into ironlake_compute_clocks(), the code gets
clearer, since there's no more if-ladders to follow.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 56 +++++++++++++++---------------------
 1 file changed, 23 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 47cd1f0..459b188 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -568,30 +568,6 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 }
 
 static const intel_limit_t *
-intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
-{
-	struct drm_device *dev = crtc_state->base.crtc->dev;
-	const intel_limit_t *limit;
-
-	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
-		if (intel_is_dual_link_lvds(dev)) {
-			if (refclk == 100000)
-				limit = &intel_limits_ironlake_dual_lvds_100m;
-			else
-				limit = &intel_limits_ironlake_dual_lvds;
-		} else {
-			if (refclk == 100000)
-				limit = &intel_limits_ironlake_single_lvds_100m;
-			else
-				limit = &intel_limits_ironlake_single_lvds;
-		}
-	} else
-		limit = &intel_limits_ironlake_dac;
-
-	return limit;
-}
-
-static const intel_limit_t *
 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = crtc_state->base.crtc->dev;
@@ -621,8 +597,8 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 
 	if (IS_BROXTON(dev))
 		limit = &intel_limits_bxt;
-	else if (HAS_PCH_SPLIT(dev))
-		limit = intel_ironlake_limit(crtc_state, refclk);
+	else if (WARN_ON(HAS_PCH_SPLIT(dev)))
+		limit = NULL;
 	else if (IS_G4X(dev)) {
 		limit = intel_g4x_limit(crtc_state);
 	} else if (IS_PINEVIEW(dev)) {
@@ -8799,13 +8775,28 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	const intel_limit_t *limit;
 	bool ret;
 
-	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
-	    intel_panel_use_ssc(dev_priv)) {
-		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
-			      dev_priv->vbt.lvds_ssc_freq);
-		refclk = dev_priv->vbt.lvds_ssc_freq;
+	refclk = 120000;
+
+	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
+		if (intel_panel_use_ssc(dev_priv)) {
+			DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
+				      dev_priv->vbt.lvds_ssc_freq);
+			refclk = dev_priv->vbt.lvds_ssc_freq;
+		}
+
+		if (intel_is_dual_link_lvds(dev)) {
+			if (refclk == 100000)
+				limit = &intel_limits_ironlake_dual_lvds_100m;
+			else
+				limit = &intel_limits_ironlake_dual_lvds;
+		} else {
+			if (refclk == 100000)
+				limit = &intel_limits_ironlake_single_lvds_100m;
+			else
+				limit = &intel_limits_ironlake_single_lvds;
+		}
 	} else {
-		refclk = 120000;
+		limit = &intel_limits_ironlake_dac;
 	}
 
 	/*
@@ -8813,7 +8804,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	 * refclk, or FALSE.  The returned values represent the clock equation:
 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 	 */
-	limit = intel_limit(crtc_state, refclk);
 	ret = dev_priv->display.find_dpll(limit, crtc_state,
 					  crtc_state->port_clock,
 					  refclk, NULL, clock);
-- 
2.4.3

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  parent reply	other threads:[~2016-03-21 16:00 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-21 16:00 [PATCH v3 00/15] Clean up ironlake clock computation code Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 01/15] drm/i915: Remove checks for cloned config with LVDS in dpll code Ander Conselvan de Oliveira
2016-03-22 10:11   ` Ville Syrjälä
2016-03-21 16:00 ` [PATCH 02/15] drm/i915: Merge ironlake_get_refclk() into its only caller Ander Conselvan de Oliveira
2016-03-21 16:00 ` Ander Conselvan de Oliveira [this message]
2016-03-21 16:00 ` [PATCH 04/15] drm/i915: Call g4x_find_best_dpll() directly from ILK+ code Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 05/15] drm/i915: Simplify ironlake reduced clock logic a bit Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 06/15] drm/i915: Don't calculate a new clock in ILK+ code if it is already set Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 07/15] drm/i915: Remove PCH type checks from ironlake_crtc_compute_clock() Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 08/15] drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 09/15] drm/i915: Pass crtc_state->dpll directly to ->find_dpll() Ander Conselvan de Oliveira
2016-03-22 10:18   ` Ville Syrjälä
2016-03-21 16:00 ` [PATCH 10/15] drm/i915: Move fp divisor calculation into ironlake_compute_dpll() Ander Conselvan de Oliveira
2016-03-22 12:49   ` Ville Syrjälä
2016-03-22 13:22     ` Ander Conselvan De Oliveira
2016-03-21 16:00 ` [PATCH 11/15] drm/i915: Merge ironlake_compute_clocks() and ironlake_crtc_compute_clock() Ander Conselvan de Oliveira
2016-03-22 12:51   ` Ville Syrjälä
2016-03-21 16:00 ` [PATCH 12/15] drm/i915: Split CHV and VLV specific crtc_compute_clock() hooks Ander Conselvan de Oliveira
2016-03-22 10:26   ` Ville Syrjälä
2016-03-21 16:00 ` [PATCH 13/15] drm/i915: Split gen2_crtc_compute_clock() Ander Conselvan de Oliveira
2016-03-22 10:24   ` Ville Syrjälä
2016-03-22 11:11     ` Daniel Vetter
2016-03-22 13:35       ` [PATCH v2 13/15] drm/i915: Split i8xx_crtc_compute_clock() Ander Conselvan de Oliveira
2016-03-21 16:00 ` [PATCH 14/15] drm/i915: Split g4x_crtc_compute_clock() Ander Conselvan de Oliveira
2016-03-22 12:52   ` Ville Syrjälä
2016-03-21 16:00 ` [PATCH 15/15] drm/i915: Split PNV version of crtc_compute_clock() Ander Conselvan de Oliveira
2016-03-22 12:55   ` Ville Syrjälä
2016-03-22  9:33 ` ✗ Fi.CI.BAT: warning for Clean up ironlake clock computation code (rev3) Patchwork
2016-03-22 14:32 ` ✓ Fi.CI.BAT: success for Clean up ironlake clock computation code (rev4) Patchwork
2016-03-23 12:26   ` Ander Conselvan De Oliveira

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