* [PATCH linux v4 0/4] Updated SCU88 register and SCU90 init values
@ 2016-03-22 5:30 OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 1/4] " OpenBMC Patches
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: OpenBMC Patches @ 2016-03-22 5:30 UTC (permalink / raw)
To: openbmc
Before This change:
a) SCU90[0]=1, function pin Incorrectly defined. It must be pull down internally.
b) For SCU88, bits 7:0 were set to 1. That is: We were reading : PWMx or VPIGx instead of GPIONx (GPIONx gives us the PCIe inventory status, where x is bit number). Because of this PCIe inventory was showing up wrong.
After This Change:
a) SCU90[0]=0
b) Bits (7:0) of SCU 88 are set to 0 . (According to Page 111 of data sheet these have to be set to 0 for us to to read GPION0 to GPIO N7 which indicate if PCIe device is present ).
Description of pins 0 of SCU 90:
Enable SD1 Function Pin
Description of pins 7:0 of SCU 88:
7 RW Enable PWM7 or VPIG7 function pin (SCU90[5:4]=0x2 select Video pin)
6 RW Enable PWM6 or VPIG6 function pin (SCU90[5:4]=0x2 select Video pin)
5 RW Enable PWM5 or VPIG5 function pin (SCU90[5:4]!=0 select Video pin)
4 RW Enable PWM4 or VPIG4 function pin (SCU90[5:4]!=0 select Video pin)
3 RW Enable PWM3 or VPIG3 function pin (SCU90[5:4]!=0 select Video pin)
2 RW Enable PWM2 or VPIG2 function pin (SCU90[5:4]!=0 select Video pin)
1 RW Enable PWM1 or VPIG1 function pin (SCU90[5:4]=0x3 select Video pin)
0 RW Enable PWM0 or VPIG0 function pin (SCU90[5:4]=0x3 select Video pin)
<!-- Reviewable:start -->
---
This change is [<img src="https://reviewable.io/review_button.svg" height="35" align="absmiddle" alt="Reviewable"/>](https://reviewable.io/reviews/openbmc/linux/63)
<!-- Reviewable:end -->
https://github.com/openbmc/linux/pull/63
Adi Gangidi (4):
Updated SCU88 register and SCU90 init values
Barreleye SCU88 Setup to do_barreleye_setup
Updated SCU88 register and SCU90 init values
Updated SCU88 register and SCU90 init values
arch/arm/mach-aspeed/aspeed.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--
2.7.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH linux v4 1/4] Updated SCU88 register and SCU90 init values
2016-03-22 5:30 [PATCH linux v4 0/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
@ 2016-03-22 5:30 ` OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 2/4] Barreleye SCU88 Setup to do_barreleye_setup OpenBMC Patches
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: OpenBMC Patches @ 2016-03-22 5:30 UTC (permalink / raw)
To: openbmc; +Cc: Adi Gangidi
From: Adi Gangidi <adi.gangidi@rackspace.com>
Before This change:
a) SCU90[0]=1, function pin Incorrectly defined. It must be pull down internally.
b) For SCU88, bits 7:0 were set to 1. That is: We were reading : PWMx or VPIGx instead of GPIONx (GPIONx gives us the PCIe inventory status, where x is bit number). Because of this PCIe inventory was showing up wrong.
After This Change:
a) SCU90[0]=0
b) Bits (7:0) of SCU 88 are set to 0 . (According to Page 111 of data sheet these have to be set to 0 for us to to read GPION0 to GPIO N7 which indicate if PCIe device is present ).
Description of pins 0 of SCU 90:
Enable SD1 Function Pin
Description of pins 7:0 of SCU 88:
7 RW Enable PWM7 or VPIG7 function pin (SCU90[5:4]=0x2 select Video pin)
6 RW Enable PWM6 or VPIG6 function pin (SCU90[5:4]=0x2 select Video pin)
5 RW Enable PWM5 or VPIG5 function pin (SCU90[5:4]!=0 select Video pin)
4 RW Enable PWM4 or VPIG4 function pin (SCU90[5:4]!=0 select Video pin)
3 RW Enable PWM3 or VPIG3 function pin (SCU90[5:4]!=0 select Video pin)
2 RW Enable PWM2 or VPIG2 function pin (SCU90[5:4]!=0 select Video pin)
1 RW Enable PWM1 or VPIG1 function pin (SCU90[5:4]=0x3 select Video pin)
0 RW Enable PWM0 or VPIG0 function pin (SCU90[5:4]=0x3 select Video pin)
---
arch/arm/mach-aspeed/aspeed.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 15672f5..684c1b7 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -118,8 +118,8 @@ static void __init do_common_setup(void)
/* SCU setup */
writel(0x01C000FF, AST_IO(AST_BASE_SCU | 0x88));
writel(0xC1C000FF, AST_IO(AST_BASE_SCU | 0x8c));
- writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
- writel(0x003FA009, AST_IO(AST_BASE_SCU | 0x90));
+ writel(0x01C00000, AST_IO(AST_BASE_SCU | 0x88));
+ writel(0x003FA008, AST_IO(AST_BASE_SCU | 0x90));
/* Setup scratch registers */
writel(0x00000042, AST_IO(AST_BASE_LPC | 0x170));
--
2.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH linux v4 2/4] Barreleye SCU88 Setup to do_barreleye_setup
2016-03-22 5:30 [PATCH linux v4 0/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 1/4] " OpenBMC Patches
@ 2016-03-22 5:30 ` OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 3/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 4/4] " OpenBMC Patches
3 siblings, 0 replies; 5+ messages in thread
From: OpenBMC Patches @ 2016-03-22 5:30 UTC (permalink / raw)
To: openbmc; +Cc: Adi Gangidi
From: Adi Gangidi <adi.gangidi@rackspace.com>
I moved the Barreleye SCU88 Setup to do_barreleye_setup. This way the SCU88 value gets overwritten to 0x01C00000 only for Barreleye. For Palmetto it remains what it was previously.
SCU 90 Setup though is common for chip sets we have, so it still remains in common setup.
---
arch/arm/mach-aspeed/aspeed.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 684c1b7..143a45e 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -118,7 +118,7 @@ static void __init do_common_setup(void)
/* SCU setup */
writel(0x01C000FF, AST_IO(AST_BASE_SCU | 0x88));
writel(0xC1C000FF, AST_IO(AST_BASE_SCU | 0x8c));
- writel(0x01C00000, AST_IO(AST_BASE_SCU | 0x88));
+ writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
writel(0x003FA008, AST_IO(AST_BASE_SCU | 0x90));
/* Setup scratch registers */
@@ -139,6 +139,10 @@ static void __init do_barreleye_setup(void)
/* GPIO setup */
writel(0x9E82FCE7, AST_IO(AST_BASE_GPIO | 0x00));
writel(0x0370E677, AST_IO(AST_BASE_GPIO | 0x04));
+
+ /* Barreleye SCU setup for PCIe Inventory */
+ writel(0x01C00000, AST_IO(AST_BASE_SCU | 0x88));
+
/*
* Do read/modify/write on power gpio to prevent resetting power on
--
2.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH linux v4 3/4] Updated SCU88 register and SCU90 init values
2016-03-22 5:30 [PATCH linux v4 0/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 1/4] " OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 2/4] Barreleye SCU88 Setup to do_barreleye_setup OpenBMC Patches
@ 2016-03-22 5:30 ` OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 4/4] " OpenBMC Patches
3 siblings, 0 replies; 5+ messages in thread
From: OpenBMC Patches @ 2016-03-22 5:30 UTC (permalink / raw)
To: openbmc; +Cc: Adi Gangidi
From: Adi Gangidi <adi.gangidi@rackspace.com>
a) Updated SCU88 init value in barreleye init
b) Updated SCU90 init values in common init
c) Removed some some white spaces
---
arch/arm/mach-aspeed/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 143a45e..5c18316 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -118,7 +118,7 @@ static void __init do_common_setup(void)
/* SCU setup */
writel(0x01C000FF, AST_IO(AST_BASE_SCU | 0x88));
writel(0xC1C000FF, AST_IO(AST_BASE_SCU | 0x8c));
- writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
+ writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
writel(0x003FA008, AST_IO(AST_BASE_SCU | 0x90));
/* Setup scratch registers */
--
2.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH linux v4 4/4] Updated SCU88 register and SCU90 init values
2016-03-22 5:30 [PATCH linux v4 0/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
` (2 preceding siblings ...)
2016-03-22 5:30 ` [PATCH linux v4 3/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
@ 2016-03-22 5:30 ` OpenBMC Patches
3 siblings, 0 replies; 5+ messages in thread
From: OpenBMC Patches @ 2016-03-22 5:30 UTC (permalink / raw)
To: openbmc; +Cc: Adi Gangidi
From: Adi Gangidi <adi.gangidi@rackspace.com>
a) Updated SCU88 init value in barreleye init
b) Updated SCU90 init values in common init
c) Removed some some white spaces
---
arch/arm/mach-aspeed/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 5c18316..fa76c40 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -118,7 +118,7 @@ static void __init do_common_setup(void)
/* SCU setup */
writel(0x01C000FF, AST_IO(AST_BASE_SCU | 0x88));
writel(0xC1C000FF, AST_IO(AST_BASE_SCU | 0x8c));
- writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
+ writel(0x01C0007F, AST_IO(AST_BASE_SCU | 0x88));
writel(0x003FA008, AST_IO(AST_BASE_SCU | 0x90));
/* Setup scratch registers */
--
2.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-03-22 5:31 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2016-03-22 5:30 [PATCH linux v4 0/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 1/4] " OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 2/4] Barreleye SCU88 Setup to do_barreleye_setup OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 3/4] Updated SCU88 register and SCU90 init values OpenBMC Patches
2016-03-22 5:30 ` [PATCH linux v4 4/4] " OpenBMC Patches
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