From: <tthayer@opensource.altera.com>
To: <bp@alien8.de>, <dougthompson@xmission.com>,
<m.chehab@samsung.com>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<linux@arm.linux.org.uk>, <dinguyen@opensource.altera.com>,
<grant.likely@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<tthayer@opensource.altera.com>
Subject: [PATCH 4/7] Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding
Date: Wed, 30 Mar 2016 10:27:45 -0500 [thread overview]
Message-ID: <1459351668-14622-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1459351668-14622-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 37ff9bf..2f409d5 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -71,6 +71,11 @@ Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
+On-Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-a10-ocram-ecc"
+- reg : Address and size for ECC block registers.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -86,4 +91,9 @@ Example:
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
};
+
+ ocram-ecc@ff8c3000 {
+ compatible = "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8c3000 0x90>;
+ };
};
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: <tthayer@opensource.altera.com>
To: bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
tthayer@opensource.altera.com
Subject: [PATCH 4/7] Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding
Date: Wed, 30 Mar 2016 10:27:45 -0500 [thread overview]
Message-ID: <1459351668-14622-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1459351668-14622-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 37ff9bf..2f409d5 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -71,6 +71,11 @@ Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
+On-Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-a10-ocram-ecc"
+- reg : Address and size for ECC block registers.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -86,4 +91,9 @@ Example:
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
};
+
+ ocram-ecc@ff8c3000 {
+ compatible = "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8c3000 0x90>;
+ };
};
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: tthayer@opensource.altera.com (tthayer at opensource.altera.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/7] Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding
Date: Wed, 30 Mar 2016 10:27:45 -0500 [thread overview]
Message-ID: <1459351668-14622-5-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1459351668-14622-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 37ff9bf..2f409d5 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -71,6 +71,11 @@ Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
+On-Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-a10-ocram-ecc"
+- reg : Address and size for ECC block registers.
+
Example:
eccmgr: eccmgr at ffd06000 {
@@ -86,4 +91,9 @@ Example:
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
};
+
+ ocram-ecc at ff8c3000 {
+ compatible = "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8c3000 0x90>;
+ };
};
--
1.7.9.5
next prev parent reply other threads:[~2016-03-30 15:23 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 15:27 [PATCH] Addition of Altera Arria10 On-Chip RAM ECC tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-03-30 15:27 ` [PATCH 1/7] EDAC, altera: New file operations for Arria10 ECC modules tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-03-30 15:27 ` [PATCH 2/7] EDAC, altera: Add register offset for ECC Enable tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-03-30 15:27 ` [PATCH 3/7] EDAC, altera: Make OCRAM ECC dependency check generic tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-03-30 15:27 ` tthayer [this message]
2016-03-30 15:27 ` [PATCH 4/7] Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-04-01 17:03 ` Rob Herring
2016-04-01 17:03 ` Rob Herring
2016-04-01 17:03 ` Rob Herring
2016-03-30 15:27 ` [PATCH 5/7] EDAC, altera: Addition of Arria10 OCRAM ECC tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-03-30 15:27 ` [PATCH 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
2016-03-30 17:11 ` Dinh Nguyen
2016-03-30 17:11 ` Dinh Nguyen
2016-03-30 17:11 ` Dinh Nguyen
2016-03-31 16:08 ` Thor Thayer
2016-03-31 16:08 ` Thor Thayer
2016-03-31 16:08 ` Thor Thayer
2016-03-30 15:27 ` [PATCH 7/7] ARM: dts: Add Altera Arria10 OCRAM EDAC devicetree entry tthayer
2016-03-30 15:27 ` tthayer at opensource.altera.com
2016-03-30 15:27 ` tthayer
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