[PATCH 0/3] drm/i915: Exorcise ilk underruns

[PATCH 0/3] drm/i915: Exorcise ilk underruns

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With this series I seem to have succeeded in eliminating all the underruns
from my ILK. Let's hope it's as effective for others as well.

Ville Syrjälä (3):
  drm/i915: Try to shut up more ILK underruns
  drm/i915: Make sure LP1+ watermarks levels are preserved when going
    from 1 to 2 pipes
  drm/i915: Replace ILK eDP underrun suppression with something better

 drivers/gpu/drm/i915/intel_display.c | 45 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_dp.c      | 48 +++++++-----------------------------
 drivers/gpu/drm/i915/intel_pm.c      |  2 +-
 3 files changed, 33 insertions(+), 62 deletions(-)

-- 
2.7.4

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[PATCH 1/3] drm/i915: Try to shut up more ILK underruns

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Take a bigger hammer to the underrun suppression on ILK. Instead of
trying to suppress them at specific points in the modeset sequence just
silence them across the entire sequence. This gets rid of some underruns
at least on my ILK. Note that this changes SNB and IVB to follow the
same approach just to keep the code less convoluted. The difference is
that on those platforms we won't suppress CPU underruns for port A since
it doesn't seem to be necessary.

My ILK has port A eDP and two PCH HDMI ports, so I can't be sure this is
as effective on other PCH port types. Perhaps we still need some of
Daniel's extra vblank waits [2]?

I've still been able to trigger an underrun on the other pipe, but
fixing that perhaps needs the LP1+ disable trick I implemented here [1]
which never got merged.

A few details which hamper stress testing on my ILK are that sometimes
the PCH transcoder gets messed up and refuses to shut down, and sometimes
even the panel power sequencer apparently gets stuck on the always on
position.

[1] https://lists.freedesktop.org/archives/intel-gfx/2014-March/041317.html
[2] https://lists.freedesktop.org/archives/intel-gfx/2016-January/086397.html

v2: Add a note that we also get underruns when enabling PCH ports

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)
---
 drivers/gpu/drm/i915/intel_display.c | 45 ++++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_dp.c      | 12 ----------
 2 files changed, 23 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e6b5ee51739b..8d2c547b57ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4083,12 +4083,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(FDI_RX_TUSIZE1(pipe),
 		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
 
-	/*
-	 * Sometimes spurious CPU pipe underruns happen during FDI
-	 * training, at least with VGA+HDMI cloning. Suppress them.
-	 */
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 	/* For PCH output, training FDI link */
 	dev_priv->display.fdi_link_train(crtc);
 
@@ -4123,8 +4117,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 
 	intel_fdi_normal_train(crtc);
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
 		const struct drm_display_mode *adjusted_mode =
@@ -4727,6 +4719,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	if (WARN_ON(intel_crtc->active))
 		return;
 
+	/*
+	 * Sometimes spurious CPU pipe underruns happen during FDI
+	 * training, at least with VGA+HDMI cloning. Suppress them.
+	 *
+	 * On ILK we get an occasional spurious CPU pipe underruns
+	 * between eDP port A enable and vdd enable. Also PCH port
+	 * enable seems to result in the occasional CPU pipe underrun.
+	 *
+	 * Spurious PCH underruns also occur during PCH enabling.
+	 */
+	if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 	if (intel_crtc->config->has_pch_encoder)
 		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
 
@@ -4748,8 +4752,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	intel_crtc->active = true;
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
@@ -4791,6 +4793,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	/* Must wait for vblank to avoid spurious PCH FIFO underruns */
 	if (intel_crtc->config->has_pch_encoder)
 		intel_wait_for_vblank(dev, pipe);
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
@@ -4943,8 +4946,15 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 
-	if (intel_crtc->config->has_pch_encoder)
+	/*
+	 * Sometimes spurious CPU pipe underruns happen when the
+	 * pipe is already disabled, but FDI RX/TX is still enabled.
+	 * Happens at least with VGA+HDMI cloning. Suppress them.
+	 */
+	if (intel_crtc->config->has_pch_encoder) {
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
+	}
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->disable(encoder);
@@ -4952,22 +4962,12 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	drm_crtc_vblank_off(crtc);
 	assert_vblank_disabled(crtc);
 
-	/*
-	 * Sometimes spurious CPU pipe underruns happen when the
-	 * pipe is already disabled, but FDI RX/TX is still enabled.
-	 * Happens at least with VGA+HDMI cloning. Suppress them.
-	 */
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 	intel_disable_pipe(intel_crtc);
 
 	ironlake_pfit_disable(intel_crtc, false);
 
-	if (intel_crtc->config->has_pch_encoder) {
+	if (intel_crtc->config->has_pch_encoder)
 		ironlake_fdi_disable(crtc);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-	}
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->post_disable)
@@ -4997,6 +4997,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 		ironlake_fdi_pll_disable(intel_crtc);
 	}
 
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da0c3d29fda8..95fe01d55bce 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2641,15 +2641,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		vlv_init_panel_power_sequencer(intel_dp);
 
-	/*
-	 * We get an occasional spurious underrun between the port
-	 * enable and vdd enable, when enabling port A eDP.
-	 *
-	 * FIXME: Not sure if this applies to (PCH) port D eDP as well
-	 */
-	if (port == PORT_A)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 	intel_dp_enable_port(intel_dp);
 
 	if (port == PORT_A && IS_GEN5(dev_priv)) {
@@ -2667,9 +2658,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 	edp_panel_on(intel_dp);
 	edp_panel_vdd_off(intel_dp, true);
 
-	if (port == PORT_A)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	pps_unlock(intel_dp);
 
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-- 
2.7.4

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[PATCH 2/3] drm/i915: Make sure LP1+ watermarks levels are preserved when going from 1 to 2 pipes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Once again ILK is unhappy if we clear out the LP1+ watermark levels
outright, and instead we must disable the levels we don't want while
still leaving the actual programmed watermark levels intact.

Fixes underruns on the already enabled pipe when programming watermarks
while enabling the second pipe.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Matt Roper <matthew.d.roper@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93787
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9bc9c25423e9..a7fd5d464838 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2483,7 +2483,7 @@ static void ilk_wm_merge(struct drm_device *dev,
 	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
 	if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
 	    config->num_pipes_active > 1)
-		return;
+		last_enabled_level = 0;
 
 	/* ILK: FBC WM must be disabled always */
 	merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
-- 
2.7.4

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[PATCH 3/3] drm/i915: Replace ILK eDP underrun suppression with something better

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The underruns we were seeing when enabling eDP port A on ILK seem to
have been caused by prematurely clearing the LP1+ watermark values when
disabling LP1+ watermarks. Now that the watermarks are handled
properly, we can rip out the underrun suppression around the port A
enable.

We still need to worry about the underruns on FDI when enabling
the eDP PLL. But as Bspec tells us, we can avoid that by a vblank
wait on the pipe driving FDI just prior to enabling the eDP PLL.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 36 +++++++++---------------------------
 1 file changed, 9 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 95fe01d55bce..7523558190d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2215,6 +2215,15 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
 	POSTING_READ(DP_A);
 	udelay(500);
 
+	/*
+	 * [DevILK] Work around required when enabling DP PLL
+	 * while a pipe is enabled going to FDI:
+	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
+	 * 2. Program DP PLL enable
+	 */
+	if (IS_GEN5(dev_priv))
+		intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
+
 	intel_dp->DP |= DP_PLL_ENABLE;
 
 	I915_WRITE(DP_A, intel_dp->DP);
@@ -2630,7 +2639,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
-	enum port port = dp_to_dig_port(intel_dp)->port;
 	enum pipe pipe = crtc->pipe;
 
 	if (WARN_ON(dp_reg & DP_PORT_EN))
@@ -2643,17 +2651,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 
 	intel_dp_enable_port(intel_dp);
 
-	if (port == PORT_A && IS_GEN5(dev_priv)) {
-		/*
-		 * Underrun reporting for the other pipe was disabled in
-		 * g4x_pre_enable_dp(). The eDP PLL and port have now been
-		 * enabled, so it's now safe to re-enable underrun reporting.
-		 */
-		intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
-	}
-
 	edp_panel_vdd_on(intel_dp);
 	edp_panel_on(intel_dp);
 	edp_panel_vdd_off(intel_dp, true);
@@ -2699,26 +2696,11 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
 
 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = dp_to_dig_port(intel_dp)->port;
-	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
 
 	intel_dp_prepare(encoder);
 
-	if (port == PORT_A && IS_GEN5(dev_priv)) {
-		/*
-		 * We get FIFO underruns on the other pipe when
-		 * enabling the CPU eDP PLL, and when enabling CPU
-		 * eDP port. We could potentially avoid the PLL
-		 * underrun with a vblank wait just prior to enabling
-		 * the PLL, but that doesn't appear to help the port
-		 * enable case. Just sweep it all under the rug.
-		 */
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
-	}
-
 	/* Only ilk+ has port A */
 	if (port == PORT_A)
 		ironlake_edp_pll_on(intel_dp);
-- 
2.7.4

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✓ Fi.CI.BAT: success for drm/i915: Exorcise ilk underruns

[Patchwork]

== Series Details ==

Series: drm/i915: Exorcise ilk underruns
URL   : https://patchwork.freedesktop.org/series/5193/
State : success

== Summary ==

Series 5193v1 drm/i915: Exorcise ilk underruns
http://patchwork.freedesktop.org/api/1.0/series/5193/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (snb-x220t)
                fail       -> PASS       (ilk-hp8440p) UNSTABLE

bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:196  pass:159  dwarn:0   dfail:0   fail:0   skip:37 
byt-nuc          total:196  pass:161  dwarn:0   dfail:0   fail:0   skip:35 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
ilk-hp8440p      total:196  pass:132  dwarn:0   dfail:0   fail:0   skip:64 
ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
snb-x220t        total:196  pass:162  dwarn:0   dfail:0   fail:1   skip:33 

Results at /archive/results/CI_IGT_test/Patchwork_1780/

ce3f49e2a53a54308ed171613c2567f04fab8228 drm-intel-nightly: 2016y-04m-01d-20h-30m-13s UTC integration manifest
8701c68b5638647e2dbd4664d76e52e78e5e16fb drm/i915: Replace ILK eDP underrun suppression with something better
167cd07c5de09ae92f0d7856c9c0ce9afde601b8 drm/i915: Make sure LP1+ watermarks levels are preserved when going from 1 to 2 pipes
5c2946c3a3fae641dc9460b231f533f8e7e562d3 drm/i915: Try to shut up more ILK underruns

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Re: [PATCH 1/3] drm/i915: Try to shut up more ILK underruns

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 09:53:17PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Take a bigger hammer to the underrun suppression on ILK. Instead of
> trying to suppress them at specific points in the modeset sequence just
> silence them across the entire sequence. This gets rid of some underruns
> at least on my ILK. Note that this changes SNB and IVB to follow the
> same approach just to keep the code less convoluted. The difference is
> that on those platforms we won't suppress CPU underruns for port A since
> it doesn't seem to be necessary.
> 
> My ILK has port A eDP and two PCH HDMI ports, so I can't be sure this is
> as effective on other PCH port types. Perhaps we still need some of
> Daniel's extra vblank waits [2]?
> 
> I've still been able to trigger an underrun on the other pipe, but
> fixing that perhaps needs the LP1+ disable trick I implemented here [1]
> which never got merged.
> 
> A few details which hamper stress testing on my ILK are that sometimes
> the PCH transcoder gets messed up and refuses to shut down, and sometimes
> even the panel power sequencer apparently gets stuck on the always on
> position.
> 
> [1] https://lists.freedesktop.org/archives/intel-gfx/2014-March/041317.html
> [2] https://lists.freedesktop.org/archives/intel-gfx/2016-January/086397.html
> 
> v2: Add a note that we also get underruns when enabling PCH ports
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)

I've not been able to find any additional ILK hardware to test this on but LGTM

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 45 ++++++++++++++++++------------------
>  drivers/gpu/drm/i915/intel_dp.c      | 12 ----------
>  2 files changed, 23 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e6b5ee51739b..8d2c547b57ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4083,12 +4083,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	I915_WRITE(FDI_RX_TUSIZE1(pipe),
>  		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
>  
> -	/*
> -	 * Sometimes spurious CPU pipe underruns happen during FDI
> -	 * training, at least with VGA+HDMI cloning. Suppress them.
> -	 */
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> -
>  	/* For PCH output, training FDI link */
>  	dev_priv->display.fdi_link_train(crtc);
>  
> @@ -4123,8 +4117,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  
>  	intel_fdi_normal_train(crtc);
>  
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -
>  	/* For PCH DP, enable TRANS_DP_CTL */
>  	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
>  		const struct drm_display_mode *adjusted_mode =
> @@ -4727,6 +4719,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	if (WARN_ON(intel_crtc->active))
>  		return;
>  
> +	/*
> +	 * Sometimes spurious CPU pipe underruns happen during FDI
> +	 * training, at least with VGA+HDMI cloning. Suppress them.
> +	 *
> +	 * On ILK we get an occasional spurious CPU pipe underruns
> +	 * between eDP port A enable and vdd enable. Also PCH port
> +	 * enable seems to result in the occasional CPU pipe underrun.
> +	 *
> +	 * Spurious PCH underruns also occur during PCH enabling.
> +	 */
> +	if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  	if (intel_crtc->config->has_pch_encoder)
>  		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>  
> @@ -4748,8 +4752,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_crtc->active = true;
>  
> -	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
>  			encoder->pre_enable(encoder);
> @@ -4791,6 +4793,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	/* Must wait for vblank to avoid spurious PCH FIFO underruns */
>  	if (intel_crtc->config->has_pch_encoder)
>  		intel_wait_for_vblank(dev, pipe);
> +	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>  	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
>  }
>  
> @@ -4943,8 +4946,15 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
>  
> -	if (intel_crtc->config->has_pch_encoder)
> +	/*
> +	 * Sometimes spurious CPU pipe underruns happen when the
> +	 * pipe is already disabled, but FDI RX/TX is still enabled.
> +	 * Happens at least with VGA+HDMI cloning. Suppress them.
> +	 */
> +	if (intel_crtc->config->has_pch_encoder) {
> +		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  		intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> +	}
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		encoder->disable(encoder);
> @@ -4952,22 +4962,12 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  	drm_crtc_vblank_off(crtc);
>  	assert_vblank_disabled(crtc);
>  
> -	/*
> -	 * Sometimes spurious CPU pipe underruns happen when the
> -	 * pipe is already disabled, but FDI RX/TX is still enabled.
> -	 * Happens at least with VGA+HDMI cloning. Suppress them.
> -	 */
> -	if (intel_crtc->config->has_pch_encoder)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> -
>  	intel_disable_pipe(intel_crtc);
>  
>  	ironlake_pfit_disable(intel_crtc, false);
>  
> -	if (intel_crtc->config->has_pch_encoder) {
> +	if (intel_crtc->config->has_pch_encoder)
>  		ironlake_fdi_disable(crtc);
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -	}
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->post_disable)
> @@ -4997,6 +4997,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  		ironlake_fdi_pll_disable(intel_crtc);
>  	}
>  
> +	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>  	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da0c3d29fda8..95fe01d55bce 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2641,15 +2641,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  		vlv_init_panel_power_sequencer(intel_dp);
>  
> -	/*
> -	 * We get an occasional spurious underrun between the port
> -	 * enable and vdd enable, when enabling port A eDP.
> -	 *
> -	 * FIXME: Not sure if this applies to (PCH) port D eDP as well
> -	 */
> -	if (port == PORT_A)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> -
>  	intel_dp_enable_port(intel_dp);
>  
>  	if (port == PORT_A && IS_GEN5(dev_priv)) {
> @@ -2667,9 +2658,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  	edp_panel_on(intel_dp);
>  	edp_panel_vdd_off(intel_dp, true);
>  
> -	if (port == PORT_A)
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -
>  	pps_unlock(intel_dp);
>  
>  	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 3/3] drm/i915: Replace ILK eDP underrun suppression with something better

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 09:53:19PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The underruns we were seeing when enabling eDP port A on ILK seem to
> have been caused by prematurely clearing the LP1+ watermark values when
> disabling LP1+ watermarks. Now that the watermarks are handled
> properly, we can rip out the underrun suppression around the port A
> enable.
> 
> We still need to worry about the underruns on FDI when enabling
> the eDP PLL. But as Bspec tells us, we can avoid that by a vblank
> wait on the pipe driving FDI just prior to enabling the eDP PLL.
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 36 +++++++++---------------------------
>  1 file changed, 9 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 95fe01d55bce..7523558190d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2215,6 +2215,15 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
>  	POSTING_READ(DP_A);
>  	udelay(500);
>  
> +	/*
> +	 * [DevILK] Work around required when enabling DP PLL
> +	 * while a pipe is enabled going to FDI:
> +	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
> +	 * 2. Program DP PLL enable
> +	 */
> +	if (IS_GEN5(dev_priv))
> +		intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
> +
>  	intel_dp->DP |= DP_PLL_ENABLE;
>  
>  	I915_WRITE(DP_A, intel_dp->DP);
> @@ -2630,7 +2639,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>  	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
> -	enum port port = dp_to_dig_port(intel_dp)->port;
>  	enum pipe pipe = crtc->pipe;
>  
>  	if (WARN_ON(dp_reg & DP_PORT_EN))
> @@ -2643,17 +2651,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  
>  	intel_dp_enable_port(intel_dp);
>  
> -	if (port == PORT_A && IS_GEN5(dev_priv)) {
> -		/*
> -		 * Underrun reporting for the other pipe was disabled in
> -		 * g4x_pre_enable_dp(). The eDP PLL and port have now been
> -		 * enabled, so it's now safe to re-enable underrun reporting.
> -		 */
> -		intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
> -	}
> -
>  	edp_panel_vdd_on(intel_dp);
>  	edp_panel_on(intel_dp);
>  	edp_panel_vdd_off(intel_dp, true);
> @@ -2699,26 +2696,11 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
>  
>  static void g4x_pre_enable_dp(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	enum port port = dp_to_dig_port(intel_dp)->port;
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
>  
>  	intel_dp_prepare(encoder);
>  
> -	if (port == PORT_A && IS_GEN5(dev_priv)) {
> -		/*
> -		 * We get FIFO underruns on the other pipe when
> -		 * enabling the CPU eDP PLL, and when enabling CPU
> -		 * eDP port. We could potentially avoid the PLL
> -		 * underrun with a vblank wait just prior to enabling
> -		 * the PLL, but that doesn't appear to help the port
> -		 * enable case. Just sweep it all under the rug.
> -		 */
> -		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
> -	}
> -
>  	/* Only ilk+ has port A */
>  	if (port == PORT_A)
>  		ironlake_edp_pll_on(intel_dp);
> -- 
> 2.7.4
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 2/3] drm/i915: Make sure LP1+ watermarks levels are preserved when going from 1 to 2 pipes

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 09:53:18PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Once again ILK is unhappy if we clear out the LP1+ watermark levels
> outright, and instead we must disable the levels we don't want while
> still leaving the actual programmed watermark levels intact.
> 
> Fixes underruns on the already enabled pipe when programming watermarks
> while enabling the second pipe.
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93787
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9bc9c25423e9..a7fd5d464838 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2483,7 +2483,7 @@ static void ilk_wm_merge(struct drm_device *dev,
>  	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
>  	if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
>  	    config->num_pipes_active > 1)
> -		return;
> +		last_enabled_level = 0;
>  
>  	/* ILK: FBC WM must be disabled always */
>  	merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
> -- 
> 2.7.4
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 3/3] drm/i915: Replace ILK eDP underrun suppression with something better

[Ville Syrjälä]

On Tue, Apr 12, 2016 at 10:16:26AM +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 09:53:19PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The underruns we were seeing when enabling eDP port A on ILK seem to
> > have been caused by prematurely clearing the LP1+ watermark values when
> > disabling LP1+ watermarks. Now that the watermarks are handled
> > properly, we can rip out the underrun suppression around the port A
> > enable.
> > 
> > We still need to worry about the underruns on FDI when enabling
> > the eDP PLL. But as Bspec tells us, we can avoid that by a vblank
> > wait on the pipe driving FDI just prior to enabling the eDP PLL.
> > 
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

Series pushed to dinq. Thanks for the reviews.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 36 +++++++++---------------------------
> >  1 file changed, 9 insertions(+), 27 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 95fe01d55bce..7523558190d1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2215,6 +2215,15 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
> >  	POSTING_READ(DP_A);
> >  	udelay(500);
> >  
> > +	/*
> > +	 * [DevILK] Work around required when enabling DP PLL
> > +	 * while a pipe is enabled going to FDI:
> > +	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
> > +	 * 2. Program DP PLL enable
> > +	 */
> > +	if (IS_GEN5(dev_priv))
> > +		intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
> > +
> >  	intel_dp->DP |= DP_PLL_ENABLE;
> >  
> >  	I915_WRITE(DP_A, intel_dp->DP);
> > @@ -2630,7 +2639,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> >  	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
> > -	enum port port = dp_to_dig_port(intel_dp)->port;
> >  	enum pipe pipe = crtc->pipe;
> >  
> >  	if (WARN_ON(dp_reg & DP_PORT_EN))
> > @@ -2643,17 +2651,6 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> >  
> >  	intel_dp_enable_port(intel_dp);
> >  
> > -	if (port == PORT_A && IS_GEN5(dev_priv)) {
> > -		/*
> > -		 * Underrun reporting for the other pipe was disabled in
> > -		 * g4x_pre_enable_dp(). The eDP PLL and port have now been
> > -		 * enabled, so it's now safe to re-enable underrun reporting.
> > -		 */
> > -		intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
> > -		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
> > -		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
> > -	}
> > -
> >  	edp_panel_vdd_on(intel_dp);
> >  	edp_panel_on(intel_dp);
> >  	edp_panel_vdd_off(intel_dp, true);
> > @@ -2699,26 +2696,11 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
> >  
> >  static void g4x_pre_enable_dp(struct intel_encoder *encoder)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> >  	enum port port = dp_to_dig_port(intel_dp)->port;
> > -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> >  
> >  	intel_dp_prepare(encoder);
> >  
> > -	if (port == PORT_A && IS_GEN5(dev_priv)) {
> > -		/*
> > -		 * We get FIFO underruns on the other pipe when
> > -		 * enabling the CPU eDP PLL, and when enabling CPU
> > -		 * eDP port. We could potentially avoid the PLL
> > -		 * underrun with a vblank wait just prior to enabling
> > -		 * the PLL, but that doesn't appear to help the port
> > -		 * enable case. Just sweep it all under the rug.
> > -		 */
> > -		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
> > -		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
> > -	}
> > -
> >  	/* Only ilk+ has port A */
> >  	if (port == PORT_A)
> >  		ironlake_edp_pll_on(intel_dp);
> > -- 
> > 2.7.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 

-- 
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