* [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2
@ 2020-03-28 1:01 Marek Vasut
2020-03-30 10:12 ` Patrice CHOTARD
2020-04-10 16:26 ` Patrick DELAUNAY
0 siblings, 2 replies; 4+ messages in thread
From: Marek Vasut @ 2020-03-28 1:01 UTC (permalink / raw)
To: u-boot
Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
---
V2: Configure FMC2 nCS4 for SRAM as well
V3: Adjust the register macros
V4: Use more macros
---
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 68 ++++++++++++++++++++++
board/dhelectronics/dh_stm32mp1/board.c | 52 +++++++++++++++++
configs/stm32mp15_dhcom_basic_defconfig | 1 +
3 files changed, 121 insertions(+)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 6c952a57ee..eba3588540 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -37,6 +37,12 @@
default-state = "on";
};
};
+
+ /* This is actually on FMC2, but we do not have bus driver for that */
+ ksz8851: ks8851mll at 64000000 {
+ compatible = "micrel,ks8851-mll";
+ reg = <0x64000000 0x20000>;
+ };
};
&i2c4 {
@@ -50,6 +56,68 @@
};
};
+&pinctrl {
+ /* These should bound to FMC2 bus driver, but we do not have one */
+ pinctrl-0 = <&fmc_pins_b>;
+ pinctrl-1 = <&fmc_sleep_pins_b>;
+ pinctrl-names = "default", "sleep";
+
+ fmc_pins_b: fmc-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
+ <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
+ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
+ <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
+ <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
+ <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
+ <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
+ <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
+ <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
+ <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
+ <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
+ <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ fmc_sleep_pins_b: fmc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
+ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
+ <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
+ <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
+ <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
+ <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
+ };
+ };
+};
+
&pmic {
u-boot,dm-pre-reloc;
};
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 7bcd713a86..a3458a2623 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -375,6 +375,56 @@ static void sysconf_init(void)
#endif
}
+static void board_init_fmc2(void)
+{
+#define STM32_FMC2_BCR1 0x0
+#define STM32_FMC2_BTR1 0x4
+#define STM32_FMC2_BWTR1 0x104
+#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
+#define STM32_FMC2_BCRx_FMCEN BIT(31)
+#define STM32_FMC2_BCRx_WREN BIT(12)
+#define STM32_FMC2_BCRx_RSVD BIT(7)
+#define STM32_FMC2_BCRx_FACCEN BIT(6)
+#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
+#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
+#define STM32_FMC2_BCRx_MUXEN BIT(1)
+#define STM32_FMC2_BCRx_MBKEN BIT(0)
+#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
+#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
+#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
+#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
+#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
+#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
+
+#define RCC_MP_AHB6RSTCLRR 0x218
+#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
+#define RCC_MP_AHB6ENSETR 0x19c
+#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
+
+ const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
+ STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
+ STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
+ STM32_FMC2_BCRx_MBKEN;
+ const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
+ STM32_FMC2_BTRx_BUSTURN(2) |
+ STM32_FMC2_BTRx_DATAST(0x22) |
+ STM32_FMC2_BTRx_ADDHLD(2) |
+ STM32_FMC2_BTRx_ADDSET(2);
+
+ /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
+ writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
+ writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
+
+ /* KS8851-16MLL -- Muxed mode */
+ writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
+ writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
+ /* AS7C34098 SRAM on X11 -- Muxed mode */
+ writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
+ writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
+
+ setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
+}
+
/* board dependent setup after realloc */
int board_init(void)
{
@@ -398,6 +448,8 @@ int board_init(void)
sysconf_init();
+ board_init_fmc2();
+
if (CONFIG_IS_ENABLED(CONFIG_LED))
led_default_state();
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index 921dea242a..683f15e7d5 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_MTD=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
+CONFIG_KS8851_MLL=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PINCONF=y
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2
2020-03-28 1:01 [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2 Marek Vasut
@ 2020-03-30 10:12 ` Patrice CHOTARD
2020-04-15 7:29 ` Patrice CHOTARD
2020-04-10 16:26 ` Patrick DELAUNAY
1 sibling, 1 reply; 4+ messages in thread
From: Patrice CHOTARD @ 2020-03-30 10:12 UTC (permalink / raw)
To: u-boot
Hi Marek
On 3/28/20 2:01 AM, Marek Vasut wrote:
> Add DT entries, Kconfig entries and board-specific entries to configure
> FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: Configure FMC2 nCS4 for SRAM as well
> V3: Adjust the register macros
> V4: Use more macros
> ---
> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 68 ++++++++++++++++++++++
> board/dhelectronics/dh_stm32mp1/board.c | 52 +++++++++++++++++
> configs/stm32mp15_dhcom_basic_defconfig | 1 +
> 3 files changed, 121 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> index 6c952a57ee..eba3588540 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> @@ -37,6 +37,12 @@
> default-state = "on";
> };
> };
> +
> + /* This is actually on FMC2, but we do not have bus driver for that */
> + ksz8851: ks8851mll at 64000000 {
> + compatible = "micrel,ks8851-mll";
> + reg = <0x64000000 0x20000>;
> + };
> };
>
> &i2c4 {
> @@ -50,6 +56,68 @@
> };
> };
>
> +&pinctrl {
> + /* These should bound to FMC2 bus driver, but we do not have one */
> + pinctrl-0 = <&fmc_pins_b>;
> + pinctrl-1 = <&fmc_sleep_pins_b>;
> + pinctrl-names = "default", "sleep";
> +
> + fmc_pins_b: fmc-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
> + <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
> + <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
> + <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
> + <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
> + <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
> + <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
> + <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
> + <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
> + <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
> + <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
> + <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
> + <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
> + <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
> + <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
> + <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
> + <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
> + <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
> + <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
> + <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
> + <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <3>;
> + };
> + };
> +
> + fmc_sleep_pins_b: fmc-sleep-0 {
> + pins {
> + pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
> + <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
> + <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
> + <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
> + <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
> + <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
> + <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
> + <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
> + <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
> + <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
> + <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
> + <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
> + <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
> + <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
> + <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
> + <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
> + <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
> + <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
> + <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
> + <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
> + <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
> + };
> + };
> +};
> +
> &pmic {
> u-boot,dm-pre-reloc;
> };
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
> index 7bcd713a86..a3458a2623 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -375,6 +375,56 @@ static void sysconf_init(void)
> #endif
> }
>
> +static void board_init_fmc2(void)
> +{
> +#define STM32_FMC2_BCR1 0x0
> +#define STM32_FMC2_BTR1 0x4
> +#define STM32_FMC2_BWTR1 0x104
> +#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
> +#define STM32_FMC2_BCRx_FMCEN BIT(31)
> +#define STM32_FMC2_BCRx_WREN BIT(12)
> +#define STM32_FMC2_BCRx_RSVD BIT(7)
> +#define STM32_FMC2_BCRx_FACCEN BIT(6)
> +#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
> +#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
> +#define STM32_FMC2_BCRx_MUXEN BIT(1)
> +#define STM32_FMC2_BCRx_MBKEN BIT(0)
> +#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
> +#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
> +#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
> +#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
> +#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
> +#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
> +
> +#define RCC_MP_AHB6RSTCLRR 0x218
> +#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
> +#define RCC_MP_AHB6ENSETR 0x19c
> +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
> +
> + const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
> + STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
> + STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
> + STM32_FMC2_BCRx_MBKEN;
> + const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
> + STM32_FMC2_BTRx_BUSTURN(2) |
> + STM32_FMC2_BTRx_DATAST(0x22) |
> + STM32_FMC2_BTRx_ADDHLD(2) |
> + STM32_FMC2_BTRx_ADDSET(2);
> +
> + /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
> + writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
> + writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
> +
> + /* KS8851-16MLL -- Muxed mode */
> + writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
> + writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
> + /* AS7C34098 SRAM on X11 -- Muxed mode */
> + writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
> + writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
> +
> + setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
> +}
> +
> /* board dependent setup after realloc */
> int board_init(void)
> {
> @@ -398,6 +448,8 @@ int board_init(void)
>
> sysconf_init();
>
> + board_init_fmc2();
> +
> if (CONFIG_IS_ENABLED(CONFIG_LED))
> led_default_state();
>
> diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
> index 921dea242a..683f15e7d5 100644
> --- a/configs/stm32mp15_dhcom_basic_defconfig
> +++ b/configs/stm32mp15_dhcom_basic_defconfig
> @@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_MTD=y
> CONFIG_SPL_SPI_FLASH_MTD=y
> CONFIG_DM_ETH=y
> CONFIG_DWC_ETH_QOS=y
> +CONFIG_KS8851_MLL=y
> CONFIG_PHY=y
> CONFIG_PHY_STM32_USBPHYC=y
> CONFIG_PINCONF=y
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
Patrice
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2
2020-03-28 1:01 [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2 Marek Vasut
2020-03-30 10:12 ` Patrice CHOTARD
@ 2020-04-10 16:26 ` Patrick DELAUNAY
1 sibling, 0 replies; 4+ messages in thread
From: Patrick DELAUNAY @ 2020-04-10 16:26 UTC (permalink / raw)
To: u-boot
Dear Marek,
> From: Marek Vasut <marex@denx.de>
> Sent: samedi 28 mars 2020 02:02
>
> Add DT entries, Kconfig entries and board-specific entries to configure
> FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> ---
> V2: Configure FMC2 nCS4 for SRAM as well
> V3: Adjust the register macros
> V4: Use more macros
> ---
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Thanks
Patrick
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2
2020-03-30 10:12 ` Patrice CHOTARD
@ 2020-04-15 7:29 ` Patrice CHOTARD
0 siblings, 0 replies; 4+ messages in thread
From: Patrice CHOTARD @ 2020-04-15 7:29 UTC (permalink / raw)
To: u-boot
Hi
On 3/30/20 12:12 PM, Patrice CHOTARD wrote:
> Hi Marek
>
> On 3/28/20 2:01 AM, Marek Vasut wrote:
>> Add DT entries, Kconfig entries and board-specific entries to configure
>> FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Patrick Delaunay <patrick.delaunay@st.com>
>> Cc: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> V2: Configure FMC2 nCS4 for SRAM as well
>> V3: Adjust the register macros
>> V4: Use more macros
>> ---
>> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 68 ++++++++++++++++++++++
>> board/dhelectronics/dh_stm32mp1/board.c | 52 +++++++++++++++++
>> configs/stm32mp15_dhcom_basic_defconfig | 1 +
>> 3 files changed, 121 insertions(+)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> index 6c952a57ee..eba3588540 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
>> @@ -37,6 +37,12 @@
>> default-state = "on";
>> };
>> };
>> +
>> + /* This is actually on FMC2, but we do not have bus driver for that */
>> + ksz8851: ks8851mll at 64000000 {
>> + compatible = "micrel,ks8851-mll";
>> + reg = <0x64000000 0x20000>;
>> + };
>> };
>>
>> &i2c4 {
>> @@ -50,6 +56,68 @@
>> };
>> };
>>
>> +&pinctrl {
>> + /* These should bound to FMC2 bus driver, but we do not have one */
>> + pinctrl-0 = <&fmc_pins_b>;
>> + pinctrl-1 = <&fmc_sleep_pins_b>;
>> + pinctrl-names = "default", "sleep";
>> +
>> + fmc_pins_b: fmc-0 {
>> + pins1 {
>> + pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
>> + <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
>> + <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
>> + <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
>> + <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
>> + <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
>> + <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
>> + <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
>> + <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
>> + <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
>> + <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
>> + <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
>> + <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
>> + <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
>> + <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
>> + <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
>> + <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
>> + <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
>> + <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
>> + <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
>> + <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
>> + bias-disable;
>> + drive-push-pull;
>> + slew-rate = <3>;
>> + };
>> + };
>> +
>> + fmc_sleep_pins_b: fmc-sleep-0 {
>> + pins {
>> + pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
>> + <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
>> + <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
>> + <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
>> + <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
>> + <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
>> + <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
>> + <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
>> + <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
>> + <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
>> + <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
>> + <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
>> + <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
>> + <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
>> + <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
>> + <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
>> + <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
>> + <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
>> + <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
>> + <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
>> + <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
>> + };
>> + };
>> +};
>> +
>> &pmic {
>> u-boot,dm-pre-reloc;
>> };
>> diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
>> index 7bcd713a86..a3458a2623 100644
>> --- a/board/dhelectronics/dh_stm32mp1/board.c
>> +++ b/board/dhelectronics/dh_stm32mp1/board.c
>> @@ -375,6 +375,56 @@ static void sysconf_init(void)
>> #endif
>> }
>>
>> +static void board_init_fmc2(void)
>> +{
>> +#define STM32_FMC2_BCR1 0x0
>> +#define STM32_FMC2_BTR1 0x4
>> +#define STM32_FMC2_BWTR1 0x104
>> +#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
>> +#define STM32_FMC2_BCRx_FMCEN BIT(31)
>> +#define STM32_FMC2_BCRx_WREN BIT(12)
>> +#define STM32_FMC2_BCRx_RSVD BIT(7)
>> +#define STM32_FMC2_BCRx_FACCEN BIT(6)
>> +#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
>> +#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
>> +#define STM32_FMC2_BCRx_MUXEN BIT(1)
>> +#define STM32_FMC2_BCRx_MBKEN BIT(0)
>> +#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
>> +#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
>> +#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
>> +#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
>> +#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
>> +#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
>> +
>> +#define RCC_MP_AHB6RSTCLRR 0x218
>> +#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
>> +#define RCC_MP_AHB6ENSETR 0x19c
>> +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
>> +
>> + const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
>> + STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
>> + STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
>> + STM32_FMC2_BCRx_MBKEN;
>> + const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
>> + STM32_FMC2_BTRx_BUSTURN(2) |
>> + STM32_FMC2_BTRx_DATAST(0x22) |
>> + STM32_FMC2_BTRx_ADDHLD(2) |
>> + STM32_FMC2_BTRx_ADDSET(2);
>> +
>> + /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
>> + writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
>> + writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
>> +
>> + /* KS8851-16MLL -- Muxed mode */
>> + writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
>> + writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
>> + /* AS7C34098 SRAM on X11 -- Muxed mode */
>> + writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
>> + writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
>> +
>> + setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
>> +}
>> +
>> /* board dependent setup after realloc */
>> int board_init(void)
>> {
>> @@ -398,6 +448,8 @@ int board_init(void)
>>
>> sysconf_init();
>>
>> + board_init_fmc2();
>> +
>> if (CONFIG_IS_ENABLED(CONFIG_LED))
>> led_default_state();
>>
>> diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
>> index 921dea242a..683f15e7d5 100644
>> --- a/configs/stm32mp15_dhcom_basic_defconfig
>> +++ b/configs/stm32mp15_dhcom_basic_defconfig
>> @@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_MTD=y
>> CONFIG_SPL_SPI_FLASH_MTD=y
>> CONFIG_DM_ETH=y
>> CONFIG_DWC_ETH_QOS=y
>> +CONFIG_KS8851_MLL=y
>> CONFIG_PHY=y
>> CONFIG_PHY_STM32_USBPHYC=y
>> CONFIG_PINCONF=y
> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
>
> Thanks
>
> Patrice
>
Applied to u-boot-stm/next
Thanks
Patrice
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-04-15 7:29 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-28 1:01 [PATCH V4] ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2 Marek Vasut
2020-03-30 10:12 ` Patrice CHOTARD
2020-04-15 7:29 ` Patrice CHOTARD
2020-04-10 16:26 ` Patrick DELAUNAY
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.