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* [PATCH] drm/i915: Fix CHV data lane soft reset for HDMI
@ 2016-04-08 14:06 Ander Conselvan de Oliveira
  2016-04-08 14:11 ` Ville Syrjälä
  2016-04-08 14:55 ` ✗ Fi.CI.BAT: warning for " Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 14:06 UTC (permalink / raw)
  To: intel-gfx; +Cc: Ander Conselvan de Oliveira

The function chv_data_lane_soft_reset() uses the lane count to decide
which lanes to set/reset. However, the HDMI code never sets lane count,
since it always uses the four lanes of the phy. Note that before commit
a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming"), all
lanes were reset, regardless of lane count, so this patch restores that
behavior.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Deepak S <deepak.s@linux.intel.com>
Fixes: a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming")
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---

I noticed this while reading CHV code, so this is only compiled tested. I
don't know if this could cause real issues.

Ander

---
 drivers/gpu/drm/i915/intel_hdmi.c | 30 +++++++++++++-----------------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b199ede..5410d1a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1670,14 +1670,12 @@ static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-	if (crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
-		if (reset)
-			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-		else
-			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-	}
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+	if (reset)
+		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	else
+		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
@@ -1687,15 +1685,13 @@ static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 		val |= DPIO_PCS_CLK_SOFT_RESET;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
 
-	if (crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
-		val |= CHV_PCS_REQ_SOFTRESET_EN;
-		if (reset)
-			val &= ~DPIO_PCS_CLK_SOFT_RESET;
-		else
-			val |= DPIO_PCS_CLK_SOFT_RESET;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
-	}
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	if (reset)
+		val &= ~DPIO_PCS_CLK_SOFT_RESET;
+	else
+		val |= DPIO_PCS_CLK_SOFT_RESET;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
 }
 
 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
-- 
2.4.11

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Fix CHV data lane soft reset for HDMI
  2016-04-08 14:06 [PATCH] drm/i915: Fix CHV data lane soft reset for HDMI Ander Conselvan de Oliveira
@ 2016-04-08 14:11 ` Ville Syrjälä
  2016-04-08 15:33   ` Ander Conselvan De Oliveira
  2016-04-08 14:55 ` ✗ Fi.CI.BAT: warning for " Patchwork
  1 sibling, 1 reply; 4+ messages in thread
From: Ville Syrjälä @ 2016-04-08 14:11 UTC (permalink / raw)
  To: Ander Conselvan de Oliveira; +Cc: intel-gfx

On Fri, Apr 08, 2016 at 05:06:04PM +0300, Ander Conselvan de Oliveira wrote:
> The function chv_data_lane_soft_reset() uses the lane count to decide
> which lanes to set/reset. However, the HDMI code never sets lane count,
> since it always uses the four lanes of the phy. Note that before commit
> a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming"), all
> lanes were reset, regardless of lane count, so this patch restores that
> behavior.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Deepak S <deepak.s@linux.intel.com>
> Fixes: a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming")
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

At some point we really should just eliminate the duplicated PHY code
by moving it to someting like intel_dpio.c, and then I suppose we should
populate lane_count for HDMI as well. But for now this is good enough.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
> 
> I noticed this while reading CHV code, so this is only compiled tested. I
> don't know if this could cause real issues.
> 
> Ander
> 
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 30 +++++++++++++-----------------
>  1 file changed, 13 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index b199ede..5410d1a 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1670,14 +1670,12 @@ static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>  
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> -		if (reset)
> -			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -		else
> -			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> -	}
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> +	if (reset)
> +		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	else
> +		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>  
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> @@ -1687,15 +1685,13 @@ static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  		val |= DPIO_PCS_CLK_SOFT_RESET;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
>  
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> -		val |= CHV_PCS_REQ_SOFTRESET_EN;
> -		if (reset)
> -			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -		else
> -			val |= DPIO_PCS_CLK_SOFT_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> -	}
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	if (reset)
> +		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> +	else
> +		val |= DPIO_PCS_CLK_SOFT_RESET;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
>  }
>  
>  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> -- 
> 2.4.11

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: Fix CHV data lane soft reset for HDMI
  2016-04-08 14:06 [PATCH] drm/i915: Fix CHV data lane soft reset for HDMI Ander Conselvan de Oliveira
  2016-04-08 14:11 ` Ville Syrjälä
@ 2016-04-08 14:55 ` Patchwork
  1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2016-04-08 14:55 UTC (permalink / raw)
  To: Ander Conselvan de Oliveira; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Fix CHV data lane soft reset for HDMI
URL   : https://patchwork.freedesktop.org/series/5461/
State : warning

== Summary ==

Series 5461v1 drm/i915: Fix CHV data lane soft reset for HDMI
http://patchwork.freedesktop.org/api/1.0/series/5461/revisions/1/mbox/

Test gem_exec_basic:
        Subgroup basic-bsd:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test gem_exec_suspend:
        Subgroup basic-s3:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test gem_sync:
        Subgroup basic-bsd:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                pass       -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Test kms_force_connector_basic:
        Subgroup force-edid:
                pass       -> SKIP       (snb-x220t)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup basic-rte:
                dmesg-warn -> PASS       (bsw-nuc-2)

bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:196  pass:158  dwarn:1   dfail:0   fail:0   skip:37 
byt-nuc          total:196  pass:161  dwarn:0   dfail:0   fail:0   skip:35 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
hsw-gt2          total:196  pass:179  dwarn:0   dfail:0   fail:0   skip:17 
ilk-hp8440p      total:196  pass:131  dwarn:1   dfail:0   fail:0   skip:64 
ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
skl-i7k-2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
skl-nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
snb-x220t        total:196  pass:161  dwarn:0   dfail:0   fail:1   skip:34 

Results at /archive/results/CI_IGT_test/Patchwork_1846/

949884a57b51aa158e3ae9afe1f08130cdb7a3ef drm-intel-nightly: 2016y-04m-08d-10h-45m-28s UTC integration manifest
a63f315f919d3cdb8acab94b53951dbfa4cbbe9c drm/i915: Fix CHV data lane soft reset for HDMI

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Fix CHV data lane soft reset for HDMI
  2016-04-08 14:11 ` Ville Syrjälä
@ 2016-04-08 15:33   ` Ander Conselvan De Oliveira
  0 siblings, 0 replies; 4+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-04-08 15:33 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, 2016-04-08 at 17:11 +0300, Ville Syrjälä wrote:
> On Fri, Apr 08, 2016 at 05:06:04PM +0300, Ander Conselvan de Oliveira wrote:
> > The function chv_data_lane_soft_reset() uses the lane count to decide
> > which lanes to set/reset. However, the HDMI code never sets lane count,
> > since it always uses the four lanes of the phy. Note that before commit
> > a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming"), all
> > lanes were reset, regardless of lane count, so this patch restores that
> > behavior.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Deepak S <deepak.s@linux.intel.com>
> > Fixes: a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming")
> > Signed-off-by: Ander Conselvan de Oliveira <
> > ander.conselvan.de.oliveira@intel.com>
> 
> At some point we really should just eliminate the duplicated PHY code
> by moving it to someting like intel_dpio.c, and then I suppose we should
> populate lane_count for HDMI as well. But for now this is good enough.

I took the bait and did that for CHV, except I couldn't come up with good names
and kerneldoc for stuff. I can do the same for VLV, but that will have to wait
until Monday.

Cheers,
Ander

> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > ---
> > 
> > I noticed this while reading CHV code, so this is only compiled tested. I
> > don't know if this could cause real issues.
> > 
> > Ander
> > 
> > ---
> >  drivers/gpu/drm/i915/intel_hdmi.c | 30 +++++++++++++-----------------
> >  1 file changed, 13 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index b199ede..5410d1a 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1670,14 +1670,12 @@ static void chv_data_lane_soft_reset(struct
> > intel_encoder *encoder,
> >  		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> >  
> > -	if (crtc->config->lane_count > 2) {
> > -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > -		if (reset)
> > -			val &= ~(DPIO_PCS_TX_LANE2_RESET |
> > DPIO_PCS_TX_LANE1_RESET);
> > -		else
> > -			val |= DPIO_PCS_TX_LANE2_RESET |
> > DPIO_PCS_TX_LANE1_RESET;
> > -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > -	}
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > +	if (reset)
> > +		val &= ~(DPIO_PCS_TX_LANE2_RESET |
> > DPIO_PCS_TX_LANE1_RESET);
> > +	else
> > +		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> >  
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > @@ -1687,15 +1685,13 @@ static void chv_data_lane_soft_reset(struct
> > intel_encoder *encoder,
> >  		val |= DPIO_PCS_CLK_SOFT_RESET;
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> >  
> > -	if (crtc->config->lane_count > 2) {
> > -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > -		val |= CHV_PCS_REQ_SOFTRESET_EN;
> > -		if (reset)
> > -			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> > -		else
> > -			val |= DPIO_PCS_CLK_SOFT_RESET;
> > -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> > -	}
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> > +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > +	if (reset)
> > +		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> > +	else
> > +		val |= DPIO_PCS_CLK_SOFT_RESET;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> >  }
> >  
> >  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> > -- 
> > 2.4.11
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-04-08 15:33 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-04-08 14:06 [PATCH] drm/i915: Fix CHV data lane soft reset for HDMI Ander Conselvan de Oliveira
2016-04-08 14:11 ` Ville Syrjälä
2016-04-08 15:33   ` Ander Conselvan De Oliveira
2016-04-08 14:55 ` ✗ Fi.CI.BAT: warning for " Patchwork

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