[PATCH 0/5] drm/i915: Rest of my DSI and DPLL stuff

[PATCH 0/5] drm/i915: Rest of my DSI and DPLL stuff

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here is the remainder of my DSI/DPLL series [1]. Everything else got merged
already. The first patch in the series is the only one to lack an r-b.

Tested on BYT FFRD8 only, BXT stuff is not tested.

[1] https://lists.freedesktop.org/archives/intel-gfx/2016-March/089782.html

Ville Syrjälä (5):
  drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
  drm/i915: Compute DSI PLL parameters during .compute_config()
  drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()
  drm/i915: Hook up pfit for DSI
  drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms

 drivers/gpu/drm/i915/intel_display.c | 123 ++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp.c      |   5 ++
 drivers/gpu/drm/i915/intel_drv.h     |   5 ++
 drivers/gpu/drm/i915/intel_dsi.c     | 113 ++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_dsi.h     |  14 ++--
 drivers/gpu/drm/i915/intel_dsi_pll.c | 144 +++++++++++++++++------------------
 6 files changed, 252 insertions(+), 152 deletions(-)

-- 
2.7.4

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[PATCH 1/5] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Set up DPLL and DPLL_MD even when driving DSI output on VLV/CHV. While
the DPLL isn't used to provide the clock we still need the refclock, and
it appears that the pixel repeat factor also has an effect on DSI
output. So set up eveyrhing in DPLL and DPLL_MD as we would do for
DP/HDMI/VGA, but don't actually enable the DPLL or configure the
dividers via DPIO.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 120 +++++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_dsi.c     |  28 ++------
 2 files changed, 80 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 607dc41bcc68..7c74a930f45d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1530,45 +1530,47 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
+static void _vlv_enable_pll(struct intel_crtc *crtc,
+			    const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("DPLL %d failed to lock\n", pipe);
+}
+
 static void vlv_enable_pll(struct intel_crtc *crtc,
 			   const struct intel_crtc_state *pipe_config)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	i915_reg_t reg = DPLL(pipe);
-	u32 dpll = pipe_config->dpll_hw_state.dpll;
 
 	assert_pipe_disabled(dev_priv, pipe);
 
 	/* PLL is protected by panel, make sure we can write it */
 	assert_panel_unlocked(dev_priv, pipe);
 
-	I915_WRITE(reg, dpll);
-	POSTING_READ(reg);
-	udelay(150);
-
-	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
-		DRM_ERROR("DPLL %d failed to lock\n", pipe);
+	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
+		_vlv_enable_pll(crtc, pipe_config);
 
 	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
 	POSTING_READ(DPLL_MD(pipe));
 }
 
-static void chv_enable_pll(struct intel_crtc *crtc,
-			   const struct intel_crtc_state *pipe_config)
+
+static void _chv_enable_pll(struct intel_crtc *crtc,
+			    const struct intel_crtc_state *pipe_config)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 tmp;
 
-	assert_pipe_disabled(dev_priv, pipe);
-
-	/* PLL is protected by panel, make sure we can write it */
-	assert_panel_unlocked(dev_priv, pipe);
-
 	mutex_lock(&dev_priv->sb_lock);
 
 	/* Enable back the 10bit clock to display controller */
@@ -1589,6 +1591,21 @@ static void chv_enable_pll(struct intel_crtc *crtc,
 	/* Check PLL is locked */
 	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
 		DRM_ERROR("PLL %d failed to lock\n", pipe);
+}
+
+static void chv_enable_pll(struct intel_crtc *crtc,
+			   const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	assert_pipe_disabled(dev_priv, pipe);
+
+	/* PLL is protected by panel, make sure we can write it */
+	assert_panel_unlocked(dev_priv, pipe);
+
+	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
+		_chv_enable_pll(crtc, pipe_config);
 
 	if (pipe != PIPE_A) {
 		/*
@@ -6073,14 +6090,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	if (!intel_crtc->config->has_dsi_encoder) {
-		if (IS_CHERRYVIEW(dev)) {
-			chv_prepare_pll(intel_crtc, intel_crtc->config);
-			chv_enable_pll(intel_crtc, intel_crtc->config);
-		} else {
-			vlv_prepare_pll(intel_crtc, intel_crtc->config);
-			vlv_enable_pll(intel_crtc, intel_crtc->config);
-		}
+	if (IS_CHERRYVIEW(dev)) {
+		chv_prepare_pll(intel_crtc, intel_crtc->config);
+		chv_enable_pll(intel_crtc, intel_crtc->config);
+	} else {
+		vlv_prepare_pll(intel_crtc, intel_crtc->config);
+		vlv_enable_pll(intel_crtc, intel_crtc->config);
 	}
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -6118,7 +6133,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	struct intel_crtc_state *pipe_config =
 		to_intel_crtc_state(crtc->state);
-	int pipe = intel_crtc->pipe;
+	enum pipe pipe = intel_crtc->pipe;
 
 	if (WARN_ON(intel_crtc->active))
 		return;
@@ -7174,11 +7189,15 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
 			     struct intel_crtc_state *pipe_config)
 {
 	pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
-		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
-		DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
+		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 	if (crtc->pipe != PIPE_A)
 		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
+	/* DPLL not used with DSI, but still need the rest set up */
+	if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
+		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
+			DPLL_EXT_BUFFER_ENABLE_VLV;
+
 	pipe_config->dpll_hw_state.dpll_md =
 		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 }
@@ -7187,11 +7206,14 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
 			     struct intel_crtc_state *pipe_config)
 {
 	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
-		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
-		DPLL_VCO_ENABLE;
+		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 	if (crtc->pipe != PIPE_A)
 		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
+	/* DPLL not used with DSI, but still need the rest set up */
+	if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
+		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
+
 	pipe_config->dpll_hw_state.dpll_md =
 		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 }
@@ -7201,11 +7223,20 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int pipe = crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 	u32 mdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
 	u32 coreclk, reg_val;
 
+	/* Enable Refclk */
+	I915_WRITE(DPLL(pipe),
+		   pipe_config->dpll_hw_state.dpll &
+		   ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
+
+	/* No need to actually set up the DPLL with DSI */
+	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+		return;
+
 	mutex_lock(&dev_priv->sb_lock);
 
 	bestn = pipe_config->dpll.n;
@@ -7292,14 +7323,21 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int pipe = crtc->pipe;
-	i915_reg_t dpll_reg = DPLL(crtc->pipe);
+	enum pipe pipe = crtc->pipe;
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 loopfilter, tribuf_calcntr;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	u32 dpio_val;
 	int vco;
 
+	/* Enable Refclk and SSC */
+	I915_WRITE(DPLL(pipe),
+		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
+
+	/* No need to actually set up the DPLL with DSI */
+	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+		return;
+
 	bestn = pipe_config->dpll.n;
 	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
 	bestm1 = pipe_config->dpll.m1;
@@ -7310,12 +7348,6 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	dpio_val = 0;
 	loopfilter = 0;
 
-	/*
-	 * Enable Refclk and SSC
-	 */
-	I915_WRITE(dpll_reg,
-		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
-
 	mutex_lock(&dev_priv->sb_lock);
 
 	/* p1 and p2 divider */
@@ -7930,9 +7962,6 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc,
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
-	if (crtc_state->has_dsi_encoder)
-		return 0;
-
 	if (!crtc_state->clock_set &&
 	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
 				refclk, NULL, &crtc_state->dpll)) {
@@ -7954,9 +7983,6 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
-	if (crtc_state->has_dsi_encoder)
-		return 0;
-
 	if (!crtc_state->clock_set &&
 	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
 				refclk, NULL, &crtc_state->dpll)) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9ff6435e7d38..22bd42a8aab0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -311,6 +311,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 	}
 
+	/*
+	 * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
+	 * to .compute_config().
+	 */
+	pipe_config->clock_set = true;
+
 	return true;
 }
 
@@ -498,8 +504,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum pipe pipe = intel_crtc->pipe;
 	enum port port;
 	u32 tmp;
 
@@ -521,19 +525,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 	msleep(intel_dsi->panel_on_delay);
 
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-		/*
-		 * Disable DPOunit clock gating, can stall pipe
-		 * and we need DPLL REFA always enabled
-		 */
-		tmp = I915_READ(DPLL(pipe));
-		tmp |= DPLL_REF_CLK_ENABLE_VLV;
-		I915_WRITE(DPLL(pipe), tmp);
-
-		/* update the hw state for DPLL */
-		intel_crtc->config->dpll_hw_state.dpll =
-				DPLL_INTEGRATED_REF_CLK_VLV |
-					DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
-
+		/* Disable DPOunit clock gating, can stall pipe */
 		tmp = I915_READ(DSPCLK_GATE_D);
 		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 		I915_WRITE(DSPCLK_GATE_D, tmp);
@@ -832,12 +824,6 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 	if (IS_BROXTON(dev))
 		bxt_dsi_get_pipe_config(encoder, pipe_config);
 
-	/*
-	 * DPLL_MD is not used in case of DSI, reading will get some default value
-	 * set dpll_md = 0
-	 */
-	pipe_config->dpll_hw_state.dpll_md = 0;
-
 	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
 	if (!pclk)
 		return;
-- 
2.7.4

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Re: [PATCH 1/5] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV

[Jani Nikula]

On Tue, 12 Apr 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Set up DPLL and DPLL_MD even when driving DSI output on VLV/CHV. While
> the DPLL isn't used to provide the clock we still need the refclock, and
> it appears that the pixel repeat factor also has an effect on DSI
> output. So set up eveyrhing in DPLL and DPLL_MD as we would do for
> DP/HDMI/VGA, but don't actually enable the DPLL or configure the
> dividers via DPIO.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

I quickly glanced over 2-5 too, my earlier r-b on them still stand.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 120 +++++++++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_dsi.c     |  28 ++------
>  2 files changed, 80 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 607dc41bcc68..7c74a930f45d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1530,45 +1530,47 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
>  }
>  
> +static void _vlv_enable_pll(struct intel_crtc *crtc,
> +			    const struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +
> +	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> +		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> +}
> +
>  static void vlv_enable_pll(struct intel_crtc *crtc,
>  			   const struct intel_crtc_state *pipe_config)
>  {
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> -	i915_reg_t reg = DPLL(pipe);
> -	u32 dpll = pipe_config->dpll_hw_state.dpll;
>  
>  	assert_pipe_disabled(dev_priv, pipe);
>  
>  	/* PLL is protected by panel, make sure we can write it */
>  	assert_panel_unlocked(dev_priv, pipe);
>  
> -	I915_WRITE(reg, dpll);
> -	POSTING_READ(reg);
> -	udelay(150);
> -
> -	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> -		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> +	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
> +		_vlv_enable_pll(crtc, pipe_config);
>  
>  	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
>  	POSTING_READ(DPLL_MD(pipe));
>  }
>  
> -static void chv_enable_pll(struct intel_crtc *crtc,
> -			   const struct intel_crtc_state *pipe_config)
> +
> +static void _chv_enable_pll(struct intel_crtc *crtc,
> +			    const struct intel_crtc_state *pipe_config)
>  {
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 tmp;
>  
> -	assert_pipe_disabled(dev_priv, pipe);
> -
> -	/* PLL is protected by panel, make sure we can write it */
> -	assert_panel_unlocked(dev_priv, pipe);
> -
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	/* Enable back the 10bit clock to display controller */
> @@ -1589,6 +1591,21 @@ static void chv_enable_pll(struct intel_crtc *crtc,
>  	/* Check PLL is locked */
>  	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
>  		DRM_ERROR("PLL %d failed to lock\n", pipe);
> +}
> +
> +static void chv_enable_pll(struct intel_crtc *crtc,
> +			   const struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +
> +	assert_pipe_disabled(dev_priv, pipe);
> +
> +	/* PLL is protected by panel, make sure we can write it */
> +	assert_panel_unlocked(dev_priv, pipe);
> +
> +	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
> +		_chv_enable_pll(crtc, pipe_config);
>  
>  	if (pipe != PIPE_A) {
>  		/*
> @@ -6073,14 +6090,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	if (!intel_crtc->config->has_dsi_encoder) {
> -		if (IS_CHERRYVIEW(dev)) {
> -			chv_prepare_pll(intel_crtc, intel_crtc->config);
> -			chv_enable_pll(intel_crtc, intel_crtc->config);
> -		} else {
> -			vlv_prepare_pll(intel_crtc, intel_crtc->config);
> -			vlv_enable_pll(intel_crtc, intel_crtc->config);
> -		}
> +	if (IS_CHERRYVIEW(dev)) {
> +		chv_prepare_pll(intel_crtc, intel_crtc->config);
> +		chv_enable_pll(intel_crtc, intel_crtc->config);
> +	} else {
> +		vlv_prepare_pll(intel_crtc, intel_crtc->config);
> +		vlv_enable_pll(intel_crtc, intel_crtc->config);
>  	}
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
> @@ -6118,7 +6133,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_encoder *encoder;
>  	struct intel_crtc_state *pipe_config =
>  		to_intel_crtc_state(crtc->state);
> -	int pipe = intel_crtc->pipe;
> +	enum pipe pipe = intel_crtc->pipe;
>  
>  	if (WARN_ON(intel_crtc->active))
>  		return;
> @@ -7174,11 +7189,15 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
>  			     struct intel_crtc_state *pipe_config)
>  {
>  	pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> -		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> -		DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
> +		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
>  	if (crtc->pipe != PIPE_A)
>  		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  
> +	/* DPLL not used with DSI, but still need the rest set up */
> +	if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
> +		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
> +			DPLL_EXT_BUFFER_ENABLE_VLV;
> +
>  	pipe_config->dpll_hw_state.dpll_md =
>  		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  }
> @@ -7187,11 +7206,14 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
>  			     struct intel_crtc_state *pipe_config)
>  {
>  	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> -		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> -		DPLL_VCO_ENABLE;
> +		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
>  	if (crtc->pipe != PIPE_A)
>  		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  
> +	/* DPLL not used with DSI, but still need the rest set up */
> +	if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
> +		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
> +
>  	pipe_config->dpll_hw_state.dpll_md =
>  		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  }
> @@ -7201,11 +7223,20 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int pipe = crtc->pipe;
> +	enum pipe pipe = crtc->pipe;
>  	u32 mdiv;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
>  	u32 coreclk, reg_val;
>  
> +	/* Enable Refclk */
> +	I915_WRITE(DPLL(pipe),
> +		   pipe_config->dpll_hw_state.dpll &
> +		   ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
> +
> +	/* No need to actually set up the DPLL with DSI */
> +	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> +		return;
> +
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	bestn = pipe_config->dpll.n;
> @@ -7292,14 +7323,21 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int pipe = crtc->pipe;
> -	i915_reg_t dpll_reg = DPLL(crtc->pipe);
> +	enum pipe pipe = crtc->pipe;
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	u32 dpio_val;
>  	int vco;
>  
> +	/* Enable Refclk and SSC */
> +	I915_WRITE(DPLL(pipe),
> +		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
> +
> +	/* No need to actually set up the DPLL with DSI */
> +	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> +		return;
> +
>  	bestn = pipe_config->dpll.n;
>  	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
>  	bestm1 = pipe_config->dpll.m1;
> @@ -7310,12 +7348,6 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	dpio_val = 0;
>  	loopfilter = 0;
>  
> -	/*
> -	 * Enable Refclk and SSC
> -	 */
> -	I915_WRITE(dpll_reg,
> -		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
> -
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	/* p1 and p2 divider */
> @@ -7930,9 +7962,6 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc,
>  	memset(&crtc_state->dpll_hw_state, 0,
>  	       sizeof(crtc_state->dpll_hw_state));
>  
> -	if (crtc_state->has_dsi_encoder)
> -		return 0;
> -
>  	if (!crtc_state->clock_set &&
>  	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
>  				refclk, NULL, &crtc_state->dpll)) {
> @@ -7954,9 +7983,6 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
>  	memset(&crtc_state->dpll_hw_state, 0,
>  	       sizeof(crtc_state->dpll_hw_state));
>  
> -	if (crtc_state->has_dsi_encoder)
> -		return 0;
> -
>  	if (!crtc_state->clock_set &&
>  	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
>  				refclk, NULL, &crtc_state->dpll)) {
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 9ff6435e7d38..22bd42a8aab0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -311,6 +311,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
>  	}
>  
> +	/*
> +	 * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
> +	 * to .compute_config().
> +	 */
> +	pipe_config->clock_set = true;
> +
>  	return true;
>  }
>  
> @@ -498,8 +504,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum pipe pipe = intel_crtc->pipe;
>  	enum port port;
>  	u32 tmp;
>  
> @@ -521,19 +525,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  	msleep(intel_dsi->panel_on_delay);
>  
>  	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> -		/*
> -		 * Disable DPOunit clock gating, can stall pipe
> -		 * and we need DPLL REFA always enabled
> -		 */
> -		tmp = I915_READ(DPLL(pipe));
> -		tmp |= DPLL_REF_CLK_ENABLE_VLV;
> -		I915_WRITE(DPLL(pipe), tmp);
> -
> -		/* update the hw state for DPLL */
> -		intel_crtc->config->dpll_hw_state.dpll =
> -				DPLL_INTEGRATED_REF_CLK_VLV |
> -					DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> -
> +		/* Disable DPOunit clock gating, can stall pipe */
>  		tmp = I915_READ(DSPCLK_GATE_D);
>  		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
>  		I915_WRITE(DSPCLK_GATE_D, tmp);
> @@ -832,12 +824,6 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  	if (IS_BROXTON(dev))
>  		bxt_dsi_get_pipe_config(encoder, pipe_config);
>  
> -	/*
> -	 * DPLL_MD is not used in case of DSI, reading will get some default value
> -	 * set dpll_md = 0
> -	 */
> -	pipe_config->dpll_hw_state.dpll_md = 0;
> -
>  	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
>  	if (!pclk)
>  		return;

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV

[Ville Syrjälä]

On Fri, Apr 15, 2016 at 04:09:31PM +0300, Jani Nikula wrote:
> On Tue, 12 Apr 2016, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Set up DPLL and DPLL_MD even when driving DSI output on VLV/CHV. While
> > the DPLL isn't used to provide the clock we still need the refclock, and
> > it appears that the pixel repeat factor also has an effect on DSI
> > output. So set up eveyrhing in DPLL and DPLL_MD as we would do for
> > DP/HDMI/VGA, but don't actually enable the DPLL or configure the
> > dividers via DPIO.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> I quickly glanced over 2-5 too, my earlier r-b on them still stand.

Thanks. Series pushed to dinq.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 120 +++++++++++++++++++++--------------
> >  drivers/gpu/drm/i915/intel_dsi.c     |  28 ++------
> >  2 files changed, 80 insertions(+), 68 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 607dc41bcc68..7c74a930f45d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1530,45 +1530,47 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> >  	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
> >  }
> >  
> > +static void _vlv_enable_pll(struct intel_crtc *crtc,
> > +			    const struct intel_crtc_state *pipe_config)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> > +
> > +	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
> > +	POSTING_READ(DPLL(pipe));
> > +	udelay(150);
> > +
> > +	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> > +		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> > +}
> > +
> >  static void vlv_enable_pll(struct intel_crtc *crtc,
> >  			   const struct intel_crtc_state *pipe_config)
> >  {
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	enum pipe pipe = crtc->pipe;
> > -	i915_reg_t reg = DPLL(pipe);
> > -	u32 dpll = pipe_config->dpll_hw_state.dpll;
> >  
> >  	assert_pipe_disabled(dev_priv, pipe);
> >  
> >  	/* PLL is protected by panel, make sure we can write it */
> >  	assert_panel_unlocked(dev_priv, pipe);
> >  
> > -	I915_WRITE(reg, dpll);
> > -	POSTING_READ(reg);
> > -	udelay(150);
> > -
> > -	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> > -		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> > +	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
> > +		_vlv_enable_pll(crtc, pipe_config);
> >  
> >  	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> >  	POSTING_READ(DPLL_MD(pipe));
> >  }
> >  
> > -static void chv_enable_pll(struct intel_crtc *crtc,
> > -			   const struct intel_crtc_state *pipe_config)
> > +
> > +static void _chv_enable_pll(struct intel_crtc *crtc,
> > +			    const struct intel_crtc_state *pipe_config)
> >  {
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	enum pipe pipe = crtc->pipe;
> >  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> >  	u32 tmp;
> >  
> > -	assert_pipe_disabled(dev_priv, pipe);
> > -
> > -	/* PLL is protected by panel, make sure we can write it */
> > -	assert_panel_unlocked(dev_priv, pipe);
> > -
> >  	mutex_lock(&dev_priv->sb_lock);
> >  
> >  	/* Enable back the 10bit clock to display controller */
> > @@ -1589,6 +1591,21 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> >  	/* Check PLL is locked */
> >  	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> >  		DRM_ERROR("PLL %d failed to lock\n", pipe);
> > +}
> > +
> > +static void chv_enable_pll(struct intel_crtc *crtc,
> > +			   const struct intel_crtc_state *pipe_config)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> > +
> > +	assert_pipe_disabled(dev_priv, pipe);
> > +
> > +	/* PLL is protected by panel, make sure we can write it */
> > +	assert_panel_unlocked(dev_priv, pipe);
> > +
> > +	if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
> > +		_chv_enable_pll(crtc, pipe_config);
> >  
> >  	if (pipe != PIPE_A) {
> >  		/*
> > @@ -6073,14 +6090,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> >  		if (encoder->pre_pll_enable)
> >  			encoder->pre_pll_enable(encoder);
> >  
> > -	if (!intel_crtc->config->has_dsi_encoder) {
> > -		if (IS_CHERRYVIEW(dev)) {
> > -			chv_prepare_pll(intel_crtc, intel_crtc->config);
> > -			chv_enable_pll(intel_crtc, intel_crtc->config);
> > -		} else {
> > -			vlv_prepare_pll(intel_crtc, intel_crtc->config);
> > -			vlv_enable_pll(intel_crtc, intel_crtc->config);
> > -		}
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		chv_prepare_pll(intel_crtc, intel_crtc->config);
> > +		chv_enable_pll(intel_crtc, intel_crtc->config);
> > +	} else {
> > +		vlv_prepare_pll(intel_crtc, intel_crtc->config);
> > +		vlv_enable_pll(intel_crtc, intel_crtc->config);
> >  	}
> >  
> >  	for_each_encoder_on_crtc(dev, crtc, encoder)
> > @@ -6118,7 +6133,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> >  	struct intel_encoder *encoder;
> >  	struct intel_crtc_state *pipe_config =
> >  		to_intel_crtc_state(crtc->state);
> > -	int pipe = intel_crtc->pipe;
> > +	enum pipe pipe = intel_crtc->pipe;
> >  
> >  	if (WARN_ON(intel_crtc->active))
> >  		return;
> > @@ -7174,11 +7189,15 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
> >  			     struct intel_crtc_state *pipe_config)
> >  {
> >  	pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> > -		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> > -		DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
> > +		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> >  	if (crtc->pipe != PIPE_A)
> >  		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >  
> > +	/* DPLL not used with DSI, but still need the rest set up */
> > +	if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
> > +		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
> > +			DPLL_EXT_BUFFER_ENABLE_VLV;
> > +
> >  	pipe_config->dpll_hw_state.dpll_md =
> >  		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> >  }
> > @@ -7187,11 +7206,14 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
> >  			     struct intel_crtc_state *pipe_config)
> >  {
> >  	pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> > -		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> > -		DPLL_VCO_ENABLE;
> > +		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> >  	if (crtc->pipe != PIPE_A)
> >  		pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >  
> > +	/* DPLL not used with DSI, but still need the rest set up */
> > +	if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
> > +		pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
> > +
> >  	pipe_config->dpll_hw_state.dpll_md =
> >  		(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> >  }
> > @@ -7201,11 +7223,20 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	int pipe = crtc->pipe;
> > +	enum pipe pipe = crtc->pipe;
> >  	u32 mdiv;
> >  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> >  	u32 coreclk, reg_val;
> >  
> > +	/* Enable Refclk */
> > +	I915_WRITE(DPLL(pipe),
> > +		   pipe_config->dpll_hw_state.dpll &
> > +		   ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
> > +
> > +	/* No need to actually set up the DPLL with DSI */
> > +	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> > +		return;
> > +
> >  	mutex_lock(&dev_priv->sb_lock);
> >  
> >  	bestn = pipe_config->dpll.n;
> > @@ -7292,14 +7323,21 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	int pipe = crtc->pipe;
> > -	i915_reg_t dpll_reg = DPLL(crtc->pipe);
> > +	enum pipe pipe = crtc->pipe;
> >  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> >  	u32 loopfilter, tribuf_calcntr;
> >  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> >  	u32 dpio_val;
> >  	int vco;
> >  
> > +	/* Enable Refclk and SSC */
> > +	I915_WRITE(DPLL(pipe),
> > +		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
> > +
> > +	/* No need to actually set up the DPLL with DSI */
> > +	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> > +		return;
> > +
> >  	bestn = pipe_config->dpll.n;
> >  	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
> >  	bestm1 = pipe_config->dpll.m1;
> > @@ -7310,12 +7348,6 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> >  	dpio_val = 0;
> >  	loopfilter = 0;
> >  
> > -	/*
> > -	 * Enable Refclk and SSC
> > -	 */
> > -	I915_WRITE(dpll_reg,
> > -		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
> > -
> >  	mutex_lock(&dev_priv->sb_lock);
> >  
> >  	/* p1 and p2 divider */
> > @@ -7930,9 +7962,6 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc,
> >  	memset(&crtc_state->dpll_hw_state, 0,
> >  	       sizeof(crtc_state->dpll_hw_state));
> >  
> > -	if (crtc_state->has_dsi_encoder)
> > -		return 0;
> > -
> >  	if (!crtc_state->clock_set &&
> >  	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> >  				refclk, NULL, &crtc_state->dpll)) {
> > @@ -7954,9 +7983,6 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
> >  	memset(&crtc_state->dpll_hw_state, 0,
> >  	       sizeof(crtc_state->dpll_hw_state));
> >  
> > -	if (crtc_state->has_dsi_encoder)
> > -		return 0;
> > -
> >  	if (!crtc_state->clock_set &&
> >  	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> >  				refclk, NULL, &crtc_state->dpll)) {
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index 9ff6435e7d38..22bd42a8aab0 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -311,6 +311,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> >  			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
> >  	}
> >  
> > +	/*
> > +	 * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
> > +	 * to .compute_config().
> > +	 */
> > +	pipe_config->clock_set = true;
> > +
> >  	return true;
> >  }
> >  
> > @@ -498,8 +504,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> >  	struct drm_device *dev = encoder->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> > -	enum pipe pipe = intel_crtc->pipe;
> >  	enum port port;
> >  	u32 tmp;
> >  
> > @@ -521,19 +525,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> >  	msleep(intel_dsi->panel_on_delay);
> >  
> >  	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > -		/*
> > -		 * Disable DPOunit clock gating, can stall pipe
> > -		 * and we need DPLL REFA always enabled
> > -		 */
> > -		tmp = I915_READ(DPLL(pipe));
> > -		tmp |= DPLL_REF_CLK_ENABLE_VLV;
> > -		I915_WRITE(DPLL(pipe), tmp);
> > -
> > -		/* update the hw state for DPLL */
> > -		intel_crtc->config->dpll_hw_state.dpll =
> > -				DPLL_INTEGRATED_REF_CLK_VLV |
> > -					DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > -
> > +		/* Disable DPOunit clock gating, can stall pipe */
> >  		tmp = I915_READ(DSPCLK_GATE_D);
> >  		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
> >  		I915_WRITE(DSPCLK_GATE_D, tmp);
> > @@ -832,12 +824,6 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> >  	if (IS_BROXTON(dev))
> >  		bxt_dsi_get_pipe_config(encoder, pipe_config);
> >  
> > -	/*
> > -	 * DPLL_MD is not used in case of DSI, reading will get some default value
> > -	 * set dpll_md = 0
> > -	 */
> > -	pipe_config->dpll_hw_state.dpll_md = 0;
> > -
> >  	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
> >  	if (!pclk)
> >  		return;
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/5] drm/i915: Compute DSI PLL parameters during .compute_config()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Compute the DSI PLL parameters during .compute_config() rather than
.pre_pll_enable() so that we can fail gracefully if we can't find
suitable parameters.

In order to do that we need to store the DSI PLL parameters in
pipe_config.

v2: Handle BXT too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   3 +
 drivers/gpu/drm/i915/intel_drv.h     |   5 ++
 drivers/gpu/drm/i915/intel_dsi.c     |  15 ++--
 drivers/gpu/drm/i915/intel_dsi.h     |  14 ++--
 drivers/gpu/drm/i915/intel_dsi_pll.c | 156 +++++++++++++++++++----------------
 5 files changed, 112 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7c74a930f45d..017dad536492 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12752,6 +12752,9 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
 	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
 
+	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+	PIPE_CONF_CHECK_X(dsi_pll.div);
+
 	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e0fcfa1683cc..a4d375dd068f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -497,6 +497,11 @@ struct intel_crtc_state {
 	/* Actual register state of the dpll, for shared dpll cross-checking. */
 	struct intel_dpll_hw_state dpll_hw_state;
 
+	/* DSI PLL registers */
+	struct {
+		u32 ctrl, div;
+	} dsi_pll;
+
 	int pipe_bpp;
 	struct intel_link_m_n dp_m_n;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 22bd42a8aab0..c43c8caf8c95 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -292,6 +292,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	int ret;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -311,10 +312,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 	}
 
-	/*
-	 * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
-	 * to .compute_config().
-	 */
+	ret = intel_compute_dsi_pll(encoder, pipe_config);
+	if (ret)
+		return false;
+
 	pipe_config->clock_set = true;
 
 	return true;
@@ -504,6 +505,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	enum port port;
 	u32 tmp;
 
@@ -514,7 +516,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 	 * lock. It needs to be fully powered down to fix it.
 	 */
 	intel_disable_dsi_pll(encoder);
-	intel_enable_dsi_pll(encoder);
+	intel_enable_dsi_pll(encoder, crtc->config);
 
 	intel_dsi_prepare(encoder);
 
@@ -824,7 +826,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 	if (IS_BROXTON(dev))
 		bxt_dsi_get_pipe_config(encoder, pipe_config);
 
-	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
+	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
+				  pipe_config);
 	if (!pclk)
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index dabde19ee8aa..61a6957fc6c2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -127,11 +127,15 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 }
 
 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
-extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
-extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
-extern u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp);
-extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
-							enum port port);
+int intel_compute_dsi_pll(struct intel_encoder *encoder,
+			  struct intel_crtc_state *config);
+void intel_enable_dsi_pll(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *config);
+void intel_disable_dsi_pll(struct intel_encoder *encoder);
+u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+		       struct intel_crtc_state *config);
+void intel_dsi_reset_clocks(struct intel_encoder *encoder,
+			    enum port port);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 7ad59d13dd4c..115f59646514 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -30,11 +30,6 @@
 #include "i915_drv.h"
 #include "intel_dsi.h"
 
-struct dsi_mnp {
-	u32 dsi_pll_ctrl;
-	u32 dsi_pll_div;
-};
-
 static const u16 lfsr_converts[] = {
 	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
 	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
@@ -57,7 +52,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
 }
 
 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
-			struct dsi_mnp *dsi_mnp, int target_dsi_clk)
+			struct intel_crtc_state *config,
+			int target_dsi_clk)
 {
 	unsigned int calc_m = 0, calc_p = 0;
 	unsigned int m_min, m_max, p_min = 2, p_max = 6;
@@ -103,8 +99,8 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
 	/* register has log2(N1), this works fine for powers of two */
 	n = ffs(n) - 1;
 	m_seed = lfsr_converts[calc_m - 62];
-	dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
-	dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
+	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
+	config->dsi_pll.div = n << DSI_PLL_N1_DIV_SHIFT |
 		m_seed << DSI_PLL_M1_DIV_SHIFT;
 
 	return 0;
@@ -114,54 +110,63 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
  * XXX: The muxing and gating is hard coded for now. Need to add support for
  * sharing PLLs with two DSI outputs.
  */
-static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
+static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
+			       struct intel_crtc_state *config)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	int ret;
-	struct dsi_mnp dsi_mnp;
 	u32 dsi_clk;
 
 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
 				    intel_dsi->lane_count);
 
-	ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
+	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
 	if (ret) {
 		DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
-		return;
+		return ret;
 	}
 
 	if (intel_dsi->ports & (1 << PORT_A))
-		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
+		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
 	if (intel_dsi->ports & (1 << PORT_C))
-		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+
+	config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
 
 	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
-		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
+		      config->dsi_pll.div, config->dsi_pll.ctrl);
+
+	return 0;
+}
+
+static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
-	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
-	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
+	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
+	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
+		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
 }
 
-static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
+static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *config)
 {
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	u32 tmp;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	DRM_DEBUG_KMS("\n");
 
 	mutex_lock(&dev_priv->sb_lock);
 
-	vlv_configure_dsi_pll(encoder);
+	vlv_configure_dsi_pll(encoder, config);
 
 	/* wait at least 0.5 us after ungating before enabling VCO */
 	usleep_range(1, 10);
 
-	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
-	tmp |= DSI_PLL_VCO_EN;
-	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
+	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
 
 	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
 						DSI_PLL_LOCK, 20)) {
@@ -177,7 +182,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
 
 static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u32 tmp;
 
 	DRM_DEBUG_KMS("\n");
@@ -224,7 +229,7 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
 
 static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
@@ -251,9 +256,10 @@ static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
 	     bpp, pipe_bpp);
 }
 
-static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
+static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+			    struct intel_crtc_state *config)
 {
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 dsi_clock, pclk;
 	u32 pll_ctl, pll_div;
@@ -268,6 +274,9 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
 	mutex_unlock(&dev_priv->sb_lock);
 
+	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
+	config->dsi_pll.div = pll_div;
+
 	/* mask out other bits and extract the P1 divisor */
 	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
 	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
@@ -313,7 +322,8 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	return pclk;
 }
 
-static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
+static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+			    struct intel_crtc_state *config)
 {
 	u32 pclk;
 	u32 dsi_clk;
@@ -327,15 +337,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
 		return 0;
 	}
 
-	dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
-				BXT_DSI_PLL_RATIO_MASK;
+	config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
 
-	/* Invalid DSI ratio ? */
-	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
-			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
-		DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
-		return 0;
-	}
+	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
 
 	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
 
@@ -348,12 +352,13 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	return pclk;
 }
 
-u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
+u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+		       struct intel_crtc_state *config)
 {
 	if (IS_BROXTON(encoder->base.dev))
-		return bxt_dsi_get_pclk(encoder, pipe_bpp);
+		return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
 	else
-		return vlv_dsi_get_pclk(encoder, pipe_bpp);
+		return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
 }
 
 static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
@@ -370,7 +375,8 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 }
 
 /* Program BXT Mipi clocks and dividers */
-static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
+static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
+				   const struct intel_crtc_state *config)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 tmp;
@@ -390,8 +396,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
 	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
 
 	/* Get the current DSI rate(actual) */
-	pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
-				BXT_DSI_PLL_RATIO_MASK;
+	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
 	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
 
 	/*
@@ -427,16 +432,15 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
 	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
 }
 
-static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
+static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
+			       struct intel_crtc_state *config)
 {
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u8 dsi_ratio;
 	u32 dsi_clk;
-	u32 val;
 
 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
-			intel_dsi->lane_count);
+				    intel_dsi->lane_count);
 
 	/*
 	 * From clock diagram, to get PLL ratio divider, divide double of DSI
@@ -445,9 +449,9 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 	 */
 	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
 	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
-			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+	    dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
 		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
-		return false;
+		return -ECHRNG;
 	}
 
 	/*
@@ -455,27 +459,28 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 	 * Spec says both have to be programmed, even if one is not getting
 	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
 	 */
-	val = I915_READ(BXT_DSI_PLL_CTL);
-	val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
-	val &= ~BXT_DSI_FREQ_SEL_MASK;
-	val &= ~BXT_DSI_PLL_RATIO_MASK;
-	val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
+	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
 
 	/* As per recommendation from hardware team,
 	 * Prog PVD ratio =1 if dsi ratio <= 50
 	 */
-	if (dsi_ratio <= 50) {
-		val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
-		val |= BXT_DSI_PLL_PVD_RATIO_1;
-	}
+	if (dsi_ratio <= 50)
+		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
 
-	I915_WRITE(BXT_DSI_PLL_CTL, val);
-	POSTING_READ(BXT_DSI_PLL_CTL);
+	return 0;
+}
 
-	return true;
+static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
+	POSTING_READ(BXT_DSI_PLL_CTL);
 }
 
-static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
+static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *config)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -485,14 +490,11 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
 	DRM_DEBUG_KMS("\n");
 
 	/* Configure PLL vales */
-	if (!bxt_configure_dsi_pll(encoder)) {
-		DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
-		return;
-	}
+	bxt_configure_dsi_pll(encoder, config);
 
 	/* Program TX, RX, Dphy clocks */
 	for_each_dsi_port(port, intel_dsi->ports)
-		bxt_dsi_program_clocks(encoder->base.dev, port);
+		bxt_dsi_program_clocks(encoder->base.dev, port, config);
 
 	/* Enable DSI PLL */
 	val = I915_READ(BXT_DSI_PLL_ENABLE);
@@ -518,14 +520,28 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
 	return false;
 }
 
-void intel_enable_dsi_pll(struct intel_encoder *encoder)
+int intel_compute_dsi_pll(struct intel_encoder *encoder,
+			  struct intel_crtc_state *config)
+{
+	struct drm_device *dev = encoder->base.dev;
+
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+		return vlv_compute_dsi_pll(encoder, config);
+	else if (IS_BROXTON(dev))
+		return bxt_compute_dsi_pll(encoder, config);
+
+	return -ENODEV;
+}
+
+void intel_enable_dsi_pll(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *config)
 {
 	struct drm_device *dev = encoder->base.dev;
 
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
-		vlv_enable_dsi_pll(encoder);
+		vlv_enable_dsi_pll(encoder, config);
 	else if (IS_BROXTON(dev))
-		bxt_enable_dsi_pll(encoder);
+		bxt_enable_dsi_pll(encoder, config);
 }
 
 void intel_disable_dsi_pll(struct intel_encoder *encoder)
-- 
2.7.4

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[PATCH 3/5] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fold the DSI PLL configuration functions into the DSI PLL
enable functions since they are small and not called from anywhere else.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 28 ++++++----------------------
 1 file changed, 6 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 115f59646514..1765e6e18f2c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -141,17 +141,6 @@ static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
 	return 0;
 }
 
-static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *config)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
-	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
-	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
-	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
-		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
-}
-
 static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *config)
 {
@@ -161,7 +150,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->sb_lock);
 
-	vlv_configure_dsi_pll(encoder, config);
+	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
+	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
+	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
+		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
 
 	/* wait at least 0.5 us after ungating before enabling VCO */
 	usleep_range(1, 10);
@@ -470,15 +462,6 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
 	return 0;
 }
 
-static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *config)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
-	I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
-	POSTING_READ(BXT_DSI_PLL_CTL);
-}
-
 static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *config)
 {
@@ -490,7 +473,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 	DRM_DEBUG_KMS("\n");
 
 	/* Configure PLL vales */
-	bxt_configure_dsi_pll(encoder, config);
+	I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
+	POSTING_READ(BXT_DSI_PLL_CTL);
 
 	/* Program TX, RX, Dphy clocks */
 	for_each_dsi_port(port, intel_dsi->ports)
-- 
2.7.4

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[PATCH 4/5] drm/i915: Hook up pfit for DSI

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the scaling mode property to DSI connectors, handle changes in the
property value, and compute the panel fitter state during
.compute_config().

v2: Handle BXT as well

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 73 +++++++++++++++++++++++++++++++++++++---
 1 file changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c43c8caf8c95..d94193aa6ffc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -290,7 +290,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 						   base);
 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
-	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int ret;
 
@@ -298,9 +299,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 
 	pipe_config->has_dsi_encoder = true;
 
-	if (fixed_mode)
+	if (fixed_mode) {
 		intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 
+		if (HAS_GMCH_DISPLAY(dev_priv))
+			intel_gmch_panel_fitting(crtc, pipe_config,
+						 intel_connector->panel.fitting_mode);
+		else
+			intel_pch_panel_fitting(crtc, pipe_config,
+						intel_connector->panel.fitting_mode);
+	}
+
 	/* DSI uses short packets for sync events, so clear mode flags for DSI */
 	adjusted_mode->flags = 0;
 
@@ -840,7 +849,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
-	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	DRM_DEBUG_KMS("\n");
@@ -1178,6 +1187,43 @@ static int intel_dsi_get_modes(struct drm_connector *connector)
 	return 1;
 }
 
+static int intel_dsi_set_property(struct drm_connector *connector,
+				  struct drm_property *property,
+				  uint64_t val)
+{
+	struct drm_device *dev = connector->dev;
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct drm_crtc *crtc;
+	int ret;
+
+	ret = drm_object_property_set_value(&connector->base, property, val);
+	if (ret)
+		return ret;
+
+	if (property == dev->mode_config.scaling_mode_property) {
+		if (val == DRM_MODE_SCALE_NONE) {
+			DRM_DEBUG_KMS("no scaling not supported\n");
+			return -EINVAL;
+		}
+
+		if (intel_connector->panel.fitting_mode == val)
+			return 0;
+
+		intel_connector->panel.fitting_mode = val;
+	}
+
+	crtc = intel_attached_encoder(connector)->base.crtc;
+	if (crtc && crtc->state->enable) {
+		/*
+		 * If the CRTC is enabled, the display will be changed
+		 * according to the new panel fitting mode.
+		 */
+		intel_crtc_restore_mode(crtc);
+	}
+
+	return 0;
+}
+
 static void intel_dsi_connector_destroy(struct drm_connector *connector)
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -1220,11 +1266,25 @@ static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 	.detect = intel_dsi_detect,
 	.destroy = intel_dsi_connector_destroy,
 	.fill_modes = drm_helper_probe_single_connector_modes,
+	.set_property = intel_dsi_set_property,
 	.atomic_get_property = intel_connector_atomic_get_property,
 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 };
 
+static void intel_dsi_add_properties(struct intel_connector *connector)
+{
+	struct drm_device *dev = connector->base.dev;
+
+	if (connector->panel.fixed_mode) {
+		drm_mode_create_scaling_mode_property(dev);
+		drm_object_attach_property(&connector->base.base,
+					   dev->mode_config.scaling_mode_property,
+					   DRM_MODE_SCALE_ASPECT);
+		connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
+	}
+}
+
 void intel_dsi_init(struct drm_device *dev)
 {
 	struct intel_dsi *intel_dsi;
@@ -1348,8 +1408,6 @@ void intel_dsi_init(struct drm_device *dev)
 
 	intel_connector_attach_encoder(intel_connector, intel_encoder);
 
-	drm_connector_register(connector);
-
 	drm_panel_attach(intel_dsi->panel, connector);
 
 	mutex_lock(&dev->mode_config.mutex);
@@ -1368,6 +1426,11 @@ void intel_dsi_init(struct drm_device *dev)
 	}
 
 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+
+	intel_dsi_add_properties(intel_connector);
+
+	drm_connector_register(connector);
+
 	intel_panel_setup_backlight(connector, INVALID_PIPE);
 
 	return;
-- 
2.7.4

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[PATCH 5/5] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We don't have a LVDS_BORDER_ENABLE type of bit for either eDP or DSI,
and just trying to frob the display timings to include borders results
in a corrupted picture. So reject the 'Center' scaling mode on GMCH
platforms for eDP and DSI.

TODO: Should really filter out the unsupported modes from the prop,
but that would be fairly invasive since the prop is now created and
stored by drm core. So leave it for a rainy day.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 5 +++++
 drivers/gpu/drm/i915/intel_dsi.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7523558190d1..61ee22664ee7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4821,6 +4821,11 @@ intel_dp_set_property(struct drm_connector *connector,
 			DRM_DEBUG_KMS("no scaling not supported\n");
 			return -EINVAL;
 		}
+		if (HAS_GMCH_DISPLAY(dev_priv) &&
+		    val == DRM_MODE_SCALE_CENTER) {
+			DRM_DEBUG_KMS("centering not supported\n");
+			return -EINVAL;
+		}
 
 		if (intel_connector->panel.fitting_mode == val) {
 			/* the eDP scaling property is not changed */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d94193aa6ffc..a3cb89ee7fd0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1205,6 +1205,11 @@ static int intel_dsi_set_property(struct drm_connector *connector,
 			DRM_DEBUG_KMS("no scaling not supported\n");
 			return -EINVAL;
 		}
+		if (HAS_GMCH_DISPLAY(dev) &&
+		    val == DRM_MODE_SCALE_CENTER) {
+			DRM_DEBUG_KMS("centering not supported\n");
+			return -EINVAL;
+		}
 
 		if (intel_connector->panel.fitting_mode == val)
 			return 0;
-- 
2.7.4

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✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Rest of my DSI and DPLL stuff
URL   : https://patchwork.freedesktop.org/series/5610/
State : failure

== Summary ==

Series 5610v1 drm/i915: Rest of my DSI and DPLL stuff
http://patchwork.freedesktop.org/api/1.0/series/5610/revisions/1/mbox/

Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> DMESG-WARN (ilk-hp8440p)
Test gem_busy:
        Subgroup basic-bsd:
                pass       -> SKIP       (ilk-hp8440p)
        Subgroup basic-render:
                pass       -> SKIP       (ilk-hp8440p)
Test gem_cpu_reloc:
        Subgroup basic:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_cs_tlb:
        Subgroup basic-default:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_exec_basic:
        Subgroup basic-default:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup basic-render:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup gtt-bsd:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup gtt-default:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup readonly-bsd:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup readonly-default:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_exec_create:
        Subgroup basic:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_exec_nop:
        Subgroup basic:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_exec_store:
        Subgroup basic-bsd:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup basic-default:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup basic-render:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_exec_suspend:
        Subgroup basic-s3:
                incomplete -> PASS       (hsw-gt2)
                pass       -> SKIP       (ilk-hp8440p)
Test gem_exec_whisper:
        Subgroup basic:
                pass       -> SKIP       (ilk-hp8440p)
Test gem_linear_blits:
        Subgroup basic:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_ringfill:
        Subgroup basic-default:
                pass       -> SKIP       (ilk-hp8440p)
        Subgroup basic-default-interruptible:
                pass       -> SKIP       (ilk-hp8440p)
Test gem_sync:
        Subgroup basic-all:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup basic-default:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup basic-each:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup basic-render:
                pass       -> FAIL       (ilk-hp8440p)
Test gem_tiled_fence_blits:
        Subgroup basic:
                pass       -> FAIL       (ilk-hp8440p)
Test kms_force_connector_basic:
        Subgroup prune-stale-modes:
                pass       -> SKIP       (ivb-t430s)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup hang-read-crc-pipe-b:
                pass       -> FAIL       (ilk-hp8440p)
        Subgroup hang-read-crc-pipe-c:
                skip       -> FAIL       (ilk-hp8440p)
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-FAIL (ilk-hp8440p)
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-FAIL (ilk-hp8440p)

bdw-nuci7        total:203  pass:191  dwarn:0   dfail:0   fail:0   skip:12 
bsw-nuc-2        total:202  pass:163  dwarn:0   dfail:0   fail:0   skip:39 
byt-nuc          total:202  pass:164  dwarn:0   dfail:0   fail:0   skip:38 
hsw-brixbox      total:203  pass:179  dwarn:0   dfail:0   fail:0   skip:24 
hsw-gt2          total:203  pass:184  dwarn:0   dfail:0   fail:0   skip:19 
ilk-hp8440p      total:203  pass:105  dwarn:1   dfail:2   fail:22  skip:73 
ivb-t430s        total:203  pass:174  dwarn:0   dfail:0   fail:0   skip:29 
skl-i7k-2        total:203  pass:178  dwarn:0   dfail:0   fail:0   skip:25 
skl-nuci5        total:203  pass:192  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:203  pass:165  dwarn:0   dfail:0   fail:0   skip:38 
snb-x220t        total:203  pass:165  dwarn:0   dfail:0   fail:1   skip:37 
BOOT FAILED for bdw-ultra

Results at /archive/results/CI_IGT_test/Patchwork_1881/

631ffd2f45bb43964f729e8661532fb115f5eeec drm-intel-nightly: 2016y-04m-13d-13h-00m-18s UTC integration manifest
cb48288 drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
9498c94 drm/i915: Hook up pfit for DSI
b94623e drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()
546b2ef drm/i915: Compute DSI PLL parameters during .compute_config()
ae0326a drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV

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Re: ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff

[Ville Syrjälä]

On Wed, Apr 13, 2016 at 04:02:17PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Rest of my DSI and DPLL stuff
> URL   : https://patchwork.freedesktop.org/series/5610/
> State : failure
> 
> == Summary ==
> 
> Series 5610v1 drm/i915: Rest of my DSI and DPLL stuff
> http://patchwork.freedesktop.org/api/1.0/series/5610/revisions/1/mbox/
> 
> Test drv_hangman:
>         Subgroup error-state-basic:
>                 pass       -> DMESG-WARN (ilk-hp8440p)
> Test gem_busy:
>         Subgroup basic-bsd:
>                 pass       -> SKIP       (ilk-hp8440p)
>         Subgroup basic-render:
>                 pass       -> SKIP       (ilk-hp8440p)
> Test gem_cpu_reloc:
>         Subgroup basic:
>                 pass       -> FAIL       (ilk-hp8440p)

...

[  265.316531] drm/i915: Resetting chip after gpu hang
[  265.316585] [drm:i915_reset [i915]] *ERROR* Failed to reset chip: -110

Looks like the GPU died for some reason.

> Test kms_force_connector_basic:
>         Subgroup prune-stale-modes:
>                 pass       -> SKIP       (ivb-t430s)

No clue what happened here. The change isn't visible in the results
visualization page, nor can I see this subtest even being run in
the dmesg for Patchwork_1881. The dmesg ends at gtt-blt, but based on
the json there were a ton of tests run after that. In fact the json
and dmesg seem totally out of sync.

Tomi, any idea what's going on here?

> Test kms_pipe_crc_basic:
>         Subgroup hang-read-crc-pipe-a:
>                 pass       -> FAIL       (ilk-hp8440p)
>         Subgroup hang-read-crc-pipe-b:
>                 pass       -> FAIL       (ilk-hp8440p)
>         Subgroup hang-read-crc-pipe-c:
>                 skip       -> FAIL       (ilk-hp8440p)
>         Subgroup suspend-read-crc-pipe-a:
>                 pass       -> DMESG-FAIL (ilk-hp8440p)
>         Subgroup suspend-read-crc-pipe-b:
>                 pass       -> DMESG-FAIL (ilk-hp8440p)
> 
> bdw-nuci7        total:203  pass:191  dwarn:0   dfail:0   fail:0   skip:12 
> bsw-nuc-2        total:202  pass:163  dwarn:0   dfail:0   fail:0   skip:39 
> byt-nuc          total:202  pass:164  dwarn:0   dfail:0   fail:0   skip:38 
> hsw-brixbox      total:203  pass:179  dwarn:0   dfail:0   fail:0   skip:24 
> hsw-gt2          total:203  pass:184  dwarn:0   dfail:0   fail:0   skip:19 
> ilk-hp8440p      total:203  pass:105  dwarn:1   dfail:2   fail:22  skip:73 
> ivb-t430s        total:203  pass:174  dwarn:0   dfail:0   fail:0   skip:29 
> skl-i7k-2        total:203  pass:178  dwarn:0   dfail:0   fail:0   skip:25 
> skl-nuci5        total:203  pass:192  dwarn:0   dfail:0   fail:0   skip:11 
> snb-dellxps      total:203  pass:165  dwarn:0   dfail:0   fail:0   skip:38 
> snb-x220t        total:203  pass:165  dwarn:0   dfail:0   fail:1   skip:37 
> BOOT FAILED for bdw-ultra
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1881/
> 
> 631ffd2f45bb43964f729e8661532fb115f5eeec drm-intel-nightly: 2016y-04m-13d-13h-00m-18s UTC integration manifest
> cb48288 drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
> 9498c94 drm/i915: Hook up pfit for DSI
> b94623e drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()
> 546b2ef drm/i915: Compute DSI PLL parameters during .compute_config()
> ae0326a drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV

-- 
Ville Syrjälä
Intel OTC
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Re: ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff

[Tomi Sarvela]

[-- Attachment #1.1: Type: text/plain, Size: 1462 bytes --]

On Wednesday 13 April 2016 19:29:25 Ville Syrjälä wrote:
[ILK-hp8440p problems]
> ...
> 
> [  265.316531] drm/i915: Resetting chip after gpu hang
> [  265.316585] [drm:i915_reset [i915]] *ERROR* Failed to reset chip: -110
> 
> Looks like the GPU died for some reason.
> 
> > Test kms_force_connector_basic:
> >         Subgroup prune-stale-modes:
> >                 pass       -> SKIP       (ivb-t430s)
> 
> No clue what happened here. The change isn't visible in the results
> visualization page, nor can I see this subtest even being run in
> the dmesg for Patchwork_1881. The dmesg ends at gtt-blt, but based on
> the json there were a ton of tests run after that. In fact the json
> and dmesg seem totally out of sync.
> 
> Tomi, any idea what's going on here?

The link from Patchwork page is hosed, but the full dmesgs are at
http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ilk-hp8440p/[1] 
http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ivb-t430s/[2] 

The dmesg is synced, but if the reset happens with delay, then it might be in wrong 
place. I'm suggesting to search for  test name and looking upwards from there.

> > Results at /archive/results/CI_IGT_test/Patchwork_1881/

Tomi

--------
[1] http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ilk-hp8440p/
[2] http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ivb-t430s/

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Re: ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff

[Ville Syrjälä]

On Thu, Apr 14, 2016 at 10:24:23AM +0300, Tomi Sarvela wrote:
> On Wednesday 13 April 2016 19:29:25 Ville Syrjälä wrote:
> [ILK-hp8440p problems]
> > ...
> > 
> > [  265.316531] drm/i915: Resetting chip after gpu hang
> > [  265.316585] [drm:i915_reset [i915]] *ERROR* Failed to reset chip: -110
> > 
> > Looks like the GPU died for some reason.
> > 
> > > Test kms_force_connector_basic:
> > >         Subgroup prune-stale-modes:
> > >                 pass       -> SKIP       (ivb-t430s)
> > 
> > No clue what happened here. The change isn't visible in the results
> > visualization page, nor can I see this subtest even being run in
> > the dmesg for Patchwork_1881. The dmesg ends at gtt-blt, but based on
> > the json there were a ton of tests run after that. In fact the json
> > and dmesg seem totally out of sync.
> > 
> > Tomi, any idea what's going on here?
> 
> The link from Patchwork page is hosed, but the full dmesgs are at
> http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ilk-hp8440p/[1] 
> http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ivb-t430s/[2] 

Not sure what you mean with hosed. It took me to the same place where I
was before (ie. [2]). But if you look at the dmesg vs. results.json the
order of the tests is totally different. I thought the json would show
them in the order they were run, but maybe I'm wrong?

I did find the skipped kms_force_connector_basic/prune-stale-modes in
the dmesg eventually, but it was a bit more difficult since it skipped
already from a fixture, and so the subtest name was never recorded in
the dmesg, which is a bit unfortunate. As far as the skipping goes, it
look like the VGA connector flips to 'connected' after every suspend
for some reason, and then goes back to 'disconnected' at some point. So
it feels like we have a bug in the connector resume handling still.

> 
> The dmesg is synced, but if the reset happens with delay, then it might be in wrong 
> place. I'm suggesting to search for  test name and looking upwards from there.
> 
> > > Results at /archive/results/CI_IGT_test/Patchwork_1881/
> 
> Tomi
> 
> --------
> [1] http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ilk-hp8440p/
> [2] http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ivb-t430s/

-- 
Ville Syrjälä
Intel OTC
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Re: ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff

[Tomi Sarvela]

On Thursday 14 April 2016 11:46:12 Ville Syrjälä wrote:
> On Thu, Apr 14, 2016 at 10:24:23AM +0300, Tomi Sarvela wrote:
> > On Wednesday 13 April 2016 19:29:25 Ville Syrjälä wrote:
> > [ILK-hp8440p problems]
> > 
> > > ...
> > > 
> > > [  265.316531] drm/i915: Resetting chip after gpu hang
> > > [  265.316585] [drm:i915_reset [i915]] *ERROR* Failed to reset chip:
> > > -110
> > > 
> > > Looks like the GPU died for some reason.
> > > 
> > > > Test kms_force_connector_basic:
> > > >         Subgroup prune-stale-modes:
> > > >                 pass       -> SKIP       (ivb-t430s)
> > > 
> > > No clue what happened here. The change isn't visible in the results
> > > visualization page, nor can I see this subtest even being run in
> > > the dmesg for Patchwork_1881. The dmesg ends at gtt-blt, but based on
> > > the json there were a ton of tests run after that. In fact the json
> > > and dmesg seem totally out of sync.
> > > 
> > > Tomi, any idea what's going on here?
> > 
> > The link from Patchwork page is hosed, but the full dmesgs are at
> > http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/il
> > k-hp8440p/[1]
> > http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/i
> > vb-t430s/[2]
> Not sure what you mean with hosed. It took me to the same place where I
> was before (ie. [2]). But if you look at the dmesg vs. results.json the
> order of the tests is totally different. I thought the json would show
> them in the order they were run, but maybe I'm wrong?

HOst link took me to unexisting host.html page instead of host/ directory.

Looking at results.json and dmesg-during.log, they seem same. Example, ivb-
t430s start of the logs:

[   54.485575] kms_addfb_basic: starting subtest addfb25-Yf-tiled
[   54.580441] gem_mmap_gtt: starting subtest basic-short
[   54.728538] gem_storedw_loop: starting subtest basic-vebox

    "tests": {
        "igt@kms_addfb_basic@addfb25-yf-tiled": {
        "igt@gem_mmap_gtt@basic-short": {
        "igt@gem_storedw_loop@basic-vebox": {

Do you have specific build/host/test which shows the inconsistency between 
logs?

Also: I'm trying to get the piglit output added to the logdir. It might help 
even in cases where host hangs, because it's collected externally.

Tomi
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Re: ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff

[Ville Syrjälä]

On Thu, Apr 14, 2016 at 11:54:53AM +0300, Tomi Sarvela wrote:
> On Thursday 14 April 2016 11:46:12 Ville Syrjälä wrote:
> > On Thu, Apr 14, 2016 at 10:24:23AM +0300, Tomi Sarvela wrote:
> > > On Wednesday 13 April 2016 19:29:25 Ville Syrjälä wrote:
> > > [ILK-hp8440p problems]
> > > 
> > > > ...
> > > > 
> > > > [  265.316531] drm/i915: Resetting chip after gpu hang
> > > > [  265.316585] [drm:i915_reset [i915]] *ERROR* Failed to reset chip:
> > > > -110
> > > > 
> > > > Looks like the GPU died for some reason.
> > > > 
> > > > > Test kms_force_connector_basic:
> > > > >         Subgroup prune-stale-modes:
> > > > >                 pass       -> SKIP       (ivb-t430s)
> > > > 
> > > > No clue what happened here. The change isn't visible in the results
> > > > visualization page, nor can I see this subtest even being run in
> > > > the dmesg for Patchwork_1881. The dmesg ends at gtt-blt, but based on
> > > > the json there were a ton of tests run after that. In fact the json
> > > > and dmesg seem totally out of sync.
> > > > 
> > > > Tomi, any idea what's going on here?
> > > 
> > > The link from Patchwork page is hosed, but the full dmesgs are at
> > > http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/il
> > > k-hp8440p/[1]
> > > http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/i
> > > vb-t430s/[2]
> > Not sure what you mean with hosed. It took me to the same place where I
> > was before (ie. [2]). But if you look at the dmesg vs. results.json the
> > order of the tests is totally different. I thought the json would show
> > them in the order they were run, but maybe I'm wrong?
> 
> HOst link took me to unexisting host.html page instead of host/ directory.
> 
> Looking at results.json and dmesg-during.log, they seem same. Example, ivb-
> t430s start of the logs:
> 
> [   54.485575] kms_addfb_basic: starting subtest addfb25-Yf-tiled
> [   54.580441] gem_mmap_gtt: starting subtest basic-short
> [   54.728538] gem_storedw_loop: starting subtest basic-vebox
> 
>     "tests": {
>         "igt@kms_addfb_basic@addfb25-yf-tiled": {
>         "igt@gem_mmap_gtt@basic-short": {
>         "igt@gem_storedw_loop@basic-vebox": {
> 
> Do you have specific build/host/test which shows the inconsistency between 
> logs?

results.json looks like this around gtt-blt:
igt@kms_flip@basic-flip-vs-modeset
igt@gem_exec_parse@basic-allowed
igt@gem_exec_basic@gtt-blt
igt@kms_setmode@basic-clone-single-crtc
igt@kms_pipe_crc_basic@read-crc-pipe-a

The dmesg on the other hand ends like this:
[  574.506500] kms_pipe_crc_basic: executing
[  574.518000] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
[  577.846181] kms_pipe_crc_basic: exiting, ret=0
[  579.048483] gem_sync: executing
[  579.055032] gem_sync: starting subtest basic-bsd2
[  579.058293] gem_sync: exiting, ret=0
[  579.285709] kms_addfb_basic: executing
[  579.289292] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
[  579.289848] kms_addfb_basic: exiting, ret=0
[  579.456086] gem_exec_basic: executing
[  579.459748] gem_exec_basic: starting subtest gtt-blt
[  579.461952] gem_exec_basic: exiting, ret=0

So based on dmesg gtt-blt was the last one executed, but according to
the json it wasn't.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 0/5] drm/i915: Rest of my DSI and DPLL stuff

[Jani Nikula]

On Tue, 12 Apr 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Here is the remainder of my DSI/DPLL series [1]. Everything else got merged
> already. The first patch in the series is the only one to lack an r-b.
>
> Tested on BYT FFRD8 only, BXT stuff is not tested.

I didn't run IGT, but this fixes a dpll related state checker warning.

Tested-by: Jani Nikula <jani.nikula@intel.com>


>
> [1] https://lists.freedesktop.org/archives/intel-gfx/2016-March/089782.html
>
> Ville Syrjälä (5):
>   drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
>   drm/i915: Compute DSI PLL parameters during .compute_config()
>   drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()
>   drm/i915: Hook up pfit for DSI
>   drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
>
>  drivers/gpu/drm/i915/intel_display.c | 123 ++++++++++++++++++------------
>  drivers/gpu/drm/i915/intel_dp.c      |   5 ++
>  drivers/gpu/drm/i915/intel_drv.h     |   5 ++
>  drivers/gpu/drm/i915/intel_dsi.c     | 113 ++++++++++++++++++++-------
>  drivers/gpu/drm/i915/intel_dsi.h     |  14 ++--
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 144 +++++++++++++++++------------------
>  6 files changed, 252 insertions(+), 152 deletions(-)

-- 
Jani Nikula, Intel Open Source Technology Center
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