* [PATCHv2 01/28] clk: ti: add ti_clk_get helper API
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:07 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
The API can be used to fetch directly DT clocks based on name. Using
this new API allows getting rid of most of the DT_CLK() entries under
drivers/clk/ti.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk.c | 35 +++++++++++++++++++++++++++++------
include/linux/clk/ti.h | 2 ++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 5fcf247..3dcf97e 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -68,6 +68,33 @@ static u32 clk_memmap_readl(void __iomem *reg)
}
/**
+ * ti_clk_get - lookup a TI clock handle
+ * @name: clock to find
+ *
+ * Searches for a TI clock handle. Will first attempt to search for a
+ * clock based on a DT node name, but if this fails, will revert to
+ * looking up a clock alias. Returns the pointer to the clock handle,
+ * or ERR_PTR in failure.
+ */
+struct clk *ti_clk_get(const char *name)
+{
+ struct of_phandle_args clkspec;
+ struct device_node *node;
+ struct clk *clk;
+
+ if (of_have_populated_dt()) {
+ node = of_find_node_by_name(NULL, name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(&clkspec);
+
+ if (!IS_ERR(clk))
+ return clk;
+ }
+
+ return clk_get(NULL, name);
+}
+
+/**
* ti_clk_setup_ll_ops - setup low level clock operations
* @ops: low level clock ops descriptor
*
@@ -102,14 +129,10 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
{
struct ti_dt_clk *c;
- struct device_node *node;
struct clk *clk;
- struct of_phandle_args clkspec;
for (c = oclks; c->node_name != NULL; c++) {
- node = of_find_node_by_name(NULL, c->node_name);
- clkspec.np = node;
- clk = of_clk_get_from_provider(&clkspec);
+ clk = ti_clk_get(c->node_name);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
@@ -446,7 +469,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
int i;
for (i = 0; i < num_clocks; i++) {
- init_clk = clk_get(NULL, clk_names[i]);
+ init_clk = ti_clk_get(clk_names[i]);
if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
clk_names[i]))
continue;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index dc5164a..210e946 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -292,6 +292,8 @@ struct ti_clk_features {
void ti_clk_setup_features(struct ti_clk_features *features);
const struct ti_clk_features *ti_clk_get_features(void);
+struct clk *ti_clk_get(const char *name);
+
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
#ifdef CONFIG_ATAGS
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 01/28] clk: ti: add ti_clk_get helper API
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: linux-arm-kernel
The API can be used to fetch directly DT clocks based on name. Using
this new API allows getting rid of most of the DT_CLK() entries under
drivers/clk/ti.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk.c | 35 +++++++++++++++++++++++++++++------
include/linux/clk/ti.h | 2 ++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 5fcf247..3dcf97e 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -68,6 +68,33 @@ static u32 clk_memmap_readl(void __iomem *reg)
}
/**
+ * ti_clk_get - lookup a TI clock handle
+ * @name: clock to find
+ *
+ * Searches for a TI clock handle. Will first attempt to search for a
+ * clock based on a DT node name, but if this fails, will revert to
+ * looking up a clock alias. Returns the pointer to the clock handle,
+ * or ERR_PTR in failure.
+ */
+struct clk *ti_clk_get(const char *name)
+{
+ struct of_phandle_args clkspec;
+ struct device_node *node;
+ struct clk *clk;
+
+ if (of_have_populated_dt()) {
+ node = of_find_node_by_name(NULL, name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(&clkspec);
+
+ if (!IS_ERR(clk))
+ return clk;
+ }
+
+ return clk_get(NULL, name);
+}
+
+/**
* ti_clk_setup_ll_ops - setup low level clock operations
* @ops: low level clock ops descriptor
*
@@ -102,14 +129,10 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
{
struct ti_dt_clk *c;
- struct device_node *node;
struct clk *clk;
- struct of_phandle_args clkspec;
for (c = oclks; c->node_name != NULL; c++) {
- node = of_find_node_by_name(NULL, c->node_name);
- clkspec.np = node;
- clk = of_clk_get_from_provider(&clkspec);
+ clk = ti_clk_get(c->node_name);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
@@ -446,7 +469,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
int i;
for (i = 0; i < num_clocks; i++) {
- init_clk = clk_get(NULL, clk_names[i]);
+ init_clk = ti_clk_get(clk_names[i]);
if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
clk_names[i]))
continue;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index dc5164a..210e946 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -292,6 +292,8 @@ struct ti_clk_features {
void ti_clk_setup_features(struct ti_clk_features *features);
const struct ti_clk_features *ti_clk_get_features(void);
+struct clk *ti_clk_get(const char *name);
+
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
#ifdef CONFIG_ATAGS
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 01/28] clk: ti: add ti_clk_get helper API
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
The API can be used to fetch directly DT clocks based on name. Using
this new API allows getting rid of most of the DT_CLK() entries under
drivers/clk/ti.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk.c | 35 +++++++++++++++++++++++++++++------
include/linux/clk/ti.h | 2 ++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 5fcf247..3dcf97e 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -68,6 +68,33 @@ static u32 clk_memmap_readl(void __iomem *reg)
}
/**
+ * ti_clk_get - lookup a TI clock handle
+ * @name: clock to find
+ *
+ * Searches for a TI clock handle. Will first attempt to search for a
+ * clock based on a DT node name, but if this fails, will revert to
+ * looking up a clock alias. Returns the pointer to the clock handle,
+ * or ERR_PTR in failure.
+ */
+struct clk *ti_clk_get(const char *name)
+{
+ struct of_phandle_args clkspec;
+ struct device_node *node;
+ struct clk *clk;
+
+ if (of_have_populated_dt()) {
+ node = of_find_node_by_name(NULL, name);
+ clkspec.np = node;
+ clk = of_clk_get_from_provider(&clkspec);
+
+ if (!IS_ERR(clk))
+ return clk;
+ }
+
+ return clk_get(NULL, name);
+}
+
+/**
* ti_clk_setup_ll_ops - setup low level clock operations
* @ops: low level clock ops descriptor
*
@@ -102,14 +129,10 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
{
struct ti_dt_clk *c;
- struct device_node *node;
struct clk *clk;
- struct of_phandle_args clkspec;
for (c = oclks; c->node_name != NULL; c++) {
- node = of_find_node_by_name(NULL, c->node_name);
- clkspec.np = node;
- clk = of_clk_get_from_provider(&clkspec);
+ clk = ti_clk_get(c->node_name);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
@@ -446,7 +469,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
int i;
for (i = 0; i < num_clocks; i++) {
- init_clk = clk_get(NULL, clk_names[i]);
+ init_clk = ti_clk_get(clk_names[i]);
if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
clk_names[i]))
continue;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index dc5164a..210e946 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -292,6 +292,8 @@ struct ti_clk_features {
void ti_clk_setup_features(struct ti_clk_features *features);
const struct ti_clk_features *ti_clk_get_features(void);
+struct clk *ti_clk_get(const char *name);
+
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
#ifdef CONFIG_ATAGS
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 05/28] ARM: OMAP2+: clock: use the new ti_clk_get for fetching clocks
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:07 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Use the new ti_clk_get API instead of common implementation, to get rid
of most of the DT_CLK() aliases under drivers/clk/ti.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 2 +-
arch/arm/mach-omap2/clock.c | 6 +++---
arch/arm/mach-omap2/io.c | 2 +-
arch/arm/mach-omap2/mcbsp.c | 2 +-
arch/arm/mach-omap2/omap2-restart.c | 5 +++--
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/mach-omap2/pm24xx.c | 4 ++--
arch/arm/mach-omap2/timer.c | 7 ++++---
arch/arm/mach-omap2/voltage.c | 3 ++-
9 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index b64d717..2a9739e 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -200,7 +200,7 @@ void omap2xxx_clkt_vps_late_init(void)
{
struct clk *c;
- c = clk_get(NULL, "sys_ck");
+ c = ti_clk_get("sys_ck");
if (IS_ERR(c)) {
WARN(1, "could not locate sys_ck\n");
} else {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d058125..50fbff0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -151,15 +151,15 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
struct clk *hfclkin_ck, *core_ck, *mpu_ck;
unsigned long hfclkin_rate;
- mpu_ck = clk_get(NULL, mpu_ck_name);
+ mpu_ck = ti_clk_get(mpu_ck_name);
if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
return;
- core_ck = clk_get(NULL, core_ck_name);
+ core_ck = ti_clk_get(core_ck_name);
if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
return;
- hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
+ hfclkin_ck = ti_clk_get(hfclkin_ck_name);
if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
return;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3c87e40..42e502f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -389,7 +389,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
if (!cpu_is_omap34xx())
return 0;
- dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+ dpll3_m2_ck = ti_clk_get("dpll3_m2_ck");
if (IS_ERR(dpll3_m2_ck))
return -EINVAL;
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index b4ac3af..8098546 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
pdata->enable_st_clock = omap3_enable_st_clock;
sprintf(clk_name, "mcbsp%d_ick", id);
- mcbsp_iclks[id] = clk_get(NULL, clk_name);
+ mcbsp_iclks[id] = ti_clk_get(clk_name);
count++;
}
pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 497269d..0540495 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/clk/ti.h>
#include "soc.h"
#include "common.h"
@@ -52,11 +53,11 @@ void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
*/
static int __init omap2xxx_common_look_up_clks_for_reset(void)
{
- reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
+ reset_virt_prcm_set_ck = ti_clk_get("virt_prcm_set");
if (IS_ERR(reset_virt_prcm_set_ck))
return -EINVAL;
- reset_sys_ck = clk_get(NULL, "sys_ck");
+ reset_sys_ck = ti_clk_get("sys_ck");
if (IS_ERR(reset_sys_ck))
return -EINVAL;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 58920bc..83143fe 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -164,7 +164,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
goto exit;
}
- clk = clk_get(NULL, clk_name);
+ clk = ti_clk_get(clk_name);
if (IS_ERR(clk)) {
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
goto exit;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2a1a418..f74a46f 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -286,14 +286,14 @@ int __init omap2_pm_init(void)
pr_err("PM: gfx_clkdm not found\n");
- osc_ck = clk_get(NULL, "osc_ck");
+ osc_ck = ti_clk_get("osc_ck");
if (IS_ERR(osc_ck)) {
printk(KERN_ERR "could not get osc_ck\n");
return -ENODEV;
}
if (cpu_is_omap242x()) {
- emul_ck = clk_get(NULL, "emul_ck");
+ emul_ck = ti_clk_get("emul_ck");
if (IS_ERR(emul_ck)) {
printk(KERN_ERR "could not get emul_ck\n");
clk_put(osc_ck);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5b385bb..08e08db 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -42,6 +42,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <linux/sched_clock.h>
+#include <linux/clk/ti.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
@@ -290,11 +291,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
return -ENXIO;
/* After the dmtimer is using hwmod these clocks won't be needed */
- timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+ timer->fclk = ti_clk_get(omap_hwmod_get_main_clk(oh));
if (IS_ERR(timer->fclk))
return PTR_ERR(timer->fclk);
- src = clk_get(NULL, fck_source);
+ src = ti_clk_get(fck_source);
if (IS_ERR(src))
return PTR_ERR(src);
@@ -556,7 +557,7 @@ static void __init realtime_counter_init(void)
pr_err("%s: ioremap failed\n", __func__);
return;
}
- sys_clk = clk_get(NULL, "sys_clkin");
+ sys_clk = ti_clk_get("sys_clkin");
if (IS_ERR(sys_clk)) {
pr_err("%s: failed to get system clock handle\n", __func__);
iounmap(base);
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index cba8cad..68d2852 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -26,6 +26,7 @@
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/clk.h>
+#include <linux/clk/ti.h>
#include "common.h"
@@ -246,7 +247,7 @@ int __init omap_voltage_late_init(void)
if (!voltdm->scalable)
continue;
- sys_ck = clk_get(NULL, voltdm->sys_clk.name);
+ sys_ck = ti_clk_get(voltdm->sys_clk.name);
if (IS_ERR(sys_ck)) {
pr_warn("%s: Could not get sys clk.\n", __func__);
return -EINVAL;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 05/28] ARM: OMAP2+: clock: use the new ti_clk_get for fetching clocks
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Use the new ti_clk_get API instead of common implementation, to get rid
of most of the DT_CLK() aliases under drivers/clk/ti.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 2 +-
arch/arm/mach-omap2/clock.c | 6 +++---
arch/arm/mach-omap2/io.c | 2 +-
arch/arm/mach-omap2/mcbsp.c | 2 +-
arch/arm/mach-omap2/omap2-restart.c | 5 +++--
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/mach-omap2/pm24xx.c | 4 ++--
arch/arm/mach-omap2/timer.c | 7 ++++---
arch/arm/mach-omap2/voltage.c | 3 ++-
9 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index b64d717..2a9739e 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -200,7 +200,7 @@ void omap2xxx_clkt_vps_late_init(void)
{
struct clk *c;
- c = clk_get(NULL, "sys_ck");
+ c = ti_clk_get("sys_ck");
if (IS_ERR(c)) {
WARN(1, "could not locate sys_ck\n");
} else {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d058125..50fbff0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -151,15 +151,15 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
struct clk *hfclkin_ck, *core_ck, *mpu_ck;
unsigned long hfclkin_rate;
- mpu_ck = clk_get(NULL, mpu_ck_name);
+ mpu_ck = ti_clk_get(mpu_ck_name);
if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
return;
- core_ck = clk_get(NULL, core_ck_name);
+ core_ck = ti_clk_get(core_ck_name);
if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
return;
- hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
+ hfclkin_ck = ti_clk_get(hfclkin_ck_name);
if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
return;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3c87e40..42e502f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -389,7 +389,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
if (!cpu_is_omap34xx())
return 0;
- dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+ dpll3_m2_ck = ti_clk_get("dpll3_m2_ck");
if (IS_ERR(dpll3_m2_ck))
return -EINVAL;
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index b4ac3af..8098546 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
pdata->enable_st_clock = omap3_enable_st_clock;
sprintf(clk_name, "mcbsp%d_ick", id);
- mcbsp_iclks[id] = clk_get(NULL, clk_name);
+ mcbsp_iclks[id] = ti_clk_get(clk_name);
count++;
}
pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 497269d..0540495 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/clk/ti.h>
#include "soc.h"
#include "common.h"
@@ -52,11 +53,11 @@ void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
*/
static int __init omap2xxx_common_look_up_clks_for_reset(void)
{
- reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
+ reset_virt_prcm_set_ck = ti_clk_get("virt_prcm_set");
if (IS_ERR(reset_virt_prcm_set_ck))
return -EINVAL;
- reset_sys_ck = clk_get(NULL, "sys_ck");
+ reset_sys_ck = ti_clk_get("sys_ck");
if (IS_ERR(reset_sys_ck))
return -EINVAL;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 58920bc..83143fe 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -164,7 +164,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
goto exit;
}
- clk = clk_get(NULL, clk_name);
+ clk = ti_clk_get(clk_name);
if (IS_ERR(clk)) {
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
goto exit;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2a1a418..f74a46f 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -286,14 +286,14 @@ int __init omap2_pm_init(void)
pr_err("PM: gfx_clkdm not found\n");
- osc_ck = clk_get(NULL, "osc_ck");
+ osc_ck = ti_clk_get("osc_ck");
if (IS_ERR(osc_ck)) {
printk(KERN_ERR "could not get osc_ck\n");
return -ENODEV;
}
if (cpu_is_omap242x()) {
- emul_ck = clk_get(NULL, "emul_ck");
+ emul_ck = ti_clk_get("emul_ck");
if (IS_ERR(emul_ck)) {
printk(KERN_ERR "could not get emul_ck\n");
clk_put(osc_ck);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5b385bb..08e08db 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -42,6 +42,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <linux/sched_clock.h>
+#include <linux/clk/ti.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
@@ -290,11 +291,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
return -ENXIO;
/* After the dmtimer is using hwmod these clocks won't be needed */
- timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+ timer->fclk = ti_clk_get(omap_hwmod_get_main_clk(oh));
if (IS_ERR(timer->fclk))
return PTR_ERR(timer->fclk);
- src = clk_get(NULL, fck_source);
+ src = ti_clk_get(fck_source);
if (IS_ERR(src))
return PTR_ERR(src);
@@ -556,7 +557,7 @@ static void __init realtime_counter_init(void)
pr_err("%s: ioremap failed\n", __func__);
return;
}
- sys_clk = clk_get(NULL, "sys_clkin");
+ sys_clk = ti_clk_get("sys_clkin");
if (IS_ERR(sys_clk)) {
pr_err("%s: failed to get system clock handle\n", __func__);
iounmap(base);
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index cba8cad..68d2852 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -26,6 +26,7 @@
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/clk.h>
+#include <linux/clk/ti.h>
#include "common.h"
@@ -246,7 +247,7 @@ int __init omap_voltage_late_init(void)
if (!voltdm->scalable)
continue;
- sys_ck = clk_get(NULL, voltdm->sys_clk.name);
+ sys_ck = ti_clk_get(voltdm->sys_clk.name);
if (IS_ERR(sys_ck)) {
pr_warn("%s: Could not get sys clk.\n", __func__);
return -EINVAL;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 05/28] ARM: OMAP2+: clock: use the new ti_clk_get for fetching clocks
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Use the new ti_clk_get API instead of common implementation, to get rid
of most of the DT_CLK() aliases under drivers/clk/ti.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 2 +-
arch/arm/mach-omap2/clock.c | 6 +++---
arch/arm/mach-omap2/io.c | 2 +-
arch/arm/mach-omap2/mcbsp.c | 2 +-
arch/arm/mach-omap2/omap2-restart.c | 5 +++--
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/mach-omap2/pm24xx.c | 4 ++--
arch/arm/mach-omap2/timer.c | 7 ++++---
arch/arm/mach-omap2/voltage.c | 3 ++-
9 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index b64d717..2a9739e 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -200,7 +200,7 @@ void omap2xxx_clkt_vps_late_init(void)
{
struct clk *c;
- c = clk_get(NULL, "sys_ck");
+ c = ti_clk_get("sys_ck");
if (IS_ERR(c)) {
WARN(1, "could not locate sys_ck\n");
} else {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d058125..50fbff0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -151,15 +151,15 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
struct clk *hfclkin_ck, *core_ck, *mpu_ck;
unsigned long hfclkin_rate;
- mpu_ck = clk_get(NULL, mpu_ck_name);
+ mpu_ck = ti_clk_get(mpu_ck_name);
if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
return;
- core_ck = clk_get(NULL, core_ck_name);
+ core_ck = ti_clk_get(core_ck_name);
if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
return;
- hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
+ hfclkin_ck = ti_clk_get(hfclkin_ck_name);
if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
return;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3c87e40..42e502f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -389,7 +389,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
if (!cpu_is_omap34xx())
return 0;
- dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+ dpll3_m2_ck = ti_clk_get("dpll3_m2_ck");
if (IS_ERR(dpll3_m2_ck))
return -EINVAL;
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index b4ac3af..8098546 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -98,7 +98,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
pdata->enable_st_clock = omap3_enable_st_clock;
sprintf(clk_name, "mcbsp%d_ick", id);
- mcbsp_iclks[id] = clk_get(NULL, clk_name);
+ mcbsp_iclks[id] = ti_clk_get(clk_name);
count++;
}
pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 497269d..0540495 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/clk/ti.h>
#include "soc.h"
#include "common.h"
@@ -52,11 +53,11 @@ void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
*/
static int __init omap2xxx_common_look_up_clks_for_reset(void)
{
- reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
+ reset_virt_prcm_set_ck = ti_clk_get("virt_prcm_set");
if (IS_ERR(reset_virt_prcm_set_ck))
return -EINVAL;
- reset_sys_ck = clk_get(NULL, "sys_ck");
+ reset_sys_ck = ti_clk_get("sys_ck");
if (IS_ERR(reset_sys_ck))
return -EINVAL;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 58920bc..83143fe 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -164,7 +164,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
goto exit;
}
- clk = clk_get(NULL, clk_name);
+ clk = ti_clk_get(clk_name);
if (IS_ERR(clk)) {
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
goto exit;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2a1a418..f74a46f 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -286,14 +286,14 @@ int __init omap2_pm_init(void)
pr_err("PM: gfx_clkdm not found\n");
- osc_ck = clk_get(NULL, "osc_ck");
+ osc_ck = ti_clk_get("osc_ck");
if (IS_ERR(osc_ck)) {
printk(KERN_ERR "could not get osc_ck\n");
return -ENODEV;
}
if (cpu_is_omap242x()) {
- emul_ck = clk_get(NULL, "emul_ck");
+ emul_ck = ti_clk_get("emul_ck");
if (IS_ERR(emul_ck)) {
printk(KERN_ERR "could not get emul_ck\n");
clk_put(osc_ck);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5b385bb..08e08db 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -42,6 +42,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <linux/sched_clock.h>
+#include <linux/clk/ti.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
@@ -290,11 +291,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
return -ENXIO;
/* After the dmtimer is using hwmod these clocks won't be needed */
- timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+ timer->fclk = ti_clk_get(omap_hwmod_get_main_clk(oh));
if (IS_ERR(timer->fclk))
return PTR_ERR(timer->fclk);
- src = clk_get(NULL, fck_source);
+ src = ti_clk_get(fck_source);
if (IS_ERR(src))
return PTR_ERR(src);
@@ -556,7 +557,7 @@ static void __init realtime_counter_init(void)
pr_err("%s: ioremap failed\n", __func__);
return;
}
- sys_clk = clk_get(NULL, "sys_clkin");
+ sys_clk = ti_clk_get("sys_clkin");
if (IS_ERR(sys_clk)) {
pr_err("%s: failed to get system clock handle\n", __func__);
iounmap(base);
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index cba8cad..68d2852 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -26,6 +26,7 @@
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/clk.h>
+#include <linux/clk/ti.h>
#include "common.h"
@@ -246,7 +247,7 @@ int __init omap_voltage_late_init(void)
if (!voltdm->scalable)
continue;
- sys_ck = clk_get(NULL, voltdm->sys_clk.name);
+ sys_ck = ti_clk_get(voltdm->sys_clk.name);
if (IS_ERR(sys_ck)) {
pr_warn("%s: Could not get sys clk.\n", __func__);
return -EINVAL;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 08/28] ARM: OMAP2+: clockdomain: add usecounting support to autoidle APIs
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:07 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
The previous implementation was racy in many locations, where the current
status of the clockdomain was read out, some operations were executed,
and the previous status info was used afterwards to decide next state
for the clockdomain. Instead, fix the implementation of the allow_idle /
deny_idle APIs to properly have usecounting support. This allows clean
handling internally within the clockdomain core, and simplifies the
usage also within hwmod.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/clockdomain.c | 36 ++++++++++++++++++++++++------------
arch/arm/mach-omap2/clockdomain.h | 2 ++
arch/arm/mach-omap2/cpuidle44xx.c | 2 +-
arch/arm/mach-omap2/omap-smp.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.c | 27 ++++++++++++---------------
arch/arm/mach-omap2/pm.c | 8 +-------
arch/arm/mach-omap2/powerdomain.c | 20 ++++++--------------
7 files changed, 47 insertions(+), 50 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 2da3b5e..b79b1ca 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -465,10 +465,7 @@ int clkdm_complete_init(void)
return -EACCES;
list_for_each_entry(clkdm, &clkdm_list, node) {
- if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- clkdm_wakeup(clkdm);
- else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
- clkdm_deny_idle(clkdm);
+ clkdm_deny_idle(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
clkdm_clear_all_wkdeps(clkdm);
@@ -925,11 +922,20 @@ void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
if (!clkdm)
return;
- if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
- pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
- clkdm->name);
+ if (!WARN_ON(!clkdm->forcewake_count))
+ clkdm->forcewake_count--;
+
+ if (clkdm->forcewake_count)
+ return;
+
+ if (!clkdm->usecount && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+ clkdm_sleep_nolock(clkdm);
+
+ if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO))
+ return;
+
+ if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)
return;
- }
if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
return;
@@ -974,11 +980,17 @@ void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
if (!clkdm)
return;
- if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
- pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
- clkdm->name);
+ if (clkdm->forcewake_count++)
+ return;
+
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ clkdm_wakeup_nolock(clkdm);
+
+ if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO))
+ return;
+
+ if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)
return;
- }
if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
return;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2c398ce..24667a5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -114,6 +114,7 @@ struct omap_hwmod;
* @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
* @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
* @usecount: Usecount tracking
+ * @forcewake_count: Usecount for forcing the domain active
* @node: list_head to link all clockdomains together
*
* @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
@@ -138,6 +139,7 @@ struct clockdomain {
struct clkdm_dep *wkdep_srcs;
struct clkdm_dep *sleepdep_srcs;
int usecount;
+ int forcewake_count;
struct list_head node;
};
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4b8e9f4..fa138d4 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -140,7 +140,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
mpuss_can_lose_context)
gic_dist_disable();
- clkdm_wakeup(cpu_clkdm[1]);
+ clkdm_deny_idle(cpu_clkdm[1]);
omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
clkdm_allow_idle(cpu_clkdm[1]);
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index c625cc1..690bfa5 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -143,7 +143,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Ensure that CPU power state is set to ON to avoid CPU
* powerdomain transition on wfi
*/
- clkdm_wakeup_nolock(cpu1_clkdm);
+ clkdm_deny_idle_nolock(cpu1_clkdm);
pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
clkdm_allow_idle_nolock(cpu1_clkdm);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 31da3b5..310bd95 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1696,7 +1696,6 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
int ret = -EINVAL;
- int hwsup = 0;
if (!oh)
return -EINVAL;
@@ -1714,7 +1713,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
* might not be completed. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
- hwsup = clkdm_in_hwsup(oh->clkdm);
+ clkdm_deny_idle(oh->clkdm);
ret = clkdm_hwmod_enable(oh->clkdm, oh);
if (ret) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1741,8 +1740,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
* Set the clockdomain to HW_AUTO, assuming that the
* previous state was HW_AUTO.
*/
- if (hwsup)
- clkdm_allow_idle(oh->clkdm);
+ clkdm_allow_idle(oh->clkdm);
clkdm_hwmod_disable(oh->clkdm, oh);
}
@@ -2096,7 +2094,6 @@ static int _enable_preprogram(struct omap_hwmod *oh)
static int _enable(struct omap_hwmod *oh)
{
int r;
- int hwsup = 0;
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
@@ -2156,8 +2153,7 @@ static int _enable(struct omap_hwmod *oh)
* completely the module. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
- hwsup = clkdm_in_hwsup(oh->clkdm) &&
- !clkdm_missing_idle_reporting(oh->clkdm);
+ clkdm_deny_idle(oh->clkdm);
r = clkdm_hwmod_enable(oh->clkdm, oh);
if (r) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -2177,14 +2173,10 @@ static int _enable(struct omap_hwmod *oh)
r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
-EINVAL;
- if (!r) {
- /*
- * Set the clockdomain to HW_AUTO only if the target is ready,
- * assuming that the previous state was HW_AUTO
- */
- if (oh->clkdm && hwsup)
- clkdm_allow_idle(oh->clkdm);
+ if (oh->clkdm)
+ clkdm_allow_idle(oh->clkdm);
+ if (!r) {
oh->_state = _HWMOD_STATE_ENABLED;
/* Access the sysconfig only if the target is ready */
@@ -2238,6 +2230,9 @@ static int _idle(struct omap_hwmod *oh)
_idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh);
+ if (oh->clkdm)
+ clkdm_deny_idle(oh->clkdm);
+
if (oh->flags & HWMOD_BLOCK_WFI)
cpu_idle_poll_ctrl(false);
if (soc_ops.disable_module)
@@ -2250,8 +2245,10 @@ static int _idle(struct omap_hwmod *oh)
* transition to complete properly.
*/
_disable_clocks(oh);
- if (oh->clkdm)
+ if (oh->clkdm) {
+ clkdm_allow_idle(oh->clkdm);
clkdm_hwmod_disable(oh->clkdm, oh);
+ }
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic) {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 83143fe..630b305 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -110,13 +110,7 @@ static void __init omap2_init_processor_devices(void)
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
- /* XXX The usecount test is racy */
- if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
- !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
- clkdm_allow_idle(clkdm);
- else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
- clkdm->usecount == 0)
- clkdm_sleep(clkdm);
+ clkdm_allow_idle(clkdm);
return 0;
}
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 78af6d8..be7a976 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -222,7 +222,6 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
* @pwrdm: struct powerdomain * to operate on
* @curr_pwrst: current power state of @pwrdm
* @pwrst: power state to switch to
- * @hwsup: ptr to a bool to return whether the clkdm is hardware-supervised
*
* Determine whether the powerdomain needs to be turned on before
* attempting to switch power states. Called by
@@ -233,8 +232,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
* "Types of sleep_switch" comment above).
*/
static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
- u8 curr_pwrst, u8 pwrst,
- bool *hwsup)
+ u8 curr_pwrst, u8 pwrst)
{
u8 sleep_switch;
@@ -244,8 +242,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
arch_pwrdm->pwrdm_set_lowpwrstchange) {
sleep_switch = LOWPOWERSTATE_SWITCH;
} else {
- *hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
- clkdm_wakeup_nolock(pwrdm->pwrdm_clkdms[0]);
+ clkdm_deny_idle_nolock(pwrdm->pwrdm_clkdms[0]);
sleep_switch = FORCEWAKEUP_SWITCH;
}
} else {
@@ -259,7 +256,6 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
* _pwrdm_restore_clkdm_state - restore the clkdm hwsup state after pwrst change
* @pwrdm: struct powerdomain * to operate on
* @sleep_switch: return value from _pwrdm_save_clkdm_state_and_activate()
- * @hwsup: should @pwrdm's first clockdomain be set to hardware-supervised mode?
*
* Restore the clockdomain state perturbed by
* _pwrdm_save_clkdm_state_and_activate(), and call the power state
@@ -270,14 +266,11 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
* software-supervised sleep. No return value.
*/
static void _pwrdm_restore_clkdm_state(struct powerdomain *pwrdm,
- u8 sleep_switch, bool hwsup)
+ u8 sleep_switch)
{
switch (sleep_switch) {
case FORCEWAKEUP_SWITCH:
- if (hwsup)
- clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
- else
- clkdm_sleep_nolock(pwrdm->pwrdm_clkdms[0]);
+ clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
break;
case LOWPOWERSTATE_SWITCH:
if (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
@@ -1092,7 +1085,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
u8 next_pwrst, sleep_switch;
int curr_pwrst;
int ret = 0;
- bool hwsup = false;
if (!pwrdm || IS_ERR(pwrdm))
return -EINVAL;
@@ -1116,14 +1108,14 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
goto osps_out;
sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
- pwrst, &hwsup);
+ pwrst);
ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
if (ret)
pr_err("%s: unable to set power state of powerdomain: %s\n",
__func__, pwrdm->name);
- _pwrdm_restore_clkdm_state(pwrdm, sleep_switch, hwsup);
+ _pwrdm_restore_clkdm_state(pwrdm, sleep_switch);
osps_out:
pwrdm_unlock(pwrdm);
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 08/28] ARM: OMAP2+: clockdomain: add usecounting support to autoidle APIs
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: linux-arm-kernel
The previous implementation was racy in many locations, where the current
status of the clockdomain was read out, some operations were executed,
and the previous status info was used afterwards to decide next state
for the clockdomain. Instead, fix the implementation of the allow_idle /
deny_idle APIs to properly have usecounting support. This allows clean
handling internally within the clockdomain core, and simplifies the
usage also within hwmod.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clockdomain.c | 36 ++++++++++++++++++++++++------------
arch/arm/mach-omap2/clockdomain.h | 2 ++
arch/arm/mach-omap2/cpuidle44xx.c | 2 +-
arch/arm/mach-omap2/omap-smp.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.c | 27 ++++++++++++---------------
arch/arm/mach-omap2/pm.c | 8 +-------
arch/arm/mach-omap2/powerdomain.c | 20 ++++++--------------
7 files changed, 47 insertions(+), 50 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 2da3b5e..b79b1ca 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -465,10 +465,7 @@ int clkdm_complete_init(void)
return -EACCES;
list_for_each_entry(clkdm, &clkdm_list, node) {
- if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- clkdm_wakeup(clkdm);
- else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
- clkdm_deny_idle(clkdm);
+ clkdm_deny_idle(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
clkdm_clear_all_wkdeps(clkdm);
@@ -925,11 +922,20 @@ void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
if (!clkdm)
return;
- if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
- pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
- clkdm->name);
+ if (!WARN_ON(!clkdm->forcewake_count))
+ clkdm->forcewake_count--;
+
+ if (clkdm->forcewake_count)
+ return;
+
+ if (!clkdm->usecount && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+ clkdm_sleep_nolock(clkdm);
+
+ if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO))
+ return;
+
+ if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)
return;
- }
if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
return;
@@ -974,11 +980,17 @@ void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
if (!clkdm)
return;
- if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
- pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
- clkdm->name);
+ if (clkdm->forcewake_count++)
+ return;
+
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ clkdm_wakeup_nolock(clkdm);
+
+ if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO))
+ return;
+
+ if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)
return;
- }
if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
return;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2c398ce..24667a5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -114,6 +114,7 @@ struct omap_hwmod;
* @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
* @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
* @usecount: Usecount tracking
+ * @forcewake_count: Usecount for forcing the domain active
* @node: list_head to link all clockdomains together
*
* @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
@@ -138,6 +139,7 @@ struct clockdomain {
struct clkdm_dep *wkdep_srcs;
struct clkdm_dep *sleepdep_srcs;
int usecount;
+ int forcewake_count;
struct list_head node;
};
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4b8e9f4..fa138d4 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -140,7 +140,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
mpuss_can_lose_context)
gic_dist_disable();
- clkdm_wakeup(cpu_clkdm[1]);
+ clkdm_deny_idle(cpu_clkdm[1]);
omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
clkdm_allow_idle(cpu_clkdm[1]);
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index c625cc1..690bfa5 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -143,7 +143,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Ensure that CPU power state is set to ON to avoid CPU
* powerdomain transition on wfi
*/
- clkdm_wakeup_nolock(cpu1_clkdm);
+ clkdm_deny_idle_nolock(cpu1_clkdm);
pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
clkdm_allow_idle_nolock(cpu1_clkdm);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 31da3b5..310bd95 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1696,7 +1696,6 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
int ret = -EINVAL;
- int hwsup = 0;
if (!oh)
return -EINVAL;
@@ -1714,7 +1713,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
* might not be completed. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
- hwsup = clkdm_in_hwsup(oh->clkdm);
+ clkdm_deny_idle(oh->clkdm);
ret = clkdm_hwmod_enable(oh->clkdm, oh);
if (ret) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1741,8 +1740,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
* Set the clockdomain to HW_AUTO, assuming that the
* previous state was HW_AUTO.
*/
- if (hwsup)
- clkdm_allow_idle(oh->clkdm);
+ clkdm_allow_idle(oh->clkdm);
clkdm_hwmod_disable(oh->clkdm, oh);
}
@@ -2096,7 +2094,6 @@ static int _enable_preprogram(struct omap_hwmod *oh)
static int _enable(struct omap_hwmod *oh)
{
int r;
- int hwsup = 0;
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
@@ -2156,8 +2153,7 @@ static int _enable(struct omap_hwmod *oh)
* completely the module. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
- hwsup = clkdm_in_hwsup(oh->clkdm) &&
- !clkdm_missing_idle_reporting(oh->clkdm);
+ clkdm_deny_idle(oh->clkdm);
r = clkdm_hwmod_enable(oh->clkdm, oh);
if (r) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -2177,14 +2173,10 @@ static int _enable(struct omap_hwmod *oh)
r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
-EINVAL;
- if (!r) {
- /*
- * Set the clockdomain to HW_AUTO only if the target is ready,
- * assuming that the previous state was HW_AUTO
- */
- if (oh->clkdm && hwsup)
- clkdm_allow_idle(oh->clkdm);
+ if (oh->clkdm)
+ clkdm_allow_idle(oh->clkdm);
+ if (!r) {
oh->_state = _HWMOD_STATE_ENABLED;
/* Access the sysconfig only if the target is ready */
@@ -2238,6 +2230,9 @@ static int _idle(struct omap_hwmod *oh)
_idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh);
+ if (oh->clkdm)
+ clkdm_deny_idle(oh->clkdm);
+
if (oh->flags & HWMOD_BLOCK_WFI)
cpu_idle_poll_ctrl(false);
if (soc_ops.disable_module)
@@ -2250,8 +2245,10 @@ static int _idle(struct omap_hwmod *oh)
* transition to complete properly.
*/
_disable_clocks(oh);
- if (oh->clkdm)
+ if (oh->clkdm) {
+ clkdm_allow_idle(oh->clkdm);
clkdm_hwmod_disable(oh->clkdm, oh);
+ }
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic) {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 83143fe..630b305 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -110,13 +110,7 @@ static void __init omap2_init_processor_devices(void)
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
- /* XXX The usecount test is racy */
- if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
- !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
- clkdm_allow_idle(clkdm);
- else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
- clkdm->usecount == 0)
- clkdm_sleep(clkdm);
+ clkdm_allow_idle(clkdm);
return 0;
}
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 78af6d8..be7a976 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -222,7 +222,6 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
* @pwrdm: struct powerdomain * to operate on
* @curr_pwrst: current power state of @pwrdm
* @pwrst: power state to switch to
- * @hwsup: ptr to a bool to return whether the clkdm is hardware-supervised
*
* Determine whether the powerdomain needs to be turned on before
* attempting to switch power states. Called by
@@ -233,8 +232,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
* "Types of sleep_switch" comment above).
*/
static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
- u8 curr_pwrst, u8 pwrst,
- bool *hwsup)
+ u8 curr_pwrst, u8 pwrst)
{
u8 sleep_switch;
@@ -244,8 +242,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
arch_pwrdm->pwrdm_set_lowpwrstchange) {
sleep_switch = LOWPOWERSTATE_SWITCH;
} else {
- *hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
- clkdm_wakeup_nolock(pwrdm->pwrdm_clkdms[0]);
+ clkdm_deny_idle_nolock(pwrdm->pwrdm_clkdms[0]);
sleep_switch = FORCEWAKEUP_SWITCH;
}
} else {
@@ -259,7 +256,6 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
* _pwrdm_restore_clkdm_state - restore the clkdm hwsup state after pwrst change
* @pwrdm: struct powerdomain * to operate on
* @sleep_switch: return value from _pwrdm_save_clkdm_state_and_activate()
- * @hwsup: should @pwrdm's first clockdomain be set to hardware-supervised mode?
*
* Restore the clockdomain state perturbed by
* _pwrdm_save_clkdm_state_and_activate(), and call the power state
@@ -270,14 +266,11 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
* software-supervised sleep. No return value.
*/
static void _pwrdm_restore_clkdm_state(struct powerdomain *pwrdm,
- u8 sleep_switch, bool hwsup)
+ u8 sleep_switch)
{
switch (sleep_switch) {
case FORCEWAKEUP_SWITCH:
- if (hwsup)
- clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
- else
- clkdm_sleep_nolock(pwrdm->pwrdm_clkdms[0]);
+ clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
break;
case LOWPOWERSTATE_SWITCH:
if (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
@@ -1092,7 +1085,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
u8 next_pwrst, sleep_switch;
int curr_pwrst;
int ret = 0;
- bool hwsup = false;
if (!pwrdm || IS_ERR(pwrdm))
return -EINVAL;
@@ -1116,14 +1108,14 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
goto osps_out;
sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
- pwrst, &hwsup);
+ pwrst);
ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
if (ret)
pr_err("%s: unable to set power state of powerdomain: %s\n",
__func__, pwrdm->name);
- _pwrdm_restore_clkdm_state(pwrdm, sleep_switch, hwsup);
+ _pwrdm_restore_clkdm_state(pwrdm, sleep_switch);
osps_out:
pwrdm_unlock(pwrdm);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 08/28] ARM: OMAP2+: clockdomain: add usecounting support to autoidle APIs
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
The previous implementation was racy in many locations, where the current
status of the clockdomain was read out, some operations were executed,
and the previous status info was used afterwards to decide next state
for the clockdomain. Instead, fix the implementation of the allow_idle /
deny_idle APIs to properly have usecounting support. This allows clean
handling internally within the clockdomain core, and simplifies the
usage also within hwmod.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/clockdomain.c | 36 ++++++++++++++++++++++++------------
arch/arm/mach-omap2/clockdomain.h | 2 ++
arch/arm/mach-omap2/cpuidle44xx.c | 2 +-
arch/arm/mach-omap2/omap-smp.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.c | 27 ++++++++++++---------------
arch/arm/mach-omap2/pm.c | 8 +-------
arch/arm/mach-omap2/powerdomain.c | 20 ++++++--------------
7 files changed, 47 insertions(+), 50 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 2da3b5e..b79b1ca 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -465,10 +465,7 @@ int clkdm_complete_init(void)
return -EACCES;
list_for_each_entry(clkdm, &clkdm_list, node) {
- if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- clkdm_wakeup(clkdm);
- else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
- clkdm_deny_idle(clkdm);
+ clkdm_deny_idle(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
clkdm_clear_all_wkdeps(clkdm);
@@ -925,11 +922,20 @@ void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
if (!clkdm)
return;
- if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
- pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
- clkdm->name);
+ if (!WARN_ON(!clkdm->forcewake_count))
+ clkdm->forcewake_count--;
+
+ if (clkdm->forcewake_count)
+ return;
+
+ if (!clkdm->usecount && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+ clkdm_sleep_nolock(clkdm);
+
+ if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO))
+ return;
+
+ if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)
return;
- }
if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
return;
@@ -974,11 +980,17 @@ void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
if (!clkdm)
return;
- if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
- pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
- clkdm->name);
+ if (clkdm->forcewake_count++)
+ return;
+
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ clkdm_wakeup_nolock(clkdm);
+
+ if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO))
+ return;
+
+ if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)
return;
- }
if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
return;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2c398ce..24667a5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -114,6 +114,7 @@ struct omap_hwmod;
* @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
* @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
* @usecount: Usecount tracking
+ * @forcewake_count: Usecount for forcing the domain active
* @node: list_head to link all clockdomains together
*
* @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
@@ -138,6 +139,7 @@ struct clockdomain {
struct clkdm_dep *wkdep_srcs;
struct clkdm_dep *sleepdep_srcs;
int usecount;
+ int forcewake_count;
struct list_head node;
};
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4b8e9f4..fa138d4 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -140,7 +140,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
mpuss_can_lose_context)
gic_dist_disable();
- clkdm_wakeup(cpu_clkdm[1]);
+ clkdm_deny_idle(cpu_clkdm[1]);
omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
clkdm_allow_idle(cpu_clkdm[1]);
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index c625cc1..690bfa5 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -143,7 +143,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Ensure that CPU power state is set to ON to avoid CPU
* powerdomain transition on wfi
*/
- clkdm_wakeup_nolock(cpu1_clkdm);
+ clkdm_deny_idle_nolock(cpu1_clkdm);
pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
clkdm_allow_idle_nolock(cpu1_clkdm);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 31da3b5..310bd95 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1696,7 +1696,6 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
int ret = -EINVAL;
- int hwsup = 0;
if (!oh)
return -EINVAL;
@@ -1714,7 +1713,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
* might not be completed. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
- hwsup = clkdm_in_hwsup(oh->clkdm);
+ clkdm_deny_idle(oh->clkdm);
ret = clkdm_hwmod_enable(oh->clkdm, oh);
if (ret) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1741,8 +1740,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
* Set the clockdomain to HW_AUTO, assuming that the
* previous state was HW_AUTO.
*/
- if (hwsup)
- clkdm_allow_idle(oh->clkdm);
+ clkdm_allow_idle(oh->clkdm);
clkdm_hwmod_disable(oh->clkdm, oh);
}
@@ -2096,7 +2094,6 @@ static int _enable_preprogram(struct omap_hwmod *oh)
static int _enable(struct omap_hwmod *oh)
{
int r;
- int hwsup = 0;
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
@@ -2156,8 +2153,7 @@ static int _enable(struct omap_hwmod *oh)
* completely the module. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
- hwsup = clkdm_in_hwsup(oh->clkdm) &&
- !clkdm_missing_idle_reporting(oh->clkdm);
+ clkdm_deny_idle(oh->clkdm);
r = clkdm_hwmod_enable(oh->clkdm, oh);
if (r) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -2177,14 +2173,10 @@ static int _enable(struct omap_hwmod *oh)
r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
-EINVAL;
- if (!r) {
- /*
- * Set the clockdomain to HW_AUTO only if the target is ready,
- * assuming that the previous state was HW_AUTO
- */
- if (oh->clkdm && hwsup)
- clkdm_allow_idle(oh->clkdm);
+ if (oh->clkdm)
+ clkdm_allow_idle(oh->clkdm);
+ if (!r) {
oh->_state = _HWMOD_STATE_ENABLED;
/* Access the sysconfig only if the target is ready */
@@ -2238,6 +2230,9 @@ static int _idle(struct omap_hwmod *oh)
_idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh);
+ if (oh->clkdm)
+ clkdm_deny_idle(oh->clkdm);
+
if (oh->flags & HWMOD_BLOCK_WFI)
cpu_idle_poll_ctrl(false);
if (soc_ops.disable_module)
@@ -2250,8 +2245,10 @@ static int _idle(struct omap_hwmod *oh)
* transition to complete properly.
*/
_disable_clocks(oh);
- if (oh->clkdm)
+ if (oh->clkdm) {
+ clkdm_allow_idle(oh->clkdm);
clkdm_hwmod_disable(oh->clkdm, oh);
+ }
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic) {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 83143fe..630b305 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -110,13 +110,7 @@ static void __init omap2_init_processor_devices(void)
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
- /* XXX The usecount test is racy */
- if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
- !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
- clkdm_allow_idle(clkdm);
- else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
- clkdm->usecount == 0)
- clkdm_sleep(clkdm);
+ clkdm_allow_idle(clkdm);
return 0;
}
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 78af6d8..be7a976 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -222,7 +222,6 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
* @pwrdm: struct powerdomain * to operate on
* @curr_pwrst: current power state of @pwrdm
* @pwrst: power state to switch to
- * @hwsup: ptr to a bool to return whether the clkdm is hardware-supervised
*
* Determine whether the powerdomain needs to be turned on before
* attempting to switch power states. Called by
@@ -233,8 +232,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
* "Types of sleep_switch" comment above).
*/
static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
- u8 curr_pwrst, u8 pwrst,
- bool *hwsup)
+ u8 curr_pwrst, u8 pwrst)
{
u8 sleep_switch;
@@ -244,8 +242,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
arch_pwrdm->pwrdm_set_lowpwrstchange) {
sleep_switch = LOWPOWERSTATE_SWITCH;
} else {
- *hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
- clkdm_wakeup_nolock(pwrdm->pwrdm_clkdms[0]);
+ clkdm_deny_idle_nolock(pwrdm->pwrdm_clkdms[0]);
sleep_switch = FORCEWAKEUP_SWITCH;
}
} else {
@@ -259,7 +256,6 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
* _pwrdm_restore_clkdm_state - restore the clkdm hwsup state after pwrst change
* @pwrdm: struct powerdomain * to operate on
* @sleep_switch: return value from _pwrdm_save_clkdm_state_and_activate()
- * @hwsup: should @pwrdm's first clockdomain be set to hardware-supervised mode?
*
* Restore the clockdomain state perturbed by
* _pwrdm_save_clkdm_state_and_activate(), and call the power state
@@ -270,14 +266,11 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
* software-supervised sleep. No return value.
*/
static void _pwrdm_restore_clkdm_state(struct powerdomain *pwrdm,
- u8 sleep_switch, bool hwsup)
+ u8 sleep_switch)
{
switch (sleep_switch) {
case FORCEWAKEUP_SWITCH:
- if (hwsup)
- clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
- else
- clkdm_sleep_nolock(pwrdm->pwrdm_clkdms[0]);
+ clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
break;
case LOWPOWERSTATE_SWITCH:
if (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
@@ -1092,7 +1085,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
u8 next_pwrst, sleep_switch;
int curr_pwrst;
int ret = 0;
- bool hwsup = false;
if (!pwrdm || IS_ERR(pwrdm))
return -EINVAL;
@@ -1116,14 +1108,14 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
goto osps_out;
sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
- pwrst, &hwsup);
+ pwrst);
ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
if (ret)
pr_err("%s: unable to set power state of powerdomain: %s\n",
__func__, pwrdm->name);
- _pwrdm_restore_clkdm_state(pwrdm, sleep_switch, hwsup);
+ _pwrdm_restore_clkdm_state(pwrdm, sleep_switch);
osps_out:
pwrdm_unlock(pwrdm);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 09/28] ARM: AM33xx: fix module_wait_ready without clkctrl register
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:07 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
If the module has no clkctrl register defined, module_wait_ready should
not try to access this. This can potentially cause an illegal register
access, and result in bad idle reporting also.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/cm33xx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 7b181f9..c073fb5 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -220,6 +220,9 @@ static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
{
int i = 0;
+ if (!clkctrl_offs)
+ return 0;
+
omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
MAX_MODULE_READY_TIME, i);
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 09/28] ARM: AM33xx: fix module_wait_ready without clkctrl register
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: linux-arm-kernel
If the module has no clkctrl register defined, module_wait_ready should
not try to access this. This can potentially cause an illegal register
access, and result in bad idle reporting also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/cm33xx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 7b181f9..c073fb5 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -220,6 +220,9 @@ static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
{
int i = 0;
+ if (!clkctrl_offs)
+ return 0;
+
omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
MAX_MODULE_READY_TIME, i);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 09/28] ARM: AM33xx: fix module_wait_ready without clkctrl register
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
If the module has no clkctrl register defined, module_wait_ready should
not try to access this. This can potentially cause an illegal register
access, and result in bad idle reporting also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/cm33xx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 7b181f9..c073fb5 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -220,6 +220,9 @@ static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
{
int i = 0;
+ if (!clkctrl_offs)
+ return 0;
+
omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
MAX_MODULE_READY_TIME, i);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 10/28] clk: ti: omap2: transition to usage of ti_clk_get
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:07 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cleanup any unnecessary DT_CLK() alias entries from OMAP2 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk-2xxx.c | 151 ++-------------------------------------------
1 file changed, 4 insertions(+), 147 deletions(-)
diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c
index 657c4fe..0b9d7fa 100644
--- a/drivers/clk/ti/clk-2xxx.c
+++ b/drivers/clk/ti/clk-2xxx.c
@@ -22,126 +22,22 @@
#include "clock.h"
static struct ti_dt_clk omap2xxx_clks[] = {
- DT_CLK(NULL, "func_32k_ck", "func_32k_ck"),
- DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"),
- DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"),
- DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"),
- DT_CLK(NULL, "osc_ck", "osc_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "alt_ck", "alt_ck"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "dpll_ck", "dpll_ck"),
- DT_CLK(NULL, "apll96_ck", "apll96_ck"),
- DT_CLK(NULL, "apll54_ck", "apll54_ck"),
- DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "func_96m_ck", "func_96m_ck"),
- DT_CLK(NULL, "func_48m_ck", "func_48m_ck"),
- DT_CLK(NULL, "func_12m_ck", "func_12m_ck"),
- DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"),
- DT_CLK(NULL, "sys_clkout", "sys_clkout"),
- DT_CLK(NULL, "emul_ck", "emul_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "dsp_fck", "dsp_fck"),
- DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"),
- DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"),
- DT_CLK(NULL, "gfx_ick", "gfx_ick"),
DT_CLK("omapdss_dss", "ick", "dss_ick"),
- DT_CLK(NULL, "dss_ick", "dss_ick"),
- DT_CLK(NULL, "dss1_fck", "dss1_fck"),
- DT_CLK(NULL, "dss2_fck", "dss2_fck"),
- DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"),
- DT_CLK(NULL, "core_l3_ck", "core_l3_ck"),
DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
- DT_CLK(NULL, "l4_ck", "l4_ck"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpios_ick", "gpios_ick"),
- DT_CLK(NULL, "gpios_fck", "gpios_fck"),
DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"),
- DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"),
- DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"),
- DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
DT_CLK("omap24xxcam", "fck", "cam_fck"),
- DT_CLK(NULL, "cam_fck", "cam_fck"),
DT_CLK("omap24xxcam", "ick", "cam_ick"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "wdt4_ick", "wdt4_ick"),
- DT_CLK(NULL, "wdt4_fck", "wdt4_fck"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
- DT_CLK(NULL, "fac_fck", "fac_fck"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "sdma_fck", "sdma_fck"),
- DT_CLK(NULL, "sdma_ick", "sdma_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "des_ick", "des_ick"),
DT_CLK("omap-sham", "ick", "sha_ick"),
- DT_CLK(NULL, "sha_ick", "sha_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
- DT_CLK(NULL, "rng_ick", "rng_ick"),
DT_CLK("omap-aes", "ick", "aes_ick"),
- DT_CLK(NULL, "aes_ick", "aes_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "usb_fck", "usb_fck"),
DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "timer_ext_ck", "alt_ck"),
@@ -149,62 +45,23 @@ static struct ti_dt_clk omap2xxx_clks[] = {
};
static struct ti_dt_clk omap2420_clks[] = {
- DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "dsp_ick", "dsp_ick"),
- DT_CLK(NULL, "iva1_ifck", "iva1_ifck"),
- DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
DT_CLK("mmci-omap.0", "ick", "mmc_ick"),
- DT_CLK(NULL, "mmc_ick", "mmc_ick"),
DT_CLK("mmci-omap.0", "fck", "mmc_fck"),
- DT_CLK(NULL, "mmc_fck", "mmc_fck"),
- DT_CLK(NULL, "eac_ick", "eac_ick"),
- DT_CLK(NULL, "eac_fck", "eac_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "vlynq_ick", "vlynq_ick"),
- DT_CLK(NULL, "vlynq_fck", "vlynq_fck"),
DT_CLK("musb-hdrc", "fck", "osc_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap2430_clks[] = {
DT_CLK("twl", "fck", "osc_ck"),
- DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"),
- DT_CLK(NULL, "mdm_ick", "mdm_ick"),
- DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"),
DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
- DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"),
- DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"),
DT_CLK("musb-omap2430", "ick", "usbhs_ick"),
- DT_CLK(NULL, "usbhs_ick", "usbhs_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio5_fck", "gpio5_fck"),
- DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"),
DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"),
- DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"),
DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"),
- DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
{ .node_name = NULL },
};
@@ -239,10 +96,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type)
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
- (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
+ (clk_get_rate(ti_clk_get("sys_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("sys_ck")) / 100000) % 10,
+ (clk_get_rate(ti_clk_get("dpll_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("mpu_ck")) / 1000000));
return 0;
}
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 10/28] clk: ti: omap2: transition to usage of ti_clk_get
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: linux-arm-kernel
Cleanup any unnecessary DT_CLK() alias entries from OMAP2 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-2xxx.c | 151 ++-------------------------------------------
1 file changed, 4 insertions(+), 147 deletions(-)
diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c
index 657c4fe..0b9d7fa 100644
--- a/drivers/clk/ti/clk-2xxx.c
+++ b/drivers/clk/ti/clk-2xxx.c
@@ -22,126 +22,22 @@
#include "clock.h"
static struct ti_dt_clk omap2xxx_clks[] = {
- DT_CLK(NULL, "func_32k_ck", "func_32k_ck"),
- DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"),
- DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"),
- DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"),
- DT_CLK(NULL, "osc_ck", "osc_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "alt_ck", "alt_ck"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "dpll_ck", "dpll_ck"),
- DT_CLK(NULL, "apll96_ck", "apll96_ck"),
- DT_CLK(NULL, "apll54_ck", "apll54_ck"),
- DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "func_96m_ck", "func_96m_ck"),
- DT_CLK(NULL, "func_48m_ck", "func_48m_ck"),
- DT_CLK(NULL, "func_12m_ck", "func_12m_ck"),
- DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"),
- DT_CLK(NULL, "sys_clkout", "sys_clkout"),
- DT_CLK(NULL, "emul_ck", "emul_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "dsp_fck", "dsp_fck"),
- DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"),
- DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"),
- DT_CLK(NULL, "gfx_ick", "gfx_ick"),
DT_CLK("omapdss_dss", "ick", "dss_ick"),
- DT_CLK(NULL, "dss_ick", "dss_ick"),
- DT_CLK(NULL, "dss1_fck", "dss1_fck"),
- DT_CLK(NULL, "dss2_fck", "dss2_fck"),
- DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"),
- DT_CLK(NULL, "core_l3_ck", "core_l3_ck"),
DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
- DT_CLK(NULL, "l4_ck", "l4_ck"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpios_ick", "gpios_ick"),
- DT_CLK(NULL, "gpios_fck", "gpios_fck"),
DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"),
- DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"),
- DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"),
- DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
DT_CLK("omap24xxcam", "fck", "cam_fck"),
- DT_CLK(NULL, "cam_fck", "cam_fck"),
DT_CLK("omap24xxcam", "ick", "cam_ick"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "wdt4_ick", "wdt4_ick"),
- DT_CLK(NULL, "wdt4_fck", "wdt4_fck"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
- DT_CLK(NULL, "fac_fck", "fac_fck"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "sdma_fck", "sdma_fck"),
- DT_CLK(NULL, "sdma_ick", "sdma_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "des_ick", "des_ick"),
DT_CLK("omap-sham", "ick", "sha_ick"),
- DT_CLK(NULL, "sha_ick", "sha_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
- DT_CLK(NULL, "rng_ick", "rng_ick"),
DT_CLK("omap-aes", "ick", "aes_ick"),
- DT_CLK(NULL, "aes_ick", "aes_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "usb_fck", "usb_fck"),
DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "timer_ext_ck", "alt_ck"),
@@ -149,62 +45,23 @@ static struct ti_dt_clk omap2xxx_clks[] = {
};
static struct ti_dt_clk omap2420_clks[] = {
- DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "dsp_ick", "dsp_ick"),
- DT_CLK(NULL, "iva1_ifck", "iva1_ifck"),
- DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
DT_CLK("mmci-omap.0", "ick", "mmc_ick"),
- DT_CLK(NULL, "mmc_ick", "mmc_ick"),
DT_CLK("mmci-omap.0", "fck", "mmc_fck"),
- DT_CLK(NULL, "mmc_fck", "mmc_fck"),
- DT_CLK(NULL, "eac_ick", "eac_ick"),
- DT_CLK(NULL, "eac_fck", "eac_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "vlynq_ick", "vlynq_ick"),
- DT_CLK(NULL, "vlynq_fck", "vlynq_fck"),
DT_CLK("musb-hdrc", "fck", "osc_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap2430_clks[] = {
DT_CLK("twl", "fck", "osc_ck"),
- DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"),
- DT_CLK(NULL, "mdm_ick", "mdm_ick"),
- DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"),
DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
- DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"),
- DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"),
DT_CLK("musb-omap2430", "ick", "usbhs_ick"),
- DT_CLK(NULL, "usbhs_ick", "usbhs_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio5_fck", "gpio5_fck"),
- DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"),
DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"),
- DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"),
DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"),
- DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
{ .node_name = NULL },
};
@@ -239,10 +96,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type)
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
- (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
+ (clk_get_rate(ti_clk_get("sys_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("sys_ck")) / 100000) % 10,
+ (clk_get_rate(ti_clk_get("dpll_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("mpu_ck")) / 1000000));
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 10/28] clk: ti: omap2: transition to usage of ti_clk_get
@ 2016-04-14 11:07 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:07 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Cleanup any unnecessary DT_CLK() alias entries from OMAP2 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-2xxx.c | 151 ++-------------------------------------------
1 file changed, 4 insertions(+), 147 deletions(-)
diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c
index 657c4fe..0b9d7fa 100644
--- a/drivers/clk/ti/clk-2xxx.c
+++ b/drivers/clk/ti/clk-2xxx.c
@@ -22,126 +22,22 @@
#include "clock.h"
static struct ti_dt_clk omap2xxx_clks[] = {
- DT_CLK(NULL, "func_32k_ck", "func_32k_ck"),
- DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"),
- DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"),
- DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"),
- DT_CLK(NULL, "osc_ck", "osc_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "alt_ck", "alt_ck"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "dpll_ck", "dpll_ck"),
- DT_CLK(NULL, "apll96_ck", "apll96_ck"),
- DT_CLK(NULL, "apll54_ck", "apll54_ck"),
- DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "func_96m_ck", "func_96m_ck"),
- DT_CLK(NULL, "func_48m_ck", "func_48m_ck"),
- DT_CLK(NULL, "func_12m_ck", "func_12m_ck"),
- DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"),
- DT_CLK(NULL, "sys_clkout", "sys_clkout"),
- DT_CLK(NULL, "emul_ck", "emul_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "dsp_fck", "dsp_fck"),
- DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"),
- DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"),
- DT_CLK(NULL, "gfx_ick", "gfx_ick"),
DT_CLK("omapdss_dss", "ick", "dss_ick"),
- DT_CLK(NULL, "dss_ick", "dss_ick"),
- DT_CLK(NULL, "dss1_fck", "dss1_fck"),
- DT_CLK(NULL, "dss2_fck", "dss2_fck"),
- DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"),
- DT_CLK(NULL, "core_l3_ck", "core_l3_ck"),
DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
- DT_CLK(NULL, "l4_ck", "l4_ck"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpios_ick", "gpios_ick"),
- DT_CLK(NULL, "gpios_fck", "gpios_fck"),
DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"),
- DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"),
- DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"),
- DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
DT_CLK("omap24xxcam", "fck", "cam_fck"),
- DT_CLK(NULL, "cam_fck", "cam_fck"),
DT_CLK("omap24xxcam", "ick", "cam_ick"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "wdt4_ick", "wdt4_ick"),
- DT_CLK(NULL, "wdt4_fck", "wdt4_fck"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
- DT_CLK(NULL, "fac_fck", "fac_fck"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "sdma_fck", "sdma_fck"),
- DT_CLK(NULL, "sdma_ick", "sdma_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "des_ick", "des_ick"),
DT_CLK("omap-sham", "ick", "sha_ick"),
- DT_CLK(NULL, "sha_ick", "sha_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
- DT_CLK(NULL, "rng_ick", "rng_ick"),
DT_CLK("omap-aes", "ick", "aes_ick"),
- DT_CLK(NULL, "aes_ick", "aes_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "usb_fck", "usb_fck"),
DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "timer_ext_ck", "alt_ck"),
@@ -149,62 +45,23 @@ static struct ti_dt_clk omap2xxx_clks[] = {
};
static struct ti_dt_clk omap2420_clks[] = {
- DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "dsp_ick", "dsp_ick"),
- DT_CLK(NULL, "iva1_ifck", "iva1_ifck"),
- DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
DT_CLK("mmci-omap.0", "ick", "mmc_ick"),
- DT_CLK(NULL, "mmc_ick", "mmc_ick"),
DT_CLK("mmci-omap.0", "fck", "mmc_fck"),
- DT_CLK(NULL, "mmc_fck", "mmc_fck"),
- DT_CLK(NULL, "eac_ick", "eac_ick"),
- DT_CLK(NULL, "eac_fck", "eac_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "vlynq_ick", "vlynq_ick"),
- DT_CLK(NULL, "vlynq_fck", "vlynq_fck"),
DT_CLK("musb-hdrc", "fck", "osc_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap2430_clks[] = {
DT_CLK("twl", "fck", "osc_ck"),
- DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"),
- DT_CLK(NULL, "mdm_ick", "mdm_ick"),
- DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"),
DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
- DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"),
- DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"),
DT_CLK("musb-omap2430", "ick", "usbhs_ick"),
- DT_CLK(NULL, "usbhs_ick", "usbhs_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio5_fck", "gpio5_fck"),
- DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"),
DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"),
- DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"),
DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"),
- DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
{ .node_name = NULL },
};
@@ -239,10 +96,10 @@ static int __init omap2xxx_dt_clk_init(int soc_type)
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
- (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
+ (clk_get_rate(ti_clk_get("sys_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("sys_ck")) / 100000) % 10,
+ (clk_get_rate(ti_clk_get("dpll_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("mpu_ck")) / 1000000));
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 11/28] clk: ti: am33xx: transition to usage of ti_clk_get
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cleanup any unnecessary DT_CLK() alias entries from the AM33xx clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk-33xx.c | 92 ++++-----------------------------------------
1 file changed, 7 insertions(+), 85 deletions(-)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index ef2ec64..43847bc 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -23,88 +23,10 @@
#include "clock.h"
static struct ti_dt_clk am33xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "mmu_fck", "mmu_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
- DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
- DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
- DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
- DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
- DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
- DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+ DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+ DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
@@ -142,11 +64,11 @@ int __init am33xx_dt_clk_init(void)
* oscillator clock.
*/
- clk1 = clk_get_sys(NULL, "sys_clkin_ck");
- clk2 = clk_get_sys(NULL, "timer3_fck");
+ clk1 = ti_clk_get("sys_clkin_ck");
+ clk2 = ti_clk_get("timer3_fck");
clk_set_parent(clk2, clk1);
- clk2 = clk_get_sys(NULL, "timer6_fck");
+ clk2 = ti_clk_get("timer6_fck");
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
@@ -155,8 +77,8 @@ int __init am33xx_dt_clk_init(void)
* not expected by any use-case, so change WDT1 clock source to PRCM
* 32KHz clock.
*/
- clk1 = clk_get_sys(NULL, "wdt1_fck");
- clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+ clk1 = ti_clk_get("wdt1_fck");
+ clk2 = ti_clk_get("clkdiv32k_ick");
clk_set_parent(clk1, clk2);
return 0;
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 11/28] clk: ti: am33xx: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Cleanup any unnecessary DT_CLK() alias entries from the AM33xx clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-33xx.c | 92 ++++-----------------------------------------
1 file changed, 7 insertions(+), 85 deletions(-)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index ef2ec64..43847bc 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -23,88 +23,10 @@
#include "clock.h"
static struct ti_dt_clk am33xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "mmu_fck", "mmu_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
- DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
- DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
- DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
- DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
- DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
- DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+ DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+ DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
@@ -142,11 +64,11 @@ int __init am33xx_dt_clk_init(void)
* oscillator clock.
*/
- clk1 = clk_get_sys(NULL, "sys_clkin_ck");
- clk2 = clk_get_sys(NULL, "timer3_fck");
+ clk1 = ti_clk_get("sys_clkin_ck");
+ clk2 = ti_clk_get("timer3_fck");
clk_set_parent(clk2, clk1);
- clk2 = clk_get_sys(NULL, "timer6_fck");
+ clk2 = ti_clk_get("timer6_fck");
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
@@ -155,8 +77,8 @@ int __init am33xx_dt_clk_init(void)
* not expected by any use-case, so change WDT1 clock source to PRCM
* 32KHz clock.
*/
- clk1 = clk_get_sys(NULL, "wdt1_fck");
- clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+ clk1 = ti_clk_get("wdt1_fck");
+ clk2 = ti_clk_get("clkdiv32k_ick");
clk_set_parent(clk1, clk2);
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 11/28] clk: ti: am33xx: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Cleanup any unnecessary DT_CLK() alias entries from the AM33xx clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-33xx.c | 92 ++++-----------------------------------------
1 file changed, 7 insertions(+), 85 deletions(-)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index ef2ec64..43847bc 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -23,88 +23,10 @@
#include "clock.h"
static struct ti_dt_clk am33xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "mmu_fck", "mmu_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
- DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
- DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
- DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
- DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
- DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
- DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
+ DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+ DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
@@ -142,11 +64,11 @@ int __init am33xx_dt_clk_init(void)
* oscillator clock.
*/
- clk1 = clk_get_sys(NULL, "sys_clkin_ck");
- clk2 = clk_get_sys(NULL, "timer3_fck");
+ clk1 = ti_clk_get("sys_clkin_ck");
+ clk2 = ti_clk_get("timer3_fck");
clk_set_parent(clk2, clk1);
- clk2 = clk_get_sys(NULL, "timer6_fck");
+ clk2 = ti_clk_get("timer6_fck");
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
@@ -155,8 +77,8 @@ int __init am33xx_dt_clk_init(void)
* not expected by any use-case, so change WDT1 clock source to PRCM
* 32KHz clock.
*/
- clk1 = clk_get_sys(NULL, "wdt1_fck");
- clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+ clk1 = ti_clk_get("wdt1_fck");
+ clk2 = ti_clk_get("clkdiv32k_ick");
clk_set_parent(clk1, clk2);
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 12/28] clk: ti: omap3: transition to usage of ti_clk_get
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cleanup any unnecessary DT_CLK() alias entries from the OMAP3 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk-3xxx.c | 224 ++-------------------------------------------
1 file changed, 6 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 8831e1a..f485495 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -233,176 +233,24 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
static struct ti_dt_clk omap3xxx_clks[] = {
DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
- DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
- DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
DT_CLK("twl", "fck", "osc_sys_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
- DT_CLK(NULL, "sys_altclk", "sys_altclk"),
- DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
- DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
- DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
- DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
- DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
- DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
- DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
- DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
- DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
- DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
- DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
- DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
- DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
- DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
- DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
- DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
- DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
- DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
- DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
- DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
- DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
- DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
- DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
- DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
- DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
- DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
- DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "corex2_fck", "corex2_fck"),
- DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "arm_fck", "arm_fck"),
DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
- DT_CLK(NULL, "l3_ick", "l3_ick"),
- DT_CLK(NULL, "l4_ick", "l4_ick"),
- DT_CLK(NULL, "rm_ick", "rm_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
- DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
- DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
- DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
- DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
- DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
- DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "aes2_ick", "aes2_ick"),
- DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
- DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
- DT_CLK(NULL, "sha12_ick", "sha12_ick"),
- DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
DT_CLK("omap_wdt", "ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
- DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
- DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
- DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
- DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
- DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
- DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
- DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
- DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
- DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
- DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
- DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "pclk_fck", "pclk_fck"),
- DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
- DT_CLK(NULL, "atclk_fck", "atclk_fck"),
- DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
- DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
- DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
@@ -410,36 +258,10 @@ static struct ti_dt_clk omap3xxx_clks[] = {
};
static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
- DT_CLK(NULL, "aes1_ick", "aes1_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
- DT_CLK(NULL, "sha11_ick", "sha11_ick"),
- DT_CLK(NULL, "des1_ick", "des1_ick"),
- DT_CLK(NULL, "cam_mclk", "cam_mclk"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
- DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
DT_CLK("omap-aes", "ick", "aes2_ick"),
DT_CLK("omap-sham", "ick", "sha12_ick"),
- DT_CLK(NULL, "des2_ick", "des2_ick"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "sr1_fck", "sr1_fck"),
- DT_CLK(NULL, "sr2_fck", "sr2_fck"),
- DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
- DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
- DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
- DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
- DT_CLK(NULL, "iva2_ck", "iva2_ck"),
- DT_CLK(NULL, "modem_fck", "modem_fck"),
- DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
- DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
- DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
{ .node_name = NULL },
};
@@ -449,26 +271,15 @@ static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
- DT_CLK(NULL, "usim_fck", "usim_fck"),
- DT_CLK(NULL, "usim_ick", "usim_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap3430es1_clks[] = {
- DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
- DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
- DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
- DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
- DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
- DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
- DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
@@ -476,49 +287,26 @@ static struct ti_dt_clk omap3430es1_clks[] = {
};
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
- DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
- DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
- DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
- DT_CLK(NULL, "sgx_fck", "sgx_fck"),
- DT_CLK(NULL, "sgx_ick", "sgx_ick"),
- DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
- DT_CLK(NULL, "ts_fck", "ts_fck"),
- DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
- DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
- DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
- DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
- DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk am35xx_clks[] = {
- DT_CLK(NULL, "ipss_ick", "ipss_ick"),
- DT_CLK(NULL, "rmii_ck", "rmii_ck"),
- DT_CLK(NULL, "pclk_ck", "pclk_ck"),
- DT_CLK(NULL, "emac_ick", "emac_ick"),
- DT_CLK(NULL, "emac_fck", "emac_fck"),
DT_CLK("davinci_emac.0", NULL, "emac_ick"),
DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
DT_CLK("vpfe-capture", "master", "vpfe_ick"),
DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
- DT_CLK(NULL, "hecc_ck", "hecc_ck"),
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_clks[] = {
- DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
- DT_CLK(NULL, "uart4_fck", "uart4_fck"),
- DT_CLK(NULL, "uart4_ick", "uart4_ick"),
{ .node_name = NULL },
};
@@ -546,12 +334,12 @@ void __init omap3_clk_lock_dpll5(void)
struct clk *dpll5_clk;
struct clk *dpll5_m2_clk;
- dpll5_clk = clk_get(NULL, "dpll5_ck");
+ dpll5_clk = ti_clk_get("dpll5_ck");
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
clk_prepare_enable(dpll5_clk);
/* Program dpll5_m2_clk divider for no division */
- dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
+ dpll5_m2_clk = ti_clk_get("dpll5_m2_ck");
clk_prepare_enable(dpll5_m2_clk);
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
@@ -594,10 +382,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
- (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+ (clk_get_rate(ti_clk_get("osc_sys_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("osc_sys_ck")) / 100000) % 10,
+ (clk_get_rate(ti_clk_get("core_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("arm_fck")) / 1000000));
if (soc_type != OMAP3_SOC_OMAP3430_ES1)
omap3_clk_lock_dpll5();
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 12/28] clk: ti: omap3: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Cleanup any unnecessary DT_CLK() alias entries from the OMAP3 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-3xxx.c | 224 ++-------------------------------------------
1 file changed, 6 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 8831e1a..f485495 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -233,176 +233,24 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
static struct ti_dt_clk omap3xxx_clks[] = {
DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
- DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
- DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
DT_CLK("twl", "fck", "osc_sys_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
- DT_CLK(NULL, "sys_altclk", "sys_altclk"),
- DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
- DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
- DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
- DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
- DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
- DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
- DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
- DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
- DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
- DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
- DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
- DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
- DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
- DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
- DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
- DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
- DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
- DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
- DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
- DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
- DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
- DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
- DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
- DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
- DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
- DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
- DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "corex2_fck", "corex2_fck"),
- DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "arm_fck", "arm_fck"),
DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
- DT_CLK(NULL, "l3_ick", "l3_ick"),
- DT_CLK(NULL, "l4_ick", "l4_ick"),
- DT_CLK(NULL, "rm_ick", "rm_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
- DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
- DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
- DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
- DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
- DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
- DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "aes2_ick", "aes2_ick"),
- DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
- DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
- DT_CLK(NULL, "sha12_ick", "sha12_ick"),
- DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
DT_CLK("omap_wdt", "ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
- DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
- DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
- DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
- DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
- DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
- DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
- DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
- DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
- DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
- DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
- DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "pclk_fck", "pclk_fck"),
- DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
- DT_CLK(NULL, "atclk_fck", "atclk_fck"),
- DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
- DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
- DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
@@ -410,36 +258,10 @@ static struct ti_dt_clk omap3xxx_clks[] = {
};
static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
- DT_CLK(NULL, "aes1_ick", "aes1_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
- DT_CLK(NULL, "sha11_ick", "sha11_ick"),
- DT_CLK(NULL, "des1_ick", "des1_ick"),
- DT_CLK(NULL, "cam_mclk", "cam_mclk"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
- DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
DT_CLK("omap-aes", "ick", "aes2_ick"),
DT_CLK("omap-sham", "ick", "sha12_ick"),
- DT_CLK(NULL, "des2_ick", "des2_ick"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "sr1_fck", "sr1_fck"),
- DT_CLK(NULL, "sr2_fck", "sr2_fck"),
- DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
- DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
- DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
- DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
- DT_CLK(NULL, "iva2_ck", "iva2_ck"),
- DT_CLK(NULL, "modem_fck", "modem_fck"),
- DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
- DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
- DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
{ .node_name = NULL },
};
@@ -449,26 +271,15 @@ static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
- DT_CLK(NULL, "usim_fck", "usim_fck"),
- DT_CLK(NULL, "usim_ick", "usim_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap3430es1_clks[] = {
- DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
- DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
- DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
- DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
- DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
- DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
- DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
@@ -476,49 +287,26 @@ static struct ti_dt_clk omap3430es1_clks[] = {
};
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
- DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
- DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
- DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
- DT_CLK(NULL, "sgx_fck", "sgx_fck"),
- DT_CLK(NULL, "sgx_ick", "sgx_ick"),
- DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
- DT_CLK(NULL, "ts_fck", "ts_fck"),
- DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
- DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
- DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
- DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
- DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk am35xx_clks[] = {
- DT_CLK(NULL, "ipss_ick", "ipss_ick"),
- DT_CLK(NULL, "rmii_ck", "rmii_ck"),
- DT_CLK(NULL, "pclk_ck", "pclk_ck"),
- DT_CLK(NULL, "emac_ick", "emac_ick"),
- DT_CLK(NULL, "emac_fck", "emac_fck"),
DT_CLK("davinci_emac.0", NULL, "emac_ick"),
DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
DT_CLK("vpfe-capture", "master", "vpfe_ick"),
DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
- DT_CLK(NULL, "hecc_ck", "hecc_ck"),
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_clks[] = {
- DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
- DT_CLK(NULL, "uart4_fck", "uart4_fck"),
- DT_CLK(NULL, "uart4_ick", "uart4_ick"),
{ .node_name = NULL },
};
@@ -546,12 +334,12 @@ void __init omap3_clk_lock_dpll5(void)
struct clk *dpll5_clk;
struct clk *dpll5_m2_clk;
- dpll5_clk = clk_get(NULL, "dpll5_ck");
+ dpll5_clk = ti_clk_get("dpll5_ck");
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
clk_prepare_enable(dpll5_clk);
/* Program dpll5_m2_clk divider for no division */
- dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
+ dpll5_m2_clk = ti_clk_get("dpll5_m2_ck");
clk_prepare_enable(dpll5_m2_clk);
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
@@ -594,10 +382,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
- (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+ (clk_get_rate(ti_clk_get("osc_sys_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("osc_sys_ck")) / 100000) % 10,
+ (clk_get_rate(ti_clk_get("core_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("arm_fck")) / 1000000));
if (soc_type != OMAP3_SOC_OMAP3430_ES1)
omap3_clk_lock_dpll5();
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 12/28] clk: ti: omap3: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Cleanup any unnecessary DT_CLK() alias entries from the OMAP3 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-3xxx.c | 224 ++-------------------------------------------
1 file changed, 6 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 8831e1a..f485495 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -233,176 +233,24 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
static struct ti_dt_clk omap3xxx_clks[] = {
DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
- DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
- DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
DT_CLK("twl", "fck", "osc_sys_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
- DT_CLK(NULL, "sys_altclk", "sys_altclk"),
- DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
- DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
- DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
- DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
- DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
- DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
- DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
- DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
- DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
- DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
- DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
- DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
- DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
- DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
- DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
- DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
- DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
- DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
- DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
- DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
- DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
- DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
- DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
- DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
- DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
- DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
- DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "corex2_fck", "corex2_fck"),
- DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "arm_fck", "arm_fck"),
DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
- DT_CLK(NULL, "l3_ick", "l3_ick"),
- DT_CLK(NULL, "l4_ick", "l4_ick"),
- DT_CLK(NULL, "rm_ick", "rm_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
- DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
- DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
- DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
- DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
- DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
- DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "aes2_ick", "aes2_ick"),
- DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
- DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
- DT_CLK(NULL, "sha12_ick", "sha12_ick"),
- DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
DT_CLK("omap_wdt", "ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
- DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
- DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
- DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
- DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
- DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
- DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
- DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
- DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
- DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
- DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
- DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "pclk_fck", "pclk_fck"),
- DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
- DT_CLK(NULL, "atclk_fck", "atclk_fck"),
- DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
- DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
- DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
@@ -410,36 +258,10 @@ static struct ti_dt_clk omap3xxx_clks[] = {
};
static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
- DT_CLK(NULL, "aes1_ick", "aes1_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
- DT_CLK(NULL, "sha11_ick", "sha11_ick"),
- DT_CLK(NULL, "des1_ick", "des1_ick"),
- DT_CLK(NULL, "cam_mclk", "cam_mclk"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
- DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
DT_CLK("omap-aes", "ick", "aes2_ick"),
DT_CLK("omap-sham", "ick", "sha12_ick"),
- DT_CLK(NULL, "des2_ick", "des2_ick"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "sr1_fck", "sr1_fck"),
- DT_CLK(NULL, "sr2_fck", "sr2_fck"),
- DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
- DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
- DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
- DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
- DT_CLK(NULL, "iva2_ck", "iva2_ck"),
- DT_CLK(NULL, "modem_fck", "modem_fck"),
- DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
- DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
- DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
{ .node_name = NULL },
};
@@ -449,26 +271,15 @@ static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
- DT_CLK(NULL, "usim_fck", "usim_fck"),
- DT_CLK(NULL, "usim_ick", "usim_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap3430es1_clks[] = {
- DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
- DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
- DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
- DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
- DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
- DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
- DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
@@ -476,49 +287,26 @@ static struct ti_dt_clk omap3430es1_clks[] = {
};
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
- DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
- DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
- DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
- DT_CLK(NULL, "sgx_fck", "sgx_fck"),
- DT_CLK(NULL, "sgx_ick", "sgx_ick"),
- DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
- DT_CLK(NULL, "ts_fck", "ts_fck"),
- DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
- DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
- DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
- DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
- DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk am35xx_clks[] = {
- DT_CLK(NULL, "ipss_ick", "ipss_ick"),
- DT_CLK(NULL, "rmii_ck", "rmii_ck"),
- DT_CLK(NULL, "pclk_ck", "pclk_ck"),
- DT_CLK(NULL, "emac_ick", "emac_ick"),
- DT_CLK(NULL, "emac_fck", "emac_fck"),
DT_CLK("davinci_emac.0", NULL, "emac_ick"),
DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
DT_CLK("vpfe-capture", "master", "vpfe_ick"),
DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
- DT_CLK(NULL, "hecc_ck", "hecc_ck"),
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_clks[] = {
- DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
- DT_CLK(NULL, "uart4_fck", "uart4_fck"),
- DT_CLK(NULL, "uart4_ick", "uart4_ick"),
{ .node_name = NULL },
};
@@ -546,12 +334,12 @@ void __init omap3_clk_lock_dpll5(void)
struct clk *dpll5_clk;
struct clk *dpll5_m2_clk;
- dpll5_clk = clk_get(NULL, "dpll5_ck");
+ dpll5_clk = ti_clk_get("dpll5_ck");
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
clk_prepare_enable(dpll5_clk);
/* Program dpll5_m2_clk divider for no division */
- dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
+ dpll5_m2_clk = ti_clk_get("dpll5_m2_ck");
clk_prepare_enable(dpll5_m2_clk);
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
@@ -594,10 +382,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
- (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
- (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+ (clk_get_rate(ti_clk_get("osc_sys_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("osc_sys_ck")) / 100000) % 10,
+ (clk_get_rate(ti_clk_get("core_ck")) / 1000000),
+ (clk_get_rate(ti_clk_get("arm_fck")) / 1000000));
if (soc_type != OMAP3_SOC_OMAP3430_ES1)
omap3_clk_lock_dpll5();
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 13/28] clk: ti: am43xx: transition to usage of ti_clk_get
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cleanup any unnecessary DT_CLK() alias entries from the AM43xx clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk-43xx.c | 88 ++-------------------------------------------
1 file changed, 2 insertions(+), 86 deletions(-)
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 097fc90..eefa62b 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -23,92 +23,8 @@
#include "clock.h"
static struct ti_dt_clk am43xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sysclk_div", "sysclk_div"),
- DT_CLK(NULL, "disp_clk", "disp_clk"),
- DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
- DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
- DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
- DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
- DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
- DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
- DT_CLK(NULL, "timer8_fck", "timer8_fck"),
- DT_CLK(NULL, "timer9_fck", "timer9_fck"),
- DT_CLK(NULL, "timer10_fck", "timer10_fck"),
- DT_CLK(NULL, "timer11_fck", "timer11_fck"),
- DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
- DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
- DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
- DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
- DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
- DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
- DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
- DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
@@ -136,8 +52,8 @@ int __init am43xx_dt_clk_init(void)
* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
* In AM335x dpll_core_m5_ck is the default clocksource.
*/
- clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
- clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
+ clk1 = ti_clk_get("cpsw_cpts_rft_clk");
+ clk2 = ti_clk_get("dpll_core_m5_ck");
clk_set_parent(clk1, clk2);
return 0;
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 13/28] clk: ti: am43xx: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Cleanup any unnecessary DT_CLK() alias entries from the AM43xx clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-43xx.c | 88 ++-------------------------------------------
1 file changed, 2 insertions(+), 86 deletions(-)
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 097fc90..eefa62b 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -23,92 +23,8 @@
#include "clock.h"
static struct ti_dt_clk am43xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sysclk_div", "sysclk_div"),
- DT_CLK(NULL, "disp_clk", "disp_clk"),
- DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
- DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
- DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
- DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
- DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
- DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
- DT_CLK(NULL, "timer8_fck", "timer8_fck"),
- DT_CLK(NULL, "timer9_fck", "timer9_fck"),
- DT_CLK(NULL, "timer10_fck", "timer10_fck"),
- DT_CLK(NULL, "timer11_fck", "timer11_fck"),
- DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
- DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
- DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
- DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
- DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
- DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
- DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
- DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
@@ -136,8 +52,8 @@ int __init am43xx_dt_clk_init(void)
* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
* In AM335x dpll_core_m5_ck is the default clocksource.
*/
- clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
- clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
+ clk1 = ti_clk_get("cpsw_cpts_rft_clk");
+ clk2 = ti_clk_get("dpll_core_m5_ck");
clk_set_parent(clk1, clk2);
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 13/28] clk: ti: am43xx: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Cleanup any unnecessary DT_CLK() alias entries from the AM43xx clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-43xx.c | 88 ++-------------------------------------------
1 file changed, 2 insertions(+), 86 deletions(-)
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 097fc90..eefa62b 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -23,92 +23,8 @@
#include "clock.h"
static struct ti_dt_clk am43xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sysclk_div", "sysclk_div"),
- DT_CLK(NULL, "disp_clk", "disp_clk"),
- DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
- DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
- DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
- DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
- DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
- DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
- DT_CLK(NULL, "timer8_fck", "timer8_fck"),
- DT_CLK(NULL, "timer9_fck", "timer9_fck"),
- DT_CLK(NULL, "timer10_fck", "timer10_fck"),
- DT_CLK(NULL, "timer11_fck", "timer11_fck"),
- DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
- DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
- DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
- DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
- DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
- DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
- DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
- DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
@@ -136,8 +52,8 @@ int __init am43xx_dt_clk_init(void)
* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
* In AM335x dpll_core_m5_ck is the default clocksource.
*/
- clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
- clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
+ clk1 = ti_clk_get("cpsw_cpts_rft_clk");
+ clk2 = ti_clk_get("dpll_core_m5_ck");
clk_set_parent(clk1, clk2);
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 14/28] clk: ti: omap4: transition to usage of ti_clk_get
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cleanup any unnecessary DT_CLK() alias entries from the OMAP4 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk-44xx.c | 194 +--------------------------------------------
1 file changed, 4 insertions(+), 190 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 7a8b51b..92fb189 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -34,196 +34,13 @@
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static struct ti_dt_clk omap44xx_clks[] = {
- DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
- DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
- DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
- DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
- DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
- DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
- DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
- DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
- DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
- DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
- DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
- DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
- DT_CLK(NULL, "div_core_ck", "div_core_ck"),
- DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
- DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
- DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
- DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
- DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
- DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
- DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
- DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
- DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
- DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
- DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
- DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
- DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
- DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
- DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
- DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
- DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
- DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
- DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
- DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
DT_CLK("smp_twd", NULL, "mpu_periphclk"),
- DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
- DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
- DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
- DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
- DT_CLK(NULL, "aes1_fck", "aes1_fck"),
- DT_CLK(NULL, "aes2_fck", "aes2_fck"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
- DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
- DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
- DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_fck", "dss_fck"),
DT_CLK("omapdss_dss", "ick", "dss_fck"),
- DT_CLK(NULL, "fdif_fck", "fdif_fck"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
- DT_CLK(NULL, "hsi_fck", "hsi_fck"),
- DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
- DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
- DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
- DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
- DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
- DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
- DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
- DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
- DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
- DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
- DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
- DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
- DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
- DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
- DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
- DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
- DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
- DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
- DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
- DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
- DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
- DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
- DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
- DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
- DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
- DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
- DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
- DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
- DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
- DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
- DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
- DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
- DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
- DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
- DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
- DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
- DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
- DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
- DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK(NULL, "usim_ck", "usim_ck"),
- DT_CLK(NULL, "usim_fclk", "usim_fclk"),
- DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
- DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
- DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
- DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
- DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
- DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
- DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
- DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
- DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
- DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
- DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
- DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
- DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
- DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
- DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
- DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
- DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
- DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
- DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
@@ -263,9 +80,6 @@ static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
- DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
- DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
{ .node_name = NULL },
};
@@ -282,7 +96,7 @@ int __init omap4xxx_dt_clk_init(void)
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
- usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ usb_dpll = ti_clk_get("dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
@@ -293,10 +107,10 @@ int __init omap4xxx_dt_clk_init(void)
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
- abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
- sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ abe_dpll_ref = ti_clk_get("abe_dpll_refclk_mux_ck");
+ sys_32k_ck = ti_clk_get("sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
- abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ abe_dpll = ti_clk_get("dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 14/28] clk: ti: omap4: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Cleanup any unnecessary DT_CLK() alias entries from the OMAP4 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-44xx.c | 194 +--------------------------------------------
1 file changed, 4 insertions(+), 190 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 7a8b51b..92fb189 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -34,196 +34,13 @@
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static struct ti_dt_clk omap44xx_clks[] = {
- DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
- DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
- DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
- DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
- DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
- DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
- DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
- DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
- DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
- DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
- DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
- DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
- DT_CLK(NULL, "div_core_ck", "div_core_ck"),
- DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
- DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
- DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
- DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
- DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
- DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
- DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
- DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
- DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
- DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
- DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
- DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
- DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
- DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
- DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
- DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
- DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
- DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
- DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
- DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
DT_CLK("smp_twd", NULL, "mpu_periphclk"),
- DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
- DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
- DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
- DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
- DT_CLK(NULL, "aes1_fck", "aes1_fck"),
- DT_CLK(NULL, "aes2_fck", "aes2_fck"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
- DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
- DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
- DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_fck", "dss_fck"),
DT_CLK("omapdss_dss", "ick", "dss_fck"),
- DT_CLK(NULL, "fdif_fck", "fdif_fck"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
- DT_CLK(NULL, "hsi_fck", "hsi_fck"),
- DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
- DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
- DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
- DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
- DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
- DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
- DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
- DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
- DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
- DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
- DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
- DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
- DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
- DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
- DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
- DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
- DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
- DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
- DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
- DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
- DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
- DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
- DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
- DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
- DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
- DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
- DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
- DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
- DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
- DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
- DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
- DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
- DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
- DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
- DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
- DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
- DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
- DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
- DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK(NULL, "usim_ck", "usim_ck"),
- DT_CLK(NULL, "usim_fclk", "usim_fclk"),
- DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
- DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
- DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
- DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
- DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
- DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
- DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
- DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
- DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
- DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
- DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
- DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
- DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
- DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
- DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
- DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
- DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
- DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
- DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
@@ -263,9 +80,6 @@ static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
- DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
- DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
{ .node_name = NULL },
};
@@ -282,7 +96,7 @@ int __init omap4xxx_dt_clk_init(void)
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
- usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ usb_dpll = ti_clk_get("dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
@@ -293,10 +107,10 @@ int __init omap4xxx_dt_clk_init(void)
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
- abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
- sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ abe_dpll_ref = ti_clk_get("abe_dpll_refclk_mux_ck");
+ sys_32k_ck = ti_clk_get("sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
- abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ abe_dpll = ti_clk_get("dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 14/28] clk: ti: omap4: transition to usage of ti_clk_get
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Cleanup any unnecessary DT_CLK() alias entries from the OMAP4 clock file.
Also, use ti_clk_get where necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-44xx.c | 194 +--------------------------------------------
1 file changed, 4 insertions(+), 190 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 7a8b51b..92fb189 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -34,196 +34,13 @@
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static struct ti_dt_clk omap44xx_clks[] = {
- DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
- DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
- DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
- DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
- DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
- DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
- DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
- DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
- DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
- DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
- DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
- DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
- DT_CLK(NULL, "div_core_ck", "div_core_ck"),
- DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
- DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
- DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
- DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
- DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
- DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
- DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
- DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
- DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
- DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
- DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
- DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
- DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
- DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
- DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
- DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
- DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
- DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
- DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
- DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
DT_CLK("smp_twd", NULL, "mpu_periphclk"),
- DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
- DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
- DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
- DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
- DT_CLK(NULL, "aes1_fck", "aes1_fck"),
- DT_CLK(NULL, "aes2_fck", "aes2_fck"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
- DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
- DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
- DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_fck", "dss_fck"),
DT_CLK("omapdss_dss", "ick", "dss_fck"),
- DT_CLK(NULL, "fdif_fck", "fdif_fck"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
- DT_CLK(NULL, "hsi_fck", "hsi_fck"),
- DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
- DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
- DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
- DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
- DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
- DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
- DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
- DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
- DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
- DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
- DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
- DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
- DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
- DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
- DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
- DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
- DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
- DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
- DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
- DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
- DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
- DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
- DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
- DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
- DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
- DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
- DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
- DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
- DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
- DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
- DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
- DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
- DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
- DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
- DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
- DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
- DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
- DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
- DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
- DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK(NULL, "usim_ck", "usim_ck"),
- DT_CLK(NULL, "usim_fclk", "usim_fclk"),
- DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
- DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
- DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
- DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
- DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
- DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
- DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
- DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
- DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
- DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
- DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
- DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
- DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
- DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
- DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
- DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
- DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
- DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
- DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
@@ -263,9 +80,6 @@ static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
- DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
- DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
{ .node_name = NULL },
};
@@ -282,7 +96,7 @@ int __init omap4xxx_dt_clk_init(void)
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
- usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+ usb_dpll = ti_clk_get("dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
@@ -293,10 +107,10 @@ int __init omap4xxx_dt_clk_init(void)
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
- abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
- sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+ abe_dpll_ref = ti_clk_get("abe_dpll_refclk_mux_ck");
+ sys_32k_ck = ti_clk_get("sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
- abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+ abe_dpll = ti_clk_get("dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 20/28] clk: ti: mux: export mux clock APIs locally
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
get_parent and set_parent are going to be required by the support of
module clocks, so export these locally.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clock.h | 3 +++
drivers/clk/ti/mux.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 90f3f47..7eca8a1 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
+u8 ti_clk_mux_get_parent(struct clk_hw *hw);
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index);
+
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 44777ab..57ff471 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -26,7 +26,7 @@
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
-static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
+u8 ti_clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
@@ -63,7 +63,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
return val;
}
-static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 20/28] clk: ti: mux: export mux clock APIs locally
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
get_parent and set_parent are going to be required by the support of
module clocks, so export these locally.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clock.h | 3 +++
drivers/clk/ti/mux.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 90f3f47..7eca8a1 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
+u8 ti_clk_mux_get_parent(struct clk_hw *hw);
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index);
+
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 44777ab..57ff471 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -26,7 +26,7 @@
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
-static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
+u8 ti_clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
@@ -63,7 +63,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
return val;
}
-static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 20/28] clk: ti: mux: export mux clock APIs locally
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
get_parent and set_parent are going to be required by the support of
module clocks, so export these locally.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clock.h | 3 +++
drivers/clk/ti/mux.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 90f3f47..7eca8a1 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
+u8 ti_clk_mux_get_parent(struct clk_hw *hw);
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index);
+
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 44777ab..57ff471 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -26,7 +26,7 @@
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
-static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
+u8 ti_clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
@@ -63,7 +63,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
return val;
}
-static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 21/28] clk: ti: am33xx: fix timer3/6 init time setup for module clocks
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
timer*_fck are going to be renamed as timer*_mod_ck:s. Fix the init
time configuration of timer3/timer6 to take this into account, and
lookup for the module clock in case the lookup for fck fails.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
drivers/clk/ti/clk-33xx.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 43847bc..2343a22 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -66,9 +66,15 @@ int __init am33xx_dt_clk_init(void)
clk1 = ti_clk_get("sys_clkin_ck");
clk2 = ti_clk_get("timer3_fck");
+ if (IS_ERR(clk2))
+ clk2 = ti_clk_get("timer3_mod_ck");
+
clk_set_parent(clk2, clk1);
clk2 = ti_clk_get("timer6_fck");
+ if (IS_ERR(clk2))
+ clk2 = ti_clk_get("timer6_mod_ck");
+
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 21/28] clk: ti: am33xx: fix timer3/6 init time setup for module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
timer*_fck are going to be renamed as timer*_mod_ck:s. Fix the init
time configuration of timer3/timer6 to take this into account, and
lookup for the module clock in case the lookup for fck fails.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-33xx.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 43847bc..2343a22 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -66,9 +66,15 @@ int __init am33xx_dt_clk_init(void)
clk1 = ti_clk_get("sys_clkin_ck");
clk2 = ti_clk_get("timer3_fck");
+ if (IS_ERR(clk2))
+ clk2 = ti_clk_get("timer3_mod_ck");
+
clk_set_parent(clk2, clk1);
clk2 = ti_clk_get("timer6_fck");
+ if (IS_ERR(clk2))
+ clk2 = ti_clk_get("timer6_mod_ck");
+
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 21/28] clk: ti: am33xx: fix timer3/6 init time setup for module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
timer*_fck are going to be renamed as timer*_mod_ck:s. Fix the init
time configuration of timer3/timer6 to take this into account, and
lookup for the module clock in case the lookup for fck fails.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-33xx.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 43847bc..2343a22 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -66,9 +66,15 @@ int __init am33xx_dt_clk_init(void)
clk1 = ti_clk_get("sys_clkin_ck");
clk2 = ti_clk_get("timer3_fck");
+ if (IS_ERR(clk2))
+ clk2 = ti_clk_get("timer3_mod_ck");
+
clk_set_parent(clk2, clk1);
clk2 = ti_clk_get("timer6_fck");
+ if (IS_ERR(clk2))
+ clk2 = ti_clk_get("timer6_mod_ck");
+
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 24/28] ARM: dts: omap4: add hwmod module clocks
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap44xx-clocks.dtsi | 853 +++++++++++++++++++++++++++++---
1 file changed, 780 insertions(+), 73 deletions(-)
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37..ac6171c 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -183,6 +183,20 @@
reg = <0x0528>;
};
+ aess_mod_ck: aess_mod_ck@528 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0528>;
+ clocks = <&aess_fclk>;
+ };
+
+ mcpdm_mod_ck: mcpdm_mod_ck@530 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -194,6 +208,34 @@
ti,invert-autoidle-bit;
};
+ mpu_mod_ck: mpu_mod_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck@420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ dsp_mod_ck: dsp_mod_ck@420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck@520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&ocp_abe_iclk>;
+ };
+
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -480,6 +522,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck@538 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&func_dmic_abe_gfclk>;
+ };
+
func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -496,6 +545,13 @@
reg = <0x0540>;
};
+ mcasp_mod_ck: mcasp_mod_ck@540 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0540>;
+ clocks = <&func_mcasp_abe_gfclk>;
+ };
+
func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -520,6 +576,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck@548 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&func_mcbsp1_gfclk>;
+ };
+
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -536,6 +599,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck@550 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&func_mcbsp2_gfclk>;
+ };
+
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -552,6 +622,13 @@
reg = <0x0558>;
};
+ mcbsp3_mod_ck: mcbsp3_mod_ck@558 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&func_mcbsp3_gfclk>;
+ };
+
slimbus1_fclk_1: slimbus1_fclk_1@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -568,52 +645,66 @@
reg = <0x0560>;
};
- slimbus1_fclk_2: slimbus1_fclk_2@560 {
+ slimbus1_mod_ck: slimbus1_mod_ck@560 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_ck>;
- ti,bit-shift = <10>;
+ compatible = "ti,omap4-sw-mod-clock";
reg = <0x0560>;
+ clocks = <&slimbus1_fclk_0>;
};
- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
+ timer5_mod_ck: timer5_mod_ck@568 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0568>, <0x0568>;
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
};
- timer5_sync_mux: timer5_sync_mux@568 {
+ timer6_mod_ck: timer6_mod_ck@570 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>, <0x0570>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0568>;
};
- timer6_sync_mux: timer6_sync_mux@570 {
+ timer7_mod_ck: timer7_mod_ck@578 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0578>, <0x0578>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0570>;
};
- timer7_sync_mux: timer7_sync_mux@578 {
+ timer8_mod_ck: timer8_mod_ck@580 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0580>, <0x0580>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0578>;
};
- timer8_sync_mux: timer8_sync_mux@580 {
+ wd_timer3_mod_ck: wd_timer3_mod_ck@588 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0588>;
+ clocks = <&sys_32k_ck>;
+ };
+
+ slimbus1_fclk_2: slimbus1_fclk_2@560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0560>;
+ };
+
+ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x0560>;
};
dummy_ck: dummy_ck {
@@ -631,6 +722,20 @@
ti,index-starts-at-one;
};
+ l4_wkup_mod_ck: l4_wkup_mod_ck@1820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1820>;
+ clocks = <&l4_wkup_clk_mux_ck>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck@1830 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1830>;
+ clocks = <&sys_32k_ck>;
+ };
+
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -677,12 +782,26 @@
reg = <0x1838>;
};
- dmt1_clk_mux: dmt1_clk_mux@1840 {
+ gpio1_mod_ck: gpio1_mod_ck@1838 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1838>;
+ clocks = <&l4_wkup_clk_mux_ck>;
+ };
+
+ timer1_mod_ck: timer1_mod_ck@1840 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1840>, <0x1840>;
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x1840>;
+ };
+
+ counter_32k_mod_ck: counter_32k_mod_ck@1850 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1850>;
+ clocks = <&sys_32k_ck>;
};
usim_ck: usim_ck@1858 {
@@ -694,6 +813,13 @@
ti,dividers = <14>, <18>;
};
+ kbd_mod_ck: kbd_mod_ck@1878 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1878>;
+ clocks = <&sys_32k_ck>;
+ };
+
usim_fclk: usim_fclk@1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -737,6 +863,13 @@
ti,dividers = <0>, <1>, <2>, <0>, <4>;
};
+ debugss_mod_ck: debugss_mod_ck@1a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1a20>;
+ clocks = <&trace_clk_div_ck>;
+ };
+
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
@@ -747,7 +880,14 @@
&prm_clockdomains {
emu_sys_clkdm: emu_sys_clkdm {
compatible = "ti,clockdomain";
- clocks = <&trace_clk_div_ck>;
+ clocks = <&debugss_mod_ck>, <&trace_clk_div_ck>;
+ };
+
+ l4_wkup_clkdm: l4_wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&timer1_mod_ck>, <&l4_wkup_mod_ck>, <&gpio1_mod_ck>,
+ <&wd_timer2_mod_ck>, <&counter_32k_mod_ck>,
+ <&kbd_mod_ck>;
};
};
@@ -993,6 +1133,55 @@
reg = <0x1120>;
};
+ dss_venc_mod_ck: dss_venc_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_tv_clk>;
+ };
+
+ dss_dispc_mod_ck: dss_dispc_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi1_mod_ck: dss_dsi1_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi2_mod_ck: dss_dsi2_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_hdmi_mod_ck: dss_hdmi_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_48mhz_clk>;
+ };
+
dss_tv_clk: dss_tv_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1028,6 +1217,13 @@
ti,index-power-of-two;
};
+ fdif_mod_ck: fdif_mod_ck@1028 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1028>;
+ clocks = <&fdif_fck>;
+ };
+
gpio2_dbclk: gpio2_dbclk@1460 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1036,6 +1232,13 @@
reg = <0x1460>;
};
+ gpio2_mod_ck: gpio2_mod_ck@1460 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1460>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio3_dbclk: gpio3_dbclk@1468 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1044,6 +1247,13 @@
reg = <0x1468>;
};
+ gpio3_mod_ck: gpio3_mod_ck@1468 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1468>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio4_dbclk: gpio4_dbclk@1470 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1052,6 +1262,13 @@
reg = <0x1470>;
};
+ gpio4_mod_ck: gpio4_mod_ck@1470 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1470>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio5_dbclk: gpio5_dbclk@1478 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1060,6 +1277,13 @@
reg = <0x1478>;
};
+ gpio5_mod_ck: gpio5_mod_ck@1478 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1478>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio6_dbclk: gpio6_dbclk@1480 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1068,6 +1292,55 @@
reg = <0x1480>;
};
+ gpio6_mod_ck: gpio6_mod_ck@1480 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1480>;
+ clocks = <&l4_div_ck>;
+ };
+
+ hdq1w_mod_ck: hdq1w_mod_ck@1488 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1488>;
+ clocks = <&func_12m_fclk>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck@14a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck@14a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck@14b0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14b0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c4_mod_ck: i2c4_mod_ck@14b8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14b8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ l4_per_mod_ck: l4_per_mod_ck@14c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x14c0>;
+ clocks = <&l4_div_ck>;
+ };
+
sgx_clk_mux: sgx_clk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1076,6 +1349,13 @@
reg = <0x1220>;
};
+ gpu_mod_ck: gpu_mod_ck@1220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1220>;
+ clocks = <&sgx_clk_mux>;
+ };
+
hsi_fck: hsi_fck@1338 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1086,6 +1366,13 @@
ti,index-power-of-two;
};
+ hsi_mod_ck: hsi_mod_ck@1338 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1338>;
+ clocks = <&hsi_fck>;
+ };
+
iss_ctrlclk: iss_ctrlclk@1020 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1094,6 +1381,13 @@
reg = <0x1020>;
};
+ iss_mod_ck: iss_mod_ck@1020 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1020>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1102,6 +1396,55 @@
reg = <0x14e0>;
};
+ mcbsp4_mod_ck: mcbsp4_mod_ck@14e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14e0>;
+ clocks = <&per_mcbsp4_gfclk>;
+ };
+
+ mcspi1_mod_ck: mcspi1_mod_ck@14f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14f0>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi2_mod_ck: mcspi2_mod_ck@14f8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14f8>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi3_mod_ck: mcspi3_mod_ck@1500 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1500>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi4_mod_ck: mcspi4_mod_ck@1508 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1508>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck@1520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1520>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc4_mod_ck: mmc4_mod_ck@1528 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1528>;
+ clocks = <&func_48m_fclk>;
+ };
+
per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1118,6 +1461,13 @@
reg = <0x1328>;
};
+ mmc1_mod_ck: mmc1_mod_ck@1328 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1328>;
+ clocks = <&hsmmc1_fclk>;
+ };
+
hsmmc2_fclk: hsmmc2_fclk@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1126,6 +1476,13 @@
reg = <0x1330>;
};
+ mmc2_mod_ck: mmc2_mod_ck@1330 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1330>;
+ clocks = <&hsmmc2_fclk>;
+ };
+
ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1134,6 +1491,68 @@
reg = <0x13e0>;
};
+ ocp2scp_usb_phy_mod_ck: ocp2scp_usb_phy_mod_ck@13e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x13e0>;
+ clocks = <&ocp2scp_usb_phy_phy_48m>;
+ };
+
+ timer10_mod_ck: timer10_mod_ck@1428 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1428>, <0x1428>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck@1430 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1430>, <0x1430>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck@1438 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1438>, <0x1438>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck@1440 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1440>, <0x1440>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck@1448 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1448>, <0x1448>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck@1450 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1450>, <0x1450>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ elm_mod_ck: elm_mod_ck@1458 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1458>;
+ clocks = <&l4_div_ck>;
+ };
+
sha2md5_fck: sha2md5_fck@15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1166,76 +1585,91 @@
reg = <0x1538>;
};
- smartreflex_core_fck: smartreflex_core_fck@638 {
+ slimbus2_mod_ck: slimbus2_mod_ck@1538 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0638>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1538>;
+ clocks = <&slimbus2_fclk_0>;
};
- smartreflex_iva_fck: smartreflex_iva_fck@630 {
+ uart1_mod_ck: uart1_mod_ck@1540 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0630>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1540>;
+ clocks = <&func_48m_fclk>;
};
- smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
+ uart2_mod_ck: uart2_mod_ck@1548 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0628>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1548>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm10_mux: cm2_dm10_mux@1428 {
+ uart3_mod_ck: uart3_mod_ck@1550 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1428>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1550>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm11_mux: cm2_dm11_mux@1430 {
+ uart4_mod_ck: uart4_mod_ck@1558 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1430>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1558>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm2_mux: cm2_dm2_mux@1438 {
+ mmc5_mod_ck: mmc5_mod_ck@1560 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1438>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1560>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm3_mux: cm2_dm3_mux@1440 {
+ smartreflex_core_fck: smartreflex_core_fck@638 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1440>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0638>;
};
- cm2_dm4_mux: cm2_dm4_mux@1448 {
+ smartreflex_core_mod_ck: smartreflex_core_mod_ck@638 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1448>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0638>;
+ clocks = <&smartreflex_core_fck>;
};
- cm2_dm9_mux: cm2_dm9_mux@1450 {
+ smartreflex_iva_fck: smartreflex_iva_fck@630 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1450>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0630>;
+ };
+
+ smartreflex_iva_mod_ck: smartreflex_iva_mod_ck@630 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0630>;
+ clocks = <&smartreflex_iva_fck>;
+ };
+
+ smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0628>;
+ };
+
+ smartreflex_mpu_mod_ck: smartreflex_mpu_mod_ck@628 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0628>;
+ clocks = <&smartreflex_mpu_fck>;
};
usb_host_fs_fck: usb_host_fs_fck@13d0 {
@@ -1246,6 +1680,13 @@
reg = <0x13d0>;
};
+ usb_host_fs_mod_ck: usb_host_fs_mod_ck@13d0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x13d0>;
+ clocks = <&usb_host_fs_fck>;
+ };
+
utmi_p1_gfclk: utmi_p1_gfclk@1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1262,6 +1703,13 @@
reg = <0x1358>;
};
+ usb_host_hs_mod_ck: usb_host_hs_mod_ck@1358 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1358>;
+ clocks = <&usb_host_hs_fck>;
+ };
+
utmi_p2_gfclk: utmi_p2_gfclk@1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1342,6 +1790,13 @@
reg = <0x1360>;
};
+ usb_otg_hs_mod_ck: usb_otg_hs_mod_ck@1360 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1360>;
+ clocks = <&usb_otg_hs_ick>;
+ };
+
usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1366,6 +1821,139 @@
reg = <0x0640>;
};
+ l3_main_1_mod_ck: l3_main_1_mod_ck@720 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0720>;
+ clocks = <&l3_div_ck>;
+ };
+
+ l3_main_2_mod_ck: l3_main_2_mod_ck@820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0820>;
+ clocks = <&l3_div_ck>;
+ };
+
+ gpmc_mod_ck: gpmc_mod_ck@828 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0828>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ocmc_ram_mod_ck: ocmc_ram_mod_ck@830 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0830>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ipu_mod_ck: ipu_mod_ck@920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
+ mmu_ipu_mod_ck: mmu_ipu_mod_ck@920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
+ dma_system_mod_ck: dma_system_mod_ck@a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0a20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ dmm_mod_ck: dmm_mod_ck@b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0b20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ emif1_mod_ck: emif1_mod_ck@b30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b30>;
+ clocks = <&ddrphy_ck>;
+ };
+
+ emif2_mod_ck: emif2_mod_ck@b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b38>;
+ clocks = <&ddrphy_ck>;
+ };
+
+ c2c_mod_ck: c2c_mod_ck@c20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0c20>;
+ clocks = <&div_core_ck>;
+ };
+
+ l4_cfg_mod_ck: l4_cfg_mod_ck@d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d20>;
+ clocks = <&l4_div_ck>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck@d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d28>;
+ clocks = <&l4_div_ck>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck@d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d30>;
+ clocks = <&l4_div_ck>;
+ };
+
+ l3_main_3_mod_ck: l3_main_3_mod_ck@e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck@e28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e28>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ocp_wp_noc_mod_ck: ocp_wp_noc_mod_ck@e40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e40>;
+ clocks = <&l3_div_ck>;
+ };
+
+ iva_mod_ck: iva_mod_ck@f20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0f20>;
+ clocks = <&dpll_iva_m5x2_ck>;
+ };
+
+ sl2if_mod_ck: sl2if_mod_ck@f28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0f28>;
+ clocks = <&dpll_iva_m5x2_ck>;
+ };
+
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1397,12 +1985,110 @@
ti,bit-shift = <0>;
reg = <0x1368>;
};
+
+ usb_tll_hs_mod_ck: usb_tll_hs_mod_ck@1368 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1368>;
+ clocks = <&usb_tll_hs_ick>;
+ };
};
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+ clocks = <&mmc2_mod_ck>, <&usb_otg_hs_mod_ck>,
+ <&usb_host_fs_mod_ck>, <&usb_tll_hs_mod_ck>,
+ <&usb_host_hs_mod_ck>, <&mmc1_mod_ck>, <&hsi_mod_ck>,
+ <&ocp2scp_usb_phy_mod_ck>, <&dpll_usb_ck>,
+ <&usb_host_fs_fck>;
+ };
+
+ l3_gfx_clkdm: l3_gfx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpu_mod_ck>;
+ };
+
+ l4_per_clkdm: l4_per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l4_per_mod_ck>, <&uart2_mod_ck>, <&uart1_mod_ck>,
+ <&timer10_mod_ck>, <&gpio2_mod_ck>, <&mcspi3_mod_ck>,
+ <&uart4_mod_ck>, <&gpio5_mod_ck>, <&hdq1w_mod_ck>,
+ <&mcbsp4_mod_ck>, <&i2c1_mod_ck>, <&i2c3_mod_ck>,
+ <&mcspi2_mod_ck>, <&timer9_mod_ck>, <&i2c4_mod_ck>,
+ <&timer2_mod_ck>, <&timer4_mod_ck>, <&mcspi4_mod_ck>,
+ <&timer11_mod_ck>, <&mcspi1_mod_ck>, <&timer3_mod_ck>,
+ <&mmc3_mod_ck>, <&mmc5_mod_ck>, <&gpio4_mod_ck>,
+ <&gpio6_mod_ck>, <&uart3_mod_ck>, <&slimbus2_mod_ck>,
+ <&gpio3_mod_ck>, <&i2c2_mod_ck>, <&mmc4_mod_ck>,
+ <&elm_mod_ck>;
+ };
+
+ ivahd_clkdm: ivahd_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sl2if_mod_ck>, <&iva_mod_ck>;
+ };
+
+ l4_cfg_clkdm: l4_cfg_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&spinlock_mod_ck>, <&mailbox_mod_ck>,
+ <&l4_cfg_mod_ck>;
+ };
+
+ l3_instr_clkdm: l3_instr_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ocp_wp_noc_mod_ck>, <&l3_main_3_mod_ck>,
+ <&l3_instr_mod_ck>;
+ };
+
+ iss_clkdm: iss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&fdif_mod_ck>, <&iss_mod_ck>;
+ };
+
+ l3_emif_clkdm: l3_emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif2_mod_ck>, <&emif1_mod_ck>, <&dmm_mod_ck>;
+ };
+
+ ducati_clkdm: ducati_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ipu_mod_ck>, <&mmu_ipu_mod_ck>;
+ };
+
+ l3_dma_clkdm: l3_dma_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dma_system_mod_ck>;
+ };
+
+ l3_2_clkdm: l3_2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpmc_mod_ck>, <&l3_main_2_mod_ck>,
+ <&ocmc_ram_mod_ck>;
+ };
+
+ l3_dss_clkdm: l3_dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_venc_mod_ck>, <&dss_hdmi_mod_ck>,
+ <&dss_dsi2_mod_ck>, <&dss_core_mod_ck>,
+ <&dss_dsi1_mod_ck>, <&dss_rfbi_mod_ck>,
+ <&dss_dispc_mod_ck>;
+ };
+
+ l4_ao_clkdm: l4_ao_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&smartreflex_core_mod_ck>, <&smartreflex_mpu_mod_ck>,
+ <&smartreflex_iva_mod_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&c2c_mod_ck>;
+ };
+
+ l3_1_clkdm: l3_1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_1_mod_ck>;
};
};
@@ -1641,3 +2327,24 @@
reg = <0x0224>;
};
};
+
+&cm1_clockdomains {
+ mpuss_clkdm: mpuss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ tesla_clkdm: tesla_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_dsp_mod_ck>, <&dsp_mod_ck>;
+ };
+
+ abe_clkdm: abe_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mcpdm_mod_ck>, <&l4_abe_mod_ck>, <&wd_timer3_mod_ck>,
+ <&timer7_mod_ck>, <&timer5_mod_ck>, <&mcbsp3_mod_ck>,
+ <&mcbsp2_mod_ck>, <&timer6_mod_ck>, <&mcbsp1_mod_ck>,
+ <&timer8_mod_ck>, <&mcasp_mod_ck>, <&dmic_mod_ck>,
+ <&aess_mod_ck>, <&slimbus1_mod_ck>;
+ };
+};
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 24/28] ARM: dts: omap4: add hwmod module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap44xx-clocks.dtsi | 853 +++++++++++++++++++++++++++++---
1 file changed, 780 insertions(+), 73 deletions(-)
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37..ac6171c 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -183,6 +183,20 @@
reg = <0x0528>;
};
+ aess_mod_ck: aess_mod_ck at 528 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0528>;
+ clocks = <&aess_fclk>;
+ };
+
+ mcpdm_mod_ck: mcpdm_mod_ck at 530 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -194,6 +208,34 @@
ti,invert-autoidle-bit;
};
+ mpu_mod_ck: mpu_mod_ck at 320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck at 420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ dsp_mod_ck: dsp_mod_ck at 420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck at 520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&ocp_abe_iclk>;
+ };
+
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck at 12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -480,6 +522,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck at 538 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&func_dmic_abe_gfclk>;
+ };
+
func_dmic_abe_gfclk: func_dmic_abe_gfclk at 538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -496,6 +545,13 @@
reg = <0x0540>;
};
+ mcasp_mod_ck: mcasp_mod_ck at 540 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0540>;
+ clocks = <&func_mcasp_abe_gfclk>;
+ };
+
func_mcasp_abe_gfclk: func_mcasp_abe_gfclk at 540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -520,6 +576,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck at 548 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&func_mcbsp1_gfclk>;
+ };
+
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -536,6 +599,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck at 550 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&func_mcbsp2_gfclk>;
+ };
+
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -552,6 +622,13 @@
reg = <0x0558>;
};
+ mcbsp3_mod_ck: mcbsp3_mod_ck at 558 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&func_mcbsp3_gfclk>;
+ };
+
slimbus1_fclk_1: slimbus1_fclk_1 at 560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -568,52 +645,66 @@
reg = <0x0560>;
};
- slimbus1_fclk_2: slimbus1_fclk_2 at 560 {
+ slimbus1_mod_ck: slimbus1_mod_ck at 560 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_ck>;
- ti,bit-shift = <10>;
+ compatible = "ti,omap4-sw-mod-clock";
reg = <0x0560>;
+ clocks = <&slimbus1_fclk_0>;
};
- slimbus1_slimbus_clk: slimbus1_slimbus_clk at 560 {
+ timer5_mod_ck: timer5_mod_ck at 568 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0568>, <0x0568>;
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
};
- timer5_sync_mux: timer5_sync_mux at 568 {
+ timer6_mod_ck: timer6_mod_ck at 570 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>, <0x0570>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0568>;
};
- timer6_sync_mux: timer6_sync_mux at 570 {
+ timer7_mod_ck: timer7_mod_ck at 578 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0578>, <0x0578>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0570>;
};
- timer7_sync_mux: timer7_sync_mux at 578 {
+ timer8_mod_ck: timer8_mod_ck at 580 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0580>, <0x0580>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0578>;
};
- timer8_sync_mux: timer8_sync_mux at 580 {
+ wd_timer3_mod_ck: wd_timer3_mod_ck at 588 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0588>;
+ clocks = <&sys_32k_ck>;
+ };
+
+ slimbus1_fclk_2: slimbus1_fclk_2 at 560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0560>;
+ };
+
+ slimbus1_slimbus_clk: slimbus1_slimbus_clk at 560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x0560>;
};
dummy_ck: dummy_ck {
@@ -631,6 +722,20 @@
ti,index-starts-at-one;
};
+ l4_wkup_mod_ck: l4_wkup_mod_ck at 1820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1820>;
+ clocks = <&l4_wkup_clk_mux_ck>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck at 1830 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1830>;
+ clocks = <&sys_32k_ck>;
+ };
+
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -677,12 +782,26 @@
reg = <0x1838>;
};
- dmt1_clk_mux: dmt1_clk_mux at 1840 {
+ gpio1_mod_ck: gpio1_mod_ck at 1838 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1838>;
+ clocks = <&l4_wkup_clk_mux_ck>;
+ };
+
+ timer1_mod_ck: timer1_mod_ck at 1840 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1840>, <0x1840>;
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x1840>;
+ };
+
+ counter_32k_mod_ck: counter_32k_mod_ck at 1850 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1850>;
+ clocks = <&sys_32k_ck>;
};
usim_ck: usim_ck at 1858 {
@@ -694,6 +813,13 @@
ti,dividers = <14>, <18>;
};
+ kbd_mod_ck: kbd_mod_ck at 1878 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1878>;
+ clocks = <&sys_32k_ck>;
+ };
+
usim_fclk: usim_fclk at 1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -737,6 +863,13 @@
ti,dividers = <0>, <1>, <2>, <0>, <4>;
};
+ debugss_mod_ck: debugss_mod_ck at 1a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1a20>;
+ clocks = <&trace_clk_div_ck>;
+ };
+
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
@@ -747,7 +880,14 @@
&prm_clockdomains {
emu_sys_clkdm: emu_sys_clkdm {
compatible = "ti,clockdomain";
- clocks = <&trace_clk_div_ck>;
+ clocks = <&debugss_mod_ck>, <&trace_clk_div_ck>;
+ };
+
+ l4_wkup_clkdm: l4_wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&timer1_mod_ck>, <&l4_wkup_mod_ck>, <&gpio1_mod_ck>,
+ <&wd_timer2_mod_ck>, <&counter_32k_mod_ck>,
+ <&kbd_mod_ck>;
};
};
@@ -993,6 +1133,55 @@
reg = <0x1120>;
};
+ dss_venc_mod_ck: dss_venc_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_tv_clk>;
+ };
+
+ dss_dispc_mod_ck: dss_dispc_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi1_mod_ck: dss_dsi1_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi2_mod_ck: dss_dsi2_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_hdmi_mod_ck: dss_hdmi_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_48mhz_clk>;
+ };
+
dss_tv_clk: dss_tv_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1028,6 +1217,13 @@
ti,index-power-of-two;
};
+ fdif_mod_ck: fdif_mod_ck at 1028 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1028>;
+ clocks = <&fdif_fck>;
+ };
+
gpio2_dbclk: gpio2_dbclk at 1460 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1036,6 +1232,13 @@
reg = <0x1460>;
};
+ gpio2_mod_ck: gpio2_mod_ck at 1460 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1460>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio3_dbclk: gpio3_dbclk at 1468 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1044,6 +1247,13 @@
reg = <0x1468>;
};
+ gpio3_mod_ck: gpio3_mod_ck at 1468 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1468>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio4_dbclk: gpio4_dbclk at 1470 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1052,6 +1262,13 @@
reg = <0x1470>;
};
+ gpio4_mod_ck: gpio4_mod_ck at 1470 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1470>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio5_dbclk: gpio5_dbclk at 1478 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1060,6 +1277,13 @@
reg = <0x1478>;
};
+ gpio5_mod_ck: gpio5_mod_ck at 1478 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1478>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio6_dbclk: gpio6_dbclk at 1480 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1068,6 +1292,55 @@
reg = <0x1480>;
};
+ gpio6_mod_ck: gpio6_mod_ck at 1480 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1480>;
+ clocks = <&l4_div_ck>;
+ };
+
+ hdq1w_mod_ck: hdq1w_mod_ck at 1488 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1488>;
+ clocks = <&func_12m_fclk>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck at 14a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck at 14a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck at 14b0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14b0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c4_mod_ck: i2c4_mod_ck at 14b8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14b8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ l4_per_mod_ck: l4_per_mod_ck at 14c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x14c0>;
+ clocks = <&l4_div_ck>;
+ };
+
sgx_clk_mux: sgx_clk_mux at 1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1076,6 +1349,13 @@
reg = <0x1220>;
};
+ gpu_mod_ck: gpu_mod_ck at 1220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1220>;
+ clocks = <&sgx_clk_mux>;
+ };
+
hsi_fck: hsi_fck at 1338 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1086,6 +1366,13 @@
ti,index-power-of-two;
};
+ hsi_mod_ck: hsi_mod_ck at 1338 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1338>;
+ clocks = <&hsi_fck>;
+ };
+
iss_ctrlclk: iss_ctrlclk at 1020 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1094,6 +1381,13 @@
reg = <0x1020>;
};
+ iss_mod_ck: iss_mod_ck at 1020 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1020>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck at 14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1102,6 +1396,55 @@
reg = <0x14e0>;
};
+ mcbsp4_mod_ck: mcbsp4_mod_ck at 14e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14e0>;
+ clocks = <&per_mcbsp4_gfclk>;
+ };
+
+ mcspi1_mod_ck: mcspi1_mod_ck at 14f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14f0>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi2_mod_ck: mcspi2_mod_ck at 14f8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14f8>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi3_mod_ck: mcspi3_mod_ck at 1500 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1500>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi4_mod_ck: mcspi4_mod_ck at 1508 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1508>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck at 1520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1520>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc4_mod_ck: mmc4_mod_ck at 1528 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1528>;
+ clocks = <&func_48m_fclk>;
+ };
+
per_mcbsp4_gfclk: per_mcbsp4_gfclk at 14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1118,6 +1461,13 @@
reg = <0x1328>;
};
+ mmc1_mod_ck: mmc1_mod_ck at 1328 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1328>;
+ clocks = <&hsmmc1_fclk>;
+ };
+
hsmmc2_fclk: hsmmc2_fclk at 1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1126,6 +1476,13 @@
reg = <0x1330>;
};
+ mmc2_mod_ck: mmc2_mod_ck at 1330 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1330>;
+ clocks = <&hsmmc2_fclk>;
+ };
+
ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 13e0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1134,6 +1491,68 @@
reg = <0x13e0>;
};
+ ocp2scp_usb_phy_mod_ck: ocp2scp_usb_phy_mod_ck at 13e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x13e0>;
+ clocks = <&ocp2scp_usb_phy_phy_48m>;
+ };
+
+ timer10_mod_ck: timer10_mod_ck at 1428 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1428>, <0x1428>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck at 1430 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1430>, <0x1430>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck at 1438 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1438>, <0x1438>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck at 1440 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1440>, <0x1440>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck at 1448 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1448>, <0x1448>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck at 1450 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1450>, <0x1450>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ elm_mod_ck: elm_mod_ck at 1458 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1458>;
+ clocks = <&l4_div_ck>;
+ };
+
sha2md5_fck: sha2md5_fck at 15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1166,76 +1585,91 @@
reg = <0x1538>;
};
- smartreflex_core_fck: smartreflex_core_fck at 638 {
+ slimbus2_mod_ck: slimbus2_mod_ck at 1538 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0638>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1538>;
+ clocks = <&slimbus2_fclk_0>;
};
- smartreflex_iva_fck: smartreflex_iva_fck at 630 {
+ uart1_mod_ck: uart1_mod_ck at 1540 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0630>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1540>;
+ clocks = <&func_48m_fclk>;
};
- smartreflex_mpu_fck: smartreflex_mpu_fck at 628 {
+ uart2_mod_ck: uart2_mod_ck at 1548 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0628>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1548>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm10_mux: cm2_dm10_mux at 1428 {
+ uart3_mod_ck: uart3_mod_ck at 1550 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1428>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1550>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm11_mux: cm2_dm11_mux at 1430 {
+ uart4_mod_ck: uart4_mod_ck at 1558 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1430>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1558>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm2_mux: cm2_dm2_mux at 1438 {
+ mmc5_mod_ck: mmc5_mod_ck at 1560 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1438>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1560>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm3_mux: cm2_dm3_mux at 1440 {
+ smartreflex_core_fck: smartreflex_core_fck at 638 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1440>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0638>;
};
- cm2_dm4_mux: cm2_dm4_mux at 1448 {
+ smartreflex_core_mod_ck: smartreflex_core_mod_ck at 638 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1448>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0638>;
+ clocks = <&smartreflex_core_fck>;
};
- cm2_dm9_mux: cm2_dm9_mux at 1450 {
+ smartreflex_iva_fck: smartreflex_iva_fck at 630 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1450>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0630>;
+ };
+
+ smartreflex_iva_mod_ck: smartreflex_iva_mod_ck at 630 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0630>;
+ clocks = <&smartreflex_iva_fck>;
+ };
+
+ smartreflex_mpu_fck: smartreflex_mpu_fck at 628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0628>;
+ };
+
+ smartreflex_mpu_mod_ck: smartreflex_mpu_mod_ck at 628 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0628>;
+ clocks = <&smartreflex_mpu_fck>;
};
usb_host_fs_fck: usb_host_fs_fck at 13d0 {
@@ -1246,6 +1680,13 @@
reg = <0x13d0>;
};
+ usb_host_fs_mod_ck: usb_host_fs_mod_ck at 13d0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x13d0>;
+ clocks = <&usb_host_fs_fck>;
+ };
+
utmi_p1_gfclk: utmi_p1_gfclk at 1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1262,6 +1703,13 @@
reg = <0x1358>;
};
+ usb_host_hs_mod_ck: usb_host_hs_mod_ck at 1358 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1358>;
+ clocks = <&usb_host_hs_fck>;
+ };
+
utmi_p2_gfclk: utmi_p2_gfclk at 1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1342,6 +1790,13 @@
reg = <0x1360>;
};
+ usb_otg_hs_mod_ck: usb_otg_hs_mod_ck at 1360 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1360>;
+ clocks = <&usb_otg_hs_ick>;
+ };
+
usb_otg_hs_xclk: usb_otg_hs_xclk at 1360 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1366,6 +1821,139 @@
reg = <0x0640>;
};
+ l3_main_1_mod_ck: l3_main_1_mod_ck at 720 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0720>;
+ clocks = <&l3_div_ck>;
+ };
+
+ l3_main_2_mod_ck: l3_main_2_mod_ck at 820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0820>;
+ clocks = <&l3_div_ck>;
+ };
+
+ gpmc_mod_ck: gpmc_mod_ck at 828 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0828>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ocmc_ram_mod_ck: ocmc_ram_mod_ck at 830 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0830>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ipu_mod_ck: ipu_mod_ck at 920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
+ mmu_ipu_mod_ck: mmu_ipu_mod_ck at 920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
+ dma_system_mod_ck: dma_system_mod_ck at a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0a20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ dmm_mod_ck: dmm_mod_ck at b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0b20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ emif1_mod_ck: emif1_mod_ck at b30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b30>;
+ clocks = <&ddrphy_ck>;
+ };
+
+ emif2_mod_ck: emif2_mod_ck at b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b38>;
+ clocks = <&ddrphy_ck>;
+ };
+
+ c2c_mod_ck: c2c_mod_ck at c20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0c20>;
+ clocks = <&div_core_ck>;
+ };
+
+ l4_cfg_mod_ck: l4_cfg_mod_ck at d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d20>;
+ clocks = <&l4_div_ck>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck at d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d28>;
+ clocks = <&l4_div_ck>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck at d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d30>;
+ clocks = <&l4_div_ck>;
+ };
+
+ l3_main_3_mod_ck: l3_main_3_mod_ck at e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck at e28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e28>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ocp_wp_noc_mod_ck: ocp_wp_noc_mod_ck at e40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e40>;
+ clocks = <&l3_div_ck>;
+ };
+
+ iva_mod_ck: iva_mod_ck at f20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0f20>;
+ clocks = <&dpll_iva_m5x2_ck>;
+ };
+
+ sl2if_mod_ck: sl2if_mod_ck at f28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0f28>;
+ clocks = <&dpll_iva_m5x2_ck>;
+ };
+
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1397,12 +1985,110 @@
ti,bit-shift = <0>;
reg = <0x1368>;
};
+
+ usb_tll_hs_mod_ck: usb_tll_hs_mod_ck at 1368 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1368>;
+ clocks = <&usb_tll_hs_ick>;
+ };
};
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+ clocks = <&mmc2_mod_ck>, <&usb_otg_hs_mod_ck>,
+ <&usb_host_fs_mod_ck>, <&usb_tll_hs_mod_ck>,
+ <&usb_host_hs_mod_ck>, <&mmc1_mod_ck>, <&hsi_mod_ck>,
+ <&ocp2scp_usb_phy_mod_ck>, <&dpll_usb_ck>,
+ <&usb_host_fs_fck>;
+ };
+
+ l3_gfx_clkdm: l3_gfx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpu_mod_ck>;
+ };
+
+ l4_per_clkdm: l4_per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l4_per_mod_ck>, <&uart2_mod_ck>, <&uart1_mod_ck>,
+ <&timer10_mod_ck>, <&gpio2_mod_ck>, <&mcspi3_mod_ck>,
+ <&uart4_mod_ck>, <&gpio5_mod_ck>, <&hdq1w_mod_ck>,
+ <&mcbsp4_mod_ck>, <&i2c1_mod_ck>, <&i2c3_mod_ck>,
+ <&mcspi2_mod_ck>, <&timer9_mod_ck>, <&i2c4_mod_ck>,
+ <&timer2_mod_ck>, <&timer4_mod_ck>, <&mcspi4_mod_ck>,
+ <&timer11_mod_ck>, <&mcspi1_mod_ck>, <&timer3_mod_ck>,
+ <&mmc3_mod_ck>, <&mmc5_mod_ck>, <&gpio4_mod_ck>,
+ <&gpio6_mod_ck>, <&uart3_mod_ck>, <&slimbus2_mod_ck>,
+ <&gpio3_mod_ck>, <&i2c2_mod_ck>, <&mmc4_mod_ck>,
+ <&elm_mod_ck>;
+ };
+
+ ivahd_clkdm: ivahd_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sl2if_mod_ck>, <&iva_mod_ck>;
+ };
+
+ l4_cfg_clkdm: l4_cfg_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&spinlock_mod_ck>, <&mailbox_mod_ck>,
+ <&l4_cfg_mod_ck>;
+ };
+
+ l3_instr_clkdm: l3_instr_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ocp_wp_noc_mod_ck>, <&l3_main_3_mod_ck>,
+ <&l3_instr_mod_ck>;
+ };
+
+ iss_clkdm: iss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&fdif_mod_ck>, <&iss_mod_ck>;
+ };
+
+ l3_emif_clkdm: l3_emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif2_mod_ck>, <&emif1_mod_ck>, <&dmm_mod_ck>;
+ };
+
+ ducati_clkdm: ducati_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ipu_mod_ck>, <&mmu_ipu_mod_ck>;
+ };
+
+ l3_dma_clkdm: l3_dma_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dma_system_mod_ck>;
+ };
+
+ l3_2_clkdm: l3_2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpmc_mod_ck>, <&l3_main_2_mod_ck>,
+ <&ocmc_ram_mod_ck>;
+ };
+
+ l3_dss_clkdm: l3_dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_venc_mod_ck>, <&dss_hdmi_mod_ck>,
+ <&dss_dsi2_mod_ck>, <&dss_core_mod_ck>,
+ <&dss_dsi1_mod_ck>, <&dss_rfbi_mod_ck>,
+ <&dss_dispc_mod_ck>;
+ };
+
+ l4_ao_clkdm: l4_ao_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&smartreflex_core_mod_ck>, <&smartreflex_mpu_mod_ck>,
+ <&smartreflex_iva_mod_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&c2c_mod_ck>;
+ };
+
+ l3_1_clkdm: l3_1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_1_mod_ck>;
};
};
@@ -1641,3 +2327,24 @@
reg = <0x0224>;
};
};
+
+&cm1_clockdomains {
+ mpuss_clkdm: mpuss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ tesla_clkdm: tesla_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_dsp_mod_ck>, <&dsp_mod_ck>;
+ };
+
+ abe_clkdm: abe_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mcpdm_mod_ck>, <&l4_abe_mod_ck>, <&wd_timer3_mod_ck>,
+ <&timer7_mod_ck>, <&timer5_mod_ck>, <&mcbsp3_mod_ck>,
+ <&mcbsp2_mod_ck>, <&timer6_mod_ck>, <&mcbsp1_mod_ck>,
+ <&timer8_mod_ck>, <&mcasp_mod_ck>, <&dmic_mod_ck>,
+ <&aess_mod_ck>, <&slimbus1_mod_ck>;
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 24/28] ARM: dts: omap4: add hwmod module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap44xx-clocks.dtsi | 853 +++++++++++++++++++++++++++++---
1 file changed, 780 insertions(+), 73 deletions(-)
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37..ac6171c 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -183,6 +183,20 @@
reg = <0x0528>;
};
+ aess_mod_ck: aess_mod_ck@528 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0528>;
+ clocks = <&aess_fclk>;
+ };
+
+ mcpdm_mod_ck: mcpdm_mod_ck@530 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -194,6 +208,34 @@
ti,invert-autoidle-bit;
};
+ mpu_mod_ck: mpu_mod_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck@420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ dsp_mod_ck: dsp_mod_ck@420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck@520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&ocp_abe_iclk>;
+ };
+
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -480,6 +522,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck@538 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&func_dmic_abe_gfclk>;
+ };
+
func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -496,6 +545,13 @@
reg = <0x0540>;
};
+ mcasp_mod_ck: mcasp_mod_ck@540 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0540>;
+ clocks = <&func_mcasp_abe_gfclk>;
+ };
+
func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -520,6 +576,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck@548 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&func_mcbsp1_gfclk>;
+ };
+
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -536,6 +599,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck@550 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&func_mcbsp2_gfclk>;
+ };
+
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -552,6 +622,13 @@
reg = <0x0558>;
};
+ mcbsp3_mod_ck: mcbsp3_mod_ck@558 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&func_mcbsp3_gfclk>;
+ };
+
slimbus1_fclk_1: slimbus1_fclk_1@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -568,52 +645,66 @@
reg = <0x0560>;
};
- slimbus1_fclk_2: slimbus1_fclk_2@560 {
+ slimbus1_mod_ck: slimbus1_mod_ck@560 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_ck>;
- ti,bit-shift = <10>;
+ compatible = "ti,omap4-sw-mod-clock";
reg = <0x0560>;
+ clocks = <&slimbus1_fclk_0>;
};
- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
+ timer5_mod_ck: timer5_mod_ck@568 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0568>, <0x0568>;
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
};
- timer5_sync_mux: timer5_sync_mux@568 {
+ timer6_mod_ck: timer6_mod_ck@570 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>, <0x0570>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0568>;
};
- timer6_sync_mux: timer6_sync_mux@570 {
+ timer7_mod_ck: timer7_mod_ck@578 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0578>, <0x0578>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0570>;
};
- timer7_sync_mux: timer7_sync_mux@578 {
+ timer8_mod_ck: timer8_mod_ck@580 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0580>, <0x0580>;
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x0578>;
};
- timer8_sync_mux: timer8_sync_mux@580 {
+ wd_timer3_mod_ck: wd_timer3_mod_ck@588 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0588>;
+ clocks = <&sys_32k_ck>;
+ };
+
+ slimbus1_fclk_2: slimbus1_fclk_2@560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&pad_clks_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x0560>;
+ };
+
+ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&slimbus_clk>;
+ ti,bit-shift = <11>;
+ reg = <0x0560>;
};
dummy_ck: dummy_ck {
@@ -631,6 +722,20 @@
ti,index-starts-at-one;
};
+ l4_wkup_mod_ck: l4_wkup_mod_ck@1820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1820>;
+ clocks = <&l4_wkup_clk_mux_ck>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck@1830 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1830>;
+ clocks = <&sys_32k_ck>;
+ };
+
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -677,12 +782,26 @@
reg = <0x1838>;
};
- dmt1_clk_mux: dmt1_clk_mux@1840 {
+ gpio1_mod_ck: gpio1_mod_ck@1838 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1838>;
+ clocks = <&l4_wkup_clk_mux_ck>;
+ };
+
+ timer1_mod_ck: timer1_mod_ck@1840 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1840>, <0x1840>;
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x1840>;
+ };
+
+ counter_32k_mod_ck: counter_32k_mod_ck@1850 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1850>;
+ clocks = <&sys_32k_ck>;
};
usim_ck: usim_ck@1858 {
@@ -694,6 +813,13 @@
ti,dividers = <14>, <18>;
};
+ kbd_mod_ck: kbd_mod_ck@1878 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1878>;
+ clocks = <&sys_32k_ck>;
+ };
+
usim_fclk: usim_fclk@1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -737,6 +863,13 @@
ti,dividers = <0>, <1>, <2>, <0>, <4>;
};
+ debugss_mod_ck: debugss_mod_ck@1a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1a20>;
+ clocks = <&trace_clk_div_ck>;
+ };
+
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
@@ -747,7 +880,14 @@
&prm_clockdomains {
emu_sys_clkdm: emu_sys_clkdm {
compatible = "ti,clockdomain";
- clocks = <&trace_clk_div_ck>;
+ clocks = <&debugss_mod_ck>, <&trace_clk_div_ck>;
+ };
+
+ l4_wkup_clkdm: l4_wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&timer1_mod_ck>, <&l4_wkup_mod_ck>, <&gpio1_mod_ck>,
+ <&wd_timer2_mod_ck>, <&counter_32k_mod_ck>,
+ <&kbd_mod_ck>;
};
};
@@ -993,6 +1133,55 @@
reg = <0x1120>;
};
+ dss_venc_mod_ck: dss_venc_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_tv_clk>;
+ };
+
+ dss_dispc_mod_ck: dss_dispc_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi1_mod_ck: dss_dsi1_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi2_mod_ck: dss_dsi2_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_hdmi_mod_ck: dss_hdmi_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1120>;
+ clocks = <&dss_48mhz_clk>;
+ };
+
dss_tv_clk: dss_tv_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1028,6 +1217,13 @@
ti,index-power-of-two;
};
+ fdif_mod_ck: fdif_mod_ck@1028 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1028>;
+ clocks = <&fdif_fck>;
+ };
+
gpio2_dbclk: gpio2_dbclk@1460 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1036,6 +1232,13 @@
reg = <0x1460>;
};
+ gpio2_mod_ck: gpio2_mod_ck@1460 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1460>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio3_dbclk: gpio3_dbclk@1468 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1044,6 +1247,13 @@
reg = <0x1468>;
};
+ gpio3_mod_ck: gpio3_mod_ck@1468 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1468>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio4_dbclk: gpio4_dbclk@1470 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1052,6 +1262,13 @@
reg = <0x1470>;
};
+ gpio4_mod_ck: gpio4_mod_ck@1470 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1470>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio5_dbclk: gpio5_dbclk@1478 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1060,6 +1277,13 @@
reg = <0x1478>;
};
+ gpio5_mod_ck: gpio5_mod_ck@1478 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1478>;
+ clocks = <&l4_div_ck>;
+ };
+
gpio6_dbclk: gpio6_dbclk@1480 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1068,6 +1292,55 @@
reg = <0x1480>;
};
+ gpio6_mod_ck: gpio6_mod_ck@1480 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1480>;
+ clocks = <&l4_div_ck>;
+ };
+
+ hdq1w_mod_ck: hdq1w_mod_ck@1488 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1488>;
+ clocks = <&func_12m_fclk>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck@14a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck@14a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck@14b0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14b0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c4_mod_ck: i2c4_mod_ck@14b8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14b8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ l4_per_mod_ck: l4_per_mod_ck@14c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x14c0>;
+ clocks = <&l4_div_ck>;
+ };
+
sgx_clk_mux: sgx_clk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1076,6 +1349,13 @@
reg = <0x1220>;
};
+ gpu_mod_ck: gpu_mod_ck@1220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1220>;
+ clocks = <&sgx_clk_mux>;
+ };
+
hsi_fck: hsi_fck@1338 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1086,6 +1366,13 @@
ti,index-power-of-two;
};
+ hsi_mod_ck: hsi_mod_ck@1338 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1338>;
+ clocks = <&hsi_fck>;
+ };
+
iss_ctrlclk: iss_ctrlclk@1020 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1094,6 +1381,13 @@
reg = <0x1020>;
};
+ iss_mod_ck: iss_mod_ck@1020 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1020>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1102,6 +1396,55 @@
reg = <0x14e0>;
};
+ mcbsp4_mod_ck: mcbsp4_mod_ck@14e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14e0>;
+ clocks = <&per_mcbsp4_gfclk>;
+ };
+
+ mcspi1_mod_ck: mcspi1_mod_ck@14f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14f0>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi2_mod_ck: mcspi2_mod_ck@14f8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14f8>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi3_mod_ck: mcspi3_mod_ck@1500 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1500>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi4_mod_ck: mcspi4_mod_ck@1508 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1508>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck@1520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1520>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc4_mod_ck: mmc4_mod_ck@1528 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1528>;
+ clocks = <&func_48m_fclk>;
+ };
+
per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1118,6 +1461,13 @@
reg = <0x1328>;
};
+ mmc1_mod_ck: mmc1_mod_ck@1328 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1328>;
+ clocks = <&hsmmc1_fclk>;
+ };
+
hsmmc2_fclk: hsmmc2_fclk@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1126,6 +1476,13 @@
reg = <0x1330>;
};
+ mmc2_mod_ck: mmc2_mod_ck@1330 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1330>;
+ clocks = <&hsmmc2_fclk>;
+ };
+
ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1134,6 +1491,68 @@
reg = <0x13e0>;
};
+ ocp2scp_usb_phy_mod_ck: ocp2scp_usb_phy_mod_ck@13e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x13e0>;
+ clocks = <&ocp2scp_usb_phy_phy_48m>;
+ };
+
+ timer10_mod_ck: timer10_mod_ck@1428 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1428>, <0x1428>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck@1430 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1430>, <0x1430>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck@1438 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1438>, <0x1438>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck@1440 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1440>, <0x1440>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck@1448 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1448>, <0x1448>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck@1450 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1450>, <0x1450>;
+ clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ elm_mod_ck: elm_mod_ck@1458 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1458>;
+ clocks = <&l4_div_ck>;
+ };
+
sha2md5_fck: sha2md5_fck@15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1166,76 +1585,91 @@
reg = <0x1538>;
};
- smartreflex_core_fck: smartreflex_core_fck@638 {
+ slimbus2_mod_ck: slimbus2_mod_ck@1538 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0638>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1538>;
+ clocks = <&slimbus2_fclk_0>;
};
- smartreflex_iva_fck: smartreflex_iva_fck@630 {
+ uart1_mod_ck: uart1_mod_ck@1540 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0630>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1540>;
+ clocks = <&func_48m_fclk>;
};
- smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
+ uart2_mod_ck: uart2_mod_ck@1548 {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0628>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1548>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm10_mux: cm2_dm10_mux@1428 {
+ uart3_mod_ck: uart3_mod_ck@1550 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1428>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1550>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm11_mux: cm2_dm11_mux@1430 {
+ uart4_mod_ck: uart4_mod_ck@1558 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1430>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1558>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm2_mux: cm2_dm2_mux@1438 {
+ mmc5_mod_ck: mmc5_mod_ck@1560 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1438>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1560>;
+ clocks = <&func_48m_fclk>;
};
- cm2_dm3_mux: cm2_dm3_mux@1440 {
+ smartreflex_core_fck: smartreflex_core_fck@638 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1440>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0638>;
};
- cm2_dm4_mux: cm2_dm4_mux@1448 {
+ smartreflex_core_mod_ck: smartreflex_core_mod_ck@638 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1448>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0638>;
+ clocks = <&smartreflex_core_fck>;
};
- cm2_dm9_mux: cm2_dm9_mux@1450 {
+ smartreflex_iva_fck: smartreflex_iva_fck@630 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1450>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0630>;
+ };
+
+ smartreflex_iva_mod_ck: smartreflex_iva_mod_ck@630 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0630>;
+ clocks = <&smartreflex_iva_fck>;
+ };
+
+ smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_wkup_clk_mux_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0628>;
+ };
+
+ smartreflex_mpu_mod_ck: smartreflex_mpu_mod_ck@628 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0628>;
+ clocks = <&smartreflex_mpu_fck>;
};
usb_host_fs_fck: usb_host_fs_fck@13d0 {
@@ -1246,6 +1680,13 @@
reg = <0x13d0>;
};
+ usb_host_fs_mod_ck: usb_host_fs_mod_ck@13d0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x13d0>;
+ clocks = <&usb_host_fs_fck>;
+ };
+
utmi_p1_gfclk: utmi_p1_gfclk@1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1262,6 +1703,13 @@
reg = <0x1358>;
};
+ usb_host_hs_mod_ck: usb_host_hs_mod_ck@1358 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1358>;
+ clocks = <&usb_host_hs_fck>;
+ };
+
utmi_p2_gfclk: utmi_p2_gfclk@1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1342,6 +1790,13 @@
reg = <0x1360>;
};
+ usb_otg_hs_mod_ck: usb_otg_hs_mod_ck@1360 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1360>;
+ clocks = <&usb_otg_hs_ick>;
+ };
+
usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1366,6 +1821,139 @@
reg = <0x0640>;
};
+ l3_main_1_mod_ck: l3_main_1_mod_ck@720 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0720>;
+ clocks = <&l3_div_ck>;
+ };
+
+ l3_main_2_mod_ck: l3_main_2_mod_ck@820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0820>;
+ clocks = <&l3_div_ck>;
+ };
+
+ gpmc_mod_ck: gpmc_mod_ck@828 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0828>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ocmc_ram_mod_ck: ocmc_ram_mod_ck@830 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0830>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ipu_mod_ck: ipu_mod_ck@920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
+ mmu_ipu_mod_ck: mmu_ipu_mod_ck@920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&ducati_clk_mux_ck>;
+ };
+
+ dma_system_mod_ck: dma_system_mod_ck@a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0a20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ dmm_mod_ck: dmm_mod_ck@b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0b20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ emif1_mod_ck: emif1_mod_ck@b30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b30>;
+ clocks = <&ddrphy_ck>;
+ };
+
+ emif2_mod_ck: emif2_mod_ck@b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b38>;
+ clocks = <&ddrphy_ck>;
+ };
+
+ c2c_mod_ck: c2c_mod_ck@c20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0c20>;
+ clocks = <&div_core_ck>;
+ };
+
+ l4_cfg_mod_ck: l4_cfg_mod_ck@d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d20>;
+ clocks = <&l4_div_ck>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck@d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d28>;
+ clocks = <&l4_div_ck>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck@d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d30>;
+ clocks = <&l4_div_ck>;
+ };
+
+ l3_main_3_mod_ck: l3_main_3_mod_ck@e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e20>;
+ clocks = <&l3_div_ck>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck@e28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e28>;
+ clocks = <&l3_div_ck>;
+ };
+
+ ocp_wp_noc_mod_ck: ocp_wp_noc_mod_ck@e40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e40>;
+ clocks = <&l3_div_ck>;
+ };
+
+ iva_mod_ck: iva_mod_ck@f20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0f20>;
+ clocks = <&dpll_iva_m5x2_ck>;
+ };
+
+ sl2if_mod_ck: sl2if_mod_ck@f28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0f28>;
+ clocks = <&dpll_iva_m5x2_ck>;
+ };
+
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1397,12 +1985,110 @@
ti,bit-shift = <0>;
reg = <0x1368>;
};
+
+ usb_tll_hs_mod_ck: usb_tll_hs_mod_ck@1368 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1368>;
+ clocks = <&usb_tll_hs_ick>;
+ };
};
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+ clocks = <&mmc2_mod_ck>, <&usb_otg_hs_mod_ck>,
+ <&usb_host_fs_mod_ck>, <&usb_tll_hs_mod_ck>,
+ <&usb_host_hs_mod_ck>, <&mmc1_mod_ck>, <&hsi_mod_ck>,
+ <&ocp2scp_usb_phy_mod_ck>, <&dpll_usb_ck>,
+ <&usb_host_fs_fck>;
+ };
+
+ l3_gfx_clkdm: l3_gfx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpu_mod_ck>;
+ };
+
+ l4_per_clkdm: l4_per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l4_per_mod_ck>, <&uart2_mod_ck>, <&uart1_mod_ck>,
+ <&timer10_mod_ck>, <&gpio2_mod_ck>, <&mcspi3_mod_ck>,
+ <&uart4_mod_ck>, <&gpio5_mod_ck>, <&hdq1w_mod_ck>,
+ <&mcbsp4_mod_ck>, <&i2c1_mod_ck>, <&i2c3_mod_ck>,
+ <&mcspi2_mod_ck>, <&timer9_mod_ck>, <&i2c4_mod_ck>,
+ <&timer2_mod_ck>, <&timer4_mod_ck>, <&mcspi4_mod_ck>,
+ <&timer11_mod_ck>, <&mcspi1_mod_ck>, <&timer3_mod_ck>,
+ <&mmc3_mod_ck>, <&mmc5_mod_ck>, <&gpio4_mod_ck>,
+ <&gpio6_mod_ck>, <&uart3_mod_ck>, <&slimbus2_mod_ck>,
+ <&gpio3_mod_ck>, <&i2c2_mod_ck>, <&mmc4_mod_ck>,
+ <&elm_mod_ck>;
+ };
+
+ ivahd_clkdm: ivahd_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sl2if_mod_ck>, <&iva_mod_ck>;
+ };
+
+ l4_cfg_clkdm: l4_cfg_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&spinlock_mod_ck>, <&mailbox_mod_ck>,
+ <&l4_cfg_mod_ck>;
+ };
+
+ l3_instr_clkdm: l3_instr_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ocp_wp_noc_mod_ck>, <&l3_main_3_mod_ck>,
+ <&l3_instr_mod_ck>;
+ };
+
+ iss_clkdm: iss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&fdif_mod_ck>, <&iss_mod_ck>;
+ };
+
+ l3_emif_clkdm: l3_emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif2_mod_ck>, <&emif1_mod_ck>, <&dmm_mod_ck>;
+ };
+
+ ducati_clkdm: ducati_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&ipu_mod_ck>, <&mmu_ipu_mod_ck>;
+ };
+
+ l3_dma_clkdm: l3_dma_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dma_system_mod_ck>;
+ };
+
+ l3_2_clkdm: l3_2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpmc_mod_ck>, <&l3_main_2_mod_ck>,
+ <&ocmc_ram_mod_ck>;
+ };
+
+ l3_dss_clkdm: l3_dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_venc_mod_ck>, <&dss_hdmi_mod_ck>,
+ <&dss_dsi2_mod_ck>, <&dss_core_mod_ck>,
+ <&dss_dsi1_mod_ck>, <&dss_rfbi_mod_ck>,
+ <&dss_dispc_mod_ck>;
+ };
+
+ l4_ao_clkdm: l4_ao_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&smartreflex_core_mod_ck>, <&smartreflex_mpu_mod_ck>,
+ <&smartreflex_iva_mod_ck>;
+ };
+
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&c2c_mod_ck>;
+ };
+
+ l3_1_clkdm: l3_1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_1_mod_ck>;
};
};
@@ -1641,3 +2327,24 @@
reg = <0x0224>;
};
};
+
+&cm1_clockdomains {
+ mpuss_clkdm: mpuss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ tesla_clkdm: tesla_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_dsp_mod_ck>, <&dsp_mod_ck>;
+ };
+
+ abe_clkdm: abe_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mcpdm_mod_ck>, <&l4_abe_mod_ck>, <&wd_timer3_mod_ck>,
+ <&timer7_mod_ck>, <&timer5_mod_ck>, <&mcbsp3_mod_ck>,
+ <&mcbsp2_mod_ck>, <&timer6_mod_ck>, <&mcbsp1_mod_ck>,
+ <&timer8_mod_ck>, <&mcasp_mod_ck>, <&dmic_mod_ck>,
+ <&aess_mod_ck>, <&slimbus1_mod_ck>;
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 26/28] ARM: dts: am43xx: add hwmod module clocks
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 747 ++++++++++++++++++++++++++++++----
1 file changed, 677 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 34fecf2..bc905036 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -383,55 +383,6 @@
clock-frequency = <32768>;
};
- timer1_fck: timer1_fck@4200 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
- reg = <0x4200>;
- };
-
- timer2_fck: timer2_fck@4204 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4204>;
- };
-
- timer3_fck: timer3_fck@4208 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4208>;
- };
-
- timer4_fck: timer4_fck@420c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x420c>;
- };
-
- timer5_fck: timer5_fck@4210 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4210>;
- };
-
- timer6_fck: timer6_fck@4214 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4214>;
- };
-
- timer7_fck: timer7_fck@4218 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4218>;
- };
-
wdt1_fck: wdt1_fck@422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -524,6 +475,13 @@
reg = <0x2b68>;
};
+ gpio1_mod_ck: gpio1_mod_ck@2b68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b68>;
+ clocks = <&sys_clkin_ck>;
+ };
+
gpio1_dbclk: gpio1_dbclk@8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -532,6 +490,13 @@
reg = <0x8c78>;
};
+ gpio2_mod_ck: gpio2_mod_ck@8c78 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c78>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio2_dbclk: gpio2_dbclk@8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -540,6 +505,13 @@
reg = <0x8c80>;
};
+ gpio3_mod_ck: gpio3_mod_ck@8c80 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c80>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio3_dbclk: gpio3_dbclk@8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -548,6 +520,13 @@
reg = <0x8c88>;
};
+ gpio4_mod_ck: gpio4_mod_ck@8c88 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c88>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio4_dbclk: gpio4_dbclk@8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -556,6 +535,13 @@
reg = <0x8c90>;
};
+ gpio5_mod_ck: gpio5_mod_ck@8c90 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c90>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio5_dbclk: gpio5_dbclk@8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -564,6 +550,255 @@
reg = <0x8c98>;
};
+ gpio6_mod_ck: gpio6_mod_ck@8c98 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c98>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ hdq1w_mod_ck: hdq1w_mod_ck@8ca0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8ca0>;
+ clocks = <&func_12m_clk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck@8ca8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8ca8>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck@8cb0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cb0>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck@8cb8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cb8>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ mmc1_mod_ck: mmc1_mod_ck@8cc0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cc0>;
+ clocks = <&mmc_clk>;
+ };
+
+ mmc2_mod_ck: mmc2_mod_ck@8cc8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cc8>;
+ clocks = <&mmc_clk>;
+ };
+
+ spi0_mod_ck: spi0_mod_ck@8d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d00>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi1_mod_ck: spi1_mod_ck@8d08 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d08>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi2_mod_ck: spi2_mod_ck@8d10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d10>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi3_mod_ck: spi3_mod_ck@8d18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d18>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi4_mod_ck: spi4_mod_ck@8d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d20>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck@8d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d28>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck@8d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d30>, <0x4204>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck@8d38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d38>, <0x4208>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck@8d40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d40>, <0x420c>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer5_mod_ck: timer5_mod_ck@8d48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d48>, <0x4210>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer6_mod_ck: timer6_mod_ck@8d50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d50>, <0x4214>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer7_mod_ck: timer7_mod_ck@8d58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d58>, <0x4218>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer8_mod_ck: timer8_mod_ck@8d60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d60>, <0x421c>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck@8d68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d68>, <0x4220>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer10_mod_ck: timer10_mod_ck@8d70 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d70>, <0x4224>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck@8d78 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d78>, <0x4228>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ uart2_mod_ck: uart2_mod_ck@8d80 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d80>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart3_mod_ck: uart3_mod_ck@8d88 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d88>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart4_mod_ck: uart4_mod_ck@8d90 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d90>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart5_mod_ck: uart5_mod_ck@8d98 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d98>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart6_mod_ck: uart6_mod_ck@8da0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8da0>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ ocp2scp0_mod_ck: ocp2scp0_mod_ck@8db8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8db8>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ ocp2scp1_mod_ck: ocp2scp1_mod_ck@8dc0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8dc0>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ emif_mod_ck: emif_mod_ck@8f20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8f20>;
+ clocks = <&dpll_ddr_m2_ck>;
+ };
+
+ dss_dispc_mod_ck: dss_dispc_mod_ck@9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck@9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck@9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ cpgmac0_mod_ck: cpgmac0_mod_ck@9320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x9320>;
+ clocks = <&cpsw_125mhz_gclk>;
+ };
+
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -629,40 +864,40 @@
reg = <0x2a30>;
};
- timer8_fck: timer8_fck@421c {
+ counter_32k_mod_ck: counter_32k_mod_ck@2a30 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x421c>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2a30>;
+ clocks = <&synctimer_32kclk>;
};
- timer9_fck: timer9_fck@4220 {
+ cpsw_50m_clkdiv: cpsw_50m_clkdiv {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4220>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
};
- timer10_fck: timer10_fck@4224 {
+ adc_tsc_mod_ck: adc_tsc_mod_ck@2920 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4224>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2920>;
+ clocks = <&adc_tsc_fck>;
};
- timer11_fck: timer11_fck@4228 {
+ l4_wkup_mod_ck: l4_wkup_mod_ck@2a20 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4228>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2a20>;
+ clocks = <&sys_clkin_ck>;
};
- cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ wkup_m3_mod_ck: wkup_m3_mod_ck@2a28 {
#clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_m5_ck>;
- clock-mult = <1>;
- clock-div = <1>;
+ compatible = "ti,omap4-sw-no-idlest-mod-clock";
+ reg = <0x2a28>;
+ clocks = <&sys_clkin_ck>;
};
cpsw_5m_clkdiv: cpsw_5m_clkdiv {
@@ -740,6 +975,146 @@
reg = <0x4260>;
};
+ mpu_mod_ck: mpu_mod_ck@8320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ gfx_mod_ck: gfx_mod_ck@8420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8420>;
+ clocks = <&gfx_fck_div_ck>;
+ };
+
+ rtc_mod_ck: rtc_mod_ck@8520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8520>;
+ clocks = <&clk_32768_ck>;
+ };
+
+ l3_main_mod_ck: l3_main_mod_ck@8820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8820>;
+ clocks = <&l3_gclk>;
+ };
+
+ aes_mod_ck: aes_mod_ck@8828 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8828>;
+ clocks = <&aes0_fck>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck@8840 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8840>;
+ clocks = <&l3_gclk>;
+ };
+
+ ocmcram_mod_ck: ocmcram_mod_ck@8850 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8850>;
+ clocks = <&l3_gclk>;
+ };
+
+ sham_mod_ck: sham_mod_ck@8858 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8858>;
+ clocks = <&l3_gclk>;
+ };
+
+ vpfe0_mod_ck: vpfe0_mod_ck@8868 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8868>;
+ clocks = <&l3_gclk>;
+ };
+
+ vpfe1_mod_ck: vpfe1_mod_ck@8870 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8870>;
+ clocks = <&l3_gclk>;
+ };
+
+ tpcc_mod_ck: tpcc_mod_ck@8878 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8878>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc0_mod_ck: tptc0_mod_ck@8880 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8880>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc1_mod_ck: tptc1_mod_ck@8888 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8888>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc2_mod_ck: tptc2_mod_ck@8890 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8890>;
+ clocks = <&l3_gclk>;
+ };
+
+ l4_hs_mod_ck: l4_hs_mod_ck@88a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x88a0>;
+ clocks = <&l4hs_gclk>;
+ };
+
+ gpmc_mod_ck: gpmc_mod_ck@8a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a20>;
+ clocks = <&l3s_gclk>;
+ };
+
+ mcasp0_mod_ck: mcasp0_mod_ck@8a38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a38>;
+ clocks = <&mcasp0_fck>;
+ };
+
+ mcasp1_mod_ck: mcasp1_mod_ck@8a40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a40>;
+ clocks = <&mcasp1_fck>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck@8a48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a48>;
+ clocks = <&mmc_clk>;
+ };
+
+ qspi_mod_ck: qspi_mod_ck@8a58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a58>;
+ clocks = <&l3s_gclk>;
+ };
+
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -756,6 +1131,56 @@
reg = <0x2a48>;
};
+ timer1_mod_ck: timer1_mod_ck@2b28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x2b28>, <0x4200>;
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>,
+ <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck@2b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b38>;
+ clocks = <&wdt1_fck>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck@2b40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b40>;
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ };
+
+ uart1_mod_ck: uart1_mod_ck@2b48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b48>;
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ };
+
+ smartreflex0_mod_ck: smartreflex0_mod_ck@2b50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b50>;
+ clocks = <&smartreflex0_fck>;
+ };
+
+ smartreflex1_mod_ck: smartreflex1_mod_ck@2b58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b58>;
+ clocks = <&smartreflex1_fck>;
+ };
+
+ control_mod_ck: control_mod_ck@2b60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b60>;
+ clocks = <&sys_clkin_ck>;
+ };
+
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -764,6 +1189,13 @@
reg = <0x8a60>;
};
+ usb_otg_ss0_mod_ck: usb_otg_ss0_mod_ck@8a60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a60>;
+ clocks = <&l3s_gclk>;
+ };
+
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -771,4 +1203,179 @@
ti,bit-shift = <8>;
reg = <0x8a68>;
};
+
+ usb_otg_ss1_mod_ck: usb_otg_ss1_mod_ck@8a68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a68>;
+ clocks = <&l3s_gclk>;
+ };
+
+ pruss_mod_ck: pruss_mod_ck@8b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8b20>;
+ clocks = <&pruss_ocp_gclk>;
+ };
+
+ l4_ls_mod_ck: l4_ls_mod_ck@8c20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c20>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ d_can0_mod_ck: d_can0_mod_ck@8c28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c28>;
+ clocks = <&dcan0_fck>;
+ };
+
+ d_can1_mod_ck: d_can1_mod_ck@8c30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c30>;
+ clocks = <&dcan1_fck>;
+ };
+
+ epwmss0_mod_ck: epwmss0_mod_ck@8c38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c38>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss1_mod_ck: epwmss1_mod_ck@8c40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c40>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss2_mod_ck: epwmss2_mod_ck@8c48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c48>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss3_mod_ck: epwmss3_mod_ck@8c50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c50>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss4_mod_ck: epwmss4_mod_ck@8c58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c58>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss5_mod_ck: epwmss5_mod_ck@8c60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c60>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ elm_mod_ck: elm_mod_ck@8c68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c68>;
+ clocks = <&l4ls_gclk>;
+ };
+};
+
+&prcm_clockdomains {
+ pruss_ocp_clkdm: pruss_ocp_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&pruss_mod_ck>;
+ };
+
+ cpsw_125mhz_clkdm: cpsw_125mhz_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cpgmac0_mod_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_rfbi_mod_ck>, <&dss_dispc_mod_ck>,
+ <&dss_core_mod_ck>;
+ };
+
+ mpu_clkdm: mpu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ l4_rtc_clkdm: l4_rtc_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&rtc_mod_ck>;
+ };
+
+ emif_clkdm: emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif_mod_ck>;
+ };
+
+ l4ls_clkdm: l4ls_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio2_mod_ck>, <&ocp2scp0_mod_ck>, <&d_can1_mod_ck>,
+ <&d_can0_mod_ck>, <&uart2_mod_ck>, <&epwmss3_mod_ck>,
+ <&gpio4_mod_ck>, <&spi0_mod_ck>, <&timer9_mod_ck>,
+ <&i2c3_mod_ck>, <&timer5_mod_ck>, <&gpio5_mod_ck>,
+ <&timer2_mod_ck>, <&uart4_mod_ck>, <&epwmss4_mod_ck>,
+ <&spi2_mod_ck>, <&spi4_mod_ck>, <&mailbox_mod_ck>,
+ <&epwmss5_mod_ck>, <&uart6_mod_ck>, <&elm_mod_ck>,
+ <&spi3_mod_ck>, <&spi1_mod_ck>, <&epwmss1_mod_ck>,
+ <&l4_ls_mod_ck>, <&uart5_mod_ck>, <&mmc1_mod_ck>,
+ <&timer6_mod_ck>, <&timer3_mod_ck>, <&timer4_mod_ck>,
+ <&i2c2_mod_ck>, <&mmc2_mod_ck>, <&gpio3_mod_ck>,
+ <&timer10_mod_ck>, <&uart3_mod_ck>, <&timer7_mod_ck>,
+ <&gpio6_mod_ck>, <&ocp2scp1_mod_ck>, <&epwmss0_mod_ck>,
+ <&timer8_mod_ck>, <&epwmss2_mod_ck>,
+ <&spinlock_mod_ck>, <&hdq1w_mod_ck>, <&timer11_mod_ck>;
+ };
+
+ gfx_l3_clkdm: gfx_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gfx_mod_ck>;
+ };
+
+ l3s_tsc_clkdm: l3s_tsc_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&adc_tsc_mod_ck>;
+ };
+
+ l3s_clkdm: l3s_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&qspi_mod_ck>, <&gpmc_mod_ck>, <&mcasp0_mod_ck>,
+ <&vpfe0_mod_ck>, <&mmc3_mod_ck>, <&vpfe1_mod_ck>,
+ <&usb_otg_ss1_mod_ck>, <&usb_otg_ss0_mod_ck>,
+ <&mcasp1_mod_ck>;
+ };
+
+ l4_wkup_clkdm: l4_wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart1_mod_ck>, <&smartreflex0_mod_ck>,
+ <&smartreflex1_mod_ck>, <&gpio1_mod_ck>,
+ <&l4_wkup_mod_ck>, <&control_mod_ck>, <&timer1_mod_ck>,
+ <&wd_timer2_mod_ck>, <&i2c1_mod_ck>;
+ };
+
+ l4_wkup_aon_clkdm: l4_wkup_aon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&counter_32k_mod_ck>, <&wkup_m3_mod_ck>;
+ };
+
+ l3_clkdm: l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_mod_ck>, <&ocmcram_mod_ck>, <&aes_mod_ck>,
+ <&sham_mod_ck>, <&l4_hs_mod_ck>, <&tpcc_mod_ck>,
+ <&tptc0_mod_ck>, <&l3_instr_mod_ck>, <&tptc2_mod_ck>,
+ <&tptc1_mod_ck>;
+ };
};
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 26/28] ARM: dts: am43xx: add hwmod module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 747 ++++++++++++++++++++++++++++++----
1 file changed, 677 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 34fecf2..bc905036 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -383,55 +383,6 @@
clock-frequency = <32768>;
};
- timer1_fck: timer1_fck at 4200 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
- reg = <0x4200>;
- };
-
- timer2_fck: timer2_fck at 4204 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4204>;
- };
-
- timer3_fck: timer3_fck at 4208 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4208>;
- };
-
- timer4_fck: timer4_fck at 420c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x420c>;
- };
-
- timer5_fck: timer5_fck at 4210 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4210>;
- };
-
- timer6_fck: timer6_fck at 4214 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4214>;
- };
-
- timer7_fck: timer7_fck at 4218 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4218>;
- };
-
wdt1_fck: wdt1_fck at 422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -524,6 +475,13 @@
reg = <0x2b68>;
};
+ gpio1_mod_ck: gpio1_mod_ck at 2b68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b68>;
+ clocks = <&sys_clkin_ck>;
+ };
+
gpio1_dbclk: gpio1_dbclk at 8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -532,6 +490,13 @@
reg = <0x8c78>;
};
+ gpio2_mod_ck: gpio2_mod_ck at 8c78 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c78>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio2_dbclk: gpio2_dbclk at 8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -540,6 +505,13 @@
reg = <0x8c80>;
};
+ gpio3_mod_ck: gpio3_mod_ck at 8c80 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c80>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio3_dbclk: gpio3_dbclk at 8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -548,6 +520,13 @@
reg = <0x8c88>;
};
+ gpio4_mod_ck: gpio4_mod_ck at 8c88 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c88>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio4_dbclk: gpio4_dbclk at 8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -556,6 +535,13 @@
reg = <0x8c90>;
};
+ gpio5_mod_ck: gpio5_mod_ck at 8c90 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c90>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio5_dbclk: gpio5_dbclk at 8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -564,6 +550,255 @@
reg = <0x8c98>;
};
+ gpio6_mod_ck: gpio6_mod_ck at 8c98 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c98>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ hdq1w_mod_ck: hdq1w_mod_ck at 8ca0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8ca0>;
+ clocks = <&func_12m_clk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck at 8ca8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8ca8>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck at 8cb0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cb0>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck at 8cb8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cb8>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ mmc1_mod_ck: mmc1_mod_ck at 8cc0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cc0>;
+ clocks = <&mmc_clk>;
+ };
+
+ mmc2_mod_ck: mmc2_mod_ck at 8cc8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cc8>;
+ clocks = <&mmc_clk>;
+ };
+
+ spi0_mod_ck: spi0_mod_ck at 8d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d00>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi1_mod_ck: spi1_mod_ck at 8d08 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d08>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi2_mod_ck: spi2_mod_ck at 8d10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d10>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi3_mod_ck: spi3_mod_ck at 8d18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d18>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi4_mod_ck: spi4_mod_ck at 8d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d20>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck at 8d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d28>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck at 8d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d30>, <0x4204>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck at 8d38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d38>, <0x4208>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck at 8d40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d40>, <0x420c>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer5_mod_ck: timer5_mod_ck at 8d48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d48>, <0x4210>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer6_mod_ck: timer6_mod_ck at 8d50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d50>, <0x4214>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer7_mod_ck: timer7_mod_ck at 8d58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d58>, <0x4218>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer8_mod_ck: timer8_mod_ck at 8d60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d60>, <0x421c>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck at 8d68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d68>, <0x4220>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer10_mod_ck: timer10_mod_ck at 8d70 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d70>, <0x4224>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck at 8d78 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d78>, <0x4228>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ uart2_mod_ck: uart2_mod_ck at 8d80 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d80>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart3_mod_ck: uart3_mod_ck at 8d88 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d88>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart4_mod_ck: uart4_mod_ck at 8d90 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d90>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart5_mod_ck: uart5_mod_ck at 8d98 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d98>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart6_mod_ck: uart6_mod_ck at 8da0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8da0>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ ocp2scp0_mod_ck: ocp2scp0_mod_ck at 8db8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8db8>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ ocp2scp1_mod_ck: ocp2scp1_mod_ck at 8dc0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8dc0>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ emif_mod_ck: emif_mod_ck at 8f20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8f20>;
+ clocks = <&dpll_ddr_m2_ck>;
+ };
+
+ dss_dispc_mod_ck: dss_dispc_mod_ck at 9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck at 9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck at 9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ cpgmac0_mod_ck: cpgmac0_mod_ck at 9320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x9320>;
+ clocks = <&cpsw_125mhz_gclk>;
+ };
+
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -629,40 +864,40 @@
reg = <0x2a30>;
};
- timer8_fck: timer8_fck at 421c {
+ counter_32k_mod_ck: counter_32k_mod_ck at 2a30 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x421c>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2a30>;
+ clocks = <&synctimer_32kclk>;
};
- timer9_fck: timer9_fck at 4220 {
+ cpsw_50m_clkdiv: cpsw_50m_clkdiv {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4220>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
};
- timer10_fck: timer10_fck at 4224 {
+ adc_tsc_mod_ck: adc_tsc_mod_ck at 2920 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4224>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2920>;
+ clocks = <&adc_tsc_fck>;
};
- timer11_fck: timer11_fck at 4228 {
+ l4_wkup_mod_ck: l4_wkup_mod_ck at 2a20 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4228>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2a20>;
+ clocks = <&sys_clkin_ck>;
};
- cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ wkup_m3_mod_ck: wkup_m3_mod_ck at 2a28 {
#clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_m5_ck>;
- clock-mult = <1>;
- clock-div = <1>;
+ compatible = "ti,omap4-sw-no-idlest-mod-clock";
+ reg = <0x2a28>;
+ clocks = <&sys_clkin_ck>;
};
cpsw_5m_clkdiv: cpsw_5m_clkdiv {
@@ -740,6 +975,146 @@
reg = <0x4260>;
};
+ mpu_mod_ck: mpu_mod_ck at 8320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ gfx_mod_ck: gfx_mod_ck at 8420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8420>;
+ clocks = <&gfx_fck_div_ck>;
+ };
+
+ rtc_mod_ck: rtc_mod_ck at 8520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8520>;
+ clocks = <&clk_32768_ck>;
+ };
+
+ l3_main_mod_ck: l3_main_mod_ck at 8820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8820>;
+ clocks = <&l3_gclk>;
+ };
+
+ aes_mod_ck: aes_mod_ck at 8828 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8828>;
+ clocks = <&aes0_fck>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck at 8840 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8840>;
+ clocks = <&l3_gclk>;
+ };
+
+ ocmcram_mod_ck: ocmcram_mod_ck at 8850 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8850>;
+ clocks = <&l3_gclk>;
+ };
+
+ sham_mod_ck: sham_mod_ck at 8858 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8858>;
+ clocks = <&l3_gclk>;
+ };
+
+ vpfe0_mod_ck: vpfe0_mod_ck at 8868 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8868>;
+ clocks = <&l3_gclk>;
+ };
+
+ vpfe1_mod_ck: vpfe1_mod_ck at 8870 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8870>;
+ clocks = <&l3_gclk>;
+ };
+
+ tpcc_mod_ck: tpcc_mod_ck at 8878 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8878>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc0_mod_ck: tptc0_mod_ck at 8880 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8880>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc1_mod_ck: tptc1_mod_ck at 8888 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8888>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc2_mod_ck: tptc2_mod_ck at 8890 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8890>;
+ clocks = <&l3_gclk>;
+ };
+
+ l4_hs_mod_ck: l4_hs_mod_ck at 88a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x88a0>;
+ clocks = <&l4hs_gclk>;
+ };
+
+ gpmc_mod_ck: gpmc_mod_ck at 8a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a20>;
+ clocks = <&l3s_gclk>;
+ };
+
+ mcasp0_mod_ck: mcasp0_mod_ck at 8a38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a38>;
+ clocks = <&mcasp0_fck>;
+ };
+
+ mcasp1_mod_ck: mcasp1_mod_ck at 8a40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a40>;
+ clocks = <&mcasp1_fck>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck at 8a48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a48>;
+ clocks = <&mmc_clk>;
+ };
+
+ qspi_mod_ck: qspi_mod_ck at 8a58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a58>;
+ clocks = <&l3s_gclk>;
+ };
+
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k at 2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -756,6 +1131,56 @@
reg = <0x2a48>;
};
+ timer1_mod_ck: timer1_mod_ck at 2b28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x2b28>, <0x4200>;
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>,
+ <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck at 2b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b38>;
+ clocks = <&wdt1_fck>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck at 2b40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b40>;
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ };
+
+ uart1_mod_ck: uart1_mod_ck at 2b48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b48>;
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ };
+
+ smartreflex0_mod_ck: smartreflex0_mod_ck at 2b50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b50>;
+ clocks = <&smartreflex0_fck>;
+ };
+
+ smartreflex1_mod_ck: smartreflex1_mod_ck at 2b58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b58>;
+ clocks = <&smartreflex1_fck>;
+ };
+
+ control_mod_ck: control_mod_ck at 2b60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b60>;
+ clocks = <&sys_clkin_ck>;
+ };
+
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m at 8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -764,6 +1189,13 @@
reg = <0x8a60>;
};
+ usb_otg_ss0_mod_ck: usb_otg_ss0_mod_ck at 8a60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a60>;
+ clocks = <&l3s_gclk>;
+ };
+
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -771,4 +1203,179 @@
ti,bit-shift = <8>;
reg = <0x8a68>;
};
+
+ usb_otg_ss1_mod_ck: usb_otg_ss1_mod_ck at 8a68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a68>;
+ clocks = <&l3s_gclk>;
+ };
+
+ pruss_mod_ck: pruss_mod_ck at 8b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8b20>;
+ clocks = <&pruss_ocp_gclk>;
+ };
+
+ l4_ls_mod_ck: l4_ls_mod_ck at 8c20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c20>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ d_can0_mod_ck: d_can0_mod_ck at 8c28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c28>;
+ clocks = <&dcan0_fck>;
+ };
+
+ d_can1_mod_ck: d_can1_mod_ck at 8c30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c30>;
+ clocks = <&dcan1_fck>;
+ };
+
+ epwmss0_mod_ck: epwmss0_mod_ck at 8c38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c38>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss1_mod_ck: epwmss1_mod_ck at 8c40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c40>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss2_mod_ck: epwmss2_mod_ck at 8c48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c48>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss3_mod_ck: epwmss3_mod_ck at 8c50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c50>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss4_mod_ck: epwmss4_mod_ck at 8c58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c58>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss5_mod_ck: epwmss5_mod_ck at 8c60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c60>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ elm_mod_ck: elm_mod_ck at 8c68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c68>;
+ clocks = <&l4ls_gclk>;
+ };
+};
+
+&prcm_clockdomains {
+ pruss_ocp_clkdm: pruss_ocp_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&pruss_mod_ck>;
+ };
+
+ cpsw_125mhz_clkdm: cpsw_125mhz_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cpgmac0_mod_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_rfbi_mod_ck>, <&dss_dispc_mod_ck>,
+ <&dss_core_mod_ck>;
+ };
+
+ mpu_clkdm: mpu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ l4_rtc_clkdm: l4_rtc_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&rtc_mod_ck>;
+ };
+
+ emif_clkdm: emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif_mod_ck>;
+ };
+
+ l4ls_clkdm: l4ls_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio2_mod_ck>, <&ocp2scp0_mod_ck>, <&d_can1_mod_ck>,
+ <&d_can0_mod_ck>, <&uart2_mod_ck>, <&epwmss3_mod_ck>,
+ <&gpio4_mod_ck>, <&spi0_mod_ck>, <&timer9_mod_ck>,
+ <&i2c3_mod_ck>, <&timer5_mod_ck>, <&gpio5_mod_ck>,
+ <&timer2_mod_ck>, <&uart4_mod_ck>, <&epwmss4_mod_ck>,
+ <&spi2_mod_ck>, <&spi4_mod_ck>, <&mailbox_mod_ck>,
+ <&epwmss5_mod_ck>, <&uart6_mod_ck>, <&elm_mod_ck>,
+ <&spi3_mod_ck>, <&spi1_mod_ck>, <&epwmss1_mod_ck>,
+ <&l4_ls_mod_ck>, <&uart5_mod_ck>, <&mmc1_mod_ck>,
+ <&timer6_mod_ck>, <&timer3_mod_ck>, <&timer4_mod_ck>,
+ <&i2c2_mod_ck>, <&mmc2_mod_ck>, <&gpio3_mod_ck>,
+ <&timer10_mod_ck>, <&uart3_mod_ck>, <&timer7_mod_ck>,
+ <&gpio6_mod_ck>, <&ocp2scp1_mod_ck>, <&epwmss0_mod_ck>,
+ <&timer8_mod_ck>, <&epwmss2_mod_ck>,
+ <&spinlock_mod_ck>, <&hdq1w_mod_ck>, <&timer11_mod_ck>;
+ };
+
+ gfx_l3_clkdm: gfx_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gfx_mod_ck>;
+ };
+
+ l3s_tsc_clkdm: l3s_tsc_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&adc_tsc_mod_ck>;
+ };
+
+ l3s_clkdm: l3s_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&qspi_mod_ck>, <&gpmc_mod_ck>, <&mcasp0_mod_ck>,
+ <&vpfe0_mod_ck>, <&mmc3_mod_ck>, <&vpfe1_mod_ck>,
+ <&usb_otg_ss1_mod_ck>, <&usb_otg_ss0_mod_ck>,
+ <&mcasp1_mod_ck>;
+ };
+
+ l4_wkup_clkdm: l4_wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart1_mod_ck>, <&smartreflex0_mod_ck>,
+ <&smartreflex1_mod_ck>, <&gpio1_mod_ck>,
+ <&l4_wkup_mod_ck>, <&control_mod_ck>, <&timer1_mod_ck>,
+ <&wd_timer2_mod_ck>, <&i2c1_mod_ck>;
+ };
+
+ l4_wkup_aon_clkdm: l4_wkup_aon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&counter_32k_mod_ck>, <&wkup_m3_mod_ck>;
+ };
+
+ l3_clkdm: l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_mod_ck>, <&ocmcram_mod_ck>, <&aes_mod_ck>,
+ <&sham_mod_ck>, <&l4_hs_mod_ck>, <&tpcc_mod_ck>,
+ <&tptc0_mod_ck>, <&l3_instr_mod_ck>, <&tptc2_mod_ck>,
+ <&tptc1_mod_ck>;
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 26/28] ARM: dts: am43xx: add hwmod module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 747 ++++++++++++++++++++++++++++++----
1 file changed, 677 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 34fecf2..bc905036 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -383,55 +383,6 @@
clock-frequency = <32768>;
};
- timer1_fck: timer1_fck@4200 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
- reg = <0x4200>;
- };
-
- timer2_fck: timer2_fck@4204 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4204>;
- };
-
- timer3_fck: timer3_fck@4208 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4208>;
- };
-
- timer4_fck: timer4_fck@420c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x420c>;
- };
-
- timer5_fck: timer5_fck@4210 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4210>;
- };
-
- timer6_fck: timer6_fck@4214 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4214>;
- };
-
- timer7_fck: timer7_fck@4218 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
- reg = <0x4218>;
- };
-
wdt1_fck: wdt1_fck@422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -524,6 +475,13 @@
reg = <0x2b68>;
};
+ gpio1_mod_ck: gpio1_mod_ck@2b68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b68>;
+ clocks = <&sys_clkin_ck>;
+ };
+
gpio1_dbclk: gpio1_dbclk@8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -532,6 +490,13 @@
reg = <0x8c78>;
};
+ gpio2_mod_ck: gpio2_mod_ck@8c78 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c78>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio2_dbclk: gpio2_dbclk@8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -540,6 +505,13 @@
reg = <0x8c80>;
};
+ gpio3_mod_ck: gpio3_mod_ck@8c80 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c80>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio3_dbclk: gpio3_dbclk@8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -548,6 +520,13 @@
reg = <0x8c88>;
};
+ gpio4_mod_ck: gpio4_mod_ck@8c88 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c88>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio4_dbclk: gpio4_dbclk@8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -556,6 +535,13 @@
reg = <0x8c90>;
};
+ gpio5_mod_ck: gpio5_mod_ck@8c90 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c90>;
+ clocks = <&l4ls_gclk>;
+ };
+
gpio5_dbclk: gpio5_dbclk@8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -564,6 +550,255 @@
reg = <0x8c98>;
};
+ gpio6_mod_ck: gpio6_mod_ck@8c98 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c98>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ hdq1w_mod_ck: hdq1w_mod_ck@8ca0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8ca0>;
+ clocks = <&func_12m_clk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck@8ca8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8ca8>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck@8cb0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cb0>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck@8cb8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cb8>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ mmc1_mod_ck: mmc1_mod_ck@8cc0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cc0>;
+ clocks = <&mmc_clk>;
+ };
+
+ mmc2_mod_ck: mmc2_mod_ck@8cc8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8cc8>;
+ clocks = <&mmc_clk>;
+ };
+
+ spi0_mod_ck: spi0_mod_ck@8d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d00>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi1_mod_ck: spi1_mod_ck@8d08 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d08>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi2_mod_ck: spi2_mod_ck@8d10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d10>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi3_mod_ck: spi3_mod_ck@8d18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d18>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spi4_mod_ck: spi4_mod_ck@8d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d20>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck@8d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d28>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck@8d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d30>, <0x4204>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck@8d38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d38>, <0x4208>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck@8d40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d40>, <0x420c>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer5_mod_ck: timer5_mod_ck@8d48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d48>, <0x4210>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer6_mod_ck: timer6_mod_ck@8d50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d50>, <0x4214>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer7_mod_ck: timer7_mod_ck@8d58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d58>, <0x4218>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ };
+
+ timer8_mod_ck: timer8_mod_ck@8d60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d60>, <0x421c>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck@8d68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d68>, <0x4220>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer10_mod_ck: timer10_mod_ck@8d70 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d70>, <0x4224>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck@8d78 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x8d78>, <0x4228>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>,
+ <&clk_32k_tpm_ck>;
+ };
+
+ uart2_mod_ck: uart2_mod_ck@8d80 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d80>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart3_mod_ck: uart3_mod_ck@8d88 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d88>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart4_mod_ck: uart4_mod_ck@8d90 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d90>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart5_mod_ck: uart5_mod_ck@8d98 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8d98>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ uart6_mod_ck: uart6_mod_ck@8da0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8da0>;
+ clocks = <&dpll_per_m2_div4_ck>;
+ };
+
+ ocp2scp0_mod_ck: ocp2scp0_mod_ck@8db8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8db8>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ ocp2scp1_mod_ck: ocp2scp1_mod_ck@8dc0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8dc0>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ emif_mod_ck: emif_mod_ck@8f20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8f20>;
+ clocks = <&dpll_ddr_m2_ck>;
+ };
+
+ dss_dispc_mod_ck: dss_dispc_mod_ck@9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck@9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck@9220 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x9220>;
+ clocks = <&disp_clk>;
+ };
+
+ cpgmac0_mod_ck: cpgmac0_mod_ck@9320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x9320>;
+ clocks = <&cpsw_125mhz_gclk>;
+ };
+
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -629,40 +864,40 @@
reg = <0x2a30>;
};
- timer8_fck: timer8_fck@421c {
+ counter_32k_mod_ck: counter_32k_mod_ck@2a30 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x421c>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2a30>;
+ clocks = <&synctimer_32kclk>;
};
- timer9_fck: timer9_fck@4220 {
+ cpsw_50m_clkdiv: cpsw_50m_clkdiv {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4220>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m5_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
};
- timer10_fck: timer10_fck@4224 {
+ adc_tsc_mod_ck: adc_tsc_mod_ck@2920 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4224>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2920>;
+ clocks = <&adc_tsc_fck>;
};
- timer11_fck: timer11_fck@4228 {
+ l4_wkup_mod_ck: l4_wkup_mod_ck@2a20 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
- reg = <0x4228>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2a20>;
+ clocks = <&sys_clkin_ck>;
};
- cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ wkup_m3_mod_ck: wkup_m3_mod_ck@2a28 {
#clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_m5_ck>;
- clock-mult = <1>;
- clock-div = <1>;
+ compatible = "ti,omap4-sw-no-idlest-mod-clock";
+ reg = <0x2a28>;
+ clocks = <&sys_clkin_ck>;
};
cpsw_5m_clkdiv: cpsw_5m_clkdiv {
@@ -740,6 +975,146 @@
reg = <0x4260>;
};
+ mpu_mod_ck: mpu_mod_ck@8320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ gfx_mod_ck: gfx_mod_ck@8420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8420>;
+ clocks = <&gfx_fck_div_ck>;
+ };
+
+ rtc_mod_ck: rtc_mod_ck@8520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8520>;
+ clocks = <&clk_32768_ck>;
+ };
+
+ l3_main_mod_ck: l3_main_mod_ck@8820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8820>;
+ clocks = <&l3_gclk>;
+ };
+
+ aes_mod_ck: aes_mod_ck@8828 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8828>;
+ clocks = <&aes0_fck>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck@8840 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8840>;
+ clocks = <&l3_gclk>;
+ };
+
+ ocmcram_mod_ck: ocmcram_mod_ck@8850 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8850>;
+ clocks = <&l3_gclk>;
+ };
+
+ sham_mod_ck: sham_mod_ck@8858 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8858>;
+ clocks = <&l3_gclk>;
+ };
+
+ vpfe0_mod_ck: vpfe0_mod_ck@8868 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8868>;
+ clocks = <&l3_gclk>;
+ };
+
+ vpfe1_mod_ck: vpfe1_mod_ck@8870 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8870>;
+ clocks = <&l3_gclk>;
+ };
+
+ tpcc_mod_ck: tpcc_mod_ck@8878 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8878>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc0_mod_ck: tptc0_mod_ck@8880 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8880>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc1_mod_ck: tptc1_mod_ck@8888 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8888>;
+ clocks = <&l3_gclk>;
+ };
+
+ tptc2_mod_ck: tptc2_mod_ck@8890 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8890>;
+ clocks = <&l3_gclk>;
+ };
+
+ l4_hs_mod_ck: l4_hs_mod_ck@88a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x88a0>;
+ clocks = <&l4hs_gclk>;
+ };
+
+ gpmc_mod_ck: gpmc_mod_ck@8a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a20>;
+ clocks = <&l3s_gclk>;
+ };
+
+ mcasp0_mod_ck: mcasp0_mod_ck@8a38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a38>;
+ clocks = <&mcasp0_fck>;
+ };
+
+ mcasp1_mod_ck: mcasp1_mod_ck@8a40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a40>;
+ clocks = <&mcasp1_fck>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck@8a48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a48>;
+ clocks = <&mmc_clk>;
+ };
+
+ qspi_mod_ck: qspi_mod_ck@8a58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a58>;
+ clocks = <&l3s_gclk>;
+ };
+
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -756,6 +1131,56 @@
reg = <0x2a48>;
};
+ timer1_mod_ck: timer1_mod_ck@2b28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x2b28>, <0x4200>;
+ clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>,
+ <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck@2b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b38>;
+ clocks = <&wdt1_fck>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck@2b40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b40>;
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ };
+
+ uart1_mod_ck: uart1_mod_ck@2b48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b48>;
+ clocks = <&dpll_per_m2_div4_wkupdm_ck>;
+ };
+
+ smartreflex0_mod_ck: smartreflex0_mod_ck@2b50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b50>;
+ clocks = <&smartreflex0_fck>;
+ };
+
+ smartreflex1_mod_ck: smartreflex1_mod_ck@2b58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b58>;
+ clocks = <&smartreflex1_fck>;
+ };
+
+ control_mod_ck: control_mod_ck@2b60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x2b60>;
+ clocks = <&sys_clkin_ck>;
+ };
+
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -764,6 +1189,13 @@
reg = <0x8a60>;
};
+ usb_otg_ss0_mod_ck: usb_otg_ss0_mod_ck@8a60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a60>;
+ clocks = <&l3s_gclk>;
+ };
+
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -771,4 +1203,179 @@
ti,bit-shift = <8>;
reg = <0x8a68>;
};
+
+ usb_otg_ss1_mod_ck: usb_otg_ss1_mod_ck@8a68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8a68>;
+ clocks = <&l3s_gclk>;
+ };
+
+ pruss_mod_ck: pruss_mod_ck@8b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8b20>;
+ clocks = <&pruss_ocp_gclk>;
+ };
+
+ l4_ls_mod_ck: l4_ls_mod_ck@8c20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c20>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ d_can0_mod_ck: d_can0_mod_ck@8c28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c28>;
+ clocks = <&dcan0_fck>;
+ };
+
+ d_can1_mod_ck: d_can1_mod_ck@8c30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c30>;
+ clocks = <&dcan1_fck>;
+ };
+
+ epwmss0_mod_ck: epwmss0_mod_ck@8c38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c38>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss1_mod_ck: epwmss1_mod_ck@8c40 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c40>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss2_mod_ck: epwmss2_mod_ck@8c48 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c48>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss3_mod_ck: epwmss3_mod_ck@8c50 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c50>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss4_mod_ck: epwmss4_mod_ck@8c58 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c58>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ epwmss5_mod_ck: epwmss5_mod_ck@8c60 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c60>;
+ clocks = <&l4ls_gclk>;
+ };
+
+ elm_mod_ck: elm_mod_ck@8c68 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x8c68>;
+ clocks = <&l4ls_gclk>;
+ };
+};
+
+&prcm_clockdomains {
+ pruss_ocp_clkdm: pruss_ocp_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&pruss_mod_ck>;
+ };
+
+ cpsw_125mhz_clkdm: cpsw_125mhz_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cpgmac0_mod_ck>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_rfbi_mod_ck>, <&dss_dispc_mod_ck>,
+ <&dss_core_mod_ck>;
+ };
+
+ mpu_clkdm: mpu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ l4_rtc_clkdm: l4_rtc_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&rtc_mod_ck>;
+ };
+
+ emif_clkdm: emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif_mod_ck>;
+ };
+
+ l4ls_clkdm: l4ls_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio2_mod_ck>, <&ocp2scp0_mod_ck>, <&d_can1_mod_ck>,
+ <&d_can0_mod_ck>, <&uart2_mod_ck>, <&epwmss3_mod_ck>,
+ <&gpio4_mod_ck>, <&spi0_mod_ck>, <&timer9_mod_ck>,
+ <&i2c3_mod_ck>, <&timer5_mod_ck>, <&gpio5_mod_ck>,
+ <&timer2_mod_ck>, <&uart4_mod_ck>, <&epwmss4_mod_ck>,
+ <&spi2_mod_ck>, <&spi4_mod_ck>, <&mailbox_mod_ck>,
+ <&epwmss5_mod_ck>, <&uart6_mod_ck>, <&elm_mod_ck>,
+ <&spi3_mod_ck>, <&spi1_mod_ck>, <&epwmss1_mod_ck>,
+ <&l4_ls_mod_ck>, <&uart5_mod_ck>, <&mmc1_mod_ck>,
+ <&timer6_mod_ck>, <&timer3_mod_ck>, <&timer4_mod_ck>,
+ <&i2c2_mod_ck>, <&mmc2_mod_ck>, <&gpio3_mod_ck>,
+ <&timer10_mod_ck>, <&uart3_mod_ck>, <&timer7_mod_ck>,
+ <&gpio6_mod_ck>, <&ocp2scp1_mod_ck>, <&epwmss0_mod_ck>,
+ <&timer8_mod_ck>, <&epwmss2_mod_ck>,
+ <&spinlock_mod_ck>, <&hdq1w_mod_ck>, <&timer11_mod_ck>;
+ };
+
+ gfx_l3_clkdm: gfx_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gfx_mod_ck>;
+ };
+
+ l3s_tsc_clkdm: l3s_tsc_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&adc_tsc_mod_ck>;
+ };
+
+ l3s_clkdm: l3s_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&qspi_mod_ck>, <&gpmc_mod_ck>, <&mcasp0_mod_ck>,
+ <&vpfe0_mod_ck>, <&mmc3_mod_ck>, <&vpfe1_mod_ck>,
+ <&usb_otg_ss1_mod_ck>, <&usb_otg_ss0_mod_ck>,
+ <&mcasp1_mod_ck>;
+ };
+
+ l4_wkup_clkdm: l4_wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart1_mod_ck>, <&smartreflex0_mod_ck>,
+ <&smartreflex1_mod_ck>, <&gpio1_mod_ck>,
+ <&l4_wkup_mod_ck>, <&control_mod_ck>, <&timer1_mod_ck>,
+ <&wd_timer2_mod_ck>, <&i2c1_mod_ck>;
+ };
+
+ l4_wkup_aon_clkdm: l4_wkup_aon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&counter_32k_mod_ck>, <&wkup_m3_mod_ck>;
+ };
+
+ l3_clkdm: l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_mod_ck>, <&ocmcram_mod_ck>, <&aes_mod_ck>,
+ <&sham_mod_ck>, <&l4_hs_mod_ck>, <&tpcc_mod_ck>,
+ <&tptc0_mod_ck>, <&l3_instr_mod_ck>, <&tptc2_mod_ck>,
+ <&tptc1_mod_ck>;
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCHv2 27/28] ARM: dts: omap5: add hwmod module clocks
2016-04-14 11:07 ` Tero Kristo
(?)
@ 2016-04-14 11:08 ` Tero Kristo
-1 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, paul-DWxLp4Yu+b8AvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 689 ++++++++++++++++++++++++++++----
1 file changed, 618 insertions(+), 71 deletions(-)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 4899c23..f353dd9 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -167,6 +167,27 @@
ti,index-starts-at-one;
};
+ mpu_mod_ck: mpu_mod_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck@420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_h11x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck@520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&abe_iclk>;
+ };
+
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -417,6 +438,38 @@
reg = <0x0560>;
};
+ timer5_mod_ck: timer5_mod_ck@568 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0568>, <0x0568>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer6_mod_ck: timer6_mod_ck@570 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>, <0x0570>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer7_mod_ck: timer7_mod_ck@578 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0578>, <0x0578>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer8_mod_ck: timer8_mod_ck@580 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0580>, <0x0580>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -426,6 +479,13 @@
reg = <0x0528>;
};
+ mcpdm_mod_ck: mcpdm_mod_ck@530 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -442,6 +502,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck@538 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&dmic_gfclk>;
+ };
+
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -466,6 +533,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck@548 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&mcbsp1_gfclk>;
+ };
+
mcbsp1_gfclk: mcbsp1_gfclk@548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -482,6 +556,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck@550 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&mcbsp2_gfclk>;
+ };
+
mcbsp2_gfclk: mcbsp2_gfclk@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -506,36 +587,11 @@
reg = <0x0558>;
};
- timer5_gfclk_mux: timer5_gfclk_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux@578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux@580 {
+ mcbsp3_mod_ck: mcbsp3_mod_ck@558 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&mcbsp3_gfclk>;
};
dummy_ck: dummy_ck {
@@ -553,6 +609,20 @@
ti,index-starts-at-one;
};
+ l4_wkup_mod_ck: l4_wkup_mod_ck@1920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1920>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck@1930 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1930>;
+ clocks = <&sys_32k_ck>;
+ };
+
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -606,13 +676,35 @@
reg = <0x1938>;
};
- timer1_gfclk_mux: timer1_gfclk_mux@1940 {
+ gpio1_mod_ck: gpio1_mod_ck@1938 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1938>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ timer1_mod_ck: timer1_mod_ck@1940 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1940>, <0x1940>;
clocks = <&sys_clkin>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x1940>;
};
+
+ counter_32k_mod_ck: counter_32k_mod_ck@1950 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1950>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ kbd_mod_ck: kbd_mod_ck@1978 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1978>;
+ clocks = <&sys_32k_ck>;
+ };
+
};
&cm_core_clocks {
@@ -852,6 +944,48 @@
reg = <0x1420>;
};
+ dss_dispc_mod_ck: dss_dispc_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi1_mod_ck: dss_dsi1_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi2_mod_ck: dss_dsi2_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ dss_hdmi_mod_ck: dss_hdmi_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_48mhz_clk>;
+ };
+
gpio2_dbclk: gpio2_dbclk@1060 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -860,6 +994,13 @@
reg = <0x1060>;
};
+ gpio2_mod_ck: gpio2_mod_ck@1060 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1060>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio3_dbclk: gpio3_dbclk@1068 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -868,6 +1009,13 @@
reg = <0x1068>;
};
+ gpio3_mod_ck: gpio3_mod_ck@1068 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1068>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio4_dbclk: gpio4_dbclk@1070 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -876,6 +1024,13 @@
reg = <0x1070>;
};
+ gpio4_mod_ck: gpio4_mod_ck@1070 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1070>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio5_dbclk: gpio5_dbclk@1078 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -884,6 +1039,13 @@
reg = <0x1078>;
};
+ gpio5_mod_ck: gpio5_mod_ck@1078 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1078>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio6_dbclk: gpio6_dbclk@1080 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -892,6 +1054,76 @@
reg = <0x1080>;
};
+ gpio6_mod_ck: gpio6_mod_ck@1080 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1080>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck@10a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck@10a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10a8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck@10b0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10b0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c4_mod_ck: i2c4_mod_ck@10b8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10b8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ l4_per_mod_ck: l4_per_mod_ck@10c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x10c0>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mcspi1_mod_ck: mcspi1_mod_ck@10f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10f0>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi2_mod_ck: mcspi2_mod_ck@10f8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10f8>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi3_mod_ck: mcspi3_mod_ck@1100 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1100>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi4_mod_ck: mcspi4_mod_ck@1108 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1108>;
+ clocks = <&func_48m_fclk>;
+ };
+
gpio7_dbclk: gpio7_dbclk@1110 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -900,6 +1132,13 @@
reg = <0x1110>;
};
+ gpio7_mod_ck: gpio7_mod_ck@1110 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1110>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio8_dbclk: gpio8_dbclk@1118 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -908,6 +1147,83 @@
reg = <0x1118>;
};
+ gpio8_mod_ck: gpio8_mod_ck@1118 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1118>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1120>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc4_mod_ck: mmc4_mod_ck@1128 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1128>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart1_mod_ck: uart1_mod_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1140>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart2_mod_ck: uart2_mod_ck@1148 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1148>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart3_mod_ck: uart3_mod_ck@1150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1150>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart4_mod_ck: uart4_mod_ck@1158 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1158>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc5_mod_ck: mmc5_mod_ck@1160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1160>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c5_mod_ck: i2c5_mod_ck@1168 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1168>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ uart5_mod_ck: uart5_mod_ck@1170 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1170>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart6_mod_ck: uart6_mod_ck@1178 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1178>;
+ clocks = <&func_48m_fclk>;
+ };
+
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -932,6 +1248,54 @@
reg = <0x0f20>;
};
+ timer10_mod_ck: timer10_mod_ck@1028 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1028>, <0x1028>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck@1030 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1030>, <0x1030>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck@1038 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1038>, <0x1038>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1040>, <0x1040>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck@1048 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1048>, <0x1048>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck@1050 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1050>, <0x1050>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
mmc1_32khz_clk: mmc1_32khz_clk@1628 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -948,6 +1312,27 @@
reg = <0x1688>;
};
+ sata_mod_ck: sata_mod_ck@1688 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1688>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ ocp2scp1_mod_ck: ocp2scp1_mod_ck@16e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16e0>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ ocp2scp3_mod_ck: ocp2scp3_mod_ck@16e8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16e8>;
+ clocks = <&l4_root_clk_div>;
+ };
+
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1012,6 +1397,13 @@
reg = <0x1658>;
};
+ usb_host_hs_mod_ck: usb_host_hs_mod_ck@1658 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1658>;
+ clocks = <&l3init_60m_fclk>;
+ };
+
utmi_p2_gfclk: utmi_p2_gfclk@1658 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1044,6 +1436,13 @@
reg = <0x16f0>;
};
+ usb_otg_ss_mod_ck: usb_otg_ss_mod_ck@16f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16f0>;
+ clocks = <&dpll_core_h13x2_ck>;
+ };
+
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1052,6 +1451,90 @@
reg = <0x0640>;
};
+ l3_main_1_mod_ck: l3_main_1_mod_ck@720 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0720>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ l3_main_2_mod_ck: l3_main_2_mod_ck@820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0820>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ mmu_ipu_mod_ck: mmu_ipu_mod_ck@920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&dpll_core_h22x2_ck>;
+ };
+
+ dma_system_mod_ck: dma_system_mod_ck@a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0a20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ dmm_mod_ck: dmm_mod_ck@b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0b20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ emif1_mod_ck: emif1_mod_ck@b30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b30>;
+ clocks = <&dpll_core_h11x2_ck>;
+ };
+
+ emif2_mod_ck: emif2_mod_ck@b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b38>;
+ clocks = <&dpll_core_h11x2_ck>;
+ };
+
+ l4_cfg_mod_ck: l4_cfg_mod_ck@d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d20>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck@d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d28>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck@d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d30>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ l3_main_3_mod_ck: l3_main_3_mod_ck@e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck@e28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e28>;
+ clocks = <&l3_iclk_div>;
+ };
+
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1060,6 +1543,13 @@
reg = <0x1668>;
};
+ usb_tll_hs_mod_ck: usb_tll_hs_mod_ck@1668 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1668>;
+ clocks = <&l4_root_clk_div>;
+ };
+
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1127,6 +1617,13 @@
reg = <0x1628>;
};
+ mmc1_mod_ck: mmc1_mod_ck@1628 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1628>;
+ clocks = <&mmc1_fclk>;
+ };
+
mmc2_fclk_mux: mmc2_fclk_mux@1630 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1144,59 +1641,80 @@
reg = <0x1630>;
};
- timer10_gfclk_mux: timer10_gfclk_mux@1028 {
+ mmc2_mod_ck: mmc2_mod_ck@1630 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1028>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1630>;
+ clocks = <&mmc2_fclk>;
};
- timer11_gfclk_mux: timer11_gfclk_mux@1030 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1030>;
+};
+
+&cm_core_clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_tll_hs_mod_ck>, <&usb_host_hs_mod_ck>,
+ <&sata_mod_ck>, <&ocp2scp1_mod_ck>, <&mmc1_mod_ck>,
+ <&mmc2_mod_ck>, <&usb_otg_ss_mod_ck>,
+ <&ocp2scp3_mod_ck>, <&dpll_usb_ck>;
};
- timer2_gfclk_mux: timer2_gfclk_mux@1038 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1038>;
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_dsi2_mod_ck>, <&dss_rfbi_mod_ck>,
+ <&dss_hdmi_mod_ck>, <&dss_dispc_mod_ck>,
+ <&dss_dsi1_mod_ck>, <&dss_core_mod_ck>;
};
- timer3_gfclk_mux: timer3_gfclk_mux@1040 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1040>;
+ emif_clkdm: emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif1_mod_ck>, <&dmm_mod_ck>, <&emif2_mod_ck>;
};
- timer4_gfclk_mux: timer4_gfclk_mux@1048 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1048>;
+ l3main1_clkdm: l3main1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_1_mod_ck>;
};
- timer9_gfclk_mux: timer9_gfclk_mux@1050 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1050>;
+ l4cfg_clkdm: l4cfg_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&spinlock_mod_ck>, <&l4_cfg_mod_ck>,
+ <&mailbox_mod_ck>;
};
-};
-&cm_core_clockdomains {
- l3init_clkdm: l3init_clkdm {
+ dma_clkdm: dma_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>;
+ clocks = <&dma_system_mod_ck>;
+ };
+
+ l3main2_clkdm: l3main2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_2_mod_ck>;
+ };
+
+ ipu_clkdm: ipu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_ipu_mod_ck>;
+ };
+
+ l3instr_clkdm: l3instr_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_3_mod_ck>, <&l3_instr_mod_ck>;
+ };
+
+ l4per_clkdm: l4per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l4_per_mod_ck>, <&uart6_mod_ck>, <&i2c4_mod_ck>,
+ <&gpio8_mod_ck>, <&uart5_mod_ck>, <&gpio4_mod_ck>,
+ <&timer4_mod_ck>, <&mcspi2_mod_ck>, <&mmc3_mod_ck>,
+ <&mmc5_mod_ck>, <&timer9_mod_ck>, <&gpio7_mod_ck>,
+ <&mcspi3_mod_ck>, <&uart4_mod_ck>, <&uart2_mod_ck>,
+ <&i2c3_mod_ck>, <&timer11_mod_ck>, <&mmc4_mod_ck>,
+ <&i2c5_mod_ck>, <&gpio2_mod_ck>, <&gpio3_mod_ck>,
+ <&uart3_mod_ck>, <&i2c2_mod_ck>, <&mcspi1_mod_ck>,
+ <&timer2_mod_ck>, <&gpio5_mod_ck>, <&uart1_mod_ck>,
+ <&timer10_mod_ck>, <&gpio6_mod_ck>, <&timer3_mod_ck>,
+ <&mcspi4_mod_ck>, <&i2c1_mod_ck>;
};
};
@@ -1388,3 +1906,32 @@
reg = <0x021c>;
};
};
+
+&prm_clockdomains {
+ wkupaon_clkdm: wkupaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&kbd_mod_ck>, <&gpio1_mod_ck>, <&counter_32k_mod_ck>,
+ <&timer1_mod_ck>, <&wd_timer2_mod_ck>,
+ <&l4_wkup_mod_ck>;
+ };
+};
+
+&cm_core_aon_clockdomains {
+ mpu_clkdm: mpu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ dsp_clkdm: dsp_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_dsp_mod_ck>;
+ };
+
+ abe_clkdm: abe_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&timer5_mod_ck>, <&timer7_mod_ck>, <&mcbsp2_mod_ck>,
+ <&mcbsp1_mod_ck>, <&dmic_mod_ck>, <&timer6_mod_ck>,
+ <&mcbsp3_mod_ck>, <&mcpdm_mod_ck>, <&l4_abe_mod_ck>,
+ <&timer8_mod_ck>;
+ };
+};
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 27/28] ARM: dts: omap5: add hwmod module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: linux-arm-kernel
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 689 ++++++++++++++++++++++++++++----
1 file changed, 618 insertions(+), 71 deletions(-)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 4899c23..f353dd9 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -167,6 +167,27 @@
ti,index-starts-at-one;
};
+ mpu_mod_ck: mpu_mod_ck at 320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck at 420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_h11x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck at 520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&abe_iclk>;
+ };
+
dpll_core_byp_mux: dpll_core_byp_mux at 12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -417,6 +438,38 @@
reg = <0x0560>;
};
+ timer5_mod_ck: timer5_mod_ck at 568 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0568>, <0x0568>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer6_mod_ck: timer6_mod_ck at 570 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>, <0x0570>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer7_mod_ck: timer7_mod_ck at 578 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0578>, <0x0578>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer8_mod_ck: timer8_mod_ck at 580 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0580>, <0x0580>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
aess_fclk: aess_fclk at 528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -426,6 +479,13 @@
reg = <0x0528>;
};
+ mcpdm_mod_ck: mcpdm_mod_ck at 530 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dmic_sync_mux_ck: dmic_sync_mux_ck at 538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -442,6 +502,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck at 538 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&dmic_gfclk>;
+ };
+
mcasp_sync_mux_ck: mcasp_sync_mux_ck at 540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -466,6 +533,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck at 548 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&mcbsp1_gfclk>;
+ };
+
mcbsp1_gfclk: mcbsp1_gfclk at 548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -482,6 +556,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck at 550 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&mcbsp2_gfclk>;
+ };
+
mcbsp2_gfclk: mcbsp2_gfclk at 550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -506,36 +587,11 @@
reg = <0x0558>;
};
- timer5_gfclk_mux: timer5_gfclk_mux at 568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux at 570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux at 578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux at 580 {
+ mcbsp3_mod_ck: mcbsp3_mod_ck at 558 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&mcbsp3_gfclk>;
};
dummy_ck: dummy_ck {
@@ -553,6 +609,20 @@
ti,index-starts-at-one;
};
+ l4_wkup_mod_ck: l4_wkup_mod_ck at 1920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1920>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck at 1930 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1930>;
+ clocks = <&sys_32k_ck>;
+ };
+
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -606,13 +676,35 @@
reg = <0x1938>;
};
- timer1_gfclk_mux: timer1_gfclk_mux at 1940 {
+ gpio1_mod_ck: gpio1_mod_ck at 1938 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1938>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ timer1_mod_ck: timer1_mod_ck at 1940 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1940>, <0x1940>;
clocks = <&sys_clkin>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x1940>;
};
+
+ counter_32k_mod_ck: counter_32k_mod_ck at 1950 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1950>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ kbd_mod_ck: kbd_mod_ck at 1978 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1978>;
+ clocks = <&sys_32k_ck>;
+ };
+
};
&cm_core_clocks {
@@ -852,6 +944,48 @@
reg = <0x1420>;
};
+ dss_dispc_mod_ck: dss_dispc_mod_ck at 1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi1_mod_ck: dss_dsi1_mod_ck at 1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi2_mod_ck: dss_dsi2_mod_ck at 1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck at 1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck at 1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ dss_hdmi_mod_ck: dss_hdmi_mod_ck at 1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_48mhz_clk>;
+ };
+
gpio2_dbclk: gpio2_dbclk at 1060 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -860,6 +994,13 @@
reg = <0x1060>;
};
+ gpio2_mod_ck: gpio2_mod_ck at 1060 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1060>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio3_dbclk: gpio3_dbclk at 1068 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -868,6 +1009,13 @@
reg = <0x1068>;
};
+ gpio3_mod_ck: gpio3_mod_ck at 1068 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1068>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio4_dbclk: gpio4_dbclk at 1070 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -876,6 +1024,13 @@
reg = <0x1070>;
};
+ gpio4_mod_ck: gpio4_mod_ck at 1070 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1070>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio5_dbclk: gpio5_dbclk at 1078 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -884,6 +1039,13 @@
reg = <0x1078>;
};
+ gpio5_mod_ck: gpio5_mod_ck at 1078 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1078>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio6_dbclk: gpio6_dbclk at 1080 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -892,6 +1054,76 @@
reg = <0x1080>;
};
+ gpio6_mod_ck: gpio6_mod_ck at 1080 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1080>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck at 10a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck at 10a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10a8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck at 10b0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10b0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c4_mod_ck: i2c4_mod_ck at 10b8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10b8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ l4_per_mod_ck: l4_per_mod_ck at 10c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x10c0>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mcspi1_mod_ck: mcspi1_mod_ck at 10f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10f0>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi2_mod_ck: mcspi2_mod_ck at 10f8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10f8>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi3_mod_ck: mcspi3_mod_ck at 1100 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1100>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi4_mod_ck: mcspi4_mod_ck at 1108 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1108>;
+ clocks = <&func_48m_fclk>;
+ };
+
gpio7_dbclk: gpio7_dbclk at 1110 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -900,6 +1132,13 @@
reg = <0x1110>;
};
+ gpio7_mod_ck: gpio7_mod_ck at 1110 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1110>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio8_dbclk: gpio8_dbclk at 1118 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -908,6 +1147,83 @@
reg = <0x1118>;
};
+ gpio8_mod_ck: gpio8_mod_ck at 1118 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1118>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck at 1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1120>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc4_mod_ck: mmc4_mod_ck at 1128 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1128>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart1_mod_ck: uart1_mod_ck at 1140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1140>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart2_mod_ck: uart2_mod_ck at 1148 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1148>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart3_mod_ck: uart3_mod_ck at 1150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1150>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart4_mod_ck: uart4_mod_ck at 1158 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1158>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc5_mod_ck: mmc5_mod_ck at 1160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1160>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c5_mod_ck: i2c5_mod_ck at 1168 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1168>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ uart5_mod_ck: uart5_mod_ck at 1170 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1170>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart6_mod_ck: uart6_mod_ck at 1178 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1178>;
+ clocks = <&func_48m_fclk>;
+ };
+
iss_ctrlclk: iss_ctrlclk at 1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -932,6 +1248,54 @@
reg = <0x0f20>;
};
+ timer10_mod_ck: timer10_mod_ck at 1028 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1028>, <0x1028>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck at 1030 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1030>, <0x1030>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck at 1038 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1038>, <0x1038>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck at 1040 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1040>, <0x1040>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck at 1048 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1048>, <0x1048>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck at 1050 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1050>, <0x1050>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
mmc1_32khz_clk: mmc1_32khz_clk at 1628 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -948,6 +1312,27 @@
reg = <0x1688>;
};
+ sata_mod_ck: sata_mod_ck at 1688 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1688>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ ocp2scp1_mod_ck: ocp2scp1_mod_ck at 16e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16e0>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ ocp2scp3_mod_ck: ocp2scp3_mod_ck at 16e8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16e8>;
+ clocks = <&l4_root_clk_div>;
+ };
+
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1012,6 +1397,13 @@
reg = <0x1658>;
};
+ usb_host_hs_mod_ck: usb_host_hs_mod_ck at 1658 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1658>;
+ clocks = <&l3init_60m_fclk>;
+ };
+
utmi_p2_gfclk: utmi_p2_gfclk at 1658 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1044,6 +1436,13 @@
reg = <0x16f0>;
};
+ usb_otg_ss_mod_ck: usb_otg_ss_mod_ck at 16f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16f0>;
+ clocks = <&dpll_core_h13x2_ck>;
+ };
+
usb_phy_cm_clk32k: usb_phy_cm_clk32k at 640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1052,6 +1451,90 @@
reg = <0x0640>;
};
+ l3_main_1_mod_ck: l3_main_1_mod_ck at 720 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0720>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ l3_main_2_mod_ck: l3_main_2_mod_ck at 820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0820>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ mmu_ipu_mod_ck: mmu_ipu_mod_ck at 920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&dpll_core_h22x2_ck>;
+ };
+
+ dma_system_mod_ck: dma_system_mod_ck at a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0a20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ dmm_mod_ck: dmm_mod_ck at b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0b20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ emif1_mod_ck: emif1_mod_ck at b30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b30>;
+ clocks = <&dpll_core_h11x2_ck>;
+ };
+
+ emif2_mod_ck: emif2_mod_ck at b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b38>;
+ clocks = <&dpll_core_h11x2_ck>;
+ };
+
+ l4_cfg_mod_ck: l4_cfg_mod_ck at d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d20>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck at d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d28>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck at d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d30>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ l3_main_3_mod_ck: l3_main_3_mod_ck at e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck at e28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e28>;
+ clocks = <&l3_iclk_div>;
+ };
+
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1060,6 +1543,13 @@
reg = <0x1668>;
};
+ usb_tll_hs_mod_ck: usb_tll_hs_mod_ck at 1668 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1668>;
+ clocks = <&l4_root_clk_div>;
+ };
+
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1127,6 +1617,13 @@
reg = <0x1628>;
};
+ mmc1_mod_ck: mmc1_mod_ck at 1628 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1628>;
+ clocks = <&mmc1_fclk>;
+ };
+
mmc2_fclk_mux: mmc2_fclk_mux at 1630 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1144,59 +1641,80 @@
reg = <0x1630>;
};
- timer10_gfclk_mux: timer10_gfclk_mux at 1028 {
+ mmc2_mod_ck: mmc2_mod_ck at 1630 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1028>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1630>;
+ clocks = <&mmc2_fclk>;
};
- timer11_gfclk_mux: timer11_gfclk_mux at 1030 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1030>;
+};
+
+&cm_core_clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_tll_hs_mod_ck>, <&usb_host_hs_mod_ck>,
+ <&sata_mod_ck>, <&ocp2scp1_mod_ck>, <&mmc1_mod_ck>,
+ <&mmc2_mod_ck>, <&usb_otg_ss_mod_ck>,
+ <&ocp2scp3_mod_ck>, <&dpll_usb_ck>;
};
- timer2_gfclk_mux: timer2_gfclk_mux at 1038 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1038>;
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_dsi2_mod_ck>, <&dss_rfbi_mod_ck>,
+ <&dss_hdmi_mod_ck>, <&dss_dispc_mod_ck>,
+ <&dss_dsi1_mod_ck>, <&dss_core_mod_ck>;
};
- timer3_gfclk_mux: timer3_gfclk_mux at 1040 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1040>;
+ emif_clkdm: emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif1_mod_ck>, <&dmm_mod_ck>, <&emif2_mod_ck>;
};
- timer4_gfclk_mux: timer4_gfclk_mux at 1048 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1048>;
+ l3main1_clkdm: l3main1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_1_mod_ck>;
};
- timer9_gfclk_mux: timer9_gfclk_mux at 1050 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1050>;
+ l4cfg_clkdm: l4cfg_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&spinlock_mod_ck>, <&l4_cfg_mod_ck>,
+ <&mailbox_mod_ck>;
};
-};
-&cm_core_clockdomains {
- l3init_clkdm: l3init_clkdm {
+ dma_clkdm: dma_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>;
+ clocks = <&dma_system_mod_ck>;
+ };
+
+ l3main2_clkdm: l3main2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_2_mod_ck>;
+ };
+
+ ipu_clkdm: ipu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_ipu_mod_ck>;
+ };
+
+ l3instr_clkdm: l3instr_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_3_mod_ck>, <&l3_instr_mod_ck>;
+ };
+
+ l4per_clkdm: l4per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l4_per_mod_ck>, <&uart6_mod_ck>, <&i2c4_mod_ck>,
+ <&gpio8_mod_ck>, <&uart5_mod_ck>, <&gpio4_mod_ck>,
+ <&timer4_mod_ck>, <&mcspi2_mod_ck>, <&mmc3_mod_ck>,
+ <&mmc5_mod_ck>, <&timer9_mod_ck>, <&gpio7_mod_ck>,
+ <&mcspi3_mod_ck>, <&uart4_mod_ck>, <&uart2_mod_ck>,
+ <&i2c3_mod_ck>, <&timer11_mod_ck>, <&mmc4_mod_ck>,
+ <&i2c5_mod_ck>, <&gpio2_mod_ck>, <&gpio3_mod_ck>,
+ <&uart3_mod_ck>, <&i2c2_mod_ck>, <&mcspi1_mod_ck>,
+ <&timer2_mod_ck>, <&gpio5_mod_ck>, <&uart1_mod_ck>,
+ <&timer10_mod_ck>, <&gpio6_mod_ck>, <&timer3_mod_ck>,
+ <&mcspi4_mod_ck>, <&i2c1_mod_ck>;
};
};
@@ -1388,3 +1906,32 @@
reg = <0x021c>;
};
};
+
+&prm_clockdomains {
+ wkupaon_clkdm: wkupaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&kbd_mod_ck>, <&gpio1_mod_ck>, <&counter_32k_mod_ck>,
+ <&timer1_mod_ck>, <&wd_timer2_mod_ck>,
+ <&l4_wkup_mod_ck>;
+ };
+};
+
+&cm_core_aon_clockdomains {
+ mpu_clkdm: mpu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ dsp_clkdm: dsp_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_dsp_mod_ck>;
+ };
+
+ abe_clkdm: abe_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&timer5_mod_ck>, <&timer7_mod_ck>, <&mcbsp2_mod_ck>,
+ <&mcbsp1_mod_ck>, <&dmic_mod_ck>, <&timer6_mod_ck>,
+ <&mcbsp3_mod_ck>, <&mcpdm_mod_ck>, <&l4_abe_mod_ck>,
+ <&timer8_mod_ck>;
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCHv2 27/28] ARM: dts: omap5: add hwmod module clocks
@ 2016-04-14 11:08 ` Tero Kristo
0 siblings, 0 replies; 92+ messages in thread
From: Tero Kristo @ 2016-04-14 11:08 UTC (permalink / raw)
To: tony, paul, sboyd, mturquette, linux-omap
Cc: linux-arm-kernel, devicetree, linux-clk
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 689 ++++++++++++++++++++++++++++----
1 file changed, 618 insertions(+), 71 deletions(-)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 4899c23..f353dd9 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -167,6 +167,27 @@
ti,index-starts-at-one;
};
+ mpu_mod_ck: mpu_mod_ck@320 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck@420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_h11x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck@520 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&abe_iclk>;
+ };
+
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -417,6 +438,38 @@
reg = <0x0560>;
};
+ timer5_mod_ck: timer5_mod_ck@568 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0568>, <0x0568>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer6_mod_ck: timer6_mod_ck@570 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>, <0x0570>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer7_mod_ck: timer7_mod_ck@578 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0578>, <0x0578>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer8_mod_ck: timer8_mod_ck@580 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0580>, <0x0580>;
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -426,6 +479,13 @@
reg = <0x0528>;
};
+ mcpdm_mod_ck: mcpdm_mod_ck@530 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -442,6 +502,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck@538 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&dmic_gfclk>;
+ };
+
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -466,6 +533,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck@548 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&mcbsp1_gfclk>;
+ };
+
mcbsp1_gfclk: mcbsp1_gfclk@548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -482,6 +556,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck@550 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&mcbsp2_gfclk>;
+ };
+
mcbsp2_gfclk: mcbsp2_gfclk@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -506,36 +587,11 @@
reg = <0x0558>;
};
- timer5_gfclk_mux: timer5_gfclk_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux@578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux@580 {
+ mcbsp3_mod_ck: mcbsp3_mod_ck@558 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&mcbsp3_gfclk>;
};
dummy_ck: dummy_ck {
@@ -553,6 +609,20 @@
ti,index-starts-at-one;
};
+ l4_wkup_mod_ck: l4_wkup_mod_ck@1920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1920>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ wd_timer2_mod_ck: wd_timer2_mod_ck@1930 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1930>;
+ clocks = <&sys_32k_ck>;
+ };
+
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -606,13 +676,35 @@
reg = <0x1938>;
};
- timer1_gfclk_mux: timer1_gfclk_mux@1940 {
+ gpio1_mod_ck: gpio1_mod_ck@1938 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1938>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ timer1_mod_ck: timer1_mod_ck@1940 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1940>, <0x1940>;
clocks = <&sys_clkin>, <&sys_32k_ck>;
ti,bit-shift = <24>;
- reg = <0x1940>;
};
+
+ counter_32k_mod_ck: counter_32k_mod_ck@1950 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1950>;
+ clocks = <&wkupaon_iclk_mux>;
+ };
+
+ kbd_mod_ck: kbd_mod_ck@1978 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1978>;
+ clocks = <&sys_32k_ck>;
+ };
+
};
&cm_core_clocks {
@@ -852,6 +944,48 @@
reg = <0x1420>;
};
+ dss_dispc_mod_ck: dss_dispc_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi1_mod_ck: dss_dsi1_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_dsi2_mod_ck: dss_dsi2_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_core_mod_ck: dss_core_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_dss_clk>;
+ };
+
+ dss_rfbi_mod_ck: dss_rfbi_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ dss_hdmi_mod_ck: dss_hdmi_mod_ck@1420 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x1420>;
+ clocks = <&dss_48mhz_clk>;
+ };
+
gpio2_dbclk: gpio2_dbclk@1060 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -860,6 +994,13 @@
reg = <0x1060>;
};
+ gpio2_mod_ck: gpio2_mod_ck@1060 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1060>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio3_dbclk: gpio3_dbclk@1068 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -868,6 +1009,13 @@
reg = <0x1068>;
};
+ gpio3_mod_ck: gpio3_mod_ck@1068 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1068>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio4_dbclk: gpio4_dbclk@1070 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -876,6 +1024,13 @@
reg = <0x1070>;
};
+ gpio4_mod_ck: gpio4_mod_ck@1070 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1070>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio5_dbclk: gpio5_dbclk@1078 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -884,6 +1039,13 @@
reg = <0x1078>;
};
+ gpio5_mod_ck: gpio5_mod_ck@1078 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1078>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio6_dbclk: gpio6_dbclk@1080 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -892,6 +1054,76 @@
reg = <0x1080>;
};
+ gpio6_mod_ck: gpio6_mod_ck@1080 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1080>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck@10a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c2_mod_ck: i2c2_mod_ck@10a8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10a8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c3_mod_ck: i2c3_mod_ck@10b0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10b0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c4_mod_ck: i2c4_mod_ck@10b8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10b8>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ l4_per_mod_ck: l4_per_mod_ck@10c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x10c0>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mcspi1_mod_ck: mcspi1_mod_ck@10f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10f0>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi2_mod_ck: mcspi2_mod_ck@10f8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x10f8>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi3_mod_ck: mcspi3_mod_ck@1100 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1100>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mcspi4_mod_ck: mcspi4_mod_ck@1108 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1108>;
+ clocks = <&func_48m_fclk>;
+ };
+
gpio7_dbclk: gpio7_dbclk@1110 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -900,6 +1132,13 @@
reg = <0x1110>;
};
+ gpio7_mod_ck: gpio7_mod_ck@1110 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1110>;
+ clocks = <&l4_root_clk_div>;
+ };
+
gpio8_dbclk: gpio8_dbclk@1118 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -908,6 +1147,83 @@
reg = <0x1118>;
};
+ gpio8_mod_ck: gpio8_mod_ck@1118 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1118>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mmc3_mod_ck: mmc3_mod_ck@1120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1120>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc4_mod_ck: mmc4_mod_ck@1128 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1128>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart1_mod_ck: uart1_mod_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1140>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart2_mod_ck: uart2_mod_ck@1148 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1148>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart3_mod_ck: uart3_mod_ck@1150 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1150>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart4_mod_ck: uart4_mod_ck@1158 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1158>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ mmc5_mod_ck: mmc5_mod_ck@1160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1160>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ i2c5_mod_ck: i2c5_mod_ck@1168 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1168>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ uart5_mod_ck: uart5_mod_ck@1170 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1170>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ uart6_mod_ck: uart6_mod_ck@1178 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1178>;
+ clocks = <&func_48m_fclk>;
+ };
+
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -932,6 +1248,54 @@
reg = <0x0f20>;
};
+ timer10_mod_ck: timer10_mod_ck@1028 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1028>, <0x1028>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer11_mod_ck: timer11_mod_ck@1030 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1030>, <0x1030>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer2_mod_ck: timer2_mod_ck@1038 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1038>, <0x1038>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer3_mod_ck: timer3_mod_ck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1040>, <0x1040>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer4_mod_ck: timer4_mod_ck@1048 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1048>, <0x1048>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ timer9_mod_ck: timer9_mod_ck@1050 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x1050>, <0x1050>;
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
mmc1_32khz_clk: mmc1_32khz_clk@1628 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -948,6 +1312,27 @@
reg = <0x1688>;
};
+ sata_mod_ck: sata_mod_ck@1688 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1688>;
+ clocks = <&func_48m_fclk>;
+ };
+
+ ocp2scp1_mod_ck: ocp2scp1_mod_ck@16e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16e0>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ ocp2scp3_mod_ck: ocp2scp3_mod_ck@16e8 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16e8>;
+ clocks = <&l4_root_clk_div>;
+ };
+
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1012,6 +1397,13 @@
reg = <0x1658>;
};
+ usb_host_hs_mod_ck: usb_host_hs_mod_ck@1658 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1658>;
+ clocks = <&l3init_60m_fclk>;
+ };
+
utmi_p2_gfclk: utmi_p2_gfclk@1658 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1044,6 +1436,13 @@
reg = <0x16f0>;
};
+ usb_otg_ss_mod_ck: usb_otg_ss_mod_ck@16f0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x16f0>;
+ clocks = <&dpll_core_h13x2_ck>;
+ };
+
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1052,6 +1451,90 @@
reg = <0x0640>;
};
+ l3_main_1_mod_ck: l3_main_1_mod_ck@720 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0720>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ l3_main_2_mod_ck: l3_main_2_mod_ck@820 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0820>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ mmu_ipu_mod_ck: mmu_ipu_mod_ck@920 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0920>;
+ clocks = <&dpll_core_h22x2_ck>;
+ };
+
+ dma_system_mod_ck: dma_system_mod_ck@a20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0a20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ dmm_mod_ck: dmm_mod_ck@b20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0b20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ emif1_mod_ck: emif1_mod_ck@b30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b30>;
+ clocks = <&dpll_core_h11x2_ck>;
+ };
+
+ emif2_mod_ck: emif2_mod_ck@b38 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0b38>;
+ clocks = <&dpll_core_h11x2_ck>;
+ };
+
+ l4_cfg_mod_ck: l4_cfg_mod_ck@d20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d20>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ spinlock_mod_ck: spinlock_mod_ck@d28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d28>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ mailbox_mod_ck: mailbox_mod_ck@d30 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0d30>;
+ clocks = <&l4_root_clk_div>;
+ };
+
+ l3_main_3_mod_ck: l3_main_3_mod_ck@e20 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e20>;
+ clocks = <&l3_iclk_div>;
+ };
+
+ l3_instr_mod_ck: l3_instr_mod_ck@e28 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0e28>;
+ clocks = <&l3_iclk_div>;
+ };
+
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1060,6 +1543,13 @@
reg = <0x1668>;
};
+ usb_tll_hs_mod_ck: usb_tll_hs_mod_ck@1668 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1668>;
+ clocks = <&l4_root_clk_div>;
+ };
+
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1127,6 +1617,13 @@
reg = <0x1628>;
};
+ mmc1_mod_ck: mmc1_mod_ck@1628 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1628>;
+ clocks = <&mmc1_fclk>;
+ };
+
mmc2_fclk_mux: mmc2_fclk_mux@1630 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1144,59 +1641,80 @@
reg = <0x1630>;
};
- timer10_gfclk_mux: timer10_gfclk_mux@1028 {
+ mmc2_mod_ck: mmc2_mod_ck@1630 {
#clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1028>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x1630>;
+ clocks = <&mmc2_fclk>;
};
- timer11_gfclk_mux: timer11_gfclk_mux@1030 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1030>;
+};
+
+&cm_core_clockdomains {
+ l3init_clkdm: l3init_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usb_tll_hs_mod_ck>, <&usb_host_hs_mod_ck>,
+ <&sata_mod_ck>, <&ocp2scp1_mod_ck>, <&mmc1_mod_ck>,
+ <&mmc2_mod_ck>, <&usb_otg_ss_mod_ck>,
+ <&ocp2scp3_mod_ck>, <&dpll_usb_ck>;
};
- timer2_gfclk_mux: timer2_gfclk_mux@1038 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1038>;
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_dsi2_mod_ck>, <&dss_rfbi_mod_ck>,
+ <&dss_hdmi_mod_ck>, <&dss_dispc_mod_ck>,
+ <&dss_dsi1_mod_ck>, <&dss_core_mod_ck>;
};
- timer3_gfclk_mux: timer3_gfclk_mux@1040 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1040>;
+ emif_clkdm: emif_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emif1_mod_ck>, <&dmm_mod_ck>, <&emif2_mod_ck>;
};
- timer4_gfclk_mux: timer4_gfclk_mux@1048 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1048>;
+ l3main1_clkdm: l3main1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_1_mod_ck>;
};
- timer9_gfclk_mux: timer9_gfclk_mux@1050 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1050>;
+ l4cfg_clkdm: l4cfg_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&spinlock_mod_ck>, <&l4_cfg_mod_ck>,
+ <&mailbox_mod_ck>;
};
-};
-&cm_core_clockdomains {
- l3init_clkdm: l3init_clkdm {
+ dma_clkdm: dma_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>;
+ clocks = <&dma_system_mod_ck>;
+ };
+
+ l3main2_clkdm: l3main2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_2_mod_ck>;
+ };
+
+ ipu_clkdm: ipu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_ipu_mod_ck>;
+ };
+
+ l3instr_clkdm: l3instr_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l3_main_3_mod_ck>, <&l3_instr_mod_ck>;
+ };
+
+ l4per_clkdm: l4per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&l4_per_mod_ck>, <&uart6_mod_ck>, <&i2c4_mod_ck>,
+ <&gpio8_mod_ck>, <&uart5_mod_ck>, <&gpio4_mod_ck>,
+ <&timer4_mod_ck>, <&mcspi2_mod_ck>, <&mmc3_mod_ck>,
+ <&mmc5_mod_ck>, <&timer9_mod_ck>, <&gpio7_mod_ck>,
+ <&mcspi3_mod_ck>, <&uart4_mod_ck>, <&uart2_mod_ck>,
+ <&i2c3_mod_ck>, <&timer11_mod_ck>, <&mmc4_mod_ck>,
+ <&i2c5_mod_ck>, <&gpio2_mod_ck>, <&gpio3_mod_ck>,
+ <&uart3_mod_ck>, <&i2c2_mod_ck>, <&mcspi1_mod_ck>,
+ <&timer2_mod_ck>, <&gpio5_mod_ck>, <&uart1_mod_ck>,
+ <&timer10_mod_ck>, <&gpio6_mod_ck>, <&timer3_mod_ck>,
+ <&mcspi4_mod_ck>, <&i2c1_mod_ck>;
};
};
@@ -1388,3 +1906,32 @@
reg = <0x021c>;
};
};
+
+&prm_clockdomains {
+ wkupaon_clkdm: wkupaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&kbd_mod_ck>, <&gpio1_mod_ck>, <&counter_32k_mod_ck>,
+ <&timer1_mod_ck>, <&wd_timer2_mod_ck>,
+ <&l4_wkup_mod_ck>;
+ };
+};
+
+&cm_core_aon_clockdomains {
+ mpu_clkdm: mpu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mpu_mod_ck>;
+ };
+
+ dsp_clkdm: dsp_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmu_dsp_mod_ck>;
+ };
+
+ abe_clkdm: abe_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&timer5_mod_ck>, <&timer7_mod_ck>, <&mcbsp2_mod_ck>,
+ <&mcbsp1_mod_ck>, <&dmic_mod_ck>, <&timer6_mod_ck>,
+ <&mcbsp3_mod_ck>, <&mcpdm_mod_ck>, <&l4_abe_mod_ck>,
+ <&timer8_mod_ck>;
+ };
+};
--
1.7.9.5
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