[PATCH v2 00/10] Unduplicate CHV phy code

[PATCH v2 00/10] Unduplicate CHV phy code

[Ander Conselvan de Oliveira]

Hi,

Here's an updated series with comments addressed. It alsos gives VLV
code the same treatment.

Thanks,
Ander

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Ander Conselvan de Oliveira (10):
  drm/i915: Set crtc_state->lane_count for HDMI
  drm/i915: Unduplicate CHV signal level code
  drm/i915: Unduplicate chv_data_lane_soft_reset()
  drm/i915: Unduplicate CHV phy-releated pre pll enabling code
  drm/i915: Unduplicate CHV pre-encoder enabling phy logic
  drm/i915: Undiplicate CHV encoders' post pll disable code
  drm/i915: Undiplicate VLV signal level code
  drm/i915: Unduplicate VLV phy pre pll enabling code
  drm/i915: Unduplicate pre encoder enabling phy code
  drm/i915: Move VLV HDMI lane reset work around logic to
    intel_dpio_phy.c

 drivers/gpu/drm/i915/Makefile         |   1 +
 drivers/gpu/drm/i915/i915_drv.h       |  18 ++
 drivers/gpu/drm/i915/intel_ddi.c      |   4 +-
 drivers/gpu/drm/i915/intel_dp.c       | 435 ++-----------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 470 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h      |   5 +
 drivers/gpu/drm/i915/intel_hdmi.c     | 356 +------------------------
 7 files changed, 538 insertions(+), 751 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c

-- 
2.4.11

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[PATCH v2 01/10] drm/i915: Set crtc_state->lane_count for HDMI

[Ander Conselvan de Oliveira]

Set the lane count for HDMI to 4. This will make it easier to
unduplicate CHV phy code.

v2: Set lane_count in *_get_config() to please state checker. (0day)
v3: Set lane_count for DDI in DVI mode too. (CI)

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c  | 4 +++-
 drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 921edf1..d8999c9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2003,8 +2003,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 		if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 			pipe_config->has_infoframe = true;
-		break;
+		/* fall through */
 	case TRANS_DDI_MODE_SELECT_DVI:
+		pipe_config->lane_count = 4;
+		break;
 	case TRANS_DDI_MODE_SELECT_FDI:
 		break;
 	case TRANS_DDI_MODE_SELECT_DP_SST:
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b199ede..80d9841 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -953,6 +953,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 		dotclock /= pipe_config->pixel_multiplier;
 
 	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+
+	pipe_config->lane_count = 4;
 }
 
 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
@@ -1337,6 +1339,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 	/* Set user selected PAR to incoming mode's member */
 	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 
+	pipe_config->lane_count = 4;
+
 	return true;
 }
 
-- 
2.4.11

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Re: [PATCH v2 01/10] drm/i915: Set crtc_state->lane_count for HDMI

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:44PM +0300, Ander Conselvan de Oliveira wrote:
> Set the lane count for HDMI to 4. This will make it easier to
> unduplicate CHV phy code.
> 
> v2: Set lane_count in *_get_config() to please state checker. (0day)
> v3: Set lane_count for DDI in DVI mode too. (CI)
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c  | 4 +++-
>  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 921edf1..d8999c9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2003,8 +2003,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  
>  		if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
>  			pipe_config->has_infoframe = true;
> -		break;
> +		/* fall through */
>  	case TRANS_DDI_MODE_SELECT_DVI:
> +		pipe_config->lane_count = 4;
> +		break;
>  	case TRANS_DDI_MODE_SELECT_FDI:
>  		break;
>  	case TRANS_DDI_MODE_SELECT_DP_SST:
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index b199ede..80d9841 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -953,6 +953,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
>  		dotclock /= pipe_config->pixel_multiplier;
>  
>  	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> +
> +	pipe_config->lane_count = 4;
>  }
>  
>  static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
> @@ -1337,6 +1339,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>  	/* Set user selected PAR to incoming mode's member */
>  	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
>  
> +	pipe_config->lane_count = 4;
> +
>  	return true;
>  }
>  
> -- 
> 2.4.11
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v2 02/10] drm/i915: Unduplicate CHV signal level code

[Ander Conselvan de Oliveira]

The code for programming voltage swing and emphasis was duplicated
between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.

v2: Keep the "Use 800mV-0dB" comment in the HDMI code. (Ville)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/Makefile         |   1 +
 drivers/gpu/drm/i915/i915_drv.h       |   5 ++
 drivers/gpu/drm/i915/intel_dp.c       | 103 ++--------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 122 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     |  70 +------------------
 5 files changed, 136 insertions(+), 165 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..eb45e28 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += intel_audio.o \
 	  intel_bios.o \
 	  intel_color.o \
 	  intel_display.o \
+	  intel_dpio_phy.o \
 	  intel_dpll_mgr.o \
 	  intel_fbc.o \
 	  intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5c91b0..233198d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3554,6 +3554,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
+/* intel_dpio_phy.c */
+void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 deemph_reg_value, u32 margin_reg_value,
+			      bool uniq_trans_scale);
+
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b89e2b..c2f774c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3339,23 +3339,12 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 	return 0;
 }
 
-static bool chv_need_uniq_trans_scale(uint8_t train_set)
-{
-	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
-		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-}
-
 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 {
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
-	u32 deemph_reg_value, margin_reg_value, val;
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	u32 deemph_reg_value, margin_reg_value;
+	bool uniq_trans_scale = false;
 	uint8_t train_set = intel_dp->train_set[0];
-	enum dpio_channel ch = vlv_dport_to_channel(dport);
-	enum pipe pipe = intel_crtc->pipe;
-	int i;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3375,7 +3364,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
 			deemph_reg_value = 128;
 			margin_reg_value = 154;
-			/* FIXME extra to set for 1200 */
+			uniq_trans_scale = true;
 			break;
 		default:
 			return 0;
@@ -3427,88 +3416,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 		return 0;
 	}
 
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* Clear calc init */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
-	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
-	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
-	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
-	if (intel_crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
-		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
-		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
-		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-	}
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
-	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
-	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
-
-	if (intel_crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
-		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
-		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
-	}
-
-	/* Program swing deemph */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
-		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
-		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
-	}
-
-	/* Program swing margin */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
-		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-
-		val &= ~DPIO_SWING_MARGIN000_MASK;
-		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
-
-		/*
-		 * Supposedly this value shouldn't matter when unique transition
-		 * scale is disabled, but in fact it does matter. Let's just
-		 * always program the same value and hope it's OK.
-		 */
-		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
-		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
-
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
-	}
-
-	/*
-	 * The document said it needs to set bit 27 for ch0 and bit 26
-	 * for ch1. Might be a typo in the doc.
-	 * For now, for this unique transition scale selection, set bit
-	 * 27 for ch0 and ch1.
-	 */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
-		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
-		if (chv_need_uniq_trans_scale(train_set))
-			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
-		else
-			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
-	}
-
-	/* Start swing calculation */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
-	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
-	if (intel_crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
-		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-	}
-
-	mutex_unlock(&dev_priv->sb_lock);
+	chv_set_phy_signal_level(encoder, deemph_reg_value,
+				 margin_reg_value, uniq_trans_scale);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
new file mode 100644
index 0000000..cbe1703d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright © 2014-2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "intel_drv.h"
+
+void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 deemph_reg_value, u32 margin_reg_value,
+			      bool uniq_trans_scale)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	enum pipe pipe = intel_crtc->pipe;
+	u32 val;
+	int i;
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	/* Clear calc init */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+	if (intel_crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
+	}
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
+
+	if (intel_crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
+		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+	}
+
+	/* Program swing deemph */
+	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
+		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
+		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
+	}
+
+	/* Program swing margin */
+	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
+
+		val &= ~DPIO_SWING_MARGIN000_MASK;
+		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
+
+		/*
+		 * Supposedly this value shouldn't matter when unique transition
+		 * scale is disabled, but in fact it does matter. Let's just
+		 * always program the same value and hope it's OK.
+		 */
+		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
+		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
+
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
+	}
+
+	/*
+	 * The document said it needs to set bit 27 for ch0 and bit 26
+	 * for ch1. Might be a typo in the doc.
+	 * For now, for this unique transition scale selection, set bit
+	 * 27 for ch0 and ch1.
+	 */
+	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
+		if (uniq_trans_scale)
+			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
+		else
+			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
+	}
+
+	/* Start swing calculation */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+	if (intel_crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
+	}
+
+	mutex_unlock(&dev_priv->sb_lock);
+
+}
+
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 80d9841..eed46c2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1913,77 +1913,11 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	/* Deassert data lane reset */
 	chv_data_lane_soft_reset(encoder, false);
 
-	/* Clear calc init */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
-	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
-	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
-	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
-	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
-	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
-	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
-	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
-	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
-	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
-	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+	mutex_unlock(&dev_priv->sb_lock);
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
-	for (i = 0; i < 4; i++) {
-		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
-		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
-	}
-
-	for (i = 0; i < 4; i++) {
-		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-
-		val &= ~DPIO_SWING_MARGIN000_MASK;
-		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
-
-		/*
-		 * Supposedly this value shouldn't matter when unique transition
-		 * scale is disabled, but in fact it does matter. Let's just
-		 * always program the same value and hope it's OK.
-		 */
-		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
-		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
-
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
-	}
-
-	/*
-	 * The document said it needs to set bit 27 for ch0 and bit 26
-	 * for ch1. Might be a typo in the doc.
-	 * For now, for this unique transition scale selection, set bit
-	 * 27 for ch0 and ch1.
-	 */
-	for (i = 0; i < 4; i++) {
-		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
-		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
-	}
-
-	/* Start swing calculation */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
-	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
-	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-
-	mutex_unlock(&dev_priv->sb_lock);
+	chv_set_phy_signal_level(encoder, 128, 102, false);
 
 	intel_hdmi->set_infoframes(&encoder->base,
 				   intel_crtc->config->has_hdmi_sink,
-- 
2.4.11

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Re: [PATCH v2 02/10] drm/i915: Unduplicate CHV signal level code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:45PM +0300, Ander Conselvan de Oliveira wrote:
> The code for programming voltage swing and emphasis was duplicated
> between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.
> 
> v2: Keep the "Use 800mV-0dB" comment in the HDMI code. (Ville)
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/Makefile         |   1 +
>  drivers/gpu/drm/i915/i915_drv.h       |   5 ++
>  drivers/gpu/drm/i915/intel_dp.c       | 103 ++--------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 122 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     |  70 +------------------
>  5 files changed, 136 insertions(+), 165 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7ffb51b..eb45e28 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,6 +57,7 @@ i915-y += intel_audio.o \
>  	  intel_bios.o \
>  	  intel_color.o \
>  	  intel_display.o \
> +	  intel_dpio_phy.o \
>  	  intel_dpll_mgr.o \
>  	  intel_fbc.o \
>  	  intel_fifo_underrun.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f5c91b0..233198d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3554,6 +3554,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  
> +/* intel_dpio_phy.c */
> +void chv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 deemph_reg_value, u32 margin_reg_value,
> +			      bool uniq_trans_scale);
> +
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1b89e2b..c2f774c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3339,23 +3339,12 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  	return 0;
>  }
>  
> -static bool chv_need_uniq_trans_scale(uint8_t train_set)
> -{
> -	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
> -		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> -}
> -
>  static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  {
> -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
> -	u32 deemph_reg_value, margin_reg_value, val;
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	u32 deemph_reg_value, margin_reg_value;
> +	bool uniq_trans_scale = false;
>  	uint8_t train_set = intel_dp->train_set[0];
> -	enum dpio_channel ch = vlv_dport_to_channel(dport);
> -	enum pipe pipe = intel_crtc->pipe;
> -	int i;
>  
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
>  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3375,7 +3364,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
>  			deemph_reg_value = 128;
>  			margin_reg_value = 154;
> -			/* FIXME extra to set for 1200 */
> +			uniq_trans_scale = true;
>  			break;
>  		default:
>  			return 0;
> @@ -3427,88 +3416,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  		return 0;
>  	}
>  
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* Clear calc init */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> -	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> -	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> -	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> -		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> -		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> -		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> -	}
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> -	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> -	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> -		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> -		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> -	}
> -
> -	/* Program swing deemph */
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> -		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> -		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> -		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
> -	}
> -
> -	/* Program swing margin */
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> -		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> -
> -		val &= ~DPIO_SWING_MARGIN000_MASK;
> -		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
> -
> -		/*
> -		 * Supposedly this value shouldn't matter when unique transition
> -		 * scale is disabled, but in fact it does matter. Let's just
> -		 * always program the same value and hope it's OK.
> -		 */
> -		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> -		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
> -
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> -	}
> -
> -	/*
> -	 * The document said it needs to set bit 27 for ch0 and bit 26
> -	 * for ch1. Might be a typo in the doc.
> -	 * For now, for this unique transition scale selection, set bit
> -	 * 27 for ch0 and ch1.
> -	 */
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> -		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
> -		if (chv_need_uniq_trans_scale(train_set))
> -			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
> -		else
> -			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
> -	}
> -
> -	/* Start swing calculation */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> -	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> -		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	chv_set_phy_signal_level(encoder, deemph_reg_value,
> +				 margin_reg_value, uniq_trans_scale);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> new file mode 100644
> index 0000000..cbe1703d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -0,0 +1,122 @@
> +/*
> + * Copyright © 2014-2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "intel_drv.h"
> +
> +void chv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 deemph_reg_value, u32 margin_reg_value,
> +			      bool uniq_trans_scale)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	enum pipe pipe = intel_crtc->pipe;
> +	u32 val;
> +	int i;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* Clear calc init */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> +		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> +		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> +	}
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> +	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> +		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> +		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> +	}
> +
> +	/* Program swing deemph */
> +	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> +		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> +		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
> +	}
> +
> +	/* Program swing margin */
> +	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> +
> +		val &= ~DPIO_SWING_MARGIN000_MASK;
> +		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
> +
> +		/*
> +		 * Supposedly this value shouldn't matter when unique transition
> +		 * scale is disabled, but in fact it does matter. Let's just
> +		 * always program the same value and hope it's OK.
> +		 */
> +		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> +		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
> +
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> +	}
> +
> +	/*
> +	 * The document said it needs to set bit 27 for ch0 and bit 26
> +	 * for ch1. Might be a typo in the doc.
> +	 * For now, for this unique transition scale selection, set bit
> +	 * 27 for ch0 and ch1.
> +	 */
> +	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
> +		if (uniq_trans_scale)
> +			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
> +		else
> +			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
> +	}
> +
> +	/* Start swing calculation */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> +	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> +		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> +	}
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 80d9841..eed46c2 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1913,77 +1913,11 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	/* Deassert data lane reset */
>  	chv_data_lane_soft_reset(encoder, false);
>  
> -	/* Clear calc init */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> -	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> -	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> -	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> -	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> -	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> -	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> -	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> -	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> -	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> -	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> +	mutex_unlock(&dev_priv->sb_lock);
>  
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
> -	for (i = 0; i < 4; i++) {
> -		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> -		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> -		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
> -	}
> -
> -	for (i = 0; i < 4; i++) {
> -		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> -
> -		val &= ~DPIO_SWING_MARGIN000_MASK;
> -		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
> -
> -		/*
> -		 * Supposedly this value shouldn't matter when unique transition
> -		 * scale is disabled, but in fact it does matter. Let's just
> -		 * always program the same value and hope it's OK.
> -		 */
> -		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> -		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
> -
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> -	}
> -
> -	/*
> -	 * The document said it needs to set bit 27 for ch0 and bit 26
> -	 * for ch1. Might be a typo in the doc.
> -	 * For now, for this unique transition scale selection, set bit
> -	 * 27 for ch0 and ch1.
> -	 */
> -	for (i = 0; i < 4; i++) {
> -		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
> -		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
> -	}
> -
> -	/* Start swing calculation */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> -	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> -	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	chv_set_phy_signal_level(encoder, 128, 102, false);
>  
>  	intel_hdmi->set_infoframes(&encoder->base,
>  				   intel_crtc->config->has_hdmi_sink,
> -- 
> 2.4.11
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v2 03/10] drm/i915: Unduplicate chv_data_lane_soft_reset()

[Ander Conselvan de Oliveira]

The function chv_data_lane_soft_reset() was duplicated in DP and HDMI
code. Move it to intel_dpio_phy.c.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  2 ++
 drivers/gpu/drm/i915/intel_dp.c       | 44 -----------------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 43 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 44 -----------------------------------
 4 files changed, 45 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 233198d..fe40761 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3558,6 +3558,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale);
+void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+			      bool reset);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c2f774c..4d63071 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2451,50 +2451,6 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder)
 	intel_dp_link_down(intel_dp);
 }
 
-static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
-				     bool reset)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
-	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-	enum pipe pipe = crtc->pipe;
-	uint32_t val;
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
-	if (reset)
-		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	else
-		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
-	if (crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
-		if (reset)
-			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-		else
-			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-	}
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
-	val |= CHV_PCS_REQ_SOFTRESET_EN;
-	if (reset)
-		val &= ~DPIO_PCS_CLK_SOFT_RESET;
-	else
-		val |= DPIO_PCS_CLK_SOFT_RESET;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
-
-	if (crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
-		val |= CHV_PCS_REQ_SOFTRESET_EN;
-		if (reset)
-			val &= ~DPIO_PCS_CLK_SOFT_RESET;
-		else
-			val |= DPIO_PCS_CLK_SOFT_RESET;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
-	}
-}
-
 static void chv_post_disable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index cbe1703d..9854c93 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -120,3 +120,46 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 
 }
 
+void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+			      bool reset)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+	enum pipe pipe = crtc->pipe;
+	uint32_t val;
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	if (reset)
+		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+	else
+		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+	if (crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+		if (reset)
+			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+		else
+			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+	}
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
+	val |= CHV_PCS_REQ_SOFTRESET_EN;
+	if (reset)
+		val &= ~DPIO_PCS_CLK_SOFT_RESET;
+	else
+		val |= DPIO_PCS_CLK_SOFT_RESET;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+	if (crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+		val |= CHV_PCS_REQ_SOFTRESET_EN;
+		if (reset)
+			val &= ~DPIO_PCS_CLK_SOFT_RESET;
+		else
+			val |= DPIO_PCS_CLK_SOFT_RESET;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index eed46c2..d1c0be5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1658,50 +1658,6 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
-static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
-				     bool reset)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
-	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-	enum pipe pipe = crtc->pipe;
-	uint32_t val;
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
-	if (reset)
-		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-	else
-		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
-	if (crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
-		if (reset)
-			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-		else
-			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-	}
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
-	val |= CHV_PCS_REQ_SOFTRESET_EN;
-	if (reset)
-		val &= ~DPIO_PCS_CLK_SOFT_RESET;
-	else
-		val |= DPIO_PCS_CLK_SOFT_RESET;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
-
-	if (crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
-		val |= CHV_PCS_REQ_SOFTRESET_EN;
-		if (reset)
-			val &= ~DPIO_PCS_CLK_SOFT_RESET;
-		else
-			val |= DPIO_PCS_CLK_SOFT_RESET;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
-	}
-}
-
 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-- 
2.4.11

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Re: [PATCH v2 03/10] drm/i915: Unduplicate chv_data_lane_soft_reset()

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:46PM +0300, Ander Conselvan de Oliveira wrote:
> The function chv_data_lane_soft_reset() was duplicated in DP and HDMI
> code. Move it to intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 ++
>  drivers/gpu/drm/i915/intel_dp.c       | 44 -----------------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 43 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 44 -----------------------------------
>  4 files changed, 45 insertions(+), 88 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 233198d..fe40761 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3558,6 +3558,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 deemph_reg_value, u32 margin_reg_value,
>  			      bool uniq_trans_scale);
> +void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> +			      bool reset);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c2f774c..4d63071 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2451,50 +2451,6 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder)
>  	intel_dp_link_down(intel_dp);
>  }
>  
> -static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> -				     bool reset)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> -	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> -	enum pipe pipe = crtc->pipe;
> -	uint32_t val;
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> -	if (reset)
> -		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	else
> -		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> -		if (reset)
> -			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -		else
> -			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> -	}
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> -	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	if (reset)
> -		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -	else
> -		val |= DPIO_PCS_CLK_SOFT_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> -		val |= CHV_PCS_REQ_SOFTRESET_EN;
> -		if (reset)
> -			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -		else
> -			val |= DPIO_PCS_CLK_SOFT_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> -	}
> -}
> -
>  static void chv_post_disable_dp(struct intel_encoder *encoder)
>  {
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index cbe1703d..9854c93 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -120,3 +120,46 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  
>  }
>  
> +void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> +			      bool reset)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> +	enum pipe pipe = crtc->pipe;
> +	uint32_t val;
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	if (reset)
> +		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	else
> +		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	if (crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> +		if (reset)
> +			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +		else
> +			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> +	}
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	if (reset)
> +		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> +	else
> +		val |= DPIO_PCS_CLK_SOFT_RESET;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	if (crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +		val |= CHV_PCS_REQ_SOFTRESET_EN;
> +		if (reset)
> +			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> +		else
> +			val |= DPIO_PCS_CLK_SOFT_RESET;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index eed46c2..d1c0be5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1658,50 +1658,6 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> -static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> -				     bool reset)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> -	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> -	enum pipe pipe = crtc->pipe;
> -	uint32_t val;
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> -	if (reset)
> -		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	else
> -		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> -		if (reset)
> -			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -		else
> -			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> -	}
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> -	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	if (reset)
> -		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -	else
> -		val |= DPIO_PCS_CLK_SOFT_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> -		val |= CHV_PCS_REQ_SOFTRESET_EN;
> -		if (reset)
> -			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -		else
> -			val |= DPIO_PCS_CLK_SOFT_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> -	}
> -}
> -
>  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -- 
> 2.4.11
> 
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[PATCH v2 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code

[Ander Conselvan de Oliveira]

The same logic is used for DP and HDMI so move it to intel_dpio_phy.c.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_dp.c       | 83 +----------------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 81 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h      |  5 +++
 drivers/gpu/drm/i915/intel_hdmi.c     | 74 +------------------------------
 5 files changed, 89 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fe40761..19bfe04 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3560,6 +3560,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 			      bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 			      bool reset);
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4d63071..dd62bf0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
 				      enum pipe pipe);
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 
-static unsigned int intel_dp_unused_lane_mask(int lane_count)
-{
-	return ~((1 << lane_count) - 1) & 0xf;
-}
-
 static int
 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 {
@@ -2945,85 +2940,9 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 {
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel ch = vlv_dport_to_channel(dport);
-	enum pipe pipe = intel_crtc->pipe;
-	unsigned int lane_mask =
-		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
-	u32 val;
-
 	intel_dp_prepare(encoder);
 
-	/*
-	 * Must trick the second common lane into life.
-	 * Otherwise we can't even access the PLL.
-	 */
-	if (ch == DPIO_CH0 && pipe == PIPE_B)
-		dport->release_cl2_override =
-			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
-
-	chv_phy_powergate_lanes(encoder, true, lane_mask);
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* Assert data lane reset */
-	chv_data_lane_soft_reset(encoder, true);
-
-	/* program left/right clock distribution */
-	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		if (ch == DPIO_CH0)
-			val |= CHV_BUFLEFTENA1_FORCE;
-		if (ch == DPIO_CH1)
-			val |= CHV_BUFRIGHTENA1_FORCE;
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-	} else {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		if (ch == DPIO_CH0)
-			val |= CHV_BUFLEFTENA2_FORCE;
-		if (ch == DPIO_CH1)
-			val |= CHV_BUFRIGHTENA2_FORCE;
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-	}
-
-	/* program clock channel usage */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
-	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-	if (pipe != PIPE_B)
-		val &= ~CHV_PCS_USEDCLKCHANNEL;
-	else
-		val |= CHV_PCS_USEDCLKCHANNEL;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
-
-	if (intel_crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
-		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-		if (pipe != PIPE_B)
-			val &= ~CHV_PCS_USEDCLKCHANNEL;
-		else
-			val |= CHV_PCS_USEDCLKCHANNEL;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
-	}
-
-	/*
-	 * This a a bit weird since generally CL
-	 * matches the pipe, but here we need to
-	 * pick the CL based on the port.
-	 */
-	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
-	if (pipe != PIPE_B)
-		val &= ~CHV_CMN_USEDCLKCHANNEL;
-	else
-		val |= CHV_CMN_USEDCLKCHANNEL;
-	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
-
-	mutex_unlock(&dev_priv->sb_lock);
+	chv_phy_pre_pll_enable(encoder);
 }
 
 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 9854c93..b4ca3ff 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -163,3 +163,84 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
 	}
 }
+
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	enum pipe pipe = intel_crtc->pipe;
+	unsigned int lane_mask =
+		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
+	u32 val;
+
+	/*
+	 * Must trick the second common lane into life.
+	 * Otherwise we can't even access the PLL.
+	 */
+	if (ch == DPIO_CH0 && pipe == PIPE_B)
+		dport->release_cl2_override =
+			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
+
+	chv_phy_powergate_lanes(encoder, true, lane_mask);
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	/* Assert data lane reset */
+	chv_data_lane_soft_reset(encoder, true);
+
+	/* program left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA1_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA1_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		if (ch == DPIO_CH0)
+			val |= CHV_BUFLEFTENA2_FORCE;
+		if (ch == DPIO_CH1)
+			val |= CHV_BUFRIGHTENA2_FORCE;
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
+	/* program clock channel usage */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
+	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe != PIPE_B)
+		val &= ~CHV_PCS_USEDCLKCHANNEL;
+	else
+		val |= CHV_PCS_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
+
+	if (intel_crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
+		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+		if (pipe != PIPE_B)
+			val &= ~CHV_PCS_USEDCLKCHANNEL;
+		else
+			val |= CHV_PCS_USEDCLKCHANNEL;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
+	}
+
+	/*
+	 * This a a bit weird since generally CL
+	 * matches the pipe, but here we need to
+	 * pick the CL based on the port.
+	 */
+	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
+	if (pipe != PIPE_B)
+		val &= ~CHV_CMN_USEDCLKCHANNEL;
+	else
+		val |= CHV_CMN_USEDCLKCHANNEL;
+	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
+
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e0fcfa1..ad11313 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1323,6 +1323,11 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
 bool
 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
 
+static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
+{
+	return ~((1 << lane_count) - 1) & 0xf;
+}
+
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index d1c0be5..e82d6e8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1660,81 +1660,9 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 
 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 {
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel ch = vlv_dport_to_channel(dport);
-	enum pipe pipe = intel_crtc->pipe;
-	u32 val;
-
 	intel_hdmi_prepare(encoder);
 
-	/*
-	 * Must trick the second common lane into life.
-	 * Otherwise we can't even access the PLL.
-	 */
-	if (ch == DPIO_CH0 && pipe == PIPE_B)
-		dport->release_cl2_override =
-			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
-
-	chv_phy_powergate_lanes(encoder, true, 0x0);
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* Assert data lane reset */
-	chv_data_lane_soft_reset(encoder, true);
-
-	/* program left/right clock distribution */
-	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		if (ch == DPIO_CH0)
-			val |= CHV_BUFLEFTENA1_FORCE;
-		if (ch == DPIO_CH1)
-			val |= CHV_BUFRIGHTENA1_FORCE;
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-	} else {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		if (ch == DPIO_CH0)
-			val |= CHV_BUFLEFTENA2_FORCE;
-		if (ch == DPIO_CH1)
-			val |= CHV_BUFRIGHTENA2_FORCE;
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-	}
-
-	/* program clock channel usage */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
-	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-	if (pipe != PIPE_B)
-		val &= ~CHV_PCS_USEDCLKCHANNEL;
-	else
-		val |= CHV_PCS_USEDCLKCHANNEL;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
-	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-	if (pipe != PIPE_B)
-		val &= ~CHV_PCS_USEDCLKCHANNEL;
-	else
-		val |= CHV_PCS_USEDCLKCHANNEL;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
-
-	/*
-	 * This a a bit weird since generally CL
-	 * matches the pipe, but here we need to
-	 * pick the CL based on the port.
-	 */
-	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
-	if (pipe != PIPE_B)
-		val &= ~CHV_CMN_USEDCLKCHANNEL;
-	else
-		val |= CHV_CMN_USEDCLKCHANNEL;
-	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
-
-	mutex_unlock(&dev_priv->sb_lock);
+	chv_phy_pre_pll_enable(encoder);
 }
 
 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
-- 
2.4.11

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Re: [PATCH v2 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:47PM +0300, Ander Conselvan de Oliveira wrote:
> The same logic is used for DP and HDMI so move it to intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 83 +----------------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 81 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h      |  5 +++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 74 +------------------------------
>  5 files changed, 89 insertions(+), 155 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe40761..19bfe04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3560,6 +3560,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      bool uniq_trans_scale);
>  void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  			      bool reset);
> +void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4d63071..dd62bf0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
>  				      enum pipe pipe);
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>  
> -static unsigned int intel_dp_unused_lane_mask(int lane_count)
> -{
> -	return ~((1 << lane_count) - 1) & 0xf;
> -}
> -
>  static int
>  intel_dp_max_link_bw(struct intel_dp  *intel_dp)
>  {
> @@ -2945,85 +2940,9 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  
>  static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel ch = vlv_dport_to_channel(dport);
> -	enum pipe pipe = intel_crtc->pipe;
> -	unsigned int lane_mask =
> -		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
> -	u32 val;
> -
>  	intel_dp_prepare(encoder);
>  
> -	/*
> -	 * Must trick the second common lane into life.
> -	 * Otherwise we can't even access the PLL.
> -	 */
> -	if (ch == DPIO_CH0 && pipe == PIPE_B)
> -		dport->release_cl2_override =
> -			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
> -
> -	chv_phy_powergate_lanes(encoder, true, lane_mask);
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* Assert data lane reset */
> -	chv_data_lane_soft_reset(encoder, true);
> -
> -	/* program left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		if (ch == DPIO_CH0)
> -			val |= CHV_BUFLEFTENA1_FORCE;
> -		if (ch == DPIO_CH1)
> -			val |= CHV_BUFRIGHTENA1_FORCE;
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		if (ch == DPIO_CH0)
> -			val |= CHV_BUFLEFTENA2_FORCE;
> -		if (ch == DPIO_CH1)
> -			val |= CHV_BUFRIGHTENA2_FORCE;
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	/* program clock channel usage */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> -	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> -	if (pipe != PIPE_B)
> -		val &= ~CHV_PCS_USEDCLKCHANNEL;
> -	else
> -		val |= CHV_PCS_USEDCLKCHANNEL;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> -		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> -		if (pipe != PIPE_B)
> -			val &= ~CHV_PCS_USEDCLKCHANNEL;
> -		else
> -			val |= CHV_PCS_USEDCLKCHANNEL;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> -	}
> -
> -	/*
> -	 * This a a bit weird since generally CL
> -	 * matches the pipe, but here we need to
> -	 * pick the CL based on the port.
> -	 */
> -	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
> -	if (pipe != PIPE_B)
> -		val &= ~CHV_CMN_USEDCLKCHANNEL;
> -	else
> -		val |= CHV_CMN_USEDCLKCHANNEL;
> -	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	chv_phy_pre_pll_enable(encoder);
>  }
>  
>  static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 9854c93..b4ca3ff 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -163,3 +163,84 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
>  	}
>  }
> +
> +void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	enum pipe pipe = intel_crtc->pipe;
> +	unsigned int lane_mask =
> +		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
> +	u32 val;
> +
> +	/*
> +	 * Must trick the second common lane into life.
> +	 * Otherwise we can't even access the PLL.
> +	 */
> +	if (ch == DPIO_CH0 && pipe == PIPE_B)
> +		dport->release_cl2_override =
> +			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
> +
> +	chv_phy_powergate_lanes(encoder, true, lane_mask);
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* Assert data lane reset */
> +	chv_data_lane_soft_reset(encoder, true);
> +
> +	/* program left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		if (ch == DPIO_CH0)
> +			val |= CHV_BUFLEFTENA1_FORCE;
> +		if (ch == DPIO_CH1)
> +			val |= CHV_BUFRIGHTENA1_FORCE;
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		if (ch == DPIO_CH0)
> +			val |= CHV_BUFLEFTENA2_FORCE;
> +		if (ch == DPIO_CH1)
> +			val |= CHV_BUFRIGHTENA2_FORCE;
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
> +	/* program clock channel usage */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> +	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_PCS_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_PCS_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> +		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> +		if (pipe != PIPE_B)
> +			val &= ~CHV_PCS_USEDCLKCHANNEL;
> +		else
> +			val |= CHV_PCS_USEDCLKCHANNEL;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> +	}
> +
> +	/*
> +	 * This a a bit weird since generally CL
> +	 * matches the pipe, but here we need to
> +	 * pick the CL based on the port.
> +	 */
> +	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
> +	if (pipe != PIPE_B)
> +		val &= ~CHV_CMN_USEDCLKCHANNEL;
> +	else
> +		val |= CHV_CMN_USEDCLKCHANNEL;
> +	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e0fcfa1..ad11313 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1323,6 +1323,11 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
>  bool
>  intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
>  
> +static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> +{
> +	return ~((1 << lane_count) - 1) & 0xf;
> +}
> +
>  /* intel_dp_mst.c */
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
>  void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index d1c0be5..e82d6e8 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1660,81 +1660,9 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel ch = vlv_dport_to_channel(dport);
> -	enum pipe pipe = intel_crtc->pipe;
> -	u32 val;
> -
>  	intel_hdmi_prepare(encoder);
>  
> -	/*
> -	 * Must trick the second common lane into life.
> -	 * Otherwise we can't even access the PLL.
> -	 */
> -	if (ch == DPIO_CH0 && pipe == PIPE_B)
> -		dport->release_cl2_override =
> -			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
> -
> -	chv_phy_powergate_lanes(encoder, true, 0x0);
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* Assert data lane reset */
> -	chv_data_lane_soft_reset(encoder, true);
> -
> -	/* program left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		if (ch == DPIO_CH0)
> -			val |= CHV_BUFLEFTENA1_FORCE;
> -		if (ch == DPIO_CH1)
> -			val |= CHV_BUFRIGHTENA1_FORCE;
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		if (ch == DPIO_CH0)
> -			val |= CHV_BUFLEFTENA2_FORCE;
> -		if (ch == DPIO_CH1)
> -			val |= CHV_BUFRIGHTENA2_FORCE;
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	/* program clock channel usage */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
> -	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> -	if (pipe != PIPE_B)
> -		val &= ~CHV_PCS_USEDCLKCHANNEL;
> -	else
> -		val |= CHV_PCS_USEDCLKCHANNEL;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
> -	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
> -	if (pipe != PIPE_B)
> -		val &= ~CHV_PCS_USEDCLKCHANNEL;
> -	else
> -		val |= CHV_PCS_USEDCLKCHANNEL;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
> -
> -	/*
> -	 * This a a bit weird since generally CL
> -	 * matches the pipe, but here we need to
> -	 * pick the CL based on the port.
> -	 */
> -	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
> -	if (pipe != PIPE_B)
> -		val &= ~CHV_CMN_USEDCLKCHANNEL;
> -	else
> -		val |= CHV_CMN_USEDCLKCHANNEL;
> -	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	chv_phy_pre_pll_enable(encoder);
>  }
>  
>  static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
> -- 
> 2.4.11
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v2 05/10] drm/i915: Unduplicate CHV pre-encoder enabling phy logic

[Ander Conselvan de Oliveira]

The only difference between the DP and HDMI versions was the lane count.
Since lane_count is now set appropriately for HDMI too, get rid of the
duplication and move this to intel_dpio_phy.c

v2: Don't move comments about 2nd common lane staying alive. (Ville)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  2 +
 drivers/gpu/drm/i915/intel_dp.c       | 83 +------------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 92 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 67 +------------------------
 4 files changed, 98 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19bfe04..6f96c44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3561,6 +3561,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 			      bool reset);
 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
+void chv_phy_release_cl2_override(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dd62bf0..76a825c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2851,91 +2851,12 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
 static void chv_pre_enable_dp(struct intel_encoder *encoder)
 {
-	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel ch = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-	int data, i, stagger;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* allow hardware to manage TX FIFO reset source */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
-	if (intel_crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-	}
-
-	/* Program Tx lane latency optimal setting*/
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
-		/* Set the upar bit */
-		if (intel_crtc->config->lane_count == 1)
-			data = 0x0;
-		else
-			data = (i == 1) ? 0x0 : 0x1;
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
-				data << DPIO_UPAR_SHIFT);
-	}
-
-	/* Data lane stagger programming */
-	if (intel_crtc->config->port_clock > 270000)
-		stagger = 0x18;
-	else if (intel_crtc->config->port_clock > 135000)
-		stagger = 0xd;
-	else if (intel_crtc->config->port_clock > 67500)
-		stagger = 0x7;
-	else if (intel_crtc->config->port_clock > 33750)
-		stagger = 0x4;
-	else
-		stagger = 0x2;
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-	val |= DPIO_TX2_STAGGER_MASK(0x1f);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
-	if (intel_crtc->config->lane_count > 2) {
-		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-		val |= DPIO_TX2_STAGGER_MASK(0x1f);
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-	}
-
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
-		       DPIO_LANESTAGGER_STRAP(stagger) |
-		       DPIO_LANESTAGGER_STRAP_OVRD |
-		       DPIO_TX1_STAGGER_MASK(0x1f) |
-		       DPIO_TX1_STAGGER_MULT(6) |
-		       DPIO_TX2_STAGGER_MULT(0));
-
-	if (intel_crtc->config->lane_count > 2) {
-		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
-			       DPIO_LANESTAGGER_STRAP(stagger) |
-			       DPIO_LANESTAGGER_STRAP_OVRD |
-			       DPIO_TX1_STAGGER_MASK(0x1f) |
-			       DPIO_TX1_STAGGER_MULT(7) |
-			       DPIO_TX2_STAGGER_MULT(5));
-	}
-
-	/* Deassert data lane reset */
-	chv_data_lane_soft_reset(encoder, false);
-
-	mutex_unlock(&dev_priv->sb_lock);
+	chv_phy_pre_encoder_enable(encoder);
 
 	intel_enable_dp(encoder);
 
 	/* Second common lane will stay alive on its own now */
-	if (dport->release_cl2_override) {
-		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
-		dport->release_cl2_override = false;
-	}
+	chv_phy_release_cl2_override(encoder);
 }
 
 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index b4ca3ff..ad0e7be 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -244,3 +244,95 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
 
 	mutex_unlock(&dev_priv->sb_lock);
 }
+
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel ch = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+	int data, i, stagger;
+	u32 val;
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	/* allow hardware to manage TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	if (intel_crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+	}
+
+	/* Program Tx lane latency optimal setting*/
+	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+		/* Set the upar bit */
+		if (intel_crtc->config->lane_count == 1)
+			data = 0x0;
+		else
+			data = (i == 1) ? 0x0 : 0x1;
+		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
+				data << DPIO_UPAR_SHIFT);
+	}
+
+	/* Data lane stagger programming */
+	if (intel_crtc->config->port_clock > 270000)
+		stagger = 0x18;
+	else if (intel_crtc->config->port_clock > 135000)
+		stagger = 0xd;
+	else if (intel_crtc->config->port_clock > 67500)
+		stagger = 0x7;
+	else if (intel_crtc->config->port_clock > 33750)
+		stagger = 0x4;
+	else
+		stagger = 0x2;
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val |= DPIO_TX2_STAGGER_MASK(0x1f);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	if (intel_crtc->config->lane_count > 2) {
+		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+		val |= DPIO_TX2_STAGGER_MASK(0x1f);
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+	}
+
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
+		       DPIO_LANESTAGGER_STRAP(stagger) |
+		       DPIO_LANESTAGGER_STRAP_OVRD |
+		       DPIO_TX1_STAGGER_MASK(0x1f) |
+		       DPIO_TX1_STAGGER_MULT(6) |
+		       DPIO_TX2_STAGGER_MULT(0));
+
+	if (intel_crtc->config->lane_count > 2) {
+		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
+			       DPIO_LANESTAGGER_STRAP(stagger) |
+			       DPIO_LANESTAGGER_STRAP_OVRD |
+			       DPIO_TX1_STAGGER_MASK(0x1f) |
+			       DPIO_TX1_STAGGER_MULT(7) |
+			       DPIO_TX2_STAGGER_MULT(5));
+	}
+
+	/* Deassert data lane reset */
+	chv_data_lane_soft_reset(encoder, false);
+
+	mutex_unlock(&dev_priv->sb_lock);
+}
+
+void chv_phy_release_cl2_override(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (dport->release_cl2_override) {
+		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
+		dport->release_cl2_override = false;
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e82d6e8..b4da7ee 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1736,68 +1736,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
 	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
-	enum dpio_channel ch = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-	int data, i, stagger;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* allow hardware to manage TX FIFO reset source */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-
-	/* Program Tx latency optimal setting */
-	for (i = 0; i < 4; i++) {
-		/* Set the upar bit */
-		data = (i == 1) ? 0x0 : 0x1;
-		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
-				data << DPIO_UPAR_SHIFT);
-	}
-
-	/* Data lane stagger programming */
-	if (intel_crtc->config->port_clock > 270000)
-		stagger = 0x18;
-	else if (intel_crtc->config->port_clock > 135000)
-		stagger = 0xd;
-	else if (intel_crtc->config->port_clock > 67500)
-		stagger = 0x7;
-	else if (intel_crtc->config->port_clock > 33750)
-		stagger = 0x4;
-	else
-		stagger = 0x2;
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-	val |= DPIO_TX2_STAGGER_MASK(0x1f);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-	val |= DPIO_TX2_STAGGER_MASK(0x1f);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
-		       DPIO_LANESTAGGER_STRAP(stagger) |
-		       DPIO_LANESTAGGER_STRAP_OVRD |
-		       DPIO_TX1_STAGGER_MASK(0x1f) |
-		       DPIO_TX1_STAGGER_MULT(6) |
-		       DPIO_TX2_STAGGER_MULT(0));
-
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
-		       DPIO_LANESTAGGER_STRAP(stagger) |
-		       DPIO_LANESTAGGER_STRAP_OVRD |
-		       DPIO_TX1_STAGGER_MASK(0x1f) |
-		       DPIO_TX1_STAGGER_MULT(7) |
-		       DPIO_TX2_STAGGER_MULT(5));
-
-	/* Deassert data lane reset */
-	chv_data_lane_soft_reset(encoder, false);
-
-	mutex_unlock(&dev_priv->sb_lock);
+	chv_phy_pre_encoder_enable(encoder);
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
@@ -1812,10 +1752,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	vlv_wait_port_ready(dev_priv, dport, 0x0);
 
 	/* Second common lane will stay alive on its own now */
-	if (dport->release_cl2_override) {
-		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
-		dport->release_cl2_override = false;
-	}
+	chv_phy_release_cl2_override(encoder);
 }
 
 static void intel_hdmi_destroy(struct drm_connector *connector)
-- 
2.4.11

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Re: [PATCH v2 05/10] drm/i915: Unduplicate CHV pre-encoder enabling phy logic

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:48PM +0300, Ander Conselvan de Oliveira wrote:
> The only difference between the DP and HDMI versions was the lane count.
> Since lane_count is now set appropriately for HDMI too, get rid of the
> duplication and move this to intel_dpio_phy.c
> 
> v2: Don't move comments about 2nd common lane staying alive. (Ville)
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 +
>  drivers/gpu/drm/i915/intel_dp.c       | 83 +------------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 92 +++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 67 +------------------------
>  4 files changed, 98 insertions(+), 146 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 19bfe04..6f96c44 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3561,6 +3561,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  			      bool reset);
>  void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
> +void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
> +void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dd62bf0..76a825c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2851,91 +2851,12 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  {
> -	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel ch = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -	int data, i, stagger;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* allow hardware to manage TX FIFO reset source */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> -	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> -		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -	}
> -
> -	/* Program Tx lane latency optimal setting*/
> -	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> -		/* Set the upar bit */
> -		if (intel_crtc->config->lane_count == 1)
> -			data = 0x0;
> -		else
> -			data = (i == 1) ? 0x0 : 0x1;
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> -				data << DPIO_UPAR_SHIFT);
> -	}
> -
> -	/* Data lane stagger programming */
> -	if (intel_crtc->config->port_clock > 270000)
> -		stagger = 0x18;
> -	else if (intel_crtc->config->port_clock > 135000)
> -		stagger = 0xd;
> -	else if (intel_crtc->config->port_clock > 67500)
> -		stagger = 0x7;
> -	else if (intel_crtc->config->port_clock > 33750)
> -		stagger = 0x4;
> -	else
> -		stagger = 0x2;
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> -	val |= DPIO_TX2_STAGGER_MASK(0x1f);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> -		val |= DPIO_TX2_STAGGER_MASK(0x1f);
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -	}
> -
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> -		       DPIO_LANESTAGGER_STRAP(stagger) |
> -		       DPIO_LANESTAGGER_STRAP_OVRD |
> -		       DPIO_TX1_STAGGER_MASK(0x1f) |
> -		       DPIO_TX1_STAGGER_MULT(6) |
> -		       DPIO_TX2_STAGGER_MULT(0));
> -
> -	if (intel_crtc->config->lane_count > 2) {
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> -			       DPIO_LANESTAGGER_STRAP(stagger) |
> -			       DPIO_LANESTAGGER_STRAP_OVRD |
> -			       DPIO_TX1_STAGGER_MASK(0x1f) |
> -			       DPIO_TX1_STAGGER_MULT(7) |
> -			       DPIO_TX2_STAGGER_MULT(5));
> -	}
> -
> -	/* Deassert data lane reset */
> -	chv_data_lane_soft_reset(encoder, false);
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	chv_phy_pre_encoder_enable(encoder);
>  
>  	intel_enable_dp(encoder);
>  
>  	/* Second common lane will stay alive on its own now */
> -	if (dport->release_cl2_override) {
> -		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> -		dport->release_cl2_override = false;
> -	}
> +	chv_phy_release_cl2_override(encoder);
>  }
>  
>  static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index b4ca3ff..ad0e7be 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -244,3 +244,95 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
>  
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
> +
> +void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel ch = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +	int data, i, stagger;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* allow hardware to manage TX FIFO reset source */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> +	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> +		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +	}
> +
> +	/* Program Tx lane latency optimal setting*/
> +	for (i = 0; i < intel_crtc->config->lane_count; i++) {
> +		/* Set the upar bit */
> +		if (intel_crtc->config->lane_count == 1)
> +			data = 0x0;
> +		else
> +			data = (i == 1) ? 0x0 : 0x1;
> +		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> +				data << DPIO_UPAR_SHIFT);
> +	}
> +
> +	/* Data lane stagger programming */
> +	if (intel_crtc->config->port_clock > 270000)
> +		stagger = 0x18;
> +	else if (intel_crtc->config->port_clock > 135000)
> +		stagger = 0xd;
> +	else if (intel_crtc->config->port_clock > 67500)
> +		stagger = 0x7;
> +	else if (intel_crtc->config->port_clock > 33750)
> +		stagger = 0x4;
> +	else
> +		stagger = 0x2;
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> +	val |= DPIO_TX2_STAGGER_MASK(0x1f);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> +		val |= DPIO_TX2_STAGGER_MASK(0x1f);
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +	}
> +
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> +		       DPIO_LANESTAGGER_STRAP(stagger) |
> +		       DPIO_LANESTAGGER_STRAP_OVRD |
> +		       DPIO_TX1_STAGGER_MASK(0x1f) |
> +		       DPIO_TX1_STAGGER_MULT(6) |
> +		       DPIO_TX2_STAGGER_MULT(0));
> +
> +	if (intel_crtc->config->lane_count > 2) {
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> +			       DPIO_LANESTAGGER_STRAP(stagger) |
> +			       DPIO_LANESTAGGER_STRAP_OVRD |
> +			       DPIO_TX1_STAGGER_MASK(0x1f) |
> +			       DPIO_TX1_STAGGER_MULT(7) |
> +			       DPIO_TX2_STAGGER_MULT(5));
> +	}
> +
> +	/* Deassert data lane reset */
> +	chv_data_lane_soft_reset(encoder, false);
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +void chv_phy_release_cl2_override(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	if (dport->release_cl2_override) {
> +		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> +		dport->release_cl2_override = false;
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e82d6e8..b4da7ee 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1736,68 +1736,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	struct intel_crtc *intel_crtc =
>  		to_intel_crtc(encoder->base.crtc);
>  	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
> -	enum dpio_channel ch = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -	int data, i, stagger;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* allow hardware to manage TX FIFO reset source */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> -	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> -	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -
> -	/* Program Tx latency optimal setting */
> -	for (i = 0; i < 4; i++) {
> -		/* Set the upar bit */
> -		data = (i == 1) ? 0x0 : 0x1;
> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> -				data << DPIO_UPAR_SHIFT);
> -	}
> -
> -	/* Data lane stagger programming */
> -	if (intel_crtc->config->port_clock > 270000)
> -		stagger = 0x18;
> -	else if (intel_crtc->config->port_clock > 135000)
> -		stagger = 0xd;
> -	else if (intel_crtc->config->port_clock > 67500)
> -		stagger = 0x7;
> -	else if (intel_crtc->config->port_clock > 33750)
> -		stagger = 0x4;
> -	else
> -		stagger = 0x2;
>  
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> -	val |= DPIO_TX2_STAGGER_MASK(0x1f);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> -	val |= DPIO_TX2_STAGGER_MASK(0x1f);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> -		       DPIO_LANESTAGGER_STRAP(stagger) |
> -		       DPIO_LANESTAGGER_STRAP_OVRD |
> -		       DPIO_TX1_STAGGER_MASK(0x1f) |
> -		       DPIO_TX1_STAGGER_MULT(6) |
> -		       DPIO_TX2_STAGGER_MULT(0));
> -
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> -		       DPIO_LANESTAGGER_STRAP(stagger) |
> -		       DPIO_LANESTAGGER_STRAP_OVRD |
> -		       DPIO_TX1_STAGGER_MASK(0x1f) |
> -		       DPIO_TX1_STAGGER_MULT(7) |
> -		       DPIO_TX2_STAGGER_MULT(5));
> -
> -	/* Deassert data lane reset */
> -	chv_data_lane_soft_reset(encoder, false);
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	chv_phy_pre_encoder_enable(encoder);
>  
>  	/* FIXME: Program the support xxx V-dB */
>  	/* Use 800mV-0dB */
> @@ -1812,10 +1752,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	vlv_wait_port_ready(dev_priv, dport, 0x0);
>  
>  	/* Second common lane will stay alive on its own now */
> -	if (dport->release_cl2_override) {
> -		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> -		dport->release_cl2_override = false;
> -	}
> +	chv_phy_release_cl2_override(encoder);
>  }
>  
>  static void intel_hdmi_destroy(struct drm_connector *connector)
> -- 
> 2.4.11
> 
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[PATCH v2 06/10] drm/i915: Undiplicate CHV encoders' post pll disable code

[Ander Conselvan de Oliveira]

The exact same code was used by HDMI and DP encoders, so move it to
intel_dpio_phy.c.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_dp.c       | 30 +-----------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 30 +-----------------------------
 4 files changed, 36 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f96c44..85c0610 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3563,6 +3563,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
+void chv_phy_post_disable(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76a825c..cdacd8b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2868,35 +2868,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* disable left/right clock distribution */
-	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-	} else {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-	}
-
-	mutex_unlock(&dev_priv->sb_lock);
-
-	/*
-	 * Leave the power down bit cleared for at least one
-	 * lane so that chv_powergate_phy_ch() will power
-	 * on something when the channel is otherwise unused.
-	 * When the port is off and the override is removed
-	 * the lanes power down anyway, so otherwise it doesn't
-	 * really matter what the state of power down bits is
-	 * after this.
-	 */
-	chv_phy_powergate_lanes(encoder, false, 0x0);
+	chv_phy_post_disable(encoder);
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index ad0e7be..2400554 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -336,3 +336,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
 		dport->release_cl2_override = false;
 	}
 }
+
+void chv_phy_post_disable(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
+	u32 val;
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	/* disable left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
+	mutex_unlock(&dev_priv->sb_lock);
+
+	/*
+	 * Leave the power down bit cleared for at least one
+	 * lane so that chv_powergate_phy_ch() will power
+	 * on something when the channel is otherwise unused.
+	 * When the port is off and the override is removed
+	 * the lanes power down anyway, so otherwise it doesn't
+	 * really matter what the state of power down bits is
+	 * after this.
+	 */
+	chv_phy_powergate_lanes(encoder, false, 0x0);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b4da7ee..f424af5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1667,35 +1667,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 
 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* disable left/right clock distribution */
-	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-	} else {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-	}
-
-	mutex_unlock(&dev_priv->sb_lock);
-
-	/*
-	 * Leave the power down bit cleared for at least one
-	 * lane so that chv_powergate_phy_ch() will power
-	 * on something when the channel is otherwise unused.
-	 * When the port is off and the override is removed
-	 * the lanes power down anyway, so otherwise it doesn't
-	 * really matter what the state of power down bits is
-	 * after this.
-	 */
-	chv_phy_powergate_lanes(encoder, false, 0x0);
+	chv_phy_post_disable(encoder);
 }
 
 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
-- 
2.4.11

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Re: [PATCH v2 06/10] drm/i915: Undiplicate CHV encoders' post pll disable code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:49PM +0300, Ander Conselvan de Oliveira wrote:
> The exact same code was used by HDMI and DP encoders, so move it to
> intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

There's a typo in the subject, but other than that:

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 30 +-----------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 30 +-----------------------------
>  4 files changed, 36 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6f96c44..85c0610 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3563,6 +3563,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> +void chv_phy_post_disable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 76a825c..cdacd8b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2868,35 +2868,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* disable left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/*
> -	 * Leave the power down bit cleared for at least one
> -	 * lane so that chv_powergate_phy_ch() will power
> -	 * on something when the channel is otherwise unused.
> -	 * When the port is off and the override is removed
> -	 * the lanes power down anyway, so otherwise it doesn't
> -	 * really matter what the state of power down bits is
> -	 * after this.
> -	 */
> -	chv_phy_powergate_lanes(encoder, false, 0x0);
> +	chv_phy_post_disable(encoder);
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index ad0e7be..2400554 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -336,3 +336,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
>  		dport->release_cl2_override = false;
>  	}
>  }
> +
> +void chv_phy_post_disable(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* disable left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +
> +	/*
> +	 * Leave the power down bit cleared for at least one
> +	 * lane so that chv_powergate_phy_ch() will power
> +	 * on something when the channel is otherwise unused.
> +	 * When the port is off and the override is removed
> +	 * the lanes power down anyway, so otherwise it doesn't
> +	 * really matter what the state of power down bits is
> +	 * after this.
> +	 */
> +	chv_phy_powergate_lanes(encoder, false, 0x0);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index b4da7ee..f424af5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1667,35 +1667,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* disable left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/*
> -	 * Leave the power down bit cleared for at least one
> -	 * lane so that chv_powergate_phy_ch() will power
> -	 * on something when the channel is otherwise unused.
> -	 * When the port is off and the override is removed
> -	 * the lanes power down anyway, so otherwise it doesn't
> -	 * really matter what the state of power down bits is
> -	 * after this.
> -	 */
> -	chv_phy_powergate_lanes(encoder, false, 0x0);
> +	chv_phy_post_disable(encoder);
>  }
>  
>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
> -- 
> 2.4.11
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Ander Conselvan de Oliveira]

The logic for setting signal levels is used for both HDMI and DP with
small variations. But it is similar enough to put behind a function
called from the encoders.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
 drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++-----------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
 4 files changed, 49 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85c0610..f2481a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
 void chv_phy_post_disable(struct intel_encoder *encoder);
 
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 demph_reg_value, u32 preemph_reg_value,
+			      u32 uniqtranscale_reg_value, u32 tx3_demph);
+
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cdacd8b..3e42355 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 
 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 {
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dport->base.base.crtc);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	unsigned long demph_reg_value, preemph_reg_value,
 		uniqtranscale_reg_value;
 	uint8_t train_set = intel_dp->train_set[0];
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 		return 0;
 	}
 
-	mutex_lock(&dev_priv->sb_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
-			 uniqtranscale_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+				 uniqtranscale_reg_value, 0);
 
 	return 0;
 }
@@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 		intel_dp->compliance_test_type = 0;
 		intel_dp->compliance_test_data = 0;
 
-		/*
-		 * If we were in MST mode, and device is not there,
-		 * get out of MST mode
-		 */
-		if (intel_dp->is_mst) {
-			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
-				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
-			intel_dp->is_mst = false;
-			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
-							intel_dp->is_mst);
-		}
 		goto out;
 	}
 
@@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 out:
 	if (status != connector_status_connected) {
 		intel_dp_unset_edid(intel_dp);
+
+		/*
+		 * If we were in MST mode, and device is not there,
+		 * get out of MST mode
+		 */
+		if (intel_dp->is_mst) {
+			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
+				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
+			intel_dp->is_mst = false;
+			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
+							intel_dp->is_mst);
+		}
 	}
 
 	intel_display_power_put(to_i915(dev), power_domain);
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 2400554..d9e6482 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
 	 */
 	chv_phy_powergate_lanes(encoder, false, 0x0);
 }
+
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 demph_reg_value, u32 preemph_reg_value,
+			      u32 uniqtranscale_reg_value, u32 tx3_demph)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
+			 uniqtranscale_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
+
+	if (tx3_demph)
+		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
+
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f424af5..9386772 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 	val |= 0x001000c4;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
 
-	/* HDMI 1.0V-2dB */
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
-
 	/* Program lane clock */
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
 	mutex_unlock(&dev_priv->sb_lock);
 
+	/* HDMI 1.0V-2dB */
+	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
+				 0x2b247878);
+
 	intel_hdmi->set_infoframes(&encoder->base,
 				   intel_crtc->config->has_hdmi_sink,
 				   adjusted_mode);
-- 
2.4.11

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Re: [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:
> The logic for setting signal levels is used for both HDMI and DP with
> small variations. But it is similar enough to put behind a function
> called from the encoders.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
>  drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++-----------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
>  4 files changed, 49 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85c0610..f2481a2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>  void chv_phy_post_disable(struct intel_encoder *encoder);
>  
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 demph_reg_value, u32 preemph_reg_value,
> +			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> +
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cdacd8b..3e42355 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  
>  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  {
> -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(dport->base.base.crtc);
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	unsigned long demph_reg_value, preemph_reg_value,
>  		uniqtranscale_reg_value;
>  	uint8_t train_set = intel_dp->train_set[0];
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
>  
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
>  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  		return 0;
>  	}
>  
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> -			 uniqtranscale_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> +				 uniqtranscale_reg_value, 0);
>  
>  	return 0;
>  }
> @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
>  		intel_dp->compliance_test_type = 0;
>  		intel_dp->compliance_test_data = 0;
>  
> -		/*
> -		 * If we were in MST mode, and device is not there,
> -		 * get out of MST mode
> -		 */
> -		if (intel_dp->is_mst) {
> -			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> -				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> -			intel_dp->is_mst = false;
> -			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> -							intel_dp->is_mst);
> -		}
>  		goto out;
>  	}
>  
> @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
>  out:
>  	if (status != connector_status_connected) {
>  		intel_dp_unset_edid(intel_dp);
> +
> +		/*
> +		 * If we were in MST mode, and device is not there,
> +		 * get out of MST mode
> +		 */
> +		if (intel_dp->is_mst) {
> +			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> +				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> +			intel_dp->is_mst = false;
> +			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> +							intel_dp->is_mst);
> +		}

The two hunks above seem unrelated to what the patch set is trying to do and
would break DP MST again. ;)

Jim


>  	}
>  
>  	intel_display_power_put(to_i915(dev), power_domain);
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2400554..d9e6482 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
>  	 */
>  	chv_phy_powergate_lanes(encoder, false, 0x0);
>  }
> +
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 demph_reg_value, u32 preemph_reg_value,
> +			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> +			 uniqtranscale_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> +
> +	if (tx3_demph)
> +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
> +
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f424af5..9386772 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	val |= 0x001000c4;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
>  
> -	/* HDMI 1.0V-2dB */
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> -
>  	/* Program lane clock */
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
>  	mutex_unlock(&dev_priv->sb_lock);
>  
> +	/* HDMI 1.0V-2dB */
> +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> +				 0x2b247878);
> +
>  	intel_hdmi->set_infoframes(&encoder->base,
>  				   intel_crtc->config->has_hdmi_sink,
>  				   adjusted_mode);
> -- 
> 2.4.11
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Jim Bride]

On Tue, Apr 19, 2016 at 01:37:26PM -0700, Jim Bride wrote:
> On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:

Same typo in this patch's subject ('Undiplicate') as the previous one.

Jim


> > The logic for setting signal levels is used for both HDMI and DP with
> > small variations. But it is similar enough to put behind a function
> > called from the encoders.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
> >  drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++-----------------------
> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
> >  4 files changed, 49 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 85c0610..f2481a2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
> >  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> >  void chv_phy_post_disable(struct intel_encoder *encoder);
> >  
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > +			      u32 demph_reg_value, u32 preemph_reg_value,
> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> > +
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> >  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index cdacd8b..3e42355 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> >  
> >  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  {
> > -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > -	struct intel_crtc *intel_crtc =
> > -		to_intel_crtc(dport->base.base.crtc);
> > +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >  	unsigned long demph_reg_value, preemph_reg_value,
> >  		uniqtranscale_reg_value;
> >  	uint8_t train_set = intel_dp->train_set[0];
> > -	enum dpio_channel port = vlv_dport_to_channel(dport);
> > -	int pipe = intel_crtc->pipe;
> >  
> >  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> >  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  		return 0;
> >  	}
> >  
> > -	mutex_lock(&dev_priv->sb_lock);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > -			 uniqtranscale_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> > -	mutex_unlock(&dev_priv->sb_lock);
> > +	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> > +				 uniqtranscale_reg_value, 0);
> >  
> >  	return 0;
> >  }
> > @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
> >  		intel_dp->compliance_test_type = 0;
> >  		intel_dp->compliance_test_data = 0;
> >  
> > -		/*
> > -		 * If we were in MST mode, and device is not there,
> > -		 * get out of MST mode
> > -		 */
> > -		if (intel_dp->is_mst) {
> > -			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> > -				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> > -			intel_dp->is_mst = false;
> > -			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > -							intel_dp->is_mst);
> > -		}
> >  		goto out;
> >  	}
> >  
> > @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
> >  out:
> >  	if (status != connector_status_connected) {
> >  		intel_dp_unset_edid(intel_dp);
> > +
> > +		/*
> > +		 * If we were in MST mode, and device is not there,
> > +		 * get out of MST mode
> > +		 */
> > +		if (intel_dp->is_mst) {
> > +			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> > +				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
> > +			intel_dp->is_mst = false;
> > +			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > +							intel_dp->is_mst);
> > +		}
> 
> The two hunks above seem unrelated to what the patch set is trying to do and
> would break DP MST again. ;)
> 
> Jim
> 
> 
> >  	}
> >  
> >  	intel_display_power_put(to_i915(dev), power_domain);
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 2400554..d9e6482 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
> >  	 */
> >  	chv_phy_powergate_lanes(encoder, false, 0x0);
> >  }
> > +
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > +			      u32 demph_reg_value, u32 preemph_reg_value,
> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> > +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> > +	enum dpio_channel port = vlv_dport_to_channel(dport);
> > +	int pipe = intel_crtc->pipe;
> > +
> > +	mutex_lock(&dev_priv->sb_lock);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > +			 uniqtranscale_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > +
> > +	if (tx3_demph)
> > +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
> > +
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> > +	mutex_unlock(&dev_priv->sb_lock);
> > +}
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index f424af5..9386772 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  	val |= 0x001000c4;
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
> >  
> > -	/* HDMI 1.0V-2dB */
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> > -
> >  	/* Program lane clock */
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> >  	mutex_unlock(&dev_priv->sb_lock);
> >  
> > +	/* HDMI 1.0V-2dB */
> > +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> > +				 0x2b247878);
> > +
> >  	intel_hdmi->set_infoframes(&encoder->base,
> >  				   intel_crtc->config->has_hdmi_sink,
> >  				   adjusted_mode);
> > -- 
> > 2.4.11
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Conselvan De Oliveira, Ander]

On Tue, 2016-04-19 at 13:37 -0700, Jim Bride wrote:
> On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:
> > The logic for setting signal levels is used for both HDMI and DP with
> > small variations. But it is similar enough to put behind a function
> > called from the encoders.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira <
> > ander.conselvan.de.oliveira@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
> >  drivers/gpu/drm/i915/intel_dp.c       | 43 ++++++++++++--------------------
> > ---
> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++--------
> >  4 files changed, 49 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 85c0610..f2481a2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder
> > *encoder);
> >  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> >  void chv_phy_post_disable(struct intel_encoder *encoder);
> >  
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > +			      u32 demph_reg_value, u32 preemph_reg_value,
> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> > +
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> >  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index cdacd8b..3e42355 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
> > uint8_t voltage_swing)
> >  
> >  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  {
> > -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > -	struct intel_crtc *intel_crtc =
> > -		to_intel_crtc(dport->base.base.crtc);
> > +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> >  	unsigned long demph_reg_value, preemph_reg_value,
> >  		uniqtranscale_reg_value;
> >  	uint8_t train_set = intel_dp->train_set[0];
> > -	enum dpio_channel port = vlv_dport_to_channel(dport);
> > -	int pipe = intel_crtc->pipe;
> >  
> >  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> >  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp
> > *intel_dp)
> >  		return 0;
> >  	}
> >  
> > -	mutex_lock(&dev_priv->sb_lock);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > -			 uniqtranscale_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port),
> > preemph_reg_value);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> > -	mutex_unlock(&dev_priv->sb_lock);
> > +	vlv_set_phy_signal_level(encoder, demph_reg_value,
> > preemph_reg_value,
> > +				 uniqtranscale_reg_value, 0);
> >  
> >  	return 0;
> >  }
> > @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector
> > *intel_connector)
> >  		intel_dp->compliance_test_type = 0;
> >  		intel_dp->compliance_test_data = 0;
> >  
> > -		/*
> > -		 * If we were in MST mode, and device is not there,
> > -		 * get out of MST mode
> > -		 */
> > -		if (intel_dp->is_mst) {
> > -			DRM_DEBUG_KMS("MST device may have disappeared %d
> > vs %d\n",
> > -				      intel_dp->is_mst, intel_dp
> > ->mst_mgr.mst_state);
> > -			intel_dp->is_mst = false;
> > -			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > -							intel_dp->is_mst);
> > -		}
> >  		goto out;
> >  	}
> >  
> > @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector
> > *intel_connector)
> >  out:
> >  	if (status != connector_status_connected) {
> >  		intel_dp_unset_edid(intel_dp);
> > +
> > +		/*
> > +		 * If we were in MST mode, and device is not there,
> > +		 * get out of MST mode
> > +		 */
> > +		if (intel_dp->is_mst) {
> > +			DRM_DEBUG_KMS("MST device may have disappeared %d
> > vs %d\n",
> > +				      intel_dp->is_mst, intel_dp
> > ->mst_mgr.mst_state);
> > +			intel_dp->is_mst = false;
> > +			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
> > +							intel_dp->is_mst);
> > +		}
> 
> The two hunks above seem unrelated to what the patch set is trying to do and
> would break DP MST again. ;)

I mixed things up when rebasing on top of your changes. I remember fixing that,
but alas, I didn't. 

Ander


> 
> Jim
> 
> 
> >  	}
> >  
> >  	intel_display_power_put(to_i915(dev), power_domain);
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 2400554..d9e6482 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder
> > *encoder)
> >  	 */
> >  	chv_phy_powergate_lanes(encoder, false, 0x0);
> >  }
> > +
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > +			      u32 demph_reg_value, u32 preemph_reg_value,
> > +			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> > +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> > +	enum dpio_channel port = vlv_dport_to_channel(dport);
> > +	int pipe = intel_crtc->pipe;
> > +
> > +	mutex_lock(&dev_priv->sb_lock);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > +			 uniqtranscale_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > +
> > +	if (tx3_demph)
> > +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port),
> > tx3_demph);
> > +
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port),
> > preemph_reg_value);
> > +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port),
> > DPIO_TX_OCALINIT_EN);
> > +	mutex_unlock(&dev_priv->sb_lock);
> > +}
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index f424af5..9386772 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder
> > *encoder)
> >  	val |= 0x001000c4;
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
> >  
> > -	/* HDMI 1.0V-2dB */
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> > -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port),
> > DPIO_TX_OCALINIT_EN);
> > -
> >  	/* Program lane clock */
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> >  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> >  	mutex_unlock(&dev_priv->sb_lock);
> >  
> > +	/* HDMI 1.0V-2dB */
> > +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000,
> > 0x5578b83a,
> > +				 0x2b247878);
> > +
> >  	intel_hdmi->set_infoframes(&encoder->base,
> >  				   intel_crtc->config->has_hdmi_sink,
> >  				   adjusted_mode);
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[PATCH v2 08/10] drm/i915: Unduplicate VLV phy pre pll enabling code

[Ander Conselvan de Oliveira]

The code used by the DP and HDMI paths was very similar, so make them
share it. Note that this removes the write to signal level registers
from the HDMI pre pll enable path, but that's OK since those are set
in vlv_hdmi_pre_enable() function.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_dp.c       | 25 +------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 28 +---------------------------
 4 files changed, 31 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2481a2..a002870 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3568,6 +3568,7 @@ void chv_phy_post_disable(struct intel_encoder *encoder);
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
+void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3e42355..4829ba9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2821,32 +2821,9 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 
 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 {
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-
 	intel_dp_prepare(encoder);
 
-	/* Program Tx lane resets to default */
-	mutex_lock(&dev_priv->sb_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
-			 DPIO_PCS_TX_LANE2_RESET |
-			 DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
-			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
-			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
-			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
-				 DPIO_PCS_CLK_SOFT_RESET);
-
-	/* Fix up inter-pair skew failure */
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_phy_pre_pll_enable(encoder);
 }
 
 static void chv_pre_enable_dp(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index d9e6482..846f35f 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -395,3 +395,31 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
 	mutex_unlock(&dev_priv->sb_lock);
 }
+
+void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+
+	/* Program Tx lane resets to default */
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
+			 DPIO_PCS_TX_LANE2_RESET |
+			 DPIO_PCS_TX_LANE1_RESET);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
+			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
+			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
+			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
+				 DPIO_PCS_CLK_SOFT_RESET);
+
+	/* Fix up inter-pair skew failure */
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9386772..f0c21e4 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1621,35 +1621,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 {
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-
 	intel_hdmi_prepare(encoder);
 
-	/* Program Tx lane resets to default */
-	mutex_lock(&dev_priv->sb_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
-			 DPIO_PCS_TX_LANE2_RESET |
-			 DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
-			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
-			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
-			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
-			 DPIO_PCS_CLK_SOFT_RESET);
-
-	/* Fix up inter-pair skew failure */
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
-
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_phy_pre_pll_enable(encoder);
 }
 
 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
-- 
2.4.11

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Re: [PATCH v2 08/10] drm/i915: Unduplicate VLV phy pre pll enabling code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:51PM +0300, Ander Conselvan de Oliveira wrote:
> The code used by the DP and HDMI paths was very similar, so make them
> share it. Note that this removes the write to signal level registers
> from the HDMI pre pll enable path, but that's OK since those are set
> in vlv_hdmi_pre_enable() function.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 25 +------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 28 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 28 +---------------------------
>  4 files changed, 31 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f2481a2..a002870 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3568,6 +3568,7 @@ void chv_phy_post_disable(struct intel_encoder *encoder);
>  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> +void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3e42355..4829ba9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2821,32 +2821,9 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
>  
>  static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -
>  	intel_dp_prepare(encoder);
>  
> -	/* Program Tx lane resets to default */
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> -			 DPIO_PCS_TX_LANE2_RESET |
> -			 DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> -			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> -			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> -			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> -				 DPIO_PCS_CLK_SOFT_RESET);
> -
> -	/* Fix up inter-pair skew failure */
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_pre_pll_enable(encoder);
>  }
>  
>  static void chv_pre_enable_dp(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index d9e6482..846f35f 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -395,3 +395,31 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
> +
> +void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	/* Program Tx lane resets to default */
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> +			 DPIO_PCS_TX_LANE2_RESET |
> +			 DPIO_PCS_TX_LANE1_RESET);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> +			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> +			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> +			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> +				 DPIO_PCS_CLK_SOFT_RESET);
> +
> +	/* Fix up inter-pair skew failure */
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9386772..f0c21e4 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1621,35 +1621,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>  
>  static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -
>  	intel_hdmi_prepare(encoder);
>  
> -	/* Program Tx lane resets to default */
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> -			 DPIO_PCS_TX_LANE2_RESET |
> -			 DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> -			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> -			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> -			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> -			 DPIO_PCS_CLK_SOFT_RESET);
> -
> -	/* Fix up inter-pair skew failure */
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> -
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_pre_pll_enable(encoder);
>  }
>  
>  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> -- 
> 2.4.11
> 
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[PATCH v2 09/10] drm/i915: Unduplicate pre encoder enabling phy code

[Ander Conselvan de Oliveira]

The phy code in vlv_pre_enable_dp() and vlv_hdmi_pre_enable() is
exectly the same, so extract it to intel_dpio_phy.c.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_dp.c       | 24 +-----------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 30 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 19 +------------------
 4 files changed, 33 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a002870..fad8ab2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3569,6 +3569,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4829ba9..1596c6d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2792,29 +2792,7 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
 
 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 {
-	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
-	val = 0;
-	if (pipe)
-		val |= (1<<21);
-	else
-		val &= ~(1<<21);
-	val |= 0x001000c4;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
-
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_phy_pre_encoder_enable(encoder);
 
 	intel_enable_dp(encoder);
 }
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 846f35f..4e1ce3a 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -423,3 +423,33 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
 	mutex_unlock(&dev_priv->sb_lock);
 }
+
+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+	u32 val;
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	/* Enable clock channels for this port */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
+	val = 0;
+	if (pipe)
+		val |= (1<<21);
+	else
+		val &= ~(1<<21);
+	val |= 0x001000c4;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
+
+	/* Program lane clock */
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
+
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f0c21e4..3794a54 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1586,25 +1586,8 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
 	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-	u32 val;
-
-	/* Enable clock channels for this port */
-	mutex_lock(&dev_priv->sb_lock);
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
-	val = 0;
-	if (pipe)
-		val |= (1<<21);
-	else
-		val &= ~(1<<21);
-	val |= 0x001000c4;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
 
-	/* Program lane clock */
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_phy_pre_encoder_enable(encoder);
 
 	/* HDMI 1.0V-2dB */
 	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
-- 
2.4.11

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Re: [PATCH v2 09/10] drm/i915: Unduplicate pre encoder enabling phy code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:52PM +0300, Ander Conselvan de Oliveira wrote:
> The phy code in vlv_pre_enable_dp() and vlv_hdmi_pre_enable() is
> exectly the same, so extract it to intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 24 +-----------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 30 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 19 +------------------
>  4 files changed, 33 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a002870..fad8ab2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3569,6 +3569,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph);
>  void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
> +void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4829ba9..1596c6d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2792,29 +2792,7 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
>  
>  static void vlv_pre_enable_dp(struct intel_encoder *encoder)
>  {
> -	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> -	val = 0;
> -	if (pipe)
> -		val |= (1<<21);
> -	else
> -		val &= ~(1<<21);
> -	val |= 0x001000c4;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_pre_encoder_enable(encoder);
>  
>  	intel_enable_dp(encoder);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 846f35f..4e1ce3a 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -423,3 +423,33 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
>  	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
> +
> +void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* Enable clock channels for this port */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> +	val = 0;
> +	if (pipe)
> +		val |= (1<<21);
> +	else
> +		val &= ~(1<<21);
> +	val |= 0x001000c4;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
> +
> +	/* Program lane clock */
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f0c21e4..3794a54 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1586,25 +1586,8 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	struct intel_crtc *intel_crtc =
>  		to_intel_crtc(encoder->base.crtc);
>  	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -	u32 val;
> -
> -	/* Enable clock channels for this port */
> -	mutex_lock(&dev_priv->sb_lock);
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> -	val = 0;
> -	if (pipe)
> -		val |= (1<<21);
> -	else
> -		val &= ~(1<<21);
> -	val |= 0x001000c4;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
>  
> -	/* Program lane clock */
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_pre_encoder_enable(encoder);
>  
>  	/* HDMI 1.0V-2dB */
>  	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> -- 
> 2.4.11
> 
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[PATCH v2 10/10] drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

This moves the last dpio phy specific code from the encoders to the phy
specific file.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_dpio_phy.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 12 +-----------
 3 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fad8ab2..1c9b1db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3570,6 +3570,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
+void vlv_phy_reset_lanes(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 4e1ce3a..9e1faaf 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -453,3 +453,18 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
 
 	mutex_unlock(&dev_priv->sb_lock);
 }
+
+void vlv_phy_reset_lanes(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(encoder->base.crtc);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 3794a54..07500aa 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1623,18 +1623,8 @@ static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
 
 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
 {
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(encoder->base.crtc);
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
-
 	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
-	mutex_lock(&dev_priv->sb_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_phy_reset_lanes(encoder);
 }
 
 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
-- 
2.4.11

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Re: [PATCH v2 10/10] drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:53PM +0300, Ander Conselvan de Oliveira wrote:
> This moves the last dpio phy specific code from the encoders to the phy
> specific file.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 12 +-----------
>  3 files changed, 17 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fad8ab2..1c9b1db 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3570,6 +3570,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph);
>  void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
> +void vlv_phy_reset_lanes(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 4e1ce3a..9e1faaf 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -453,3 +453,18 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
>  
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
> +
> +void vlv_phy_reset_lanes(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(encoder->base.crtc);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 3794a54..07500aa 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1623,18 +1623,8 @@ static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
>  
>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>  {
> -	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(encoder->base.crtc);
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
> -
>  	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_phy_reset_lanes(encoder);
>  }
>  
>  static void chv_hdmi_post_disable(struct intel_encoder *encoder)
> -- 
> 2.4.11
> 
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✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev3)

[Patchwork]

== Series Details ==

Series: Unduplicate CHV phy code (rev3)
URL   : https://patchwork.freedesktop.org/series/5463/
State : failure

== Summary ==

Series 5463v3 Unduplicate CHV phy code
http://patchwork.freedesktop.org/api/1.0/series/5463/revisions/3/mbox/

Test drv_module_reload_basic:
                pass       -> SKIP       (snb-x220t)
                pass       -> DMESG-WARN (ilk-hp8440p)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (bsw-nuc-2)

bdw-ultra        total:203  pass:180  dwarn:0   dfail:0   fail:0   skip:23 
bsw-nuc-2        total:202  pass:163  dwarn:0   dfail:0   fail:0   skip:39 
byt-nuc          total:202  pass:164  dwarn:0   dfail:0   fail:0   skip:38 
hsw-brixbox      total:203  pass:179  dwarn:0   dfail:0   fail:0   skip:24 
hsw-gt2          total:203  pass:184  dwarn:0   dfail:0   fail:0   skip:19 
ilk-hp8440p      total:203  pass:134  dwarn:1   dfail:0   fail:0   skip:68 
ivb-t430s        total:203  pass:175  dwarn:0   dfail:0   fail:0   skip:28 
skl-i7k-2        total:203  pass:178  dwarn:0   dfail:0   fail:0   skip:25 
skl-nuci5        total:203  pass:192  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:203  pass:165  dwarn:0   dfail:0   fail:0   skip:38 
snb-x220t        total:203  pass:164  dwarn:0   dfail:0   fail:1   skip:38 
BOOT FAILED for bdw-nuci7

Results at /archive/results/CI_IGT_test/Patchwork_1895/

88f5cc0db4ed45a3b5eec48e0ef909e5bc0ddead drm-intel-nightly: 2016y-04m-14d-09h-45m-59s UTC integration manifest
c1c72e1 drm/i915: Undiplicate CHV encoders' post pll disable code
c71a81d drm/i915: Unduplicate CHV pre-encoder enabling phy logic
aba23fa drm/i915: Unduplicate CHV phy-releated pre pll enabling code
5074828 drm/i915: Unduplicate chv_data_lane_soft_reset()
3090e58 drm/i915: Unduplicate CHV signal level code
c8dc113 drm/i915: Set crtc_state->lane_count for HDMI

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[PATCH v2 06/18] drm/i915: Unduplicate CHV encoders' post pll disable code

[Ander Conselvan de Oliveira]

The exact same code was used by HDMI and DP encoders, so move it to
intel_dpio_phy.c.

v2: Fix typo in the commit message. (Jim Bride)
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_dp.c       | 30 +-----------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 30 +-----------------------------
 4 files changed, 36 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3aca63f..9625b06 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3592,6 +3592,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
+void chv_phy_post_disable(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 114548d..9902aa7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2838,35 +2838,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* disable left/right clock distribution */
-	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-	} else {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-	}
-
-	mutex_unlock(&dev_priv->sb_lock);
-
-	/*
-	 * Leave the power down bit cleared for at least one
-	 * lane so that chv_powergate_phy_ch() will power
-	 * on something when the channel is otherwise unused.
-	 * When the port is off and the override is removed
-	 * the lanes power down anyway, so otherwise it doesn't
-	 * really matter what the state of power down bits is
-	 * after this.
-	 */
-	chv_phy_powergate_lanes(encoder, false, 0x0);
+	chv_phy_post_disable(encoder);
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index ad0e7be..2400554 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -336,3 +336,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
 		dport->release_cl2_override = false;
 	}
 }
+
+void chv_phy_post_disable(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
+	u32 val;
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	/* disable left/right clock distribution */
+	if (pipe != PIPE_B) {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+	} else {
+		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+	}
+
+	mutex_unlock(&dev_priv->sb_lock);
+
+	/*
+	 * Leave the power down bit cleared for at least one
+	 * lane so that chv_powergate_phy_ch() will power
+	 * on something when the channel is otherwise unused.
+	 * When the port is off and the override is removed
+	 * the lanes power down anyway, so otherwise it doesn't
+	 * really matter what the state of power down bits is
+	 * after this.
+	 */
+	chv_phy_powergate_lanes(encoder, false, 0x0);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b4da7ee..f424af5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1667,35 +1667,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 
 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
-	u32 val;
-
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* disable left/right clock distribution */
-	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
-		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
-	} else {
-		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
-		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
-	}
-
-	mutex_unlock(&dev_priv->sb_lock);
-
-	/*
-	 * Leave the power down bit cleared for at least one
-	 * lane so that chv_powergate_phy_ch() will power
-	 * on something when the channel is otherwise unused.
-	 * When the port is off and the override is removed
-	 * the lanes power down anyway, so otherwise it doesn't
-	 * really matter what the state of power down bits is
-	 * after this.
-	 */
-	chv_phy_powergate_lanes(encoder, false, 0x0);
+	chv_phy_post_disable(encoder);
 }
 
 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
-- 
2.4.11

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Re: [PATCH v2 06/18] drm/i915: Unduplicate CHV encoders' post pll disable code

[Jim Bride]

On Wed, Apr 20, 2016 at 08:20:48AM +0300, Ander Conselvan de Oliveira wrote:
> The exact same code was used by HDMI and DP encoders, so move it to
> intel_dpio_phy.c.
> 
> v2: Fix typo in the commit message. (Jim Bride)
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_dp.c       | 30 +-----------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 30 +-----------------------------
>  4 files changed, 36 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3aca63f..9625b06 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3592,6 +3592,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
>  void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> +void chv_phy_post_disable(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 114548d..9902aa7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2838,35 +2838,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* disable left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/*
> -	 * Leave the power down bit cleared for at least one
> -	 * lane so that chv_powergate_phy_ch() will power
> -	 * on something when the channel is otherwise unused.
> -	 * When the port is off and the override is removed
> -	 * the lanes power down anyway, so otherwise it doesn't
> -	 * really matter what the state of power down bits is
> -	 * after this.
> -	 */
> -	chv_phy_powergate_lanes(encoder, false, 0x0);
> +	chv_phy_post_disable(encoder);
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index ad0e7be..2400554 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -336,3 +336,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
>  		dport->release_cl2_override = false;
>  	}
>  }
> +
> +void chv_phy_post_disable(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +
> +	/* disable left/right clock distribution */
> +	if (pipe != PIPE_B) {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> +		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> +	} else {
> +		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> +		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> +		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> +	}
> +
> +	mutex_unlock(&dev_priv->sb_lock);
> +
> +	/*
> +	 * Leave the power down bit cleared for at least one
> +	 * lane so that chv_powergate_phy_ch() will power
> +	 * on something when the channel is otherwise unused.
> +	 * When the port is off and the override is removed
> +	 * the lanes power down anyway, so otherwise it doesn't
> +	 * really matter what the state of power down bits is
> +	 * after this.
> +	 */
> +	chv_phy_powergate_lanes(encoder, false, 0x0);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index b4da7ee..f424af5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1667,35 +1667,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  
>  static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -
> -	/* disable left/right clock distribution */
> -	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> -		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> -	} else {
> -		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> -		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> -	}
> -
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/*
> -	 * Leave the power down bit cleared for at least one
> -	 * lane so that chv_powergate_phy_ch() will power
> -	 * on something when the channel is otherwise unused.
> -	 * When the port is off and the override is removed
> -	 * the lanes power down anyway, so otherwise it doesn't
> -	 * really matter what the state of power down bits is
> -	 * after this.
> -	 */
> -	chv_phy_powergate_lanes(encoder, false, 0x0);
> +	chv_phy_post_disable(encoder);
>  }
>  
>  static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
> -- 
> 2.4.11
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[PATCH v2 07/18] drm/i915: Undiplicate VLV signal level code

[Ander Conselvan de Oliveira]

The logic for setting signal levels is used for both HDMI and DP with
small variations. But it is similar enough to put behind a function
called from the encoders.

v2: Remove unrelated MST changes due to rebase fumble. (Jim Bride)
    Fix typo in the commit message. (Jim Bride)

Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
 drivers/gpu/drm/i915/intel_dp.c       | 20 +++-----------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++----------
 4 files changed, 37 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9625b06..c6c457c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3594,6 +3594,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
 void chv_phy_post_disable(struct intel_encoder *encoder);
 
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 demph_reg_value, u32 preemph_reg_value,
+			      u32 uniqtranscale_reg_value, u32 tx3_demph);
+
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9902aa7..b4dd9be 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2979,16 +2979,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 
 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 {
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-	struct intel_crtc *intel_crtc =
-		to_intel_crtc(dport->base.base.crtc);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	unsigned long demph_reg_value, preemph_reg_value,
 		uniqtranscale_reg_value;
 	uint8_t train_set = intel_dp->train_set[0];
-	enum dpio_channel port = vlv_dport_to_channel(dport);
-	int pipe = intel_crtc->pipe;
 
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3063,16 +3057,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
 		return 0;
 	}
 
-	mutex_lock(&dev_priv->sb_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
-			 uniqtranscale_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
-	mutex_unlock(&dev_priv->sb_lock);
+	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+				 uniqtranscale_reg_value, 0);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 2400554..d9e6482 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
 	 */
 	chv_phy_powergate_lanes(encoder, false, 0x0);
 }
+
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      u32 demph_reg_value, u32 preemph_reg_value,
+			      u32 uniqtranscale_reg_value, u32 tx3_demph)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
+	int pipe = intel_crtc->pipe;
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
+			 uniqtranscale_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
+
+	if (tx3_demph)
+		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
+
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
+	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
+	mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f424af5..9386772 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 	val |= 0x001000c4;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
 
-	/* HDMI 1.0V-2dB */
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
-	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
-
 	/* Program lane clock */
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
 	mutex_unlock(&dev_priv->sb_lock);
 
+	/* HDMI 1.0V-2dB */
+	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
+				 0x2b247878);
+
 	intel_hdmi->set_infoframes(&encoder->base,
 				   intel_crtc->config->has_hdmi_sink,
 				   adjusted_mode);
-- 
2.4.11

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Re: [PATCH v2 07/18] drm/i915: Undiplicate VLV signal level code

[Jim Bride]

On Wed, Apr 20, 2016 at 08:22:31AM +0300, Ander Conselvan de Oliveira wrote:
> The logic for setting signal levels is used for both HDMI and DP with
> small variations. But it is similar enough to put behind a function
> called from the encoders.
> 
> v2: Remove unrelated MST changes due to rebase fumble. (Jim Bride)
>     Fix typo in the commit message. (Jim Bride)
> 
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

The typo is still in the commit message subject, but with that fixed:

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  4 ++++
>  drivers/gpu/drm/i915/intel_dp.c       | 20 +++-----------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 ++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 14 ++++----------
>  4 files changed, 37 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9625b06..c6c457c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3594,6 +3594,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>  void chv_phy_post_disable(struct intel_encoder *encoder);
>  
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 demph_reg_value, u32 preemph_reg_value,
> +			      u32 uniqtranscale_reg_value, u32 tx3_demph);
> +
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9902aa7..b4dd9be 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2979,16 +2979,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  
>  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  {
> -	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> -	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(dport->base.base.crtc);
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  	unsigned long demph_reg_value, preemph_reg_value,
>  		uniqtranscale_reg_value;
>  	uint8_t train_set = intel_dp->train_set[0];
> -	enum dpio_channel port = vlv_dport_to_channel(dport);
> -	int pipe = intel_crtc->pipe;
>  
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
>  	case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3063,16 +3057,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  		return 0;
>  	}
>  
> -	mutex_lock(&dev_priv->sb_lock);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> -			 uniqtranscale_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> -	mutex_unlock(&dev_priv->sb_lock);
> +	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> +				 uniqtranscale_reg_value, 0);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2400554..d9e6482 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -369,3 +369,29 @@ void chv_phy_post_disable(struct intel_encoder *encoder)
>  	 */
>  	chv_phy_powergate_lanes(encoder, false, 0x0);
>  }
> +
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +			      u32 demph_reg_value, u32 preemph_reg_value,
> +			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> +	enum dpio_channel port = vlv_dport_to_channel(dport);
> +	int pipe = intel_crtc->pipe;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> +			 uniqtranscale_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> +
> +	if (tx3_demph)
> +		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
> +
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> +	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f424af5..9386772 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1601,21 +1601,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>  	val |= 0x001000c4;
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
>  
> -	/* HDMI 1.0V-2dB */
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> -	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> -
>  	/* Program lane clock */
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
>  	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
>  	mutex_unlock(&dev_priv->sb_lock);
>  
> +	/* HDMI 1.0V-2dB */
> +	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
> +				 0x2b247878);
> +
>  	intel_hdmi->set_infoframes(&encoder->base,
>  				   intel_crtc->config->has_hdmi_sink,
>  				   adjusted_mode);
> -- 
> 2.4.11
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