[PATCH v2 0/3] ARM: dts: lpc32xx: update ssp / spi nodes

[PATCH v2 0/3] ARM: dts: lpc32xx: update ssp / spi nodes

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>

This patchset change the following:
1) adds clock properties to spi peripheral devices,
   clock ids are taken from dt-bindings/clock/lpc32xx-clock.h.

2) enable SSP0 used by PHY3250.
   preparatory change prior to disabling SSPx controllers.

3) disable, by default, the SSP0/SPI1 and SSP1/SPI2 shared pinout;
   shared pin should be enable in board specific dts, as needed.
---
Changes from v1 to v2:
* Update the patch as per the feedback received from:
  Arnd: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493250
  - Start subject with "ARM" instead of "arm".
  - Add a multi-line description for trivial patches.
  Vladimir: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493323
            http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493324
  - Remove "clock-names" property.
  - Switch patch #2 and #3 order.
* Rebased on the following patch:
  http://permalink.gmane.org/gmane.linux.drivers.devicetree/164584/

Sylvain Lemieux (3):
  ARM: dts: lpc32xx: add clock properties to spi nodes
  ARM: dts: phy3250: enable ssp0
  ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default

 arch/arm/boot/dts/lpc32xx.dtsi | 14 ++++++++++++++
 arch/arm/boot/dts/phy3250.dts  |  1 +
 2 files changed, 15 insertions(+)

-- 
1.8.3.1

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[PATCH v2 0/3] ARM: dts: lpc32xx: update ssp / spi nodes

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux@tycoint.com>

This patchset change the following:
1) adds clock properties to spi peripheral devices,
   clock ids are taken from dt-bindings/clock/lpc32xx-clock.h.

2) enable SSP0 used by PHY3250.
   preparatory change prior to disabling SSPx controllers.

3) disable, by default, the SSP0/SPI1 and SSP1/SPI2 shared pinout;
   shared pin should be enable in board specific dts, as needed.
---
Changes from v1 to v2:
* Update the patch as per the feedback received from:
  Arnd: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493250
  - Start subject with "ARM" instead of "arm".
  - Add a multi-line description for trivial patches.
  Vladimir: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493323
            http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493324
  - Remove "clock-names" property.
  - Switch patch #2 and #3 order.
* Rebased on the following patch:
  http://permalink.gmane.org/gmane.linux.drivers.devicetree/164584/

Sylvain Lemieux (3):
  ARM: dts: lpc32xx: add clock properties to spi nodes
  ARM: dts: phy3250: enable ssp0
  ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default

 arch/arm/boot/dts/lpc32xx.dtsi | 14 ++++++++++++++
 arch/arm/boot/dts/phy3250.dts  |  1 +
 2 files changed, 15 insertions(+)

-- 
1.8.3.1

[PATCH v2 1/3] ARM: dts: lpc32xx: add clock properties to spi nodes

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>

The change adds clock properties to spi peripheral devices,
clock ids are taken from dt-bindings/clock/lpc32xx-clock.h

Signed-off-by: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index d7b84cd..1b2f351 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -173,6 +173,7 @@
 			spi1: spi@20088000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20088000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI1>;
 			};
 
 			ssp1: ssp@2008c000 {
@@ -186,6 +187,7 @@
 			spi2: spi@20090000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20090000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI2>;
 			};
 
 			i2s0: i2s@20094000 {
-- 
1.8.3.1

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[PATCH v2 1/3] ARM: dts: lpc32xx: add clock properties to spi nodes

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux@tycoint.com>

The change adds clock properties to spi peripheral devices,
clock ids are taken from dt-bindings/clock/lpc32xx-clock.h

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index d7b84cd..1b2f351 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -173,6 +173,7 @@
 			spi1: spi at 20088000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20088000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI1>;
 			};
 
 			ssp1: ssp at 2008c000 {
@@ -186,6 +187,7 @@
 			spi2: spi at 20090000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20090000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI2>;
 			};
 
 			i2s0: i2s at 20094000 {
-- 
1.8.3.1

[PATCH v2 2/3] ARM: dts: phy3250: enable ssp0

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>

Preparatory change prior to disabling SSPx controllers
by default in the shared LPC32xx DTSI file.

Signed-off-by: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/phy3250.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index a00d7ce..26e070f 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -146,6 +146,7 @@
 				#size-cells = <0>;
 				num-cs = <1>;
 				cs-gpios = <&gpio 3 5 0>;
+				status = "okay";
 
 				eeprom: at25@0 {
 					pl022,interface = <0>;
-- 
1.8.3.1

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[PATCH v2 2/3] ARM: dts: phy3250: enable ssp0

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux@tycoint.com>

Preparatory change prior to disabling SSPx controllers
by default in the shared LPC32xx DTSI file.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
---
 arch/arm/boot/dts/phy3250.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index a00d7ce..26e070f 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -146,6 +146,7 @@
 				#size-cells = <0>;
 				num-cs = <1>;
 				cs-gpios = <&gpio 3 5 0>;
+				status = "okay";
 
 				eeprom: at25 at 0 {
 					pl022,interface = <0>;
-- 
1.8.3.1

[PATCH v2 3/3] ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>

The SSP0/SPI1 and SSP1/SPI2 shared pinout and should be disable by default.

Board specific dts should enable them, as needed.

Signed-off-by: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1b2f351..73c4746 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -162,32 +162,44 @@
 			compatible = "simple-bus";
 			ranges = <0x20000000 0x20000000 0x30000000>;
 
+			/*
+			 * ssp0 and spi1 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
 			ssp0: ssp@20084000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x20084000 0x1000>;
 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SSP0>;
 				clock-names = "apb_pclk";
+				status = "disabled";
 			};
 
 			spi1: spi@20088000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20088000 0x1000>;
 				clocks = <&clk LPC32XX_CLK_SPI1>;
+				status = "disabled";
 			};
 
+			/*
+			 * ssp1 and spi2 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
 			ssp1: ssp@2008c000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x2008c000 0x1000>;
 				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SSP1>;
 				clock-names = "apb_pclk";
+				status = "disabled";
 			};
 
 			spi2: spi@20090000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20090000 0x1000>;
 				clocks = <&clk LPC32XX_CLK_SPI2>;
+				status = "disabled";
 			};
 
 			i2s0: i2s@20094000 {
-- 
1.8.3.1

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[PATCH v2 3/3] ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default

[Sylvain Lemieux]

From: Sylvain Lemieux <slemieux@tycoint.com>

The SSP0/SPI1 and SSP1/SPI2 shared pinout and should be disable by default.

Board specific dts should enable them, as needed.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
---
 arch/arm/boot/dts/lpc32xx.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1b2f351..73c4746 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -162,32 +162,44 @@
 			compatible = "simple-bus";
 			ranges = <0x20000000 0x20000000 0x30000000>;
 
+			/*
+			 * ssp0 and spi1 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
 			ssp0: ssp at 20084000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x20084000 0x1000>;
 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SSP0>;
 				clock-names = "apb_pclk";
+				status = "disabled";
 			};
 
 			spi1: spi at 20088000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20088000 0x1000>;
 				clocks = <&clk LPC32XX_CLK_SPI1>;
+				status = "disabled";
 			};
 
+			/*
+			 * ssp1 and spi2 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
 			ssp1: ssp at 2008c000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x2008c000 0x1000>;
 				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_SSP1>;
 				clock-names = "apb_pclk";
+				status = "disabled";
 			};
 
 			spi2: spi at 20090000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20090000 0x1000>;
 				clocks = <&clk LPC32XX_CLK_SPI2>;
+				status = "disabled";
 			};
 
 			i2s0: i2s at 20094000 {
-- 
1.8.3.1

Re: [PATCH v2 0/3] ARM: dts: lpc32xx: update ssp / spi nodes

[Vladimir Zapolskiy]

Hi Sylvain,

On 20.04.2016 16:20, Sylvain Lemieux wrote:
> From: Sylvain Lemieux <slemieux-1xCVI8+nB4ZBDgjK7y7TUQ@public.gmane.org>
> 
> This patchset change the following:
> 1) adds clock properties to spi peripheral devices,
>    clock ids are taken from dt-bindings/clock/lpc32xx-clock.h.
> 
> 2) enable SSP0 used by PHY3250.
>    preparatory change prior to disabling SSPx controllers.
> 
> 3) disable, by default, the SSP0/SPI1 and SSP1/SPI2 shared pinout;
>    shared pin should be enable in board specific dts, as needed.
> ---
> Changes from v1 to v2:
> * Update the patch as per the feedback received from:
>   Arnd: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493250
>   - Start subject with "ARM" instead of "arm".
>   - Add a multi-line description for trivial patches.
>   Vladimir: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493323
>             http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493324
>   - Remove "clock-names" property.
>   - Switch patch #2 and #3 order.
> * Rebased on the following patch:
>   http://permalink.gmane.org/gmane.linux.drivers.devicetree/164584/
> 
> Sylvain Lemieux (3):
>   ARM: dts: lpc32xx: add clock properties to spi nodes
>   ARM: dts: phy3250: enable ssp0
>   ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 14 ++++++++++++++
>  arch/arm/boot/dts/phy3250.dts  |  1 +
>  2 files changed, 15 insertions(+)
> 

all changes in the series are good from my point of view, I'll apply
them shortly.

Acked-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>

--
With best wishes,
Vladimir
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[PATCH v2 0/3] ARM: dts: lpc32xx: update ssp / spi nodes

[Vladimir Zapolskiy]

Hi Sylvain,

On 20.04.2016 16:20, Sylvain Lemieux wrote:
> From: Sylvain Lemieux <slemieux@tycoint.com>
> 
> This patchset change the following:
> 1) adds clock properties to spi peripheral devices,
>    clock ids are taken from dt-bindings/clock/lpc32xx-clock.h.
> 
> 2) enable SSP0 used by PHY3250.
>    preparatory change prior to disabling SSPx controllers.
> 
> 3) disable, by default, the SSP0/SPI1 and SSP1/SPI2 shared pinout;
>    shared pin should be enable in board specific dts, as needed.
> ---
> Changes from v1 to v2:
> * Update the patch as per the feedback received from:
>   Arnd: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493250
>   - Start subject with "ARM" instead of "arm".
>   - Add a multi-line description for trivial patches.
>   Vladimir: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493323
>             http://permalink.gmane.org/gmane.linux.ports.arm.kernel/493324
>   - Remove "clock-names" property.
>   - Switch patch #2 and #3 order.
> * Rebased on the following patch:
>   http://permalink.gmane.org/gmane.linux.drivers.devicetree/164584/
> 
> Sylvain Lemieux (3):
>   ARM: dts: lpc32xx: add clock properties to spi nodes
>   ARM: dts: phy3250: enable ssp0
>   ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 14 ++++++++++++++
>  arch/arm/boot/dts/phy3250.dts  |  1 +
>  2 files changed, 15 insertions(+)
> 

all changes in the series are good from my point of view, I'll apply
them shortly.

Acked-by: Vladimir Zapolskiy <vz@mleia.com>

--
With best wishes,
Vladimir