[U-Boot] [PATCH 0/7] hikey

[U-Boot] [PATCH 0/7] hikey

[Peter Griffin]

Hi folks,

This patchset start the conversion of the hikey U-Boot port over
to being DT enabled. As more DT lands in the upstream kernel
the plan is to convert more drivers in U-Boot to use it. Currently
only serial driver is using DT, and the other drivers still use
platform data.

It also updates and simplifies the README, including updating the
mcuimage.bin location which leads to the additional a53 cores
not coming online correctly if using an outdated binary.

Additionally I've added myself as MAINTAINER of the hikey U-Boot port.

regards,

Peter.

Peter Griffin (7):
  ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.
  MAINTAINERS: Add myself as maintainer for hikey
  ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.
  ARM: hisilicon: hikey: Implement reset_cpu() for hikey.
  ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.
  ARM: hisilicon: hikey: Align memory node with upstream kernel
  ARM: hikey: Simplify README instructions.

 MAINTAINERS                              |   6 +
 arch/arm/Kconfig                         |   1 +
 arch/arm/dts/Makefile                    |   2 +
 arch/arm/dts/hi6220-hikey.dts            |  41 ++++++
 arch/arm/dts/hi6220.dtsi                 | 218 +++++++++++++++++++++++++++++++
 board/hisilicon/hikey/MAINTAINERS        |   6 +
 board/hisilicon/hikey/README             |  95 +++++++-------
 board/hisilicon/hikey/hikey.c            |  37 +++++-
 configs/hikey_defconfig                  |   1 +
 include/configs/hikey.h                  |   2 +-
 include/dt-bindings/clock/hi6220-clock.h | 173 ++++++++++++++++++++++++
 11 files changed, 532 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/dts/hi6220-hikey.dts
 create mode 100644 arch/arm/dts/hi6220.dtsi
 create mode 100644 board/hisilicon/hikey/MAINTAINERS
 create mode 100644 include/dt-bindings/clock/hi6220-clock.h

-- 
1.9.1

[U-Boot] [PATCH 1/7] ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.

[Peter Griffin]

Import the upstream kernel dts into U-Boot. Currently
only serial is supported, but a lot more DT changes are
queued for v4.7.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/dts/hi6220-hikey.dts            |  41 ++++++
 arch/arm/dts/hi6220.dtsi                 | 213 +++++++++++++++++++++++++++++++
 include/dt-bindings/clock/hi6220-clock.h | 173 +++++++++++++++++++++++++
 3 files changed, 427 insertions(+)
 create mode 100644 arch/arm/dts/hi6220-hikey.dts
 create mode 100644 arch/arm/dts/hi6220.dtsi
 create mode 100644 include/dt-bindings/clock/hi6220-clock.h

diff --git a/arch/arm/dts/hi6220-hikey.dts b/arch/arm/dts/hi6220-hikey.dts
new file mode 100644
index 0000000..8185251
--- /dev/null
+++ b/arch/arm/dts/hi6220-hikey.dts
@@ -0,0 +1,41 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e00000 0x00100000;
+
+#include "hi6220.dtsi"
+
+/ {
+	model = "HiKey Development Board";
+	compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+	aliases {
+		serial0 = &uart0; /* On board UART0 */
+		serial1 = &uart1; /* BT UART */
+		serial2 = &uart2; /* LS Expansion UART0 */
+		serial3 = &uart3; /* LS Expansion UART1 */
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&uart2 {
+	label = "LS-UART0";
+};
+&uart3 {
+	label = "LS-UART1";
+};
diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi
new file mode 100644
index 0000000..ad1f1eb
--- /dev/null
+++ b/arch/arm/dts/hi6220.dtsi
@@ -0,0 +1,213 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi6220-clock.h>
+
+/ {
+	compatible = "hisilicon,hi6220";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu at 2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu at 3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu at 100 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu at 101 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu at 102 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x102>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu at 103 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x103>;
+			enable-method = "psci";
+		};
+	};
+
+	gic: interrupt-controller at f6801000 {
+		compatible = "arm,gic-400";
+		reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
+		      <0x0 0xf6802000 0 0x2000>, /* GICC */
+		      <0x0 0xf6804000 0 0x2000>, /* GICH */
+		      <0x0 0xf6806000 0 0x2000>; /* GICV */
+		#address-cells = <0>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ao_ctrl: ao_ctrl at f7800000 {
+			compatible = "hisilicon,hi6220-aoctrl", "syscon";
+			reg = <0x0 0xf7800000 0x0 0x2000>;
+			#clock-cells = <1>;
+		};
+
+		sys_ctrl: sys_ctrl at f7030000 {
+			compatible = "hisilicon,hi6220-sysctrl", "syscon";
+			reg = <0x0 0xf7030000 0x0 0x2000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		media_ctrl: media_ctrl at f4410000 {
+			compatible = "hisilicon,hi6220-mediactrl", "syscon";
+			reg = <0x0 0xf4410000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		pm_ctrl: pm_ctrl at f7032000 {
+			compatible = "hisilicon,hi6220-pmctrl", "syscon";
+			reg = <0x0 0xf7032000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		uart0: uart at f8015000 {	/* console */
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf8015000 0x0 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
+				 <&ao_ctrl HI6220_UART0_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		uart1: uart at f7111000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7111000 0x0 0x1000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
+				 <&sys_ctrl HI6220_UART1_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: uart at f7112000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7112000 0x0 0x1000>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
+				 <&sys_ctrl HI6220_UART2_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: uart at f7113000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7113000 0x0 0x1000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
+				 <&sys_ctrl HI6220_UART3_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		uart4: uart at f7114000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7114000 0x0 0x1000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
+				 <&sys_ctrl HI6220_UART4_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
new file mode 100644
index 0000000..70ee383
--- /dev/null
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK	0
+
+/* fixed rate clocks */
+#define HI6220_REF32K		1
+#define HI6220_CLK_TCXO		2
+#define HI6220_MMC1_PAD		3
+#define HI6220_MMC2_PAD		4
+#define HI6220_MMC0_PAD		5
+#define HI6220_PLL_BBP		6
+#define HI6220_PLL_GPU		7
+#define HI6220_PLL1_DDR		8
+#define HI6220_PLL_SYS		9
+#define HI6220_PLL_SYS_MEDIA	10
+#define HI6220_DDR_SRC		11
+#define HI6220_PLL_MEDIA	12
+#define HI6220_PLL_DDR		13
+
+/* fixed factor clocks */
+#define HI6220_300M		14
+#define HI6220_150M		15
+#define HI6220_PICOPHY_SRC	16
+#define HI6220_MMC0_SRC_SEL	17
+#define HI6220_MMC1_SRC_SEL	18
+#define HI6220_MMC2_SRC_SEL	19
+#define HI6220_VPU_CODEC	20
+#define HI6220_MMC0_SMP		21
+#define HI6220_MMC1_SMP		22
+#define HI6220_MMC2_SMP		23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK	24
+#define HI6220_WDT1_PCLK	25
+#define HI6220_WDT2_PCLK	26
+#define HI6220_TIMER0_PCLK	27
+#define HI6220_TIMER1_PCLK	28
+#define HI6220_TIMER2_PCLK	29
+#define HI6220_TIMER3_PCLK	30
+#define HI6220_TIMER4_PCLK	31
+#define HI6220_TIMER5_PCLK	32
+#define HI6220_TIMER6_PCLK	33
+#define HI6220_TIMER7_PCLK	34
+#define HI6220_TIMER8_PCLK	35
+#define HI6220_UART0_PCLK	36
+
+#define HI6220_AO_NR_CLKS	37
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK		1
+#define HI6220_MMC0_CIUCLK	2
+#define HI6220_MMC1_CLK		3
+#define HI6220_MMC1_CIUCLK	4
+#define HI6220_MMC2_CLK		5
+#define HI6220_MMC2_CIUCLK	6
+#define HI6220_USBOTG_HCLK	7
+#define HI6220_CLK_PICOPHY	8
+#define HI6220_HIFI		9
+#define HI6220_DACODEC_PCLK	10
+#define HI6220_EDMAC_ACLK	11
+#define HI6220_CS_ATB		12
+#define HI6220_I2C0_CLK		13
+#define HI6220_I2C1_CLK		14
+#define HI6220_I2C2_CLK		15
+#define HI6220_I2C3_CLK		16
+#define HI6220_UART1_PCLK	17
+#define HI6220_UART2_PCLK	18
+#define HI6220_UART3_PCLK	19
+#define HI6220_UART4_PCLK	20
+#define HI6220_SPI_CLK		21
+#define HI6220_TSENSOR_CLK	22
+#define HI6220_MMU_CLK		23
+#define HI6220_HIFI_SEL		24
+#define HI6220_MMC0_SYSPLL	25
+#define HI6220_MMC1_SYSPLL	26
+#define HI6220_MMC2_SYSPLL	27
+#define HI6220_MMC0_SEL		28
+#define HI6220_MMC1_SEL		29
+#define HI6220_BBPPLL_SEL	30
+#define HI6220_MEDIA_PLL_SRC	31
+#define HI6220_MMC2_SEL		32
+#define HI6220_CS_ATB_SYSPLL	33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC		34
+#define HI6220_MMC0_SMP_IN	35
+#define HI6220_MMC1_SRC		36
+#define HI6220_MMC1_SMP_IN	37
+#define HI6220_MMC2_SRC		38
+#define HI6220_MMC2_SMP_IN	39
+#define HI6220_HIFI_SRC		40
+#define HI6220_UART1_SRC	41
+#define HI6220_UART2_SRC	42
+#define HI6220_UART3_SRC	43
+#define HI6220_UART4_SRC	44
+#define HI6220_MMC0_MUX0	45
+#define HI6220_MMC1_MUX0	46
+#define HI6220_MMC2_MUX0	47
+#define HI6220_MMC0_MUX1	48
+#define HI6220_MMC1_MUX1	49
+#define HI6220_MMC2_MUX1	50
+
+/* divider clocks */
+#define HI6220_CLK_BUS		51
+#define HI6220_MMC0_DIV		52
+#define HI6220_MMC1_DIV		53
+#define HI6220_MMC2_DIV		54
+#define HI6220_HIFI_DIV		55
+#define HI6220_BBPPLL0_DIV	56
+#define HI6220_CS_DAPB		57
+#define HI6220_CS_ATB_DIV	58
+
+#define HI6220_SYS_NR_CLKS	59
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK		1
+#define HI6220_G3D_PCLK		2
+#define HI6220_ACLK_CODEC_VPU	3
+#define HI6220_ISP_SCLK		4
+#define HI6220_ADE_CORE		5
+#define HI6220_MED_MMU		6
+#define HI6220_CFG_CSI4PHY	7
+#define HI6220_CFG_CSI2PHY	8
+#define HI6220_ISP_SCLK_GATE	9
+#define HI6220_ISP_SCLK_GATE1	10
+#define HI6220_ADE_CORE_GATE	11
+#define HI6220_CODEC_VPU_GATE	12
+#define HI6220_MED_SYSPLL	13
+
+/* mux clocks */
+#define HI6220_1440_1200	14
+#define HI6220_1000_1200	15
+#define HI6220_1000_1440	16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG	17
+#define HI6220_ISP_SCLK_SRC	18
+#define HI6220_ISP_SCLK1	19
+#define HI6220_ADE_CORE_SRC	20
+#define HI6220_ADE_PIX_SRC	21
+#define HI6220_G3D_CLK		22
+#define HI6220_CODEC_VPU_SRC	23
+
+#define HI6220_MEDIA_NR_CLKS	24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE	1
+#define HI6220_PLL1_DDR_GATE	2
+#define HI6220_PLL_DDR_GATE	3
+#define HI6220_PLL_MEDIA_GATE	4
+#define HI6220_PLL0_BBP_GATE	5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC		6
+#define HI6220_DDRC_AXI1	7
+
+#define HI6220_POWER_NR_CLKS	8
+#endif
-- 
1.9.1

[U-Boot] [PATCH 2/7] MAINTAINERS: Add myself as maintainer for hikey

[Peter Griffin]

This patch adds myself as maintainer for the hikey
U-Boot port.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 MAINTAINERS                       | 6 ++++++
 board/hisilicon/hikey/MAINTAINERS | 6 ++++++
 2 files changed, 12 insertions(+)
 create mode 100644 board/hisilicon/hikey/MAINTAINERS

diff --git a/MAINTAINERS b/MAINTAINERS
index 87e0c2e..d328524 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -93,6 +93,12 @@ F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/imx-common/
 
+ARM HISILICON
+M:	Peter Griffin <peter.griffin@linaro.org>
+S:	Maintained
+F:	arch/arm/cpu/armv8/hisilicon
+F:	arm/include/asm/arch-hi6220/
+
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
 M:	Prafulla Wadaskar <prafulla@marvell.com>
 M:	Luka Perkov <luka.perkov@sartura.hr>
diff --git a/board/hisilicon/hikey/MAINTAINERS b/board/hisilicon/hikey/MAINTAINERS
new file mode 100644
index 0000000..11088ee
--- /dev/null
+++ b/board/hisilicon/hikey/MAINTAINERS
@@ -0,0 +1,6 @@
+HIKEY BOARD
+M:     Peter Griffin <peter.griffin@linaro.org>
+S:     Maintained
+F:     board/hisilicon/hikey
+F:     include/configs/hikey.h
+F:     configs/hikey_defconfig
-- 
1.9.1

[U-Boot] [PATCH 3/7] ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.

[Peter Griffin]

Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/Kconfig              | 1 +
 arch/arm/dts/Makefile         | 2 ++
 board/hisilicon/hikey/hikey.c | 3 +++
 configs/hikey_defconfig       | 1 +
 4 files changed, 7 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf5e18a..fa506bb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -668,6 +668,7 @@ config TARGET_HIKEY
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select OF_CONTROL
 	  help
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0da9e3b..4d1981c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -11,6 +11,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4412-trats2.dtb \
 	exynos4412-odroid.dtb
 
+dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
+
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-spring.dtb \
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 3b484a9..3f0a0cc 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -71,6 +71,8 @@ U_BOOT_DEVICES(hi6220_gpios) = {
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+
 static const struct pl01x_serial_platdata serial_platdata = {
 #if CONFIG_CONS_INDEX == 1
 	.base = HI6220_UART0_BASE,
@@ -87,6 +89,7 @@ U_BOOT_DEVICE(hikey_seriala) = {
 	.name = "serial_pl01x",
 	.platdata = &serial_platdata,
 };
+#endif
 
 static struct mm_region hikey_mem_map[] = {
 	{
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 8b75642..e7b7496 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -3,3 +3,4 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
-- 
1.9.1

[U-Boot] [PATCH 4/7] ARM: hisilicon: hikey: Implement reset_cpu() for hikey.

[Peter Griffin]

This allows the reset command to reset the board from
u-boot.

=> reset
resetting ...
INFO:    BL1: 0xf9810000 - 0xf9818000 [size = 32768]
NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v1.1(debug):7fb9b0e
NOTICE:  BL1: Built : 17:06:41, Apr 19 2016

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 board/hisilicon/hikey/hikey.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 3f0a0cc..752ee6f 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -414,8 +414,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
-/* Use the Watchdog to cause reset */
 void reset_cpu(ulong addr)
 {
-	/* TODO program the watchdog */
+	writel(0x48698284, &ao_sc->stat0);
+	wfi();
 }
-- 
1.9.1

[U-Boot] [PATCH 5/7] ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.

[Peter Griffin]

This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/dts/hi6220.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi
index ad1f1eb..a610ccb 100644
--- a/arch/arm/dts/hi6220.dtsi
+++ b/arch/arm/dts/hi6220.dtsi
@@ -166,6 +166,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf8015000 0x0 0x1000>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 				 <&ao_ctrl HI6220_UART0_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -175,6 +176,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7111000 0x0 0x1000>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 				 <&sys_ctrl HI6220_UART1_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -185,6 +187,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7112000 0x0 0x1000>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 				 <&sys_ctrl HI6220_UART2_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -195,6 +198,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7113000 0x0 0x1000>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 				 <&sys_ctrl HI6220_UART3_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -204,6 +208,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7114000 0x0 0x1000>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 				 <&sys_ctrl HI6220_UART4_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
-- 
1.9.1

[U-Boot] [PATCH 6/7] ARM: hisilicon: hikey: Align memory node with upstream kernel

[Peter Griffin]

The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.

However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 board/hisilicon/hikey/hikey.c | 30 +++++++++++++++++++++++++++++-
 include/configs/hikey.h       |  2 +-
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 752ee6f..7abc678 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -410,8 +410,36 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
+	/*
+	 * Reserve regions below from DT memory node (which gets generated
+	 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
+	 * the kernel. This will then match the kernel hikey dts memory node.
+	 *
+	 *  0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
+	 *  0x05f0,1000 - 0x05f0,1fff: Reboot reason
+	 *  0x06df,f000 - 0x06df,ffff: Mailbox message data
+	 *  0x0740,f000 - 0x0740,ffff: MCU firmware section
+	 *  0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
+	 *  0x3e00,0000 - 0x3fff,ffff: OP-TEE
+	*/
+
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[0].size = 0x05e00000;
+
+	gd->bd->bi_dram[1].start = 0x05f00000;
+	gd->bd->bi_dram[1].size = 0x00001000;
+
+	gd->bd->bi_dram[2].start = 0x05f02000;
+	gd->bd->bi_dram[2].size = 0x00efd000;
+
+	gd->bd->bi_dram[3].start = 0x06e00000;
+	gd->bd->bi_dram[3].size = 0x0060f000;
+
+	gd->bd->bi_dram[4].start = 0x07410000;
+	gd->bd->bi_dram[4].size = 0x1aaf0000;
+
+	gd->bd->bi_dram[5].start = 0x22000000;
+	gd->bd->bi_dram[5].size = 0x1c000000;
 }
 
 void reset_cpu(ulong addr)
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 0851626..69ea7dc 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -33,7 +33,7 @@
 /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
 #define CONFIG_SYS_TEXT_BASE		0x35000000
 
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		6
 #define PHYS_SDRAM_1			0x00000000
 
 /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
-- 
1.9.1

[U-Boot] [PATCH 7/7] ARM: hikey: Simplify README instructions.

[Peter Griffin]

This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.

This patch also updates the link to the mcuimage.bin which was outdated.

Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 board/hisilicon/hikey/README | 95 +++++++++++++++++++++++---------------------
 1 file changed, 49 insertions(+), 46 deletions(-)

diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README
index 36adbdb..0f6aab7 100644
--- a/board/hisilicon/hikey/README
+++ b/board/hisilicon/hikey/README
@@ -22,50 +22,55 @@ Currently the u-boot port supports: -
 * SD card
 * GPIO
 
-Compile u-boot
-==============
+The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
+U-Boot as the bl33.bin executable.
 
-  > mkdir -p ./aarch64/bin
-  > cd ./aarch64
-  > git clone http://git.denx.de/u-boot.git
-  > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
-  > make CROSS_COMPILE=aarch64-linux-gnu-
-  > cp u-boot.bin ./aarch64/bin/u-boot-hikey.bin
+Compile from source
+===================
 
-ARM Trusted Firmware (ATF) & l-loader
-=====================================
+First get all the sources
 
-This u-boot port has been tested with l-loader, booting ATF, which then boots
-u-boot as the bl33.bin executable.
+  > mkdir -p ~/hikey/src ~/hikey/bin
+  > cd ~/hikey/src
+  > git clone https://github.com/96boards/edk2.git
+  > git clone https://github.com/96boards/arm-trusted-firmware.git
+  > git clone https://github.com/96boards/l-loader.git
+  > git clone https://github.com/96boards/burn-boot.git
 
-Get the BL30 mcu binary.
-  > wget -P aarch64/bin https://builds.96boards.org/releases/hikey/linaro/binaries/15.05/mcuimage.bin
+Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the edk2 repo.
 
-1. Get ATF source code
-  > cd ./aarch64
-  > git clone https://github.com/96boards/arm-trusted-firmware.git
-  > cd ./arm-trusted-firmware
+  > cp edk2/HisiPkg/HiKeyPkg/NonFree/mcuimage.bin ~/hikey/bin/
 
-2. Compile ATF, I use the build-tf.mak in the directory with this README, and copy it to ATF directory
-  > cp ../u-boot/board/hisilicon/hikey/build-tf.mak .
-  > make -f  build-tf.mak build
+Get nvme.img binary (check this link is still the latest)
+  > wget -P ~/hikey/bin https://builds.96boards.org/releases/reference-platform/debian/hikey/16.03/bootloader/nvme.img
 
-3. Get l-loader
-  > cd ../
-  > git clone https://github.com/96boards/l-loader.git
-  > cd ./l-loader
+Compile U-Boot
+==============
 
-4. Make sym links to ATF bl1 / fip binaries
-  > ln -s ../bin/bl1-hikey.bin bl1.bin
-  > ln -s ../bin/fip-hikey.bin fip.bin
+  > cd ~/hikey/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/hikey/bin
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+  > cd ~/hikey/src/atf
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+    BL30=~/hikey/bin/mcuimage.bin \
+    BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
 
-  > arm-linux-gnueabihf-gcc -c -o start.o start.S
-  > arm-linux-gnueabihf-gcc -c -o debug.o debug.S
-  > arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader
-  > arm-linux-gnueabihf-objcopy -O binary loader temp
-  > python gen_loader.py -o ../bin/l-loader.bin --img_loader=temp --img_bl1=bl1.bin
-  > sudo bash -x generate_ptable.sh
-  > python gen_loader.py -o ../bin/ptable.img --img_prm_ptable=./prm_ptable.img --img_sec_ptable=./sec_ptable.img
+Copy resulting binaries
+  > cp build/hikey/debug/bl1.bin ~/hikey/bin
+  > cp build/hikey/debug/fip.bin ~/hikey/bin
+
+Compile l-loader
+===============
+  > cd ~/hikey/l-loader
+  > make BL1=~/hikey/bin/bl1.bin all
+  > cp *.img ~/hikey/bin
+  > cp l-loader.bin ~/hikey.bin
 
 These instructions are adapted from
 https://github.com/96boards/documentation/wiki/HiKeyUEFI
@@ -74,15 +79,12 @@ FLASHING
 ========
 
 1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
-fastboot using the hisi-idt.py utility.
-
-  > cd ../
-  > git clone https://github.com/96boards/burn-boot.git
+the hisi-idt.py utility.
 
 The command below assumes HiKey enumerated as the first USB serial port
-  > sudo ./burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=./bin/l-loader.bin
+  > sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin
 
-2. Once LED 0 comes on solid, it should be detected as a fastboot device by plugging a USB A to mini B
+2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B
    cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable).
 
   > sudo fastboot devices
@@ -90,10 +92,10 @@ The command below assumes HiKey enumerated as the first USB serial port
 0123456789ABCDEF	fastboot
 
 3. Flash the images
-  > wget -P aarch64/bin wget https://builds.96boards.org/releases/hikey/linaro/binaries/latest/nvme.img
-  > sudo fastboot flash ptable ./bin/ptable.img
-  > sudo fastboot flash fastboot ./bin/fip-hikey.bin
-  > sudo fastboot flash nvme ./bin/nvme.img
+
+  > sudo fastboot flash ptable ~/hikey/bin/ptable.img
+  > sudo fastboot flash fastboot ~/hikey/bin/fip.bin
+  > sudo fastboot flash nvme ~/hikey/bin/nvme.img
 
 4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
    have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the
@@ -102,7 +104,8 @@ The command below assumes HiKey enumerated as the first USB serial port
    Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
    will get 'dwc_otg_core_host_init: Timeout!' errors.
 
-See working boot trace below: -
+See working boot trace below (by default trace is now output to UART3 not UART0 on latest
+ATF, U-Boot and Kernel sources): -
 
 debug EMMC boot: send RST_N .
 debug EMMC boot: start eMMC boot......
-- 
1.9.1

[U-Boot] [PATCH 1/7] ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:13:57PM +0100, Peter Griffin wrote:

> Import the upstream kernel dts into U-Boot. Currently
> only serial is supported, but a lot more DT changes are
> queued for v4.7.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 2/7] MAINTAINERS: Add myself as maintainer for hikey

[Tom Rini]

On Wed, Apr 20, 2016 at 05:13:58PM +0100, Peter Griffin wrote:

> This patch adds myself as maintainer for the hikey
> U-Boot port.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 3/7] ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:13:59PM +0100, Peter Griffin wrote:

> Currently only the serial pl01x driver is using DT,
> and the other drivers still use platform data but
> as more DT lands in the upstream kernel the aim is
> to migrate the other drivers over to DT as well to
> have a fully DT configured hikey u-boot.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 4/7] ARM: hisilicon: hikey: Implement reset_cpu() for hikey.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:00PM +0100, Peter Griffin wrote:

> This allows the reset command to reset the board from
> u-boot.
> 
> => reset
> resetting ...
> INFO:    BL1: 0xf9810000 - 0xf9818000 [size = 32768]
> NOTICE:  Booting Trusted Firmware
> NOTICE:  BL1: v1.1(debug):7fb9b0e
> NOTICE:  BL1: Built : 17:06:41, Apr 19 2016
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 5/7] ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:01PM +0100, Peter Griffin wrote:

> This is a binding which only exists in U-Boot, but is
> required to get working serial in U-Boot.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 6/7] ARM: hisilicon: hikey: Align memory node with upstream kernel

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:02PM +0100, Peter Griffin wrote:

> The memory node gets automatically generated by U-Boot
> in arch_fixup_fdt(), before passing control to the kernel
> using U-Boots representation of the dram banks.
> 
> However the upstream kernel uses the memory node to carve-out
> regions of RAM for various purposes. To make this work without
> changing arch_fixup_fdt() which will effect many platforms
> we replicate the upstream memory node layout using the dram
> banks.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 7/7] ARM: hikey: Simplify README instructions.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:03PM +0100, Peter Griffin wrote:

> This patch updates and simplifies the hikey README. The old
> instructions were hard to follow, and convoluted.
> 
> This patch also updates the link to the mcuimage.bin which was outdated.
> 
> Using an outdated mcuimage.bin results in the additional a53 cores
> not coming online when the kernel issues PSCI requests to
> arm trusted firmware (ATF).
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [U-Boot, 1/7] ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:13:57PM +0100, Peter Griffin wrote:

> Import the upstream kernel dts into U-Boot. Currently
> only serial is supported, but a lot more DT changes are
> queued for v4.7.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 2/7] MAINTAINERS: Add myself as maintainer for hikey

[Tom Rini]

On Wed, Apr 20, 2016 at 05:13:58PM +0100, Peter Griffin wrote:

> This patch adds myself as maintainer for the hikey
> U-Boot port.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 3/7] ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:13:59PM +0100, Peter Griffin wrote:

> Currently only the serial pl01x driver is using DT,
> and the other drivers still use platform data but
> as more DT lands in the upstream kernel the aim is
> to migrate the other drivers over to DT as well to
> have a fully DT configured hikey u-boot.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 4/7] ARM: hisilicon: hikey: Implement reset_cpu() for hikey.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:00PM +0100, Peter Griffin wrote:

> This allows the reset command to reset the board from
> u-boot.
> 
> => reset
> resetting ...
> INFO:    BL1: 0xf9810000 - 0xf9818000 [size = 32768]
> NOTICE:  Booting Trusted Firmware
> NOTICE:  BL1: v1.1(debug):7fb9b0e
> NOTICE:  BL1: Built : 17:06:41, Apr 19 2016
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 5/7] ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:01PM +0100, Peter Griffin wrote:

> This is a binding which only exists in U-Boot, but is
> required to get working serial in U-Boot.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 6/7] ARM: hisilicon: hikey: Align memory node with upstream kernel

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:02PM +0100, Peter Griffin wrote:

> The memory node gets automatically generated by U-Boot
> in arch_fixup_fdt(), before passing control to the kernel
> using U-Boots representation of the dram banks.
> 
> However the upstream kernel uses the memory node to carve-out
> regions of RAM for various purposes. To make this work without
> changing arch_fixup_fdt() which will effect many platforms
> we replicate the upstream memory node layout using the dram
> banks.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 7/7] ARM: hikey: Simplify README instructions.

[Tom Rini]

On Wed, Apr 20, 2016 at 05:14:03PM +0100, Peter Griffin wrote:

> This patch updates and simplifies the hikey README. The old
> instructions were hard to follow, and convoluted.
> 
> This patch also updates the link to the mcuimage.bin which was outdated.
> 
> Using an outdated mcuimage.bin results in the additional a53 cores
> not coming online when the kernel issues PSCI requests to
> arm trusted firmware (ATF).
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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