[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers.  They are mapped at
    the address SSCDAWCARMR + 4 * N, where N is the CPU number.

The outer cache frame work does not support a per-CPU init callback.
So this commit adopts [2]; the master CPU iterates over possible CPUs
setting up SSCDAWCARMR(N) registers.

Unfortunately, the register offsets for SSCDAWCARMR(N) are different
by SoC.  We can live with it by checking the version register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers.  They are mapped at
    the address SSCDAWCARMR + 4 * N, where N is the CPU number.

The outer cache frame work does not support a per-CPU init callback.
So this commit adopts [2]; the master CPU iterates over possible CPUs
setting up SSCDAWCARMR(N) registers.

Unfortunately, the register offsets for SSCDAWCARMR(N) are different
by SoC.  We can live with it by checking the version register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register for its own.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers, where all instances
    of SSCLPDAWCR are mirrored.  They are mapped at the address
    SSCDAWCARMR + 4 * N, where N is the CPU number.

The outer cache frame work does not support a per-CPU init callback.
So this commit adopts [2]; the master CPU iterates over possible CPUs
setting up SSCDAWCARMR(N) registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

KernelVersion: 4.6-rc4


 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register for its own.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers, where all instances
    of SSCLPDAWCR are mirrored.  They are mapped at the address
    SSCDAWCARMR + 4 * N, where N is the CPU number.

The outer cache frame work does not support a per-CPU init callback.
So this commit adopts [2]; the master CPU iterates over possible CPUs
setting up SSCDAWCARMR(N) registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

KernelVersion: 4.6-rc4


 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

2016-04-26 16:52 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
>> Hi Arnd,
>>
>> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
>> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> >> This outer cache allows to control active ways independently for
>> >> each CPU, but currently nothing is done for secondary CPUs.  In
>> >> other words, all the ways are locked for secondary CPUs by default.
>> >> This commit fixes it to fully bring out the performance of this
>> >> outer cache.
>> >>
>> >> There would be two possible ways to achieve this:
>> >>
>> >> [1] Each CPU initializes active ways for itself.  This can be done
>> >>     via the SSCLPDAWCR register.  This is a banked register, so each
>> >>     CPU sees a different instance of the register.
>> >>
>> >> [2] The master CPU initializes active ways for all the CPUs.  This
>> >>     is available via SSCDAWCARMR(N) registers.  They are mapped at
>> >>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
>> >>
>> >> Currently, the outer cache frame work does not support a per-CPU
>> >> init callback.  So this commit adopts [2]; the master CPU iterates
>> >> over possible CPUs setting up SSCDAWCARMR(N) registers.
>> >>
>> >> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
>> >> by SoC.  We can live with it by checking the version register.
>> >>
>> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>> >>
>> >
>> > Applied to next/soc, thanks!
>> >
>> > I'm a little lost with the patches you send, could you check that
>> > I have applied all the ones you sent for 4.7 so far?
>> >
>> >         Arnd
>>
>>
>> Was this one really applied, or not yet?
>>
>> My intention was to send this one just for review,
>> because outer-cache things are generally in Russell's field.
>>
>> If you have already applied it, I should drop it
>> from Russell's patch tracker.
>> (Sorry, I should have mentioned it.)
>>
>> Please let me know the status.
>
> Sorry, my mistake, I accidentally sent out my mail early and
> then did not put it into arm-soc in the end.
>
> It's not in arm-soc and it should go through Russell's patch tracker.

OK.

The others look good to me.

Thanks!


-- 
Best Regards
Masahiro Yamada

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

2016-04-26 16:52 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
>> Hi Arnd,
>>
>> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
>> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> >> This outer cache allows to control active ways independently for
>> >> each CPU, but currently nothing is done for secondary CPUs.  In
>> >> other words, all the ways are locked for secondary CPUs by default.
>> >> This commit fixes it to fully bring out the performance of this
>> >> outer cache.
>> >>
>> >> There would be two possible ways to achieve this:
>> >>
>> >> [1] Each CPU initializes active ways for itself.  This can be done
>> >>     via the SSCLPDAWCR register.  This is a banked register, so each
>> >>     CPU sees a different instance of the register.
>> >>
>> >> [2] The master CPU initializes active ways for all the CPUs.  This
>> >>     is available via SSCDAWCARMR(N) registers.  They are mapped at
>> >>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
>> >>
>> >> Currently, the outer cache frame work does not support a per-CPU
>> >> init callback.  So this commit adopts [2]; the master CPU iterates
>> >> over possible CPUs setting up SSCDAWCARMR(N) registers.
>> >>
>> >> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
>> >> by SoC.  We can live with it by checking the version register.
>> >>
>> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>> >>
>> >
>> > Applied to next/soc, thanks!
>> >
>> > I'm a little lost with the patches you send, could you check that
>> > I have applied all the ones you sent for 4.7 so far?
>> >
>> >         Arnd
>>
>>
>> Was this one really applied, or not yet?
>>
>> My intention was to send this one just for review,
>> because outer-cache things are generally in Russell's field.
>>
>> If you have already applied it, I should drop it
>> from Russell's patch tracker.
>> (Sorry, I should have mentioned it.)
>>
>> Please let me know the status.
>
> Sorry, my mistake, I accidentally sent out my mail early and
> then did not put it into arm-soc in the end.
>
> It's not in arm-soc and it should go through Russell's patch tracker.

OK.

The others look good to me.

Thanks!


-- 
Best Regards
Masahiro Yamada

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Arnd Bergmann]

On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
> Hi Arnd,
> 
> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> >> This outer cache allows to control active ways independently for
> >> each CPU, but currently nothing is done for secondary CPUs.  In
> >> other words, all the ways are locked for secondary CPUs by default.
> >> This commit fixes it to fully bring out the performance of this
> >> outer cache.
> >>
> >> There would be two possible ways to achieve this:
> >>
> >> [1] Each CPU initializes active ways for itself.  This can be done
> >>     via the SSCLPDAWCR register.  This is a banked register, so each
> >>     CPU sees a different instance of the register.
> >>
> >> [2] The master CPU initializes active ways for all the CPUs.  This
> >>     is available via SSCDAWCARMR(N) registers.  They are mapped at
> >>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
> >>
> >> Currently, the outer cache frame work does not support a per-CPU
> >> init callback.  So this commit adopts [2]; the master CPU iterates
> >> over possible CPUs setting up SSCDAWCARMR(N) registers.
> >>
> >> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
> >> by SoC.  We can live with it by checking the version register.
> >>
> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> >>
> >
> > Applied to next/soc, thanks!
> >
> > I'm a little lost with the patches you send, could you check that
> > I have applied all the ones you sent for 4.7 so far?
> >
> >         Arnd
> 
> 
> Was this one really applied, or not yet?
> 
> My intention was to send this one just for review,
> because outer-cache things are generally in Russell's field.
> 
> If you have already applied it, I should drop it
> from Russell's patch tracker.
> (Sorry, I should have mentioned it.)
> 
> Please let me know the status.

Sorry, my mistake, I accidentally sent out my mail early and
then did not put it into arm-soc in the end.

It's not in arm-soc and it should go through Russell's patch tracker.

	Arnd

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Arnd Bergmann]

On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
> Hi Arnd,
> 
> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> >> This outer cache allows to control active ways independently for
> >> each CPU, but currently nothing is done for secondary CPUs.  In
> >> other words, all the ways are locked for secondary CPUs by default.
> >> This commit fixes it to fully bring out the performance of this
> >> outer cache.
> >>
> >> There would be two possible ways to achieve this:
> >>
> >> [1] Each CPU initializes active ways for itself.  This can be done
> >>     via the SSCLPDAWCR register.  This is a banked register, so each
> >>     CPU sees a different instance of the register.
> >>
> >> [2] The master CPU initializes active ways for all the CPUs.  This
> >>     is available via SSCDAWCARMR(N) registers.  They are mapped at
> >>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
> >>
> >> Currently, the outer cache frame work does not support a per-CPU
> >> init callback.  So this commit adopts [2]; the master CPU iterates
> >> over possible CPUs setting up SSCDAWCARMR(N) registers.
> >>
> >> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
> >> by SoC.  We can live with it by checking the version register.
> >>
> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> >>
> >
> > Applied to next/soc, thanks!
> >
> > I'm a little lost with the patches you send, could you check that
> > I have applied all the ones you sent for 4.7 so far?
> >
> >         Arnd
> 
> 
> Was this one really applied, or not yet?
> 
> My intention was to send this one just for review,
> because outer-cache things are generally in Russell's field.
> 
> If you have already applied it, I should drop it
> from Russell's patch tracker.
> (Sorry, I should have mentioned it.)
> 
> Please let me know the status.

Sorry, my mistake, I accidentally sent out my mail early and
then did not put it into arm-soc in the end.

It's not in arm-soc and it should go through Russell's patch tracker.

	Arnd

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

Hi Arnd,

2016-04-26 7:13 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> This outer cache allows to control active ways independently for
>> each CPU, but currently nothing is done for secondary CPUs.  In
>> other words, all the ways are locked for secondary CPUs by default.
>> This commit fixes it to fully bring out the performance of this
>> outer cache.
>>
>> There would be two possible ways to achieve this:
>>
>> [1] Each CPU initializes active ways for itself.  This can be done
>>     via the SSCLPDAWCR register.  This is a banked register, so each
>>     CPU sees a different instance of the register.
>>
>> [2] The master CPU initializes active ways for all the CPUs.  This
>>     is available via SSCDAWCARMR(N) registers.  They are mapped at
>>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
>>
>> Currently, the outer cache frame work does not support a per-CPU
>> init callback.  So this commit adopts [2]; the master CPU iterates
>> over possible CPUs setting up SSCDAWCARMR(N) registers.
>>
>> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
>> by SoC.  We can live with it by checking the version register.
>>
>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>>
>
> Applied to next/soc, thanks!
>
> I'm a little lost with the patches you send, could you check that
> I have applied all the ones you sent for 4.7 so far?
>
>         Arnd


Was this one really applied, or not yet?

My intention was to send this one just for review,
because outer-cache things are generally in Russell's field.

If you have already applied it, I should drop it
from Russell's patch tracker.
(Sorry, I should have mentioned it.)

Please let me know the status.

-- 
Best Regards
Masahiro Yamada

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

Hi Arnd,

2016-04-26 7:13 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> This outer cache allows to control active ways independently for
>> each CPU, but currently nothing is done for secondary CPUs.  In
>> other words, all the ways are locked for secondary CPUs by default.
>> This commit fixes it to fully bring out the performance of this
>> outer cache.
>>
>> There would be two possible ways to achieve this:
>>
>> [1] Each CPU initializes active ways for itself.  This can be done
>>     via the SSCLPDAWCR register.  This is a banked register, so each
>>     CPU sees a different instance of the register.
>>
>> [2] The master CPU initializes active ways for all the CPUs.  This
>>     is available via SSCDAWCARMR(N) registers.  They are mapped at
>>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
>>
>> Currently, the outer cache frame work does not support a per-CPU
>> init callback.  So this commit adopts [2]; the master CPU iterates
>> over possible CPUs setting up SSCDAWCARMR(N) registers.
>>
>> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
>> by SoC.  We can live with it by checking the version register.
>>
>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>>
>
> Applied to next/soc, thanks!
>
> I'm a little lost with the patches you send, could you check that
> I have applied all the ones you sent for 4.7 so far?
>
>         Arnd


Was this one really applied, or not yet?

My intention was to send this one just for review,
because outer-cache things are generally in Russell's field.

If you have already applied it, I should drop it
from Russell's patch tracker.
(Sorry, I should have mentioned it.)

Please let me know the status.

-- 
Best Regards
Masahiro Yamada

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Arnd Bergmann]

On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> This outer cache allows to control active ways independently for
> each CPU, but currently nothing is done for secondary CPUs.  In
> other words, all the ways are locked for secondary CPUs by default.
> This commit fixes it to fully bring out the performance of this
> outer cache.
> 
> There would be two possible ways to achieve this:
> 
> [1] Each CPU initializes active ways for itself.  This can be done
>     via the SSCLPDAWCR register.  This is a banked register, so each
>     CPU sees a different instance of the register.
> 
> [2] The master CPU initializes active ways for all the CPUs.  This
>     is available via SSCDAWCARMR(N) registers.  They are mapped at
>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
> 
> Currently, the outer cache frame work does not support a per-CPU
> init callback.  So this commit adopts [2]; the master CPU iterates
> over possible CPUs setting up SSCDAWCARMR(N) registers.
> 
> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
> by SoC.  We can live with it by checking the version register.
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> 

Applied to next/soc, thanks!

I'm a little lost with the patches you send, could you check that
I have applied all the ones you sent for 4.7 so far?

	Arnd

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Arnd Bergmann]

On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> This outer cache allows to control active ways independently for
> each CPU, but currently nothing is done for secondary CPUs.  In
> other words, all the ways are locked for secondary CPUs by default.
> This commit fixes it to fully bring out the performance of this
> outer cache.
> 
> There would be two possible ways to achieve this:
> 
> [1] Each CPU initializes active ways for itself.  This can be done
>     via the SSCLPDAWCR register.  This is a banked register, so each
>     CPU sees a different instance of the register.
> 
> [2] The master CPU initializes active ways for all the CPUs.  This
>     is available via SSCDAWCARMR(N) registers.  They are mapped at
>     the address SSCDAWCARMR + 4 * N, where N is the CPU number.
> 
> Currently, the outer cache frame work does not support a per-CPU
> init callback.  So this commit adopts [2]; the master CPU iterates
> over possible CPUs setting up SSCDAWCARMR(N) registers.
> 
> Unfortunately, the register offsets of SSCDAWCARMR(N) are different
> by SoC.  We can live with it by checking the version register.
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> 

Applied to next/soc, thanks!

I'm a little lost with the patches you send, could you check that
I have applied all the ones you sent for 4.7 so far?

	Arnd

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register for its own.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers, where all instances
    of SSCLPDAWCR are mirrored.  They are mapped at the address
    SSCDAWCARMR + 4 * N, where N is the CPU number.

The outer cache frame work does not support a per-CPU init callback.
So this commit adopts [2]; the master CPU iterates over possible CPUs
setting up SSCDAWCARMR(N) registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

KernelVersion: 4.6-rc4


 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register for its own.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers, where all instances
    of SSCLPDAWCR are mirrored.  They are mapped at the address
    SSCDAWCARMR + 4 * N, where N is the CPU number.

The outer cache frame work does not support a per-CPU init callback.
So this commit adopts [2]; the master CPU iterates over possible CPUs
setting up SSCDAWCARMR(N) registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

KernelVersion: 4.6-rc4


 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers.  They are mapped at
    the address SSCDAWCARMR + 4 * N, where N is the CPU number.

Currently, the outer cache frame work does not support a per-CPU
init callback.  So this commit adopts [2]; the master CPU iterates
over possible CPUs setting up SSCDAWCARMR(N) registers.

Unfortunately, the register offsets of SSCDAWCARMR(N) are different
by SoC.  We can live with it by checking the version register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

[Masahiro Yamada]

This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs.  In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.

There would be two possible ways to achieve this:

[1] Each CPU initializes active ways for itself.  This can be done
    via the SSCLPDAWCR register.  This is a banked register, so each
    CPU sees a different instance of the register.

[2] The master CPU initializes active ways for all the CPUs.  This
    is available via SSCDAWCARMR(N) registers.  They are mapped at
    the address SSCDAWCARMR + 4 * N, where N is the CPU number.

Currently, the outer cache frame work does not support a per-CPU
init callback.  So this commit adopts [2]; the master CPU iterates
over possible CPUs setting up SSCDAWCARMR(N) registers.

Unfortunately, the register offsets of SSCDAWCARMR(N) are different
by SoC.  We can live with it by checking the version register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index a6fa7b7..c8e2f49 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -96,6 +96,7 @@ struct uniphier_cache_data {
 	void __iomem *ctrl_base;
 	void __iomem *rev_base;
 	void __iomem *op_base;
+	void __iomem *way_ctrl_base;
 	u32 way_present_mask;
 	u32 way_locked_mask;
 	u32 nsets;
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
 					struct uniphier_cache_data *data,
 					u32 way_mask)
 {
+	unsigned int cpu;
+
 	data->way_locked_mask = way_mask & data->way_present_mask;
 
-	writel_relaxed(~data->way_locked_mask & data->way_present_mask,
-		       data->ctrl_base + UNIPHIER_SSCLPDAWCR);
+	for_each_possible_cpu(cpu)
+		writel_relaxed(~data->way_locked_mask & data->way_present_mask,
+			       data->way_ctrl_base + 4 * cpu);
 }
 
 static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		goto err;
 	}
 
+	data->way_ctrl_base = data->ctrl_base + 0xc00;
+
 	if (*cache_level == 2) {
 		u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
 		/*
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
 		 */
 		if (revision <= 0x16)
 			data->range_op_max_size = (u32)1 << 22;
+
+		/*
+		 * Unfortunatly, the offset address of active way control base
+		 * varies from SoC to SoC.
+		 */
+		switch (revision) {
+		case 0x11:	/* sLD3 */
+			data->way_ctrl_base = data->ctrl_base + 0x870;
+			break;
+		case 0x12:	/* LD4 */
+		case 0x16:	/* sld8 */
+			data->way_ctrl_base = data->ctrl_base + 0x840;
+			break;
+		default:
+			break;
+		}
 	}
 
 	data->range_op_max_size -= data->line_size;
-- 
1.9.1