* [PATCH v2 01/11] doc/devicetree: Add Aspeed and Tyan to vendor-prefixes
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
@ 2016-04-21 8:03 ` Joel Stanley
2016-04-21 8:04 ` [PATCH v2 02/11] doc/devicetree: Add Aspeed VIC bindings Joel Stanley
` (10 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:03 UTC (permalink / raw)
To: linux-arm-kernel
ASPEED Technology Inc is a fabless IC-design company. Their web site
is http://www.aspeedtech.com/.
Tyan is a manufactuer of server and workstation platforms.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 86740d4a270d..192843189ceb 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -29,6 +29,7 @@ arm ARM Ltd.
armadeus ARMadeus Systems SARL
artesyn Artesyn Embedded Technologies Inc.
asahi-kasei Asahi Kasei Corp.
+aspeed ASPEED Technology Inc.
atlas Atlas Scientific LLC
atmel Atmel Corporation
auo AU Optronics Corporation
@@ -250,6 +251,7 @@ tplink TP-LINK Technologies Co., Ltd.
tronfy Tronfy
tronsmart Tronsmart
truly Truly Semiconductors Limited
+tyan Tyan Computer Corporation
upisemi uPI Semiconductor Corp.
urt United Radiant Technology Corporation
usi Universal Scientific Industrial Co., Ltd.
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 02/11] doc/devicetree: Add Aspeed VIC bindings
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
2016-04-21 8:03 ` [PATCH v2 01/11] doc/devicetree: Add Aspeed and Tyan to vendor-prefixes Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:04 ` [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings Joel Stanley
` (9 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
.../interrupt-controller/aspeed,ast2400-vic.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
new file mode 100644
index 000000000000..10ed0c20ee6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
@@ -0,0 +1,24 @@
+Aspeed Vectored Interrupt Controller
+
+These bindings are for the Aspeed AST2400 interrupt controller register layout.
+The SoC has an legacy register layout, but this driver does not support that
+mode of operation.
+
+Required properties:
+
+- compatible : should be "aspeed,ast2400-vic".
+
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+- valid-sources : bitmask of valid irq sources
+
+Example:
+
+ vic: interrupt-controller {
+ compatible = "aspeed,ast2400-new-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ valid-sources = < 0xffffffff 0x0007ffff>;
+ reg = <0x1e6c0080 0x80>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
2016-04-21 8:03 ` [PATCH v2 01/11] doc/devicetree: Add Aspeed and Tyan to vendor-prefixes Joel Stanley
2016-04-21 8:04 ` [PATCH v2 02/11] doc/devicetree: Add Aspeed VIC bindings Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 11:20 ` Heiko Stübner
2016-04-21 8:04 ` [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs Joel Stanley
` (8 subsequent siblings)
11 siblings, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
.../devicetree/bindings/clock/aspeed-clock.txt | 137 +++++++++++++++++++++
1 file changed, 137 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/aspeed-clock.txt b/Documentation/devicetree/bindings/clock/aspeed-clock.txt
new file mode 100644
index 000000000000..91bdf34e5473
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/aspeed-clock.txt
@@ -0,0 +1,137 @@
+Device Tree Clock bindings for the Aspeed SoCs
+
+Aspeed SoCs have a fixed frequency input osciallator is used to create the PLL
+and APB clocks. We can determine these frequencies by reading registers that
+are set according to strapping bits.
+
+Forth generation boards
+-----------------------
+
+eg, ast2400.
+
+CLKIN:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 48e6, 25e6 or 24e6 depending on the input clock
+
+PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+For example:
+
+ clk_clkin: clk_clkin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
+
+ clk_hpll: clk_hpll {
+ compatible = "aspeed,g4-hpll-clock";
+ #clock-cells = <0>;
+ reg = <0x1e6e2008 0x4>;
+ };
+
+ clk_apb: clk_apb at 1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g4-apb-clock";
+ reg = <0x1e6e2008 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+
+
+Fifth generation boards
+-----------------------
+
+eg, ast2500.
+
+CLKIN:
+Required properties:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 25000000 or 24000000 depending on the input clock
+
+H-PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g5-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+AHB:
+
+Required properties:
+ - compatible : Must be "aspeed,g5-ahb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+For example:
+ clk_clkin: clk_clkin at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-clkin-clock";
+ reg = <0x1e6e2070 0x04>;
+ };
+
+ clk_hpll: clk_hpll at 1e6e2024 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-hpll-clock";
+ reg = <0x1e6e2024 0x4>;
+ clocks = <&clk_clkin>;
+ };
+
+ clk_ahb: clk_ahb at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-ahb-clock";
+ reg = <0x1e6e2070 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+ clk_apb: clk_apb at 1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-apb-clock";
+ reg = <0x1e6e2008 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-21 8:04 ` [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings Joel Stanley
@ 2016-04-21 11:20 ` Heiko Stübner
0 siblings, 0 replies; 53+ messages in thread
From: Heiko Stübner @ 2016-04-21 11:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Joel Stanley, arnd, benh, jk, mturquette, sboyd, linux-clk
[+clock-related patches should include clock-maintainers and lists]
Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
> +For example:
> +
> + clk_clkin: clk_clkin {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <48000000>;
> + };
> +
> + clk_hpll: clk_hpll {
> + compatible = "aspeed,g4-hpll-clock";
> + #clock-cells = <0>;
> + reg = <0x1e6e2008 0x4>;
> + };
> +
> + clk_apb: clk_apb@1e6e2008 {
> + #clock-cells = <0>;
> + compatible = "aspeed,g4-apb-clock";
> + reg = <0x1e6e2008 0x4>;
> + clocks = <&clk_hpll>;
> + };
You have both the hpll and apb_clk in the same register (probably even more
clocks?) and separate clock instances where each instance will of_iomap the
register itself (and thus multiple times in general).
>From what I remember exposing the clock controller as one block (instead of
declaring each clock individually in the dts) is still the preferred way but I
don't think I can find Mike's mail from back then easily.
And I think most clock-controller implementations actually use that paradigm.
Heiko
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
@ 2016-04-21 11:20 ` Heiko Stübner
0 siblings, 0 replies; 53+ messages in thread
From: Heiko Stübner @ 2016-04-21 11:20 UTC (permalink / raw)
To: linux-arm-kernel
[+clock-related patches should include clock-maintainers and lists]
Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
> +For example:
> +
> + clk_clkin: clk_clkin {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <48000000>;
> + };
> +
> + clk_hpll: clk_hpll {
> + compatible = "aspeed,g4-hpll-clock";
> + #clock-cells = <0>;
> + reg = <0x1e6e2008 0x4>;
> + };
> +
> + clk_apb: clk_apb at 1e6e2008 {
> + #clock-cells = <0>;
> + compatible = "aspeed,g4-apb-clock";
> + reg = <0x1e6e2008 0x4>;
> + clocks = <&clk_hpll>;
> + };
You have both the hpll and apb_clk in the same register (probably even more
clocks?) and separate clock instances where each instance will of_iomap the
register itself (and thus multiple times in general).
>From what I remember exposing the clock controller as one block (instead of
declaring each clock individually in the dts) is still the preferred way but I
don't think I can find Mike's mail from back then easily.
And I think most clock-controller implementations actually use that paradigm.
Heiko
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-21 11:20 ` Heiko Stübner
@ 2016-04-27 8:31 ` Joel Stanley
-1 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-27 8:31 UTC (permalink / raw)
To: Heiko Stübner
Cc: linux-arm-kernel, Arnd Bergmann, Benjamin Herrenschmidt,
Jeremy Kerr, mturquette, sboyd, linux-clk
On Thu, Apr 21, 2016 at 8:50 PM, Heiko St=C3=BCbner <heiko@sntech.de> wrote=
:
> [+clock-related patches should include clock-maintainers and lists]
Thanks.
> Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
>> +For example:
>> +
>> + clk_clkin: clk_clkin {
>> + #clock-cells =3D <0>;
>> + compatible =3D "fixed-clock";
>> + clock-frequency =3D <48000000>;
>> + };
>> +
>> + clk_hpll: clk_hpll {
>> + compatible =3D "aspeed,g4-hpll-clock";
>> + #clock-cells =3D <0>;
>> + reg =3D <0x1e6e2008 0x4>;
>> + };
>> +
>> + clk_apb: clk_apb@1e6e2008 {
>> + #clock-cells =3D <0>;
>> + compatible =3D "aspeed,g4-apb-clock";
>> + reg =3D <0x1e6e2008 0x4>;
>> + clocks =3D <&clk_hpll>;
>> + };
>
> You have both the hpll and apb_clk in the same register (probably even mo=
re
> clocks?) and separate clock instances where each instance will of_iomap t=
he
> register itself (and thus multiple times in general).
Yep. I agree that's not ideal.
>
> From what I remember exposing the clock controller as one block (instead =
of
> declaring each clock individually in the dts) is still the preferred way =
but I
> don't think I can find Mike's mail from back then easily.
I can't picture how that would look. I took my lead from the moxart
clock driver; is there a better example that I should follow?
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
@ 2016-04-27 8:31 ` Joel Stanley
0 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-27 8:31 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 21, 2016 at 8:50 PM, Heiko St?bner <heiko@sntech.de> wrote:
> [+clock-related patches should include clock-maintainers and lists]
Thanks.
> Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
>> +For example:
>> +
>> + clk_clkin: clk_clkin {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <48000000>;
>> + };
>> +
>> + clk_hpll: clk_hpll {
>> + compatible = "aspeed,g4-hpll-clock";
>> + #clock-cells = <0>;
>> + reg = <0x1e6e2008 0x4>;
>> + };
>> +
>> + clk_apb: clk_apb at 1e6e2008 {
>> + #clock-cells = <0>;
>> + compatible = "aspeed,g4-apb-clock";
>> + reg = <0x1e6e2008 0x4>;
>> + clocks = <&clk_hpll>;
>> + };
>
> You have both the hpll and apb_clk in the same register (probably even more
> clocks?) and separate clock instances where each instance will of_iomap the
> register itself (and thus multiple times in general).
Yep. I agree that's not ideal.
>
> From what I remember exposing the clock controller as one block (instead of
> declaring each clock individually in the dts) is still the preferred way but I
> don't think I can find Mike's mail from back then easily.
I can't picture how that would look. I took my lead from the moxart
clock driver; is there a better example that I should follow?
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-27 8:31 ` Joel Stanley
@ 2016-04-27 9:12 ` Heiko Stübner
-1 siblings, 0 replies; 53+ messages in thread
From: Heiko Stübner @ 2016-04-27 9:12 UTC (permalink / raw)
To: Joel Stanley
Cc: linux-arm-kernel, Arnd Bergmann, Benjamin Herrenschmidt,
Jeremy Kerr, mturquette, sboyd, linux-clk
Hi Joel,
Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
> On Thu, Apr 21, 2016 at 8:50 PM, Heiko St=FCbner <heiko@sntech.de> wr=
ote:
> > [+clock-related patches should include clock-maintainers and lists]=
>=20
> Thanks.
>=20
> > Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
> >> +For example:
> >> +
> >> + clk_clkin: clk_clkin {
> >> + #clock-cells =3D <0>;
> >> + compatible =3D "fixed-clock";
> >> + clock-frequency =3D <48000000>;
> >> + };
> >> +
> >> + clk_hpll: clk_hpll {
> >> + compatible =3D "aspeed,g4-hpll-clock";
> >> + #clock-cells =3D <0>;
> >> + reg =3D <0x1e6e2008 0x4>;
> >> + };
> >> +
> >> + clk_apb: clk_apb@1e6e2008 {
> >> + #clock-cells =3D <0>;
> >> + compatible =3D "aspeed,g4-apb-clock";
> >> + reg =3D <0x1e6e2008 0x4>;
> >> + clocks =3D <&clk_hpll>;
> >> + };
> >=20
> > You have both the hpll and apb_clk in the same register (probably e=
ven
> > more
> > clocks?) and separate clock instances where each instance will of_i=
omap
> > the
> > register itself (and thus multiple times in general).
>=20
> Yep. I agree that's not ideal.
>=20
> > From what I remember exposing the clock controller as one block (in=
stead
> > of
> > declaring each clock individually in the dts) is still the preferre=
d way
> > but I don't think I can find Mike's mail from back then easily.
>=20
> I can't picture how that would look. I took my lead from the moxart
> clock driver; is there a better example that I should follow?
qcom, samsung, rockchip, hisilicon, imx, ...
I guess the design would depend on the actual layout of your clock- / s=
ystem-
controller - aka what else is contained there.
Heiko
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
@ 2016-04-27 9:12 ` Heiko Stübner
0 siblings, 0 replies; 53+ messages in thread
From: Heiko Stübner @ 2016-04-27 9:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Joel,
Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
> On Thu, Apr 21, 2016 at 8:50 PM, Heiko St?bner <heiko@sntech.de> wrote:
> > [+clock-related patches should include clock-maintainers and lists]
>
> Thanks.
>
> > Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
> >> +For example:
> >> +
> >> + clk_clkin: clk_clkin {
> >> + #clock-cells = <0>;
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <48000000>;
> >> + };
> >> +
> >> + clk_hpll: clk_hpll {
> >> + compatible = "aspeed,g4-hpll-clock";
> >> + #clock-cells = <0>;
> >> + reg = <0x1e6e2008 0x4>;
> >> + };
> >> +
> >> + clk_apb: clk_apb at 1e6e2008 {
> >> + #clock-cells = <0>;
> >> + compatible = "aspeed,g4-apb-clock";
> >> + reg = <0x1e6e2008 0x4>;
> >> + clocks = <&clk_hpll>;
> >> + };
> >
> > You have both the hpll and apb_clk in the same register (probably even
> > more
> > clocks?) and separate clock instances where each instance will of_iomap
> > the
> > register itself (and thus multiple times in general).
>
> Yep. I agree that's not ideal.
>
> > From what I remember exposing the clock controller as one block (instead
> > of
> > declaring each clock individually in the dts) is still the preferred way
> > but I don't think I can find Mike's mail from back then easily.
>
> I can't picture how that would look. I took my lead from the moxart
> clock driver; is there a better example that I should follow?
qcom, samsung, rockchip, hisilicon, imx, ...
I guess the design would depend on the actual layout of your clock- / system-
controller - aka what else is contained there.
Heiko
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-27 9:12 ` Heiko Stübner
@ 2016-04-28 6:50 ` Joel Stanley
-1 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-28 6:50 UTC (permalink / raw)
To: Heiko Stübner
Cc: linux-arm-kernel, Arnd Bergmann, Benjamin Herrenschmidt,
Jeremy Kerr, Michael Turquette, sboyd, linux-clk
On Wed, Apr 27, 2016 at 6:42 PM, Heiko St=C3=BCbner <heiko@sntech.de> wrote=
:
> Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
>> > From what I remember exposing the clock controller as one block (inste=
ad
>> > of
>> > declaring each clock individually in the dts) is still the preferred w=
ay
>> > but I don't think I can find Mike's mail from back then easily.
>>
>> I can't picture how that would look. I took my lead from the moxart
>> clock driver; is there a better example that I should follow?
>
> qcom, samsung, rockchip, hisilicon, imx, ...
I had a look here, and they appear to be much more complex than I
need. The qcom directory is 41000 lines of code! The moxart driver is
similar to what we do, but as you mentioned it is not arranged how you
want it.
> I guess the design would depend on the actual layout of your clock- / sys=
tem-
> controller - aka what else is contained there.
In the fourth generation parts, such as the ast2400, we have this layout:
clock rate
-----------------------------
clk_clkin 48000000
clk_hpll 384000000
clk_apb 48000000
clkin is the oscillator that may be running at 24, 25 or 48MHz. We can
determine this from the strapping register.
The hpll divisor is controlled by strapping resistors, and indicated
in the strapping register.
The apb is controlled by a register in the SCU, the Aspeed's
bucket-of-bits for controlling various parts of the soc.
In our case we want don't need to adjust any clocks. We do want struct
clk's so attached device drivers to know how fast they are being
clocked. How do you see this laid out?
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
@ 2016-04-28 6:50 ` Joel Stanley
0 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-28 6:50 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Apr 27, 2016 at 6:42 PM, Heiko St?bner <heiko@sntech.de> wrote:
> Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
>> > From what I remember exposing the clock controller as one block (instead
>> > of
>> > declaring each clock individually in the dts) is still the preferred way
>> > but I don't think I can find Mike's mail from back then easily.
>>
>> I can't picture how that would look. I took my lead from the moxart
>> clock driver; is there a better example that I should follow?
>
> qcom, samsung, rockchip, hisilicon, imx, ...
I had a look here, and they appear to be much more complex than I
need. The qcom directory is 41000 lines of code! The moxart driver is
similar to what we do, but as you mentioned it is not arranged how you
want it.
> I guess the design would depend on the actual layout of your clock- / system-
> controller - aka what else is contained there.
In the fourth generation parts, such as the ast2400, we have this layout:
clock rate
-----------------------------
clk_clkin 48000000
clk_hpll 384000000
clk_apb 48000000
clkin is the oscillator that may be running at 24, 25 or 48MHz. We can
determine this from the strapping register.
The hpll divisor is controlled by strapping resistors, and indicated
in the strapping register.
The apb is controlled by a register in the SCU, the Aspeed's
bucket-of-bits for controlling various parts of the soc.
In our case we want don't need to adjust any clocks. We do want struct
clk's so attached device drivers to know how fast they are being
clocked. How do you see this laid out?
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-28 6:50 ` Joel Stanley
@ 2016-04-28 7:25 ` Heiko Stübner
-1 siblings, 0 replies; 53+ messages in thread
From: Heiko Stübner @ 2016-04-28 7:25 UTC (permalink / raw)
To: Joel Stanley
Cc: linux-arm-kernel, Arnd Bergmann, Benjamin Herrenschmidt,
Jeremy Kerr, Michael Turquette, sboyd, linux-clk
Am Donnerstag, 28. April 2016, 16:20:04 schrieb Joel Stanley:
> On Wed, Apr 27, 2016 at 6:42 PM, Heiko St=FCbner <heiko@sntech.de> wr=
ote:
> > Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
> >> > From what I remember exposing the clock controller as one block
> >> > (instead
> >> > of
> >> > declaring each clock individually in the dts) is still the prefe=
rred
> >> > way
> >> > but I don't think I can find Mike's mail from back then easily.
> >>=20
> >> I can't picture how that would look. I took my lead from the moxar=
t
> >> clock driver; is there a better example that I should follow?
> >=20
> > qcom, samsung, rockchip, hisilicon, imx, ...
>=20
> I had a look here, and they appear to be much more complex than I
> need. The qcom directory is 41000 lines of code! The moxart driver is=
> similar to what we do, but as you mentioned it is not arranged how yo=
u
> want it.
I'm by no means authoritative ;-), but from what you describe below, cl=
k-
asm9260.c or clk-efm32gg.c might be going in that direction of very sim=
ple=20
clock-controllers.
Sorry about pointing to more complex drivers for bigger socs at first :=
-)
> > I guess the design would depend on the actual layout of your clock-=
/
> > system- controller - aka what else is contained there.
>=20
> In the fourth generation parts, such as the ast2400, we have this lay=
out:
>=20
> clock rate
> -----------------------------
> clk_clkin 48000000
> clk_hpll 384000000
> clk_apb 48000000
>=20
> clkin is the oscillator that may be running at 24, 25 or 48MHz. We ca=
n
> determine this from the strapping register.
>=20
> The hpll divisor is controlled by strapping resistors, and indicated
> in the strapping register.
>=20
> The apb is controlled by a register in the SCU, the Aspeed's
> bucket-of-bits for controlling various parts of the soc.
I remember that from working on Samsung s3c24xx socs, the system-contro=
ller=20
area also worked as sort of catch-all :-) .
>=20
> In our case we want don't need to adjust any clocks. We do want struc=
t
> clk's so attached device drivers to know how fast they are being
> clocked. How do you see this laid out?
see drivers referenced above.
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
@ 2016-04-28 7:25 ` Heiko Stübner
0 siblings, 0 replies; 53+ messages in thread
From: Heiko Stübner @ 2016-04-28 7:25 UTC (permalink / raw)
To: linux-arm-kernel
Am Donnerstag, 28. April 2016, 16:20:04 schrieb Joel Stanley:
> On Wed, Apr 27, 2016 at 6:42 PM, Heiko St?bner <heiko@sntech.de> wrote:
> > Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
> >> > From what I remember exposing the clock controller as one block
> >> > (instead
> >> > of
> >> > declaring each clock individually in the dts) is still the preferred
> >> > way
> >> > but I don't think I can find Mike's mail from back then easily.
> >>
> >> I can't picture how that would look. I took my lead from the moxart
> >> clock driver; is there a better example that I should follow?
> >
> > qcom, samsung, rockchip, hisilicon, imx, ...
>
> I had a look here, and they appear to be much more complex than I
> need. The qcom directory is 41000 lines of code! The moxart driver is
> similar to what we do, but as you mentioned it is not arranged how you
> want it.
I'm by no means authoritative ;-), but from what you describe below, clk-
asm9260.c or clk-efm32gg.c might be going in that direction of very simple
clock-controllers.
Sorry about pointing to more complex drivers for bigger socs at first :-)
> > I guess the design would depend on the actual layout of your clock- /
> > system- controller - aka what else is contained there.
>
> In the fourth generation parts, such as the ast2400, we have this layout:
>
> clock rate
> -----------------------------
> clk_clkin 48000000
> clk_hpll 384000000
> clk_apb 48000000
>
> clkin is the oscillator that may be running at 24, 25 or 48MHz. We can
> determine this from the strapping register.
>
> The hpll divisor is controlled by strapping resistors, and indicated
> in the strapping register.
>
> The apb is controlled by a register in the SCU, the Aspeed's
> bucket-of-bits for controlling various parts of the soc.
I remember that from working on Samsung s3c24xx socs, the system-controller
area also worked as sort of catch-all :-) .
>
> In our case we want don't need to adjust any clocks. We do want struct
> clk's so attached device drivers to know how fast they are being
> clocked. How do you see this laid out?
see drivers referenced above.
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
2016-04-27 9:12 ` Heiko Stübner
@ 2016-04-28 8:38 ` Benjamin Herrenschmidt
-1 siblings, 0 replies; 53+ messages in thread
From: Benjamin Herrenschmidt @ 2016-04-28 8:38 UTC (permalink / raw)
To: Heiko Stübner, Joel Stanley
Cc: linux-arm-kernel, Arnd Bergmann, Jeremy Kerr, mturquette, sboyd,
linux-clk
On Wed, 2016-04-27 at 11:12 +0200, Heiko Stübner wrote:
> I guess the design would depend on the actual layout of your clock- /
> system-
> controller - aka what else is contained there.
One register controls most clocks so it makes sense to have one driver.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings
@ 2016-04-28 8:38 ` Benjamin Herrenschmidt
0 siblings, 0 replies; 53+ messages in thread
From: Benjamin Herrenschmidt @ 2016-04-28 8:38 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2016-04-27 at 11:12 +0200, Heiko St?bner wrote:
> I guess the design would depend on the actual layout of your clock- /
> system-
> controller - aka what else is contained there.
One register controls most clocks so it makes sense to have one driver.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (2 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:22 ` Arnd Bergmann
2016-04-22 17:30 ` Daniel Lezcano
2016-04-21 8:04 ` [PATCH v2 05/11] irqchip: Add irq controller for Aspeed Joel Stanley
` (7 subsequent siblings)
11 siblings, 2 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
The moxart timer IP is shared with another soc made by Aspeed.
Generalise the registers that differ so the same driver can be used for
both.
As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver
so we can express this dependency.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
.../bindings/timer/moxa,moxart-timer.txt | 4 +-
drivers/clocksource/Kconfig | 6 ++
drivers/clocksource/Makefile | 2 +-
drivers/clocksource/moxart_timer.c | 90 +++++++++++++++++-----
4 files changed, 79 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
index da2d510cae47..4569757142f8 100644
--- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
+++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
@@ -2,7 +2,9 @@ MOXA ART timer
Required properties:
-- compatible : Must be "moxa,moxart-timer"
+- compatible : Must be one of
+ - "moxa,moxart-timer"
+ - "aspeed,ast2400-timer"
- reg : Should contain registers location and length
- interrupts : Should contain the timer interrupt number
- clocks : Should contain phandle for the clock that drives the counter
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c346be650892..b14ac4db6961 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -411,4 +411,10 @@ config CLKSRC_ST_LPC
Enable this option to use the Low Power controller timer
as clocksource.
+config MOXART_TIMER
+ def_bool ARCH_MOXART || ARCH_ASPEED
+ depends on ARM && OF
+ select CLKSRC_OF
+ select CLKSRC_MMIO
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index dc2b8997f6e6..14fe8172c174 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o
obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o
-obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
+obj-$(CONFIG_MOXART_TIMER) += moxart_timer.o
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o
obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c
index 19857af651c1..47ecef0725bd 100644
--- a/drivers/clocksource/moxart_timer.c
+++ b/drivers/clocksource/moxart_timer.c
@@ -36,45 +36,66 @@
#define TIMER_INTR_MASK 0x38
/*
- * TIMER_CR flags:
+ * Moxart TIMER_CR flags:
*
* TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
* TIMEREG_CR_*_INT overflow interrupt enable bit
*/
-#define TIMEREG_CR_1_ENABLE BIT(0)
-#define TIMEREG_CR_1_CLOCK BIT(1)
-#define TIMEREG_CR_1_INT BIT(2)
-#define TIMEREG_CR_2_ENABLE BIT(3)
-#define TIMEREG_CR_2_CLOCK BIT(4)
-#define TIMEREG_CR_2_INT BIT(5)
-#define TIMEREG_CR_3_ENABLE BIT(6)
-#define TIMEREG_CR_3_CLOCK BIT(7)
-#define TIMEREG_CR_3_INT BIT(8)
-#define TIMEREG_CR_COUNT_UP BIT(9)
-
-#define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
-#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE)
+#define MOXART_CR_1_ENABLE BIT(0)
+#define MOXART_CR_1_CLOCK BIT(1)
+#define MOXART_CR_1_INT BIT(2)
+#define MOXART_CR_2_ENABLE BIT(3)
+#define MOXART_CR_2_CLOCK BIT(4)
+#define MOXART_CR_2_INT BIT(5)
+#define MOXART_CR_3_ENABLE BIT(6)
+#define MOXART_CR_3_CLOCK BIT(7)
+#define MOXART_CR_3_INT BIT(8)
+#define MOXART_CR_COUNT_UP BIT(9)
+
+#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE)
+#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE)
+
+/*
+ * The ASpeed variant of the IP block has a different layout
+ * for the control register
+ */
+#define ASPEED_CR_1_ENABLE BIT(0)
+#define ASPEED_CR_1_CLOCK BIT(1)
+#define ASPEED_CR_1_INT BIT(2)
+#define ASPEED_CR_2_ENABLE BIT(4)
+#define ASPEED_CR_2_CLOCK BIT(5)
+#define ASPEED_CR_2_INT BIT(6)
+#define ASPEED_CR_3_ENABLE BIT(8)
+#define ASPEED_CR_3_CLOCK BIT(9)
+#define ASPEED_CR_3_INT BIT(10)
+
+#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE)
+#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE)
static void __iomem *base;
static unsigned int clock_count_per_tick;
+static unsigned int t1_disable_val, t1_enable_val;
static int moxart_shutdown(struct clock_event_device *evt)
{
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ writel(t1_disable_val, base + TIMER_CR);
return 0;
}
static int moxart_set_oneshot(struct clock_event_device *evt)
{
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ writel(t1_disable_val, base + TIMER_CR);
writel(~0, base + TIMER1_BASE + REG_LOAD);
return 0;
}
static int moxart_set_periodic(struct clock_event_device *evt)
{
+ writel(t1_disable_val, base + TIMER_CR);
writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
- writel(TIMER1_ENABLE, base + TIMER_CR);
+ writel(0, base + TIMER1_BASE + REG_MATCH1);
+ writel(t1_enable_val, base + TIMER_CR);
+
return 0;
}
@@ -83,12 +104,12 @@ static int moxart_clkevt_next_event(unsigned long cycles,
{
u32 u;
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ writel(t1_disable_val, base + TIMER_CR);
u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
writel(u, base + TIMER1_BASE + REG_MATCH1);
- writel(TIMER1_ENABLE, base + TIMER_CR);
+ writel(t1_enable_val, base + TIMER_CR);
return 0;
}
@@ -119,7 +140,7 @@ static struct irqaction moxart_timer_irq = {
.dev_id = &moxart_clockevent,
};
-static void __init moxart_timer_init(struct device_node *node)
+static void __init __moxart_timer_init(struct device_node *node)
{
int ret, irq;
unsigned long pclk;
@@ -150,8 +171,19 @@ static void __init moxart_timer_init(struct device_node *node)
clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
+ /* Clear match registers */
+ writel(0, base + TIMER1_BASE + REG_MATCH1);
+ writel(0, base + TIMER1_BASE + REG_MATCH2);
+ writel(0, base + TIMER2_BASE + REG_MATCH1);
+ writel(0, base + TIMER2_BASE + REG_MATCH2);
+
+ /* Start timer 2 rolling as our main wall clock source, keep timer 1
+ * disabled
+ */
+ writel(0, base + TIMER_CR);
writel(~0, base + TIMER2_BASE + REG_LOAD);
- writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);
+ writel(t1_disable_val, base + TIMER_CR);
+
moxart_clockevent.cpumask = cpumask_of(0);
moxart_clockevent.irq = irq;
@@ -165,4 +197,20 @@ static void __init moxart_timer_init(struct device_node *node)
clockevents_config_and_register(&moxart_clockevent, pclk,
0x4, 0xfffffffe);
}
+
+static void __init moxart_timer_init(struct device_node *node)
+{
+ t1_enable_val = MOXART_TIMER1_ENABLE;
+ t1_disable_val = MOXART_TIMER1_DISABLE;
+ __moxart_timer_init(node);
+}
+
+static void __init aspeed_timer_init(struct device_node *node)
+{
+ t1_enable_val = ASPEED_TIMER1_ENABLE;
+ t1_disable_val = ASPEED_TIMER1_DISABLE;
+ __moxart_timer_init(node);
+}
+
CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);
+CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", aspeed_timer_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-04-21 8:04 ` [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs Joel Stanley
@ 2016-04-21 8:22 ` Arnd Bergmann
2016-04-22 1:06 ` Joel Stanley
2016-04-22 17:30 ` Daniel Lezcano
1 sibling, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 8:22 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 21 April 2016 17:34:02 Joel Stanley wrote:
> The moxart timer IP is shared with another soc made by Aspeed.
> Generalise the registers that differ so the same driver can be used for
> both.
>
> As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver
> so we can express this dependency.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
>
Any idea where the IP block came from? Moxart contains a lot of
licensed IP from faraday-tech. If this is one of them, we could
maybe rename the driver accordingly.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-04-21 8:22 ` Arnd Bergmann
@ 2016-04-22 1:06 ` Joel Stanley
0 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-22 1:06 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 21, 2016 at 5:52 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 21 April 2016 17:34:02 Joel Stanley wrote:
>> The moxart timer IP is shared with another soc made by Aspeed.
>
> Any idea where the IP block came from? Moxart contains a lot of
> licensed IP from faraday-tech. If this is one of them, we could
> maybe rename the driver accordingly.
Faraday would be a good bet, given that aspeed use their ethernet mac IP.
I'll ask around.
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-04-21 8:04 ` [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs Joel Stanley
2016-04-21 8:22 ` Arnd Bergmann
@ 2016-04-22 17:30 ` Daniel Lezcano
2016-04-22 23:55 ` Benjamin Herrenschmidt
2016-05-03 5:56 ` Joel Stanley
1 sibling, 2 replies; 53+ messages in thread
From: Daniel Lezcano @ 2016-04-22 17:30 UTC (permalink / raw)
To: linux-arm-kernel
On 04/21/2016 10:04 AM, Joel Stanley wrote:
> The moxart timer IP is shared with another soc made by Aspeed.
> Generalise the registers that differ so the same driver can be used for
> both.
>
> As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver
> so we can express this dependency.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
In the future, please Cc the maintainers.
> .../bindings/timer/moxa,moxart-timer.txt | 4 +-
> drivers/clocksource/Kconfig | 6 ++
> drivers/clocksource/Makefile | 2 +-
> drivers/clocksource/moxart_timer.c | 90 +++++++++++++++++-----
> 4 files changed, 79 insertions(+), 23 deletions(-)
[ ... ]
> +config MOXART_TIMER
> + def_bool ARCH_MOXART || ARCH_ASPEED
> + depends on ARM && OF
> + select CLKSRC_OF
> + select CLKSRC_MMIO
Refer to the other drivers to see how they are selected (eg. digicolor
or mtk).
[ ... ]
> -#define TIMEREG_CR_1_ENABLE BIT(0)
> -#define TIMEREG_CR_1_CLOCK BIT(1)
> -#define TIMEREG_CR_1_INT BIT(2)
> -#define TIMEREG_CR_2_ENABLE BIT(3)
> -#define TIMEREG_CR_2_CLOCK BIT(4)
> -#define TIMEREG_CR_2_INT BIT(5)
> -#define TIMEREG_CR_3_ENABLE BIT(6)
> -#define TIMEREG_CR_3_CLOCK BIT(7)
> -#define TIMEREG_CR_3_INT BIT(8)
> -#define TIMEREG_CR_COUNT_UP BIT(9)
> -
> -#define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
> -#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE)
> +#define MOXART_CR_1_ENABLE BIT(0)
> +#define MOXART_CR_1_CLOCK BIT(1)
> +#define MOXART_CR_1_INT BIT(2)
> +#define MOXART_CR_2_ENABLE BIT(3)
> +#define MOXART_CR_2_CLOCK BIT(4)
> +#define MOXART_CR_2_INT BIT(5)
> +#define MOXART_CR_3_ENABLE BIT(6)
> +#define MOXART_CR_3_CLOCK BIT(7)
> +#define MOXART_CR_3_INT BIT(8)
> +#define MOXART_CR_COUNT_UP BIT(9)
> +
> +#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE)
> +#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE)
> +
> +/*
> + * The ASpeed variant of the IP block has a different layout
> + * for the control register
> + */
> +#define ASPEED_CR_1_ENABLE BIT(0)
> +#define ASPEED_CR_1_CLOCK BIT(1)
> +#define ASPEED_CR_1_INT BIT(2)
> +#define ASPEED_CR_2_ENABLE BIT(4)
> +#define ASPEED_CR_2_CLOCK BIT(5)
> +#define ASPEED_CR_2_INT BIT(6)
> +#define ASPEED_CR_3_ENABLE BIT(8)
> +#define ASPEED_CR_3_CLOCK BIT(9)
> +#define ASPEED_CR_3_INT BIT(10)
> +
> +#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE)
> +#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE)
You probably can remove all the unused macro definition here for both
MOXART and ASPEED to have something just a couple of definition.
> static void __iomem *base;
> static unsigned int clock_count_per_tick;
> +static unsigned int t1_disable_val, t1_enable_val;
It will be cleaner to:
1. Factor out:
writel(TIMER1_DISABLE, base + TIMER_CR);
writel(TIMER1_ENABLE, base + TIMER_CR);
diff --git a/drivers/clocksource/moxart_timer.c
b/drivers/clocksource/moxart_timer.c
index 19857af..aede6f1 100644
--- a/drivers/clocksource/moxart_timer.c
+++ b/drivers/clocksource/moxart_timer.c
@@ -58,15 +58,25 @@
static void __iomem *base;
static unsigned int clock_count_per_tick;
-static int moxart_shutdown(struct clock_event_device *evt)
+static inline void moxart_disable(struct clock_event_device *evt)
{
writel(TIMER1_DISABLE, base + TIMER_CR);
+}
+
+static inline void moxart_enable(struct clock_event_device *evt)
+{
+ writel(TIMER1_ENABLE, base + TIMER_CR);
+}
+
+static int moxart_shutdown(struct clock_event_device *evt)
+{
+ moxart_disable(evt);
return 0;
}
static int moxart_set_oneshot(struct clock_event_device *evt)
{
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ moxart_disable(evt);
writel(~0, base + TIMER1_BASE + REG_LOAD);
return 0;
}
@@ -74,7 +84,7 @@ static int moxart_set_oneshot(struct
clock_event_device *evt)
static int moxart_set_periodic(struct clock_event_device *evt)
{
writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
- writel(TIMER1_ENABLE, base + TIMER_CR);
+ moxart_enable(evt);
return 0;
}
@@ -83,12 +93,12 @@ static int moxart_clkevt_next_event(unsigned long
cycles,
{
u32 u;
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ moxart_disable(evt);
u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
writel(u, base + TIMER1_BASE + REG_MATCH1);
- writel(TIMER1_ENABLE, base + TIMER_CR);
+ moxart_enable(evt);
return 0;
}
2. Encapsulate clkevt and use container_of
-static void __iomem *base;
-static unsigned int clock_count_per_tick;
+struct moxart_timer {
+ void __iomem *base;
+ unsigned int clock_count_per_tick;
+ struct clock_event_device clkevt;
+};
+
+static struct moxart_timer moxart_timer = {
+ .clkevt = {
+ .name = "moxart_timer",
+ .rating = 200,
+ .features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = moxart_shutdown,
+ .set_state_periodic = moxart_set_periodic,
+ .set_state_oneshot = moxart_set_oneshot,
+ .tick_resume = moxart_set_oneshot,
+ .set_next_event = moxart_clkevt_next_event,
+ },
+};
+
+static inline struct moxart_timer *clkevt_to_moxart(struct
clock_event_device *evt)
+{
+ return container_of(evt, struct moxart_timer, clkevt);
+}
static inline void moxart_disable(struct clock_event_device *evt)
{
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ writel(TIMER1_DISABLE, clkevt_to_moxart(evt)->base + TIMER_CR);
}
3. And finally, add 't1_disable' / 't2_disable' to the structure.
-- Daniel
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-04-22 17:30 ` Daniel Lezcano
@ 2016-04-22 23:55 ` Benjamin Herrenschmidt
2016-05-03 5:56 ` Joel Stanley
1 sibling, 0 replies; 53+ messages in thread
From: Benjamin Herrenschmidt @ 2016-04-22 23:55 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2016-04-22 at 19:30 +0200, Daniel Lezcano wrote:
>?
> You probably can remove all the unused macro definition here for
> both?
> MOXART and ASPEED to have something just a couple of definition.
I disagree. Quite strongly in fact. These provide documentation (which
isn't otherwise publicly available) and this will be handy if somebody
wants to do something like add another timer etc.. in the future.
I much prefer when register definitions rather more exhaustive than
trimmed to be only what's used by the driver.
Cheers,
Ben
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-04-22 17:30 ` Daniel Lezcano
2016-04-22 23:55 ` Benjamin Herrenschmidt
@ 2016-05-03 5:56 ` Joel Stanley
2016-05-03 13:36 ` Daniel Lezcano
1 sibling, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-05-03 5:56 UTC (permalink / raw)
To: linux-arm-kernel
Hey Daniel,
Thanks for the review.
On Sat, Apr 23, 2016 at 3:00 AM, Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
> On 04/21/2016 10:04 AM, Joel Stanley wrote:
>>
>> The moxart timer IP is shared with another soc made by Aspeed.
>> Generalise the registers that differ so the same driver can be used for
>> both.
>>
>> As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver
>> so we can express this dependency.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> ---
>
>
> In the future, please Cc the maintainers.
Sure.
>
> You probably can remove all the unused macro definition here for both MOXART
> and ASPEED to have something just a couple of definition.
I agree with Ben; we're helping out by documenting the hardware in
lieu of a public datasheet. I'd prefer to keep this here.
>> static void __iomem *base;
>> static unsigned int clock_count_per_tick;
>> +static unsigned int t1_disable_val, t1_enable_val;
>
>
> It will be cleaner to:
>
> 1. Factor out:
> writel(TIMER1_DISABLE, base + TIMER_CR);
> writel(TIMER1_ENABLE, base + TIMER_CR);
I considered this myself but went with the minimal change. I'm not
fussed, so I will rework it as you suggest.
>From the register layout I suspect this IP block is a Faraday Tech
FTTMR010[1], but I don't have any other evidence. Would you take a
patch to change the name or would you prefer leaving it as moxart?
Cheers,
Joel
[1] https://lists.nongnu.org/archive/html/qemu-devel/2013-03/msg04333.html
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-05-03 5:56 ` Joel Stanley
@ 2016-05-03 13:36 ` Daniel Lezcano
2016-05-06 14:50 ` Jonas Jensen
0 siblings, 1 reply; 53+ messages in thread
From: Daniel Lezcano @ 2016-05-03 13:36 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 03, 2016 at 03:26:33PM +0930, Joel Stanley wrote:
> Hey Daniel,
>
> Thanks for the review.
>
> On Sat, Apr 23, 2016 at 3:00 AM, Daniel Lezcano
> <daniel.lezcano@linaro.org> wrote:
> > On 04/21/2016 10:04 AM, Joel Stanley wrote:
> >>
> >> The moxart timer IP is shared with another soc made by Aspeed.
> >> Generalise the registers that differ so the same driver can be used for
> >> both.
> >>
> >> As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver
> >> so we can express this dependency.
> >>
> >> Signed-off-by: Joel Stanley <joel@jms.id.au>
> >> ---
> >
> >
> > In the future, please Cc the maintainers.
>
> Sure.
>
> >
> > You probably can remove all the unused macro definition here for both MOXART
> > and ASPEED to have something just a couple of definition.
>
> I agree with Ben; we're helping out by documenting the hardware in
> lieu of a public datasheet. I'd prefer to keep this here.
Ok, let's keep it.
> >> static void __iomem *base;
> >> static unsigned int clock_count_per_tick;
> >> +static unsigned int t1_disable_val, t1_enable_val;
> >
> >
> > It will be cleaner to:
> >
> > 1. Factor out:
> > writel(TIMER1_DISABLE, base + TIMER_CR);
> > writel(TIMER1_ENABLE, base + TIMER_CR);
>
> I considered this myself but went with the minimal change. I'm not
> fussed, so I will rework it as you suggest.
>
> From the register layout I suspect this IP block is a Faraday Tech
> FTTMR010[1], but I don't have any other evidence.
Apparently, it could be the fttmr010 [2].
May be Jonas Jensen can confirm that.
> Would you take a
> patch to change the name or would you prefer leaving it as moxart?
If Jonas can confirm the moxart SoC is using the faraday timer, then it
would make much more sense to rename it to timer-fttmr010.c and have the
different instance of this timer to set it up with the platform specific
bits.
> [1] https://lists.nongnu.org/archive/html/qemu-devel/2013-03/msg04333.html
[2]
http://git.denx.de/?p=u-boot.git;a=blob;f=include/faraday/fttmr010.h;h=2ab68d10218ed8241e5d2c916437c5918c17173d;hb=HEAD
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs
2016-05-03 13:36 ` Daniel Lezcano
@ 2016-05-06 14:50 ` Jonas Jensen
0 siblings, 0 replies; 53+ messages in thread
From: Jonas Jensen @ 2016-05-06 14:50 UTC (permalink / raw)
To: linux-arm-kernel
On 3 May 2016 at 15:36, Daniel Lezcano <daniel.lezcano@linaro.org> wrote:
> Apparently, it could be the fttmr010 [2].
>
> May be Jonas Jensen can confirm that.
The best I can do is infer (if that helps).
Also I can test on UC-7112-LX Plus hardware (the patch I got from Ben
back in May 2015 was verified OK).
Jonas
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 05/11] irqchip: Add irq controller for Aspeed
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (3 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:04 ` [PATCH v2 06/11] clk: Add driver for Aspeed fourth gen SoCs Joel Stanley
` (6 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-aspeed-vic.c | 238 +++++++++++++++++++++++++++++++++++++++
2 files changed, 239 insertions(+)
create mode 100644 drivers/irqchip/irq-aspeed-vic.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b03cfcbbac6b..ec82e6e15a38 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
+obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
diff --git a/drivers/irqchip/irq-aspeed-vic.c b/drivers/irqchip/irq-aspeed-vic.c
new file mode 100644
index 000000000000..db15fc3e831a
--- /dev/null
+++ b/drivers/irqchip/irq-aspeed-vic.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
+ *
+ * Driver for Aspeed "new" VIC as found in SoC generation 3 and later
+ *
+ * Based on irq-vic.c:
+ *
+ * Copyright (C) 1999 - 2003 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/syscore_ops.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+
+#include <asm/exception.h>
+#include <asm/irq.h>
+
+/* These definitions correspond to the "new mapping" of the
+ * register set that interleaves "high" and "low". The offsets
+ * below are for the "low" register, add 4 to get to the high one
+ */
+#define AVIC_IRQ_STATUS 0x00
+#define AVIC_FIQ_STATUS 0x08
+#define AVIC_RAW_STATUS 0x10
+#define AVIC_INT_SELECT 0x18
+#define AVIC_INT_ENABLE 0x20
+#define AVIC_INT_ENABLE_CLR 0x28
+#define AVIC_INT_TRIGGER 0x30
+#define AVIC_INT_TRIGGER_CLR 0x38
+#define AVIC_INT_SENSE 0x40
+#define AVIC_INT_DUAL_EDGE 0x48
+#define AVIC_INT_EVENT 0x50
+#define AVIC_EDGE_CLR 0x58
+#define AVIC_EDGE_STATUS 0x60
+
+struct aspeed_vic {
+ void __iomem *base;
+ u32 valid_sources[2];
+ u32 edge_sources[2];
+ struct irq_domain *dom;
+};
+static struct aspeed_vic *system_avic;
+
+static void vic_init_hw(struct aspeed_vic *vic)
+{
+ u32 sense;
+
+ /* Disable all interrupts */
+ writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
+ writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
+
+ /* Make sure no soft trigger is on */
+ writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
+ writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
+
+ /* Set everything to be IRQ */
+ writel(0, vic->base + AVIC_INT_SELECT);
+ writel(0, vic->base + AVIC_INT_SELECT + 4);
+
+ /* Some interrupts have a programable high/low level trigger
+ * (4 GPIO direct inputs), for now we assume this was configured
+ * by firmware. We read which ones are edge now.
+ */
+ sense = readl(vic->base + AVIC_INT_SENSE);
+ vic->edge_sources[0] = ~sense;
+ sense = readl(vic->base + AVIC_INT_SENSE + 4);
+ vic->edge_sources[1] = ~sense;
+
+ /* Clear edge detection latches */
+ writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
+ writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
+}
+
+static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+{
+ struct aspeed_vic *vic = system_avic;
+ u32 stat, irq;
+
+ for (;;) {
+ irq = 0;
+ stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
+ if (!stat) {
+ stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
+ irq = 32;
+ }
+ if (stat == 0)
+ break;
+ irq += ffs(stat) - 1;
+ handle_domain_irq(vic->dom, irq, regs);
+ }
+}
+
+static void avic_ack_irq(struct irq_data *d)
+{
+ struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
+ unsigned int sidx = d->hwirq >> 5;
+ unsigned int sbit = 1u << (d->hwirq & 0x1f);
+
+ /* Clear edge latch for edge interrupts, nop for level */
+ if (vic->edge_sources[sidx] & sbit)
+ writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
+}
+
+static void avic_mask_irq(struct irq_data *d)
+{
+ struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
+ unsigned int sidx = d->hwirq >> 5;
+ unsigned int sbit = 1u << (d->hwirq & 0x1f);
+
+ writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
+}
+
+static void avic_unmask_irq(struct irq_data *d)
+{
+ struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
+ unsigned int sidx = d->hwirq >> 5;
+ unsigned int sbit = 1u << (d->hwirq & 0x1f);
+
+ writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
+}
+
+/* For level irq, faster than going through a nop "ack" and mask */
+static void avic_mask_ack_irq(struct irq_data *d)
+{
+ struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
+ unsigned int sidx = d->hwirq >> 5;
+ unsigned int sbit = 1u << (d->hwirq & 0x1f);
+
+ /* First mask */
+ writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
+
+ /* Then clear edge latch for edge interrupts */
+ if (vic->edge_sources[sidx] & sbit)
+ writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
+}
+
+static struct irq_chip avic_chip = {
+ .name = "AVIC",
+ .irq_ack = avic_ack_irq,
+ .irq_mask = avic_mask_irq,
+ .irq_unmask = avic_unmask_irq,
+ .irq_mask_ack = avic_mask_ack_irq,
+};
+
+static int avic_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct aspeed_vic *vic = d->host_data;
+ unsigned int sidx = hwirq >> 5;
+ unsigned int sbit = 1u << (hwirq & 0x1f);
+
+ /* Check if interrupt exists */
+ if (sidx > 1 || !(vic->valid_sources[sidx] & sbit))
+ return -EPERM;
+
+ if (vic->edge_sources[sidx] & sbit)
+ irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
+ else
+ irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
+ irq_set_chip_data(irq, vic);
+ irq_set_probe(irq);
+ return 0;
+}
+
+static struct irq_domain_ops avic_dom_ops = {
+ .map = avic_map,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
+static int __init avic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ void __iomem *regs;
+ struct aspeed_vic *vic;
+ int nirqs;
+
+ if (WARN(parent, "non-root Aspeed VIC not supported"))
+ return -EINVAL;
+ if (WARN(system_avic, "duplicate Aspeed VIC not supported"))
+ return -EINVAL;
+
+ regs = of_iomap(node, 0);
+ if (WARN_ON(!regs))
+ return -EIO;
+
+ vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
+ if (WARN_ON(!vic)) {
+ iounmap(regs);
+ return -ENOMEM;
+ }
+ vic->base = regs;
+
+ of_property_read_u32_index(node, "valid-sources", 0,
+ &vic->valid_sources[0]);
+ of_property_read_u32_index(node, "valid-sources", 1,
+ &vic->valid_sources[1]);
+
+ nirqs = hweight32(vic->valid_sources[0]) +
+ hweight32(vic->valid_sources[1]);
+
+ /* Initialize soures, all masked */
+ vic_init_hw(vic);
+
+ /* Ready to receive interrupts */
+ system_avic = vic;
+ set_handle_irq(avic_handle_irq);
+
+ /* Register our domain */
+ vic->dom = irq_domain_add_simple(node, nirqs, 0,
+ &avic_dom_ops, vic);
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(aspeed_new_vic, "aspeed,ast2400-vic", avic_of_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 06/11] clk: Add driver for Aspeed fourth gen SoCs
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (4 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 05/11] irqchip: Add irq controller for Aspeed Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:04 ` [PATCH v2 07/11] clk: Add driver for Aspeed fifth " Joel Stanley
` (5 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
A simple driver to create fixed rate clock devices from srapping
registers.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-aspeed-g4.c | 106 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 107 insertions(+)
create mode 100644 drivers/clk/clk-aspeed-g4.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d696e4d..bd28f6c95aa1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_H8300) += h8300/
+obj-$(CONFIG_ARCH_ASPEED) += clk-aspeed-g4.o
diff --git a/drivers/clk/clk-aspeed-g4.c b/drivers/clk/clk-aspeed-g4.c
new file mode 100644
index 000000000000..36feba2a0859
--- /dev/null
+++ b/drivers/clk/clk-aspeed-g4.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2016 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/clkdev.h>
+
+static void __init aspeed_of_hpll_clk_init(struct device_node *node)
+{
+ struct clk *clk, *clkin_clk;
+ void __iomem *base;
+ int reg, rate, clkin;
+ const char *name = node->name;
+ const char *parent_name;
+ const int rates[][4] = {
+ {384, 360, 336, 408},
+ {400, 375, 350, 425},
+ };
+
+ of_property_read_string(node, "clock-output-names", &name);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: of_iomap failed\n", node->full_name);
+ return;
+ }
+ reg = readl(base) >> 8 & 0x2;
+ iounmap(base);
+
+ clkin_clk = of_clk_get(node, 0);
+ if (IS_ERR(clkin_clk)) {
+ pr_err("%s: of_clk_get failed\n", node->full_name);
+ return;
+ }
+
+ clkin = clk_get_rate(clkin_clk);
+
+ if (clkin == 48000000 || clkin == 24000000)
+ rate = rates[0][reg] * 1000000;
+ else if (clkin == 25000000)
+ rate = rates[1][reg] * 1000000;
+ else {
+ pr_err("%s: unknown clkin frequency %dHz\n",
+ node->full_name, clkin);
+ WARN_ON(1);
+ }
+
+ clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock\n", node->full_name);
+ return;
+ }
+
+ clk_register_clkdev(clk, NULL, name);
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_hpll_clock, "aspeed,g4-hpll-clock",
+ aspeed_of_hpll_clk_init);
+
+static void __init aspeed_of_apb_clk_init(struct device_node *node)
+{
+ struct clk *clk, *hpll_clk;
+ void __iomem *base;
+ int reg, rate;
+ const char *name = node->name;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &name);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: of_iomap failed\n", node->full_name);
+ return;
+ }
+ reg = readl(base) >> 23 & 0x3;
+ iounmap(base);
+
+ hpll_clk = of_clk_get(node, 0);
+ if (IS_ERR(hpll_clk)) {
+ pr_err("%s: of_clk_get failed\n", node->full_name);
+ return;
+ }
+
+ rate = clk_get_rate(hpll_clk) / (2 + 2 * reg);
+
+ clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock\n", node->full_name);
+ return;
+ }
+
+ clk_register_clkdev(clk, NULL, name);
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_apb_clock, "aspeed,g4-apb-clock",
+ aspeed_of_apb_clk_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 07/11] clk: Add driver for Aspeed fifth gen SoCs
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (5 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 06/11] clk: Add driver for Aspeed fourth gen SoCs Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:04 ` [PATCH v2 08/11] arm/dts: Add Aspeed ast2400 device tree Joel Stanley
` (4 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
Creates fixed clocks from the strapping registers.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/clk/Makefile | 2 +-
drivers/clk/clk-aspeed-g5.c | 189 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 190 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/clk-aspeed-g5.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index bd28f6c95aa1..cdd4643e9ee1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -84,4 +84,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_H8300) += h8300/
-obj-$(CONFIG_ARCH_ASPEED) += clk-aspeed-g4.o
+obj-$(CONFIG_ARCH_ASPEED) += clk-aspeed-g4.o clk-aspeed-g5.o
diff --git a/drivers/clk/clk-aspeed-g5.c b/drivers/clk/clk-aspeed-g5.c
new file mode 100644
index 000000000000..812fd9accf30
--- /dev/null
+++ b/drivers/clk/clk-aspeed-g5.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2016 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/clkdev.h>
+
+static void __init aspeed_of_clkin_clk_init(struct device_node *node)
+{
+ struct clk *clk;
+ void __iomem *base;
+ int reg, rate;
+ const char *name = node->name;
+
+ of_property_read_string(node, "clock-output-names", &name);
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: of_iomap failed\n", node->full_name);
+ return;
+ }
+ /* Strap register SCU70 */
+ reg = readl(base) & BIT(23);
+ iounmap(base);
+
+ if (reg)
+ rate = 25 * 1000 * 1000;
+ else
+ rate = 24 * 1000 * 1000;
+
+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock\n", node->full_name);
+ return;
+ }
+
+ clk_register_clkdev(clk, NULL, name);
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_clkin_clock, "aspeed,g5-clkin-clock",
+ aspeed_of_clkin_clk_init);
+
+
+static void __init aspeed_of_hpll_clk_init(struct device_node *node)
+{
+ struct clk *clk, *clkin_clk;
+ void __iomem *base;
+ int reg, rate, clkin;
+ const char *name = node->name;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &name);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: of_iomap failed\n", node->full_name);
+ return;
+ }
+ /* H-PLL parameter register SCU24 */
+ reg = readl(base);
+ iounmap(base);
+
+ clkin_clk = of_clk_get(node, 0);
+ if (IS_ERR(clkin_clk)) {
+ pr_err("%s: of_clk_get failed\n", node->full_name);
+ return;
+ }
+
+ clkin = clk_get_rate(clkin_clk);
+
+ if (reg & BIT(21)) {
+ rate = 0;
+ } else if (reg & BIT(20)) {
+ rate = clkin;
+ } else {
+ int p = (reg >> 13) & 0x3f;
+ int m = (reg >> 5) & 0xff;
+ int n = reg & 0x1f;
+
+ rate = clkin * ((m + 1) / (n + 1)) / (p + 1);
+ }
+
+ clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock\n", node->full_name);
+ return;
+ }
+
+ clk_register_clkdev(clk, NULL, name);
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_hpll_clock, "aspeed,g5-hpll-clock",
+ aspeed_of_hpll_clk_init);
+
+
+static void __init aspeed_of_ahb_clk_init(struct device_node *node)
+{
+ struct clk *clk, *hpll_clk;
+ void __iomem *base;
+ int reg, rate, hpll;
+ const char *name = node->name;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &name);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ /* Strap register SCU70 */
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: of_iomap failed\n", node->full_name);
+ return;
+ }
+ reg = (readl(base) >> 9) & 0x03;
+ iounmap(base);
+
+ /* A value of zero is undefined */
+ WARN_ON(reg == 0);
+
+ hpll_clk = of_clk_get(node, 0);
+ if (IS_ERR(hpll_clk)) {
+ pr_err("%s: of_clk_get failed\n", node->full_name);
+ return;
+ }
+
+ hpll = clk_get_rate(hpll_clk);
+
+ rate = hpll / 2 / (reg + 1);
+
+ clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock\n", node->full_name);
+ return;
+ }
+
+ clk_register_clkdev(clk, NULL, name);
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_ahb_clock, "aspeed,g5-ahb-clock",
+ aspeed_of_ahb_clk_init);
+
+
+static void __init aspeed_of_apb_clk_init(struct device_node *node)
+{
+ struct clk *clk, *hpll_clk;
+ void __iomem *base;
+ int reg, rate;
+ const char *name = node->name;
+ const char *parent_name;
+
+ of_property_read_string(node, "clock-output-names", &name);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ /* Clock selection register SCU08 */
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: of_iomap failed\n", node->full_name);
+ return;
+ }
+ reg = readl(base) >> 23 & 0x3;
+ iounmap(base);
+
+ hpll_clk = of_clk_get(node, 0);
+ if (IS_ERR(hpll_clk)) {
+ pr_err("%s: of_clk_get failed\n", node->full_name);
+ return;
+ }
+
+ rate = clk_get_rate(hpll_clk) / (4 * (reg + 1));
+
+ clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock\n", node->full_name);
+ return;
+ }
+
+ clk_register_clkdev(clk, NULL, name);
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_apb_clock, "aspeed,g5-apb-clock",
+ aspeed_of_apb_clk_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 08/11] arm/dts: Add Aspeed ast2400 device tree
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (6 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 07/11] clk: Add driver for Aspeed fifth " Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:25 ` Arnd Bergmann
2016-04-21 8:04 ` [PATCH v2 09/11] arm/dst: Add Aspeed ast2500 " Joel Stanley
` (3 subsequent siblings)
11 siblings, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
A common device tree for all forth gen/ast2400 systems and a board
specific dts for the Palmetto OpenPower developemnt machine which was
used for testing.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 21 ++++
arch/arm/boot/dts/aspeed-g4.dtsi | 152 ++++++++++++++++++++++++++
3 files changed, 174 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
create mode 100644 arch/arm/boot/dts/aspeed-g4.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923ce6fa..dee3a92cbd3c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -839,6 +839,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb
endif
dtstree := $(srctree)/$(src)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
new file mode 100644
index 000000000000..29015c4b70bb
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+
+/ {
+ model = "Palmetto BMC";
+ compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,38400";
+ };
+
+ memory {
+ reg = < 0x40000000 0x10000000 >;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
new file mode 100644
index 000000000000..64c720cfacfe
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -0,0 +1,152 @@
+#include "skeleton.dtsi"
+
+/ {
+ model = "Aspeed BMC";
+ compatible = "aspeed,ast2400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&vic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ clocks {
+ clk_clkin: clk_clkin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
+
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vic: interrupt-controller at 1e6c0080 {
+ compatible = "aspeed,ast2400-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ valid-sources = <0xffffffff 0x0007ffff>;
+ reg = <0x1e6c0080 0x80>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clk_hpll: clk_hpll at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g4-hpll-clock";
+ reg = <0x1e6e2070 0x4>;
+ clocks = <&clk_clkin>;
+ };
+
+ clk_apb: clk_apb at 1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g4-apb-clock";
+ reg = <0x1e6e2008 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+ sram at 1e720000 {
+ compatible = "mmio-sram";
+ reg = <0x1e720000 0x8000>; // 32K
+ };
+
+ timer: timer at 1e782000 {
+ compatible = "aspeed,ast2400-timer";
+ reg = <0x1e782000 0x90>;
+ // The moxart_timer driver registers only one
+ // interrupt and assumes it's for timer 1
+ //interrupts = <16 17 18 35 36 37 38 39>;
+ interrupts = <16>;
+ clocks = <&clk_apb>;
+ };
+
+ uart1: serial at 1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ clock-frequency = <1843200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart2: serial at 1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <32>;
+ clock-frequency = <1843200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart3: serial at 1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <33>;
+ clock-frequency = <1843200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart4: serial at 1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <34>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart5: serial at 1e784000 {
+ compatible = "ns16550a";
+ reg = <0x1e784000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clock-frequency = <1843200>;
+ current-speed = <38400>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart6: serial at 1e787000 {
+ compatible = "ns16550a";
+ reg = <0x1e787000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clock-frequency = <1843200>;
+ current-speed = <38400>;
+ no-loopback-test;
+ status = "disabled";
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 09/11] arm/dst: Add Aspeed ast2500 device tree
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (7 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 08/11] arm/dts: Add Aspeed ast2400 device tree Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-05-05 23:11 ` Xo Wang
2016-04-21 8:04 ` [PATCH v2 10/11] arm: Add Aspeed machine Joel Stanley
` (2 subsequent siblings)
11 siblings, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
This adds a common device tree for all fifth generation Aspeed systems,
and a board specific device tree for the ast2500 evaluation board.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 21 +++++
arch/arm/boot/dts/aspeed-g5.dtsi | 156 +++++++++++++++++++++++++++++++
3 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/aspeed-ast2500-evb.dts
create mode 100644 arch/arm/boot/dts/aspeed-g5.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dee3a92cbd3c..98251828883f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -839,7 +839,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
-dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
+ aspeed-ast2500-evb.dtb
endif
dtstree := $(srctree)/$(src)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
new file mode 100644
index 000000000000..24f2b60ed2fd
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+ model = "AST2500 EVB";
+ compatible = "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200";
+ };
+
+ memory {
+ reg = < 0x80000000 0x10000000 >;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
new file mode 100644
index 000000000000..05a5f5bf458e
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -0,0 +1,156 @@
+#include "skeleton.dtsi"
+
+/ {
+ model = "Aspeed BMC";
+ compatible = "aspeed,ast2500";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&vic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,arm1176jzf-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vic: interrupt-controller at 1e6c0080 {
+ compatible = "aspeed,ast2400-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ valid-sources = <0xfefff7ff 0x0807ffff>;
+ reg = <0x1e6c0080 0x80>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clk_clkin: clk_clkin at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-clkin-clock";
+ reg = <0x1e6e2070 0x04>;
+ };
+
+ clk_hpll: clk_hpll at 1e6e2024 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-hpll-clock";
+ reg = <0x1e6e2024 0x4>;
+ clocks = <&clk_clkin>;
+ };
+
+ clk_ahb: clk_ahb at 1e6e2070 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-ahb-clock";
+ reg = <0x1e6e2070 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+ clk_apb: clk_apb at 1e6e2008 {
+ #clock-cells = <0>;
+ compatible = "aspeed,g5-apb-clock";
+ reg = <0x1e6e2008 0x4>;
+ clocks = <&clk_hpll>;
+ };
+
+ sram at 1e720000 {
+ compatible = "mmio-sram";
+ reg = <0x1e720000 0x9000>; // 36K
+ };
+
+ timer: timer at 1e782000 {
+ compatible = "aspeed,ast2400-timer";
+ reg = <0x1e782000 0x90>;
+ // The moxart_timer driver registers only one
+ // interrupt and assumes it's for timer 1
+ //interrupts = <16 17 18 35 36 37 38 39>;
+ interrupts = <16>;
+ clocks = <&clk_apb>;
+ };
+
+ uart1: serial at 1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ clock-frequency = <1843200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart2: serial at 1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <32>;
+ clock-frequency = <1843200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart3: serial at 1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <33>;
+ clock-frequency = <1843200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart4: serial at 1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <34>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart5: serial at 1e784000 {
+ compatible = "ns16550a";
+ reg = <0x1e784000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clock-frequency = <1843200>;
+ current-speed = <38400>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart6: serial at 1e787000 {
+ compatible = "ns16550a";
+ reg = <0x1e787000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ clock-frequency = <1843200>;
+ current-speed = <38400>;
+ no-loopback-test;
+ status = "disabled";
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 09/11] arm/dst: Add Aspeed ast2500 device tree
2016-04-21 8:04 ` [PATCH v2 09/11] arm/dst: Add Aspeed ast2500 " Joel Stanley
@ 2016-05-05 23:11 ` Xo Wang
2016-05-06 7:28 ` Joel Stanley
0 siblings, 1 reply; 53+ messages in thread
From: Xo Wang @ 2016-05-05 23:11 UTC (permalink / raw)
To: linux-arm-kernel
Joel Stanley <joel <at> jms.id.au> writes:
> +/ {
> + model = "AST2500 EVB";
> + compatible = "aspeed,ast2500";
> +
> + chosen {
> + stdout-path = &uart5;
> + bootargs = "console=ttyS4,115200";
> + };
> +
> + memory {
> + reg = < 0x80000000 0x10000000 >;
The AST2500 EVB has an SK Hynix H5AN4G6NMFR 4Gb part, so this should be
0x20000000 for size.
> + uart1: serial <at> 1e783000 {
> + compatible = "ns16550a";
> + reg = <0x1e783000 0x1000>;
> + reg-shift = <2>;
> + interrupts = <9>;
> + clock-frequency = <1843200>;
The AST2500 datasheet 39.3.1 states the input clock to their 16550 IP is
24 MHz. Their u-boot code also has #define CONFIG_SYS_NS16550_CLK
24000000. I suspect we hit a path in the serial/8250 driver that doesn't
change the divisor from what u-boot set, which is why this has worked.
Thanks for the porting work!
cheers
//xo
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 09/11] arm/dst: Add Aspeed ast2500 device tree
2016-05-05 23:11 ` Xo Wang
@ 2016-05-06 7:28 ` Joel Stanley
0 siblings, 0 replies; 53+ messages in thread
From: Joel Stanley @ 2016-05-06 7:28 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 6, 2016 at 8:41 AM, Xo Wang <xow@google.com> wrote:
> Joel Stanley <joel <at> jms.id.au> writes:
>> +/ {
>> + model = "AST2500 EVB";
>> + compatible = "aspeed,ast2500";
>> +
>> + chosen {
>> + stdout-path = &uart5;
>> + bootargs = "console=ttyS4,115200";
>> + };
>> +
>> + memory {
>> + reg = < 0x80000000 0x10000000 >;
>
> The AST2500 EVB has an SK Hynix H5AN4G6NMFR 4Gb part, so this should be
> 0x20000000 for size.
Well caught. I've got a different part on my v1.1 board, but it is also 4Gbit.
>
>> + uart1: serial <at> 1e783000 {
>> + compatible = "ns16550a";
>> + reg = <0x1e783000 0x1000>;
>> + reg-shift = <2>;
>> + interrupts = <9>;
>> + clock-frequency = <1843200>;
>
> The AST2500 datasheet 39.3.1 states the input clock to their 16550 IP is
> 24 MHz. Their u-boot code also has #define CONFIG_SYS_NS16550_CLK
> 24000000. I suspect we hit a path in the serial/8250 driver that doesn't
> change the divisor from what u-boot set, which is why this has worked.
You're correct, we are relying on uboot. There's also a tricky 'div13'
register in the SCU that we are setting in our board file for these
numbers to work out.
In V3 I've added a clk driver to take are of these details.
>
> Thanks for the porting work!
Thanks for the review. Did you manage to get these patches booting on
your board?
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (8 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 09/11] arm/dst: Add Aspeed ast2500 " Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:35 ` Arnd Bergmann
2016-04-21 8:04 ` [PATCH v2 11/11] arm/configs: Add aspeed defconfig Joel Stanley
2016-04-21 8:54 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Arnd Bergmann
11 siblings, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
Aspeed devices are a common Baseboard Management Controller (BMC)
system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and
support for a large number of peripherals.
This patch adds basic support for the ast2400 and ast2500 machines,
capable of booting to a prompt in QEMU (-M palmetto-bmc), on an
Palmetto OpenPower development machine, and on the ast2500 EVB.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
MAINTAINERS | 8 +++++
arch/arm/Kconfig | 2 ++
arch/arm/Makefile | 1 +
arch/arm/mach-aspeed/Kconfig | 28 +++++++++++++++
arch/arm/mach-aspeed/Makefile | 3 ++
arch/arm/mach-aspeed/aspeed.c | 83 +++++++++++++++++++++++++++++++++++++++++++
6 files changed, 125 insertions(+)
create mode 100644 arch/arm/mach-aspeed/Kconfig
create mode 100644 arch/arm/mach-aspeed/Makefile
create mode 100644 arch/arm/mach-aspeed/aspeed.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 61a323a6b2cf..d0a1962f7753 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -975,6 +975,14 @@ F: arch/arm/mach-artpec
F: arch/arm/boot/dts/artpec6*
F: drivers/clk/clk-artpec6.c
+ARM/ASPEED MACHINE SUPPORT
+M: Joel Stanley <joel@jms.id.au>
+S: Maintained
+F: arch/arm/mach-aspeed/
+F: arch/arm/boot/dts/aspeed-*
+F: arch/arm/boot/dts/ast2400.dtsi
+F: drivers/*/*aspeed*
+
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre@atmel.com>
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cdfa6c2b7626..c4512f6b77f6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -775,6 +775,8 @@ source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
+source "arch/arm/mach-aspeed/Kconfig"
+
source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-imx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 8c3ce2ac44c4..8ab09fb78e1c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -184,6 +184,7 @@ machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart
+machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
new file mode 100644
index 000000000000..30bafc0bbd8b
--- /dev/null
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -0,0 +1,28 @@
+menuconfig ARCH_ASPEED
+ bool "Aspeed BMC architectures"
+ select OF
+ select SRAM
+ help
+ Say Y here if you want to run your kernel on hardware with an
+ ASpeed BMC SoC.
+
+if ARCH_ASPEED
+
+config MACH_AST_G4
+ bool "Aspeed SoC 4th Generation" if ARCH_MULTI_V5
+ depends on ARCH_ASPEED
+ select CPU_ARM926T
+ help
+ Say yes if you intend to run on an Aspeed ast2400 or similar
+ fourth generation BMCs, such as those used by OpenPower Power8
+ systems.
+
+config MACH_AST_G5
+ bool "Aspeed SoC 5th Generation" if ARCH_MULTI_V6
+ depends on ARCH_ASPEED
+ select CPU_V6
+ help
+ Say yes if you intend to run on an Aspeed ast2500 or similar
+ fifth generation Aspeed BMCs.
+
+endif
diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile
new file mode 100644
index 000000000000..3a4f025dd520
--- /dev/null
+++ b/arch/arm/mach-aspeed/Makefile
@@ -0,0 +1,3 @@
+# Object file lists.
+
+obj-$(CONFIG_ARCH_ASPEED) += aspeed.o
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
new file mode 100644
index 000000000000..822939113d95
--- /dev/null
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright IBM Corporation 2016
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#define AST_BASE_WDT 0x1E785000 /* Watchdog Timer (WDT) */
+#define AST_BASE_SCU 0x1E6E2000 /* System Control Unit (SCU) */
+
+static void __init aspeed_dt_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+#define AST_IO_VA 0xf0000000
+#define AST_IO_PA 0x1e600000
+#define AST_IO_SZ 0x00200000
+
+#define AST_IO(__pa) ((void __iomem *)(((__pa) & 0x001fffff) | AST_IO_VA))
+
+static struct map_desc aspeed_io_desc[] __initdata __maybe_unused = {
+ {
+ .virtual = AST_IO_VA,
+ .pfn = __phys_to_pfn(AST_IO_PA),
+ .length = AST_IO_SZ,
+ .type = MT_DEVICE
+ },
+};
+
+#define SCU_PASSWORD 0x1688A8A8
+
+static void __init aspeed_init_early(void)
+{
+ u32 reg;
+
+ /*
+ * Unlock SCU
+ */
+ writel(SCU_PASSWORD, AST_IO(AST_BASE_SCU));
+
+ /* We enable the UART clock divisor in the SCU's misc control
+ * register, as the baud rates in aspeed.dtb all assume that the
+ * divisor is active
+ */
+ reg = readl(AST_IO(AST_BASE_SCU | 0x2c));
+ writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c));
+
+ /*
+ * Disable the watchdogs
+ */
+ writel(0, AST_IO(AST_BASE_WDT | 0x0c));
+ writel(0, AST_IO(AST_BASE_WDT | 0x2c));
+}
+
+static void __init aspeed_map_io(void)
+{
+ debug_ll_io_init();
+ iotable_init(aspeed_io_desc, ARRAY_SIZE(aspeed_io_desc));
+}
+
+static const char *const aspeed_dt_match[] __initconst = {
+ "aspeed,ast2400",
+ "aspeed,ast2500",
+ NULL,
+};
+
+DT_MACHINE_START(aspeed_dt, "ASpeed SoC")
+ .map_io = aspeed_map_io,
+ .init_early = aspeed_init_early,
+ .init_machine = aspeed_dt_init,
+ .dt_compat = aspeed_dt_match,
+MACHINE_END
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-21 8:04 ` [PATCH v2 10/11] arm: Add Aspeed machine Joel Stanley
@ 2016-04-21 8:35 ` Arnd Bergmann
2016-04-21 22:28 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 8:35 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 21 April 2016 17:34:08 Joel Stanley wrote:
> diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
> new file mode 100644
> index 000000000000..30bafc0bbd8b
> --- /dev/null
> +++ b/arch/arm/mach-aspeed/Kconfig
> @@ -0,0 +1,28 @@
> +menuconfig ARCH_ASPEED
> + bool "Aspeed BMC architectures"
> + select OF
> + select SRAM
Please add
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
to hide the submenu otherwise. The 'select OF' is redundant and
can be removed.
> + help
> + Say Y here if you want to run your kernel on hardware with an
> + ASpeed BMC SoC.
> +
> +if ARCH_ASPEED
> +
> +config MACH_AST_G4
> + bool "Aspeed SoC 4th Generation" if ARCH_MULTI_V5
> + depends on ARCH_ASPEED
> + select CPU_ARM926T
> + help
> + Say yes if you intend to run on an Aspeed ast2400 or similar
> + fourth generation BMCs, such as those used by OpenPower Power8
> + systems.
> +
> +config MACH_AST_G5
> + bool "Aspeed SoC 5th Generation" if ARCH_MULTI_V6
> + depends on ARCH_ASPEED
The two 'depends on ARCH_ASPEED are redundant as well, you already have
the 'if ARCH_ASPEED' around it.
> +
> +#define AST_BASE_WDT 0x1E785000 /* Watchdog Timer (WDT) */
> +#define AST_BASE_SCU 0x1E6E2000 /* System Control Unit (SCU) */
Please try to avoid hardcoding any addresses in the platform file.
> +static void __init aspeed_dt_init(void)
> +{
> + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
We have just introduced of_platform_default_populate() that you could
use here, but the preferred way is to leave out the function entirely
as this is what we do anyway if none is provided.
> +#define AST_IO_VA 0xf0000000
> +#define AST_IO_PA 0x1e600000
> +#define AST_IO_SZ 0x00200000
> +
> +#define AST_IO(__pa) ((void __iomem *)(((__pa) & 0x001fffff) | AST_IO_VA))
> +
> +static struct map_desc aspeed_io_desc[] __initdata __maybe_unused = {
> + {
> + .virtual = AST_IO_VA,
> + .pfn = __phys_to_pfn(AST_IO_PA),
> + .length = AST_IO_SZ,
> + .type = MT_DEVICE
> + },
> +};
>
> +
> +#define SCU_PASSWORD 0x1688A8A8
> +
> +static void __init aspeed_init_early(void)
> +{
> + u32 reg;
> +
> + /*
> + * Unlock SCU
> + */
> + writel(SCU_PASSWORD, AST_IO(AST_BASE_SCU));
> +
> + /* We enable the UART clock divisor in the SCU's misc control
> + * register, as the baud rates in aspeed.dtb all assume that the
> + * divisor is active
> + */
> + reg = readl(AST_IO(AST_BASE_SCU | 0x2c));
> + writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c));
Can you explain a bit more about this? I would assume that the UART
that is used for the console is working at the point that the bootloader
hands over to the kernel, while the other uarts don't need to be
active this early. Why do you need to do this at such an early stage?
> + /*
> + * Disable the watchdogs
> + */
> + writel(0, AST_IO(AST_BASE_WDT | 0x0c));
> + writel(0, AST_IO(AST_BASE_WDT | 0x2c));
> +}
Similarly here: why so early? Is the initial timeout too short to wait
for the watchdog driver to come up? I think it makes sense to require
the watchdog driver to be loaded if a watchdog is enabled during boot,
and that keeps the register access in one place.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-21 8:35 ` Arnd Bergmann
@ 2016-04-21 22:28 ` Benjamin Herrenschmidt
2016-04-21 23:02 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 53+ messages in thread
From: Benjamin Herrenschmidt @ 2016-04-21 22:28 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2016-04-21 at 10:35 +0200, Arnd Bergmann wrote:
>
> > +#define SCU_PASSWORD 0x1688A8A8
> > +
> > +static void __init aspeed_init_early(void)
> > +{
> > + u32 reg;
> > +
> > + /*
> > + ?* Unlock SCU
> > + ?*/
> > + writel(SCU_PASSWORD, AST_IO(AST_BASE_SCU));
> > +
> > + /* We enable the UART clock divisor in the SCU's misc control
> > + ?* register, as the baud rates in aspeed.dtb all assume that the
> > + ?* divisor is active
> > + ?*/
> > + reg = readl(AST_IO(AST_BASE_SCU | 0x2c));
> > + writel(reg | 0x00001000, AST_IO(AST_BASE_SCU | 0x2c));
> Can you explain a bit more about this? I would assume that the UART
> that is used for the console is working at the point that the bootloader
> hands over to the kernel, while the other uarts don't need to be
> active this early. Why do you need to do this at such an early stage
It may or may not be already correct, you don't necessarily have a
serial enabled bootloader or it might be using a UART driver that
doesn't use the 'standard' divisors etc... This just sanitizes it.
This register contains misc controls. That specific bit controls a
clock divisor by 13 from the main 24Mhz source, which provides a
reasonably "standard" 1.84 Mhz input to the UARTs.
> >
> > + /*
> > + ?* Disable the watchdogs
> > + ?*/
> > + writel(0, AST_IO(AST_BASE_WDT | 0x0c));
> > + writel(0, AST_IO(AST_BASE_WDT | 0x2c));
> > +}
> Similarly here: why so early? Is the initial timeout too short to wait
> for the watchdog driver to come up? I think it makes sense to require
> the watchdog driver to be loaded if a watchdog is enabled during boot,
> and that keeps the register access in one place.
Cheers
Ben.
^ permalink raw reply [flat|nested] 53+ messages in thread* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-21 22:28 ` Benjamin Herrenschmidt
@ 2016-04-21 23:02 ` Benjamin Herrenschmidt
2016-04-22 5:20 ` Afzal Mohammed
0 siblings, 1 reply; 53+ messages in thread
From: Benjamin Herrenschmidt @ 2016-04-21 23:02 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2016-04-22 at 08:28 +1000, Benjamin Herrenschmidt wrote:
> It may or may not be already correct, you don't necessarily have a
> serial enabled bootloader or it might be using a UART driver that
> doesn't use the 'standard' divisors etc... This just sanitizes it.
>
> This register contains misc controls. That specific bit controls a
> clock divisor by 13 from the main 24Mhz source, which provides a
> reasonably "standard" 1.84 Mhz input to the UARTs.
On a second thought ... if we chose to not support random crap vendor
uboots, we could make it a requirement that this register is already
set appropriately by the bootloader to match what's in the device-tree
I suppose...
That, along with a watchdog driver, would allow us to completely remove
that init code.
Joel, Jeremy, your call.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-21 23:02 ` Benjamin Herrenschmidt
@ 2016-04-22 5:20 ` Afzal Mohammed
2016-04-22 5:32 ` Joel Stanley
0 siblings, 1 reply; 53+ messages in thread
From: Afzal Mohammed @ 2016-04-22 5:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Fri, Apr 22, 2016 at 09:02:54AM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2016-04-22 at 08:28 +1000, Benjamin Herrenschmidt wrote:
> > It may or may not be already correct, you don't necessarily have a
> > serial enabled bootloader or it might be using a UART driver that
> > doesn't use the 'standard' divisors etc... This just sanitizes it.
> On a second thought ... if we chose to not support random crap vendor
> uboots, we could make it a requirement that this register is already
> set appropriately by the bootloader to match what's in the device-tree
> I suppose...
ARM Linux expects bootloader to initialize one serial port
(Documentation/arm/Booting). Though mentioned as optional, recommended
so far haven't seen one w/o that. And to debug at early boot stage
like in assembly and where uart driver is not yet up, this helps in
being able to debug w/o jtag.
Regards
afzal
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-22 5:20 ` Afzal Mohammed
@ 2016-04-22 5:32 ` Joel Stanley
2016-04-22 16:37 ` Arnd Bergmann
0 siblings, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-04-22 5:32 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 22, 2016 at 2:50 PM, Afzal Mohammed <afzal.mohd.ma@gmail.com> wrote:
> On Fri, Apr 22, 2016 at 09:02:54AM +1000, Benjamin Herrenschmidt wrote:
>> On Fri, 2016-04-22 at 08:28 +1000, Benjamin Herrenschmidt wrote:
>
>> > It may or may not be already correct, you don't necessarily have a
>> > serial enabled bootloader or it might be using a UART driver that
>> > doesn't use the 'standard' divisors etc... This just sanitizes it.
>
>> On a second thought ... if we chose to not support random crap vendor
>> uboots, we could make it a requirement that this register is already
>> set appropriately by the bootloader to match what's in the device-tree
>> I suppose...
>
> ARM Linux expects bootloader to initialize one serial port
> (Documentation/arm/Booting). Though mentioned as optional, recommended
> so far haven't seen one w/o that. And to debug at early boot stage
> like in assembly and where uart driver is not yet up, this helps in
> being able to debug w/o jtag.
I did some testing and on the palmetto we still get console with our
u-boot, so I'll drop the divisor change.
Cheers,
Joel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 10/11] arm: Add Aspeed machine
2016-04-22 5:32 ` Joel Stanley
@ 2016-04-22 16:37 ` Arnd Bergmann
0 siblings, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-22 16:37 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 22 April 2016 15:02:35 Joel Stanley wrote:
> On Fri, Apr 22, 2016 at 2:50 PM, Afzal Mohammed <afzal.mohd.ma@gmail.com> wrote:
> > On Fri, Apr 22, 2016 at 09:02:54AM +1000, Benjamin Herrenschmidt wrote:
> >> On Fri, 2016-04-22 at 08:28 +1000, Benjamin Herrenschmidt wrote:
> >
> >> > It may or may not be already correct, you don't necessarily have a
> >> > serial enabled bootloader or it might be using a UART driver that
> >> > doesn't use the 'standard' divisors etc... This just sanitizes it.
> >
> >> On a second thought ... if we chose to not support random crap vendor
> >> uboots, we could make it a requirement that this register is already
> >> set appropriately by the bootloader to match what's in the device-tree
> >> I suppose...
> >
> > ARM Linux expects bootloader to initialize one serial port
> > (Documentation/arm/Booting). Though mentioned as optional, recommended
> > so far haven't seen one w/o that. And to debug at early boot stage
> > like in assembly and where uart driver is not yet up, this helps in
> > being able to debug w/o jtag.
>
> I did some testing and on the palmetto we still get console with our
> u-boot, so I'll drop the divisor change.
>
Ok, very good. We can always add it back if we see a good reason
for needing it, but I think it's better to start by adding the drivers
and leave workarounds like this for later when we know if we actually
require them.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 11/11] arm/configs: Add aspeed defconfig
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (9 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 10/11] arm: Add Aspeed machine Joel Stanley
@ 2016-04-21 8:04 ` Joel Stanley
2016-04-21 8:44 ` Arnd Bergmann
2016-04-21 8:54 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Arnd Bergmann
11 siblings, 1 reply; 53+ messages in thread
From: Joel Stanley @ 2016-04-21 8:04 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/configs/aspeed_g4_defconfig | 86 +++++++++++++++++++++++++++++++++++
arch/arm/configs/aspeed_g5_defconfig | 88 ++++++++++++++++++++++++++++++++++++
2 files changed, 174 insertions(+)
create mode 100644 arch/arm/configs/aspeed_g4_defconfig
create mode 100644 arch/arm/configs/aspeed_g5_defconfig
diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig
new file mode 100644
index 000000000000..83691bf98d09
--- /dev/null
+++ b/arch/arm/configs/aspeed_g4_defconfig
@@ -0,0 +1,86 @@
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_USELIB=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_SHMEM is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLOCK is not set
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_ASPEED=y
+CONFIG_MACH_AST_G4=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_AEABI=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_SECCOMP=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FANOTIFY=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_PAGE_POISONING=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
+CONFIG_UBSAN=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x1e784000
+CONFIG_DEBUG_UART_VIRT=0xe8784000
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig
new file mode 100644
index 000000000000..274f96e1e3bf
--- /dev/null
+++ b/arch/arm/configs/aspeed_g5_defconfig
@@ -0,0 +1,88 @@
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_USELIB=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_SHMEM is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_MULTI_V6=y
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_ASPEED=y
+CONFIG_MACH_AST_G5=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_AEABI=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_SECCOMP=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FANOTIFY=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_PAGE_POISONING=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
+CONFIG_UBSAN=y
+CONFIG_UBSAN_ALIGNMENT=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x1e784000
+CONFIG_DEBUG_UART_VIRT=0xe8784000
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_SPARC is not set
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH v2 11/11] arm/configs: Add aspeed defconfig
2016-04-21 8:04 ` [PATCH v2 11/11] arm/configs: Add aspeed defconfig Joel Stanley
@ 2016-04-21 8:44 ` Arnd Bergmann
0 siblings, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 8:44 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 21 April 2016 17:34:09 Joel Stanley wrote:
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> arch/arm/configs/aspeed_g4_defconfig | 86 +++++++++++++++++++++++++++++++++++
> arch/arm/configs/aspeed_g5_defconfig | 88 ++++++++++++++++++++++++++++++++++++
>
Please also add all drivers you need to multi_v5_defconfig. Unfortunately
we haven't come up with a good plan for a multi_v6_defconfig that allows
us to also have a combined v6+v7 config, so that doesn't exist at this time.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support
2016-04-21 8:03 ` [PATCH v2 00/11] Aspeed AST2400 and AST2500 BMC support Joel Stanley
` (10 preceding siblings ...)
2016-04-21 8:04 ` [PATCH v2 11/11] arm/configs: Add aspeed defconfig Joel Stanley
@ 2016-04-21 8:54 ` Arnd Bergmann
11 siblings, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 8:54 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 21 April 2016 17:33:58 Joel Stanley wrote:
> Hello!
>
> These patches add basic support for the Aspeed AST2400 SoC, a popular BMC
> device that is also the target for our OpenBMC[1] efforts.
>
> This series has been boot tested on a Palmetto OpenPower dev board that
> uses the ast2400 as it's BMC, as well as Qemu (-M palmetto-bmc on 2.6-rc1).
>
> Version two brings support for the AST2500. It's similar to the 2400, but with
> an ARM11 replacing the ARM9. I've boot tested it in Qemu and on the Aspeed
> AST2500 edk.
Looks good overall. I have a couple of comments, see the replies to the
individual patches.
Once the review comments are all addressed, please send a pull request
containing all the arch/arm patches to arm at kernel.org and have the
drivers (clk, irq, clocksource) merged by the respective subsystem
maintainers. The DT bindings normally go together with the drivers,
but they can also get merged with the dts files.
For pull requests sent to arm at kernel.org, please split them up into
separate pull requests for different topics (dts files, defconfig,
arch code, cleanups, ...) so we can merge them into the appropriate
branches that we send to Linus during the merge window.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread