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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: linux-arm-kernel@lists.infradead.org, Suzuki.Poulose@arm.com
Cc: linux-kernel@vger.kernel.org
Subject: [PATCH V4 01/18] coresight: tmc: modifying naming convention
Date: Tue, 26 Apr 2016 16:10:17 -0600	[thread overview]
Message-ID: <1461708634-6327-2-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org>

According to the TMC architectural state machine, the 'stopped'
state is reached when bit 2 (TMCReady) of the TMC Status register
turns to '1'.  The code is correct but the naming convention isn't.

The 'Triggered' bit occupies position '1' of the TMC Status register
and has nothing to do with the indication of the TMC entering the
stopped state. As such renaming function "tmc_wait_for_triggered()"
and changing the #define to reflect what the code is really doing.

This patch has no effect other than clarifying the semantic.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 2b42ecbd8831..3f646e29a99b 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -77,7 +77,7 @@
 #define TMC_FFCR_TRIGON_TRIGIN	BIT(8)
 #define TMC_FFCR_STOP_ON_FLUSH	BIT(12)
 
-#define TMC_STS_TRIGGERED_BIT	2
+#define TMC_STS_TMCREADY_BIT	2
 #define TMC_FFCR_FLUSHMAN_BIT	6
 
 enum tmc_config_type {
@@ -132,11 +132,11 @@ struct tmc_drvdata {
 	u32			trigger_cntr;
 };
 
-static void tmc_wait_for_ready(struct tmc_drvdata *drvdata)
+static void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
 {
 	/* Ensure formatter, unformatter and hardware fifo are empty */
 	if (coresight_timeout(drvdata->base,
-			      TMC_STS, TMC_STS_TRIGGERED_BIT, 1)) {
+			      TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
 		dev_err(drvdata->dev,
 			"timeout observed when probing at offset %#x\n",
 			TMC_STS);
@@ -160,7 +160,7 @@ static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
 			TMC_FFCR);
 	}
 
-	tmc_wait_for_ready(drvdata);
+	tmc_wait_for_tmcready(drvdata);
 }
 
 static void tmc_enable_hw(struct tmc_drvdata *drvdata)
-- 
2.5.0

WARNING: multiple messages have this Message-ID (diff)
From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V4 01/18] coresight: tmc: modifying naming convention
Date: Tue, 26 Apr 2016 16:10:17 -0600	[thread overview]
Message-ID: <1461708634-6327-2-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org>

According to the TMC architectural state machine, the 'stopped'
state is reached when bit 2 (TMCReady) of the TMC Status register
turns to '1'.  The code is correct but the naming convention isn't.

The 'Triggered' bit occupies position '1' of the TMC Status register
and has nothing to do with the indication of the TMC entering the
stopped state. As such renaming function "tmc_wait_for_triggered()"
and changing the #define to reflect what the code is really doing.

This patch has no effect other than clarifying the semantic.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 2b42ecbd8831..3f646e29a99b 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -77,7 +77,7 @@
 #define TMC_FFCR_TRIGON_TRIGIN	BIT(8)
 #define TMC_FFCR_STOP_ON_FLUSH	BIT(12)
 
-#define TMC_STS_TRIGGERED_BIT	2
+#define TMC_STS_TMCREADY_BIT	2
 #define TMC_FFCR_FLUSHMAN_BIT	6
 
 enum tmc_config_type {
@@ -132,11 +132,11 @@ struct tmc_drvdata {
 	u32			trigger_cntr;
 };
 
-static void tmc_wait_for_ready(struct tmc_drvdata *drvdata)
+static void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
 {
 	/* Ensure formatter, unformatter and hardware fifo are empty */
 	if (coresight_timeout(drvdata->base,
-			      TMC_STS, TMC_STS_TRIGGERED_BIT, 1)) {
+			      TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
 		dev_err(drvdata->dev,
 			"timeout observed when probing at offset %#x\n",
 			TMC_STS);
@@ -160,7 +160,7 @@ static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
 			TMC_FFCR);
 	}
 
-	tmc_wait_for_ready(drvdata);
+	tmc_wait_for_tmcready(drvdata);
 }
 
 static void tmc_enable_hw(struct tmc_drvdata *drvdata)
-- 
2.5.0

  reply	other threads:[~2016-04-26 22:10 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-26 22:10 [PATCH V4 00/18] coresight: tmc: make driver usable by Perf Mathieu Poirier
2016-04-26 22:10 ` Mathieu Poirier
2016-04-26 22:10 ` Mathieu Poirier [this message]
2016-04-26 22:10   ` [PATCH V4 01/18] coresight: tmc: modifying naming convention Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 02/18] coresight: tmc: waiting for TMCReady bit before programming Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 03/18] coresight: tmc: re-implementing tmc_read_prepare/unprepare() functions Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 04/18] coresight: tmc: clearly define number of transfers per burst Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 05/18] coresight: tmc: introducing new header file Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 06/18] coresight: tmc: cleaning up " Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 07/18] coresight: tmc: splitting driver in ETB/ETF and ETR components Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 08/18] coresight: tmc: making prepare/unprepare functions generic Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 09/18] coresight: tmc: allocating memory when needed Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 10/18] coresight: tmc: getting rid of multiple read access Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27  8:54   ` Suzuki K Poulose
2016-04-27  8:54     ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 11/18] coresight: tmc: adding mode of operation for link/sinks Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27  9:07   ` Suzuki K Poulose
2016-04-27  9:07     ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 12/18] coresight: tmc: dump system memory content only when needed Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27  9:08   ` Suzuki K Poulose
2016-04-27  9:08     ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 13/18] coresight: tmc: make sysFS and Perf mode mutually exclusive Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27  9:10   ` Suzuki K Poulose
2016-04-27  9:10     ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 14/18] coresight: tmc: keep track of memory width Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27  9:17   ` Suzuki K Poulose
2016-04-27  9:17     ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 15/18] coresight: moving struct cs_buffers to header file Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27  9:11   ` Suzuki K Poulose
2016-04-27  9:11     ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-27 11:21   ` Suzuki K Poulose
2016-04-27 11:21     ` Suzuki K Poulose
2016-04-27 17:22     ` Mathieu Poirier
2016-04-27 17:22       ` Mathieu Poirier
2016-04-27 17:25       ` Suzuki K Poulose
2016-04-27 17:25         ` Suzuki K Poulose
2016-04-26 22:10 ` [PATCH V4 17/18] coresight: tmc: implementing TMC-ETR " Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier
2016-04-26 22:10 ` [PATCH V4 18/18] coresight: configuring ETF in FIFO mode when acting as link Mathieu Poirier
2016-04-26 22:10   ` Mathieu Poirier

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