* [PATCH 1/3] drm/i915: Remove intel_clock_t typedef
@ 2016-05-04 9:11 Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 2/3] drm/i915: Remove intel_range_t and intel_p2_t typedefs Ander Conselvan de Oliveira
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-05-04 9:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Just use "struct dpll" everywhere. That's actually shorter than
intel_clock_t.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 62 +++++++++++++++++------------------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 8 ++---
4 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index de5fb8c..b302cd1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -948,7 +948,7 @@ static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
{
struct intel_shared_dpll *pll;
struct intel_dpll_hw_state *state;
- intel_clock_t clock;
+ struct dpll clock;
/* For DDI ports we always use a shared PLL. */
if (WARN_ON(dpll == DPLL_ID_PRIVATE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8262b23..8e41e16 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -582,7 +582,7 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
* divided-down version of it.
*/
/* m1 is reserved as 0 in Pineview, n is a ring counter */
-static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
+static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m2 + 2;
clock->p = clock->p1 * clock->p2;
@@ -599,7 +599,7 @@ static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}
-static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
+static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = i9xx_dpll_compute_m(clock);
clock->p = clock->p1 * clock->p2;
@@ -611,7 +611,7 @@ static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
return clock->dot;
}
-static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
+static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
clock->p = clock->p1 * clock->p2;
@@ -623,7 +623,7 @@ static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
return clock->dot / 5;
}
-int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
+int chv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
clock->p = clock->p1 * clock->p2;
@@ -644,7 +644,7 @@ int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
static bool intel_PLL_is_valid(struct drm_device *dev,
const intel_limit_t *limit,
- const intel_clock_t *clock)
+ const struct dpll *clock)
{
if (clock->n < limit->n.min || limit->n.max < clock->n)
INTELPllInvalid("n out of range\n");
@@ -716,11 +716,11 @@ i9xx_select_p2_div(const intel_limit_t *limit,
static bool
i9xx_find_best_dpll(const intel_limit_t *limit,
struct intel_crtc_state *crtc_state,
- int target, int refclk, intel_clock_t *match_clock,
- intel_clock_t *best_clock)
+ int target, int refclk, struct dpll *match_clock,
+ struct dpll *best_clock)
{
struct drm_device *dev = crtc_state->base.crtc->dev;
- intel_clock_t clock;
+ struct dpll clock;
int err = target;
memset(best_clock, 0, sizeof(*best_clock));
@@ -773,11 +773,11 @@ i9xx_find_best_dpll(const intel_limit_t *limit,
static bool
pnv_find_best_dpll(const intel_limit_t *limit,
struct intel_crtc_state *crtc_state,
- int target, int refclk, intel_clock_t *match_clock,
- intel_clock_t *best_clock)
+ int target, int refclk, struct dpll *match_clock,
+ struct dpll *best_clock)
{
struct drm_device *dev = crtc_state->base.crtc->dev;
- intel_clock_t clock;
+ struct dpll clock;
int err = target;
memset(best_clock, 0, sizeof(*best_clock));
@@ -828,11 +828,11 @@ pnv_find_best_dpll(const intel_limit_t *limit,
static bool
g4x_find_best_dpll(const intel_limit_t *limit,
struct intel_crtc_state *crtc_state,
- int target, int refclk, intel_clock_t *match_clock,
- intel_clock_t *best_clock)
+ int target, int refclk, struct dpll *match_clock,
+ struct dpll *best_clock)
{
struct drm_device *dev = crtc_state->base.crtc->dev;
- intel_clock_t clock;
+ struct dpll clock;
int max_n;
bool found = false;
/* approximately equals target * 0.00585 */
@@ -878,8 +878,8 @@ g4x_find_best_dpll(const intel_limit_t *limit,
* best configuration and error found so far. Return the calculated error.
*/
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
- const intel_clock_t *calculated_clock,
- const intel_clock_t *best_clock,
+ const struct dpll *calculated_clock,
+ const struct dpll *best_clock,
unsigned int best_error_ppm,
unsigned int *error_ppm)
{
@@ -921,12 +921,12 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
static bool
vlv_find_best_dpll(const intel_limit_t *limit,
struct intel_crtc_state *crtc_state,
- int target, int refclk, intel_clock_t *match_clock,
- intel_clock_t *best_clock)
+ int target, int refclk, struct dpll *match_clock,
+ struct dpll *best_clock)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
- intel_clock_t clock;
+ struct dpll clock;
unsigned int bestppm = 1000000;
/* min update 19.2 MHz */
int max_n = min(limit->n.max, refclk / 19200);
@@ -980,13 +980,13 @@ vlv_find_best_dpll(const intel_limit_t *limit,
static bool
chv_find_best_dpll(const intel_limit_t *limit,
struct intel_crtc_state *crtc_state,
- int target, int refclk, intel_clock_t *match_clock,
- intel_clock_t *best_clock)
+ int target, int refclk, struct dpll *match_clock,
+ struct dpll *best_clock)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_device *dev = crtc->base.dev;
unsigned int best_error_ppm;
- intel_clock_t clock;
+ struct dpll clock;
uint64_t m2;
int found = false;
@@ -1036,7 +1036,7 @@ chv_find_best_dpll(const intel_limit_t *limit,
}
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
- intel_clock_t *best_clock)
+ struct dpll *best_clock)
{
int refclk = 100000;
const intel_limit_t *limit = &intel_limits_bxt;
@@ -7059,7 +7059,7 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- intel_clock_t *reduced_clock)
+ struct dpll *reduced_clock)
{
struct drm_device *dev = crtc->base.dev;
u32 fp, fp2 = 0;
@@ -7483,7 +7483,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
static void i9xx_compute_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- intel_clock_t *reduced_clock)
+ struct dpll *reduced_clock)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7559,7 +7559,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
static void i8xx_compute_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
- intel_clock_t *reduced_clock)
+ struct dpll *reduced_clock)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8030,7 +8030,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = pipe_config->cpu_transcoder;
- intel_clock_t clock;
+ struct dpll clock;
u32 mdiv;
int refclk = 100000;
@@ -8127,7 +8127,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = pipe_config->cpu_transcoder;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- intel_clock_t clock;
+ struct dpll clock;
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000;
@@ -8790,7 +8790,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state,
- intel_clock_t *reduced_clock)
+ struct dpll *reduced_clock)
{
struct drm_crtc *crtc = &intel_crtc->base;
struct drm_device *dev = crtc->dev;
@@ -8898,7 +8898,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- intel_clock_t reduced_clock;
+ struct dpll reduced_clock;
bool has_reduced_clock = false;
struct intel_shared_dpll *pll;
const intel_limit_t *limit;
@@ -10628,7 +10628,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
int pipe = pipe_config->cpu_transcoder;
u32 dpll = pipe_config->dpll_hw_state.dpll;
u32 fp;
- intel_clock_t clock;
+ struct dpll clock;
int port_clock;
int refclk = i9xx_pll_refclk(dev, pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 639bf02..b57d7ba 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1508,7 +1508,7 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
int clock = crtc_state->port_clock;
if (encoder->type == INTEL_OUTPUT_HDMI) {
- intel_clock_t best_clock;
+ struct dpll best_clock;
/* Calculate HDMI div */
/*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fcc0643..7cdc1e6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -265,7 +265,7 @@ struct intel_connector {
struct intel_dp *mst_port;
};
-typedef struct dpll {
+struct dpll {
/* given values */
int n;
int m1, m2;
@@ -275,7 +275,7 @@ typedef struct dpll {
int vco;
int m;
int p;
-} intel_clock_t;
+};
struct intel_atomic_state {
struct drm_atomic_state base;
@@ -1250,8 +1250,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
- intel_clock_t *best_clock);
-int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
+ struct dpll *best_clock);
+int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
bool intel_crtc_active(struct drm_crtc *crtc);
void hsw_enable_ips(struct intel_crtc *crtc);
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] drm/i915: Remove intel_range_t and intel_p2_t typedefs
2016-05-04 9:11 [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ander Conselvan de Oliveira
@ 2016-05-04 9:11 ` Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 3/3] drm/i915: Remove intel_limit_t typedef Ander Conselvan de Oliveira
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-05-04 9:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Those are only used for defining struct intel_limit, so use anonymous
structs instead.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8e41e16..a9fad2f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -118,19 +118,16 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
static void intel_modeset_setup_hw_state(struct drm_device *dev);
static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
-typedef struct {
- int min, max;
-} intel_range_t;
-
-typedef struct {
- int dot_limit;
- int p2_slow, p2_fast;
-} intel_p2_t;
-
typedef struct intel_limit intel_limit_t;
struct intel_limit {
- intel_range_t dot, vco, n, m, m1, m2, p, p1;
- intel_p2_t p2;
+ struct {
+ int min, max;
+ } dot, vco, n, m, m1, m2, p, p1;
+
+ struct {
+ int dot_limit;
+ int p2_slow, p2_fast;
+ } p2;
};
/* returns HPLL frequency in kHz */
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] drm/i915: Remove intel_limit_t typedef
2016-05-04 9:11 [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 2/3] drm/i915: Remove intel_range_t and intel_p2_t typedefs Ander Conselvan de Oliveira
@ 2016-05-04 9:11 ` Ander Conselvan de Oliveira
2016-05-04 9:29 ` Jani Nikula
2016-05-04 9:29 ` [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ville Syrjälä
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-05-04 9:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The coding style documentation says the following about typedefs:
"In general, a pointer, or a struct that has elements that can
reasonably be directly accessed should _never_ be a typedef."
intel_limit_t falls in that category, so just use "struct intel_limit"
instead.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 69 ++++++++++++++++++------------------
1 file changed, 34 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a9fad2f..49efc84 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -118,7 +118,6 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
static void intel_modeset_setup_hw_state(struct drm_device *dev);
static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
-typedef struct intel_limit intel_limit_t;
struct intel_limit {
struct {
int min, max;
@@ -253,7 +252,7 @@ intel_fdi_link_freq(struct drm_i915_private *dev_priv,
return 270000;
}
-static const intel_limit_t intel_limits_i8xx_dac = {
+static const struct intel_limit intel_limits_i8xx_dac = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 },
@@ -266,7 +265,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
.p2_slow = 4, .p2_fast = 2 },
};
-static const intel_limit_t intel_limits_i8xx_dvo = {
+static const struct intel_limit intel_limits_i8xx_dvo = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 },
@@ -279,7 +278,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
.p2_slow = 4, .p2_fast = 4 },
};
-static const intel_limit_t intel_limits_i8xx_lvds = {
+static const struct intel_limit intel_limits_i8xx_lvds = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 908000, .max = 1512000 },
.n = { .min = 2, .max = 16 },
@@ -292,7 +291,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
.p2_slow = 14, .p2_fast = 7 },
};
-static const intel_limit_t intel_limits_i9xx_sdvo = {
+static const struct intel_limit intel_limits_i9xx_sdvo = {
.dot = { .min = 20000, .max = 400000 },
.vco = { .min = 1400000, .max = 2800000 },
.n = { .min = 1, .max = 6 },
@@ -305,7 +304,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
.p2_slow = 10, .p2_fast = 5 },
};
-static const intel_limit_t intel_limits_i9xx_lvds = {
+static const struct intel_limit intel_limits_i9xx_lvds = {
.dot = { .min = 20000, .max = 400000 },
.vco = { .min = 1400000, .max = 2800000 },
.n = { .min = 1, .max = 6 },
@@ -319,7 +318,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
};
-static const intel_limit_t intel_limits_g4x_sdvo = {
+static const struct intel_limit intel_limits_g4x_sdvo = {
.dot = { .min = 25000, .max = 270000 },
.vco = { .min = 1750000, .max = 3500000},
.n = { .min = 1, .max = 4 },
@@ -334,7 +333,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
},
};
-static const intel_limit_t intel_limits_g4x_hdmi = {
+static const struct intel_limit intel_limits_g4x_hdmi = {
.dot = { .min = 22000, .max = 400000 },
.vco = { .min = 1750000, .max = 3500000},
.n = { .min = 1, .max = 4 },
@@ -347,7 +346,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
.p2_slow = 10, .p2_fast = 5 },
};
-static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
+static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
.dot = { .min = 20000, .max = 115000 },
.vco = { .min = 1750000, .max = 3500000 },
.n = { .min = 1, .max = 3 },
@@ -361,7 +360,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
},
};
-static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
+static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
.dot = { .min = 80000, .max = 224000 },
.vco = { .min = 1750000, .max = 3500000 },
.n = { .min = 1, .max = 3 },
@@ -375,7 +374,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
},
};
-static const intel_limit_t intel_limits_pineview_sdvo = {
+static const struct intel_limit intel_limits_pineview_sdvo = {
.dot = { .min = 20000, .max = 400000},
.vco = { .min = 1700000, .max = 3500000 },
/* Pineview's Ncounter is a ring counter */
@@ -390,7 +389,7 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
.p2_slow = 10, .p2_fast = 5 },
};
-static const intel_limit_t intel_limits_pineview_lvds = {
+static const struct intel_limit intel_limits_pineview_lvds = {
.dot = { .min = 20000, .max = 400000 },
.vco = { .min = 1700000, .max = 3500000 },
.n = { .min = 3, .max = 6 },
@@ -408,7 +407,7 @@ static const intel_limit_t intel_limits_pineview_lvds = {
* We calculate clock using (register_value + 2) for N/M1/M2, so here
* the range value for them is (actual_value - 2).
*/
-static const intel_limit_t intel_limits_ironlake_dac = {
+static const struct intel_limit intel_limits_ironlake_dac = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 5 },
@@ -421,7 +420,7 @@ static const intel_limit_t intel_limits_ironlake_dac = {
.p2_slow = 10, .p2_fast = 5 },
};
-static const intel_limit_t intel_limits_ironlake_single_lvds = {
+static const struct intel_limit intel_limits_ironlake_single_lvds = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 3 },
@@ -434,7 +433,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds = {
.p2_slow = 14, .p2_fast = 14 },
};
-static const intel_limit_t intel_limits_ironlake_dual_lvds = {
+static const struct intel_limit intel_limits_ironlake_dual_lvds = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 3 },
@@ -448,7 +447,7 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds = {
};
/* LVDS 100mhz refclk limits. */
-static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
+static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 2 },
@@ -461,7 +460,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
.p2_slow = 14, .p2_fast = 14 },
};
-static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
+static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
.dot = { .min = 25000, .max = 350000 },
.vco = { .min = 1760000, .max = 3510000 },
.n = { .min = 1, .max = 3 },
@@ -474,7 +473,7 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
.p2_slow = 7, .p2_fast = 7 },
};
-static const intel_limit_t intel_limits_vlv = {
+static const struct intel_limit intel_limits_vlv = {
/*
* These are the data rate limits (measured in fast clocks)
* since those are the strictest limits we have. The fast
@@ -490,7 +489,7 @@ static const intel_limit_t intel_limits_vlv = {
.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
};
-static const intel_limit_t intel_limits_chv = {
+static const struct intel_limit intel_limits_chv = {
/*
* These are the data rate limits (measured in fast clocks)
* since those are the strictest limits we have. The fast
@@ -506,7 +505,7 @@ static const intel_limit_t intel_limits_chv = {
.p2 = { .p2_slow = 1, .p2_fast = 14 },
};
-static const intel_limit_t intel_limits_bxt = {
+static const struct intel_limit intel_limits_bxt = {
/* FIXME: find real dot limits */
.dot = { .min = 0, .max = INT_MAX },
.vco = { .min = 4800000, .max = 6700000 },
@@ -640,7 +639,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
*/
static bool intel_PLL_is_valid(struct drm_device *dev,
- const intel_limit_t *limit,
+ const struct intel_limit *limit,
const struct dpll *clock)
{
if (clock->n < limit->n.min || limit->n.max < clock->n)
@@ -676,7 +675,7 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
}
static int
-i9xx_select_p2_div(const intel_limit_t *limit,
+i9xx_select_p2_div(const struct intel_limit *limit,
const struct intel_crtc_state *crtc_state,
int target)
{
@@ -711,7 +710,7 @@ i9xx_select_p2_div(const intel_limit_t *limit,
* divider from @match_clock used for LVDS downclocking.
*/
static bool
-i9xx_find_best_dpll(const intel_limit_t *limit,
+i9xx_find_best_dpll(const struct intel_limit *limit,
struct intel_crtc_state *crtc_state,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
@@ -768,7 +767,7 @@ i9xx_find_best_dpll(const intel_limit_t *limit,
* divider from @match_clock used for LVDS downclocking.
*/
static bool
-pnv_find_best_dpll(const intel_limit_t *limit,
+pnv_find_best_dpll(const struct intel_limit *limit,
struct intel_crtc_state *crtc_state,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
@@ -823,7 +822,7 @@ pnv_find_best_dpll(const intel_limit_t *limit,
* divider from @match_clock used for LVDS downclocking.
*/
static bool
-g4x_find_best_dpll(const intel_limit_t *limit,
+g4x_find_best_dpll(const struct intel_limit *limit,
struct intel_crtc_state *crtc_state,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
@@ -916,7 +915,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
*/
static bool
-vlv_find_best_dpll(const intel_limit_t *limit,
+vlv_find_best_dpll(const struct intel_limit *limit,
struct intel_crtc_state *crtc_state,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
@@ -975,7 +974,7 @@ vlv_find_best_dpll(const intel_limit_t *limit,
* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
*/
static bool
-chv_find_best_dpll(const intel_limit_t *limit,
+chv_find_best_dpll(const struct intel_limit *limit,
struct intel_crtc_state *crtc_state,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
@@ -1036,7 +1035,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
struct dpll *best_clock)
{
int refclk = 100000;
- const intel_limit_t *limit = &intel_limits_bxt;
+ const struct intel_limit *limit = &intel_limits_bxt;
return chv_find_best_dpll(limit, crtc_state,
target_clock, refclk, NULL, best_clock);
@@ -7810,7 +7809,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- const intel_limit_t *limit;
+ const struct intel_limit *limit;
int refclk = 48000;
memset(&crtc_state->dpll_hw_state, 0,
@@ -7846,7 +7845,7 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- const intel_limit_t *limit;
+ const struct intel_limit *limit;
int refclk = 96000;
memset(&crtc_state->dpll_hw_state, 0,
@@ -7889,7 +7888,7 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- const intel_limit_t *limit;
+ const struct intel_limit *limit;
int refclk = 96000;
memset(&crtc_state->dpll_hw_state, 0,
@@ -7923,7 +7922,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- const intel_limit_t *limit;
+ const struct intel_limit *limit;
int refclk = 96000;
memset(&crtc_state->dpll_hw_state, 0,
@@ -7956,7 +7955,7 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
int refclk = 100000;
- const intel_limit_t *limit = &intel_limits_chv;
+ const struct intel_limit *limit = &intel_limits_chv;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
@@ -7977,7 +7976,7 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
int refclk = 100000;
- const intel_limit_t *limit = &intel_limits_vlv;
+ const struct intel_limit *limit = &intel_limits_vlv;
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
@@ -8898,7 +8897,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
struct dpll reduced_clock;
bool has_reduced_clock = false;
struct intel_shared_dpll *pll;
- const intel_limit_t *limit;
+ const struct intel_limit *limit;
int refclk = 120000;
memset(&crtc_state->dpll_hw_state, 0,
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] drm/i915: Remove intel_limit_t typedef
2016-05-04 9:11 ` [PATCH 3/3] drm/i915: Remove intel_limit_t typedef Ander Conselvan de Oliveira
@ 2016-05-04 9:29 ` Jani Nikula
0 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2016-05-04 9:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
On Wed, 04 May 2016, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> The coding style documentation says the following about typedefs:
>
> "In general, a pointer, or a struct that has elements that can
> reasonably be directly accessed should _never_ be a typedef."
>
> intel_limit_t falls in that category, so just use "struct intel_limit"
> instead.
On the series,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 69 ++++++++++++++++++------------------
> 1 file changed, 34 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a9fad2f..49efc84 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -118,7 +118,6 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
> static void intel_modeset_setup_hw_state(struct drm_device *dev);
> static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
>
> -typedef struct intel_limit intel_limit_t;
> struct intel_limit {
> struct {
> int min, max;
> @@ -253,7 +252,7 @@ intel_fdi_link_freq(struct drm_i915_private *dev_priv,
> return 270000;
> }
>
> -static const intel_limit_t intel_limits_i8xx_dac = {
> +static const struct intel_limit intel_limits_i8xx_dac = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 908000, .max = 1512000 },
> .n = { .min = 2, .max = 16 },
> @@ -266,7 +265,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
> .p2_slow = 4, .p2_fast = 2 },
> };
>
> -static const intel_limit_t intel_limits_i8xx_dvo = {
> +static const struct intel_limit intel_limits_i8xx_dvo = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 908000, .max = 1512000 },
> .n = { .min = 2, .max = 16 },
> @@ -279,7 +278,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
> .p2_slow = 4, .p2_fast = 4 },
> };
>
> -static const intel_limit_t intel_limits_i8xx_lvds = {
> +static const struct intel_limit intel_limits_i8xx_lvds = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 908000, .max = 1512000 },
> .n = { .min = 2, .max = 16 },
> @@ -292,7 +291,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
> .p2_slow = 14, .p2_fast = 7 },
> };
>
> -static const intel_limit_t intel_limits_i9xx_sdvo = {
> +static const struct intel_limit intel_limits_i9xx_sdvo = {
> .dot = { .min = 20000, .max = 400000 },
> .vco = { .min = 1400000, .max = 2800000 },
> .n = { .min = 1, .max = 6 },
> @@ -305,7 +304,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
> .p2_slow = 10, .p2_fast = 5 },
> };
>
> -static const intel_limit_t intel_limits_i9xx_lvds = {
> +static const struct intel_limit intel_limits_i9xx_lvds = {
> .dot = { .min = 20000, .max = 400000 },
> .vco = { .min = 1400000, .max = 2800000 },
> .n = { .min = 1, .max = 6 },
> @@ -319,7 +318,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
> };
>
>
> -static const intel_limit_t intel_limits_g4x_sdvo = {
> +static const struct intel_limit intel_limits_g4x_sdvo = {
> .dot = { .min = 25000, .max = 270000 },
> .vco = { .min = 1750000, .max = 3500000},
> .n = { .min = 1, .max = 4 },
> @@ -334,7 +333,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
> },
> };
>
> -static const intel_limit_t intel_limits_g4x_hdmi = {
> +static const struct intel_limit intel_limits_g4x_hdmi = {
> .dot = { .min = 22000, .max = 400000 },
> .vco = { .min = 1750000, .max = 3500000},
> .n = { .min = 1, .max = 4 },
> @@ -347,7 +346,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
> .p2_slow = 10, .p2_fast = 5 },
> };
>
> -static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
> +static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
> .dot = { .min = 20000, .max = 115000 },
> .vco = { .min = 1750000, .max = 3500000 },
> .n = { .min = 1, .max = 3 },
> @@ -361,7 +360,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
> },
> };
>
> -static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
> +static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
> .dot = { .min = 80000, .max = 224000 },
> .vco = { .min = 1750000, .max = 3500000 },
> .n = { .min = 1, .max = 3 },
> @@ -375,7 +374,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
> },
> };
>
> -static const intel_limit_t intel_limits_pineview_sdvo = {
> +static const struct intel_limit intel_limits_pineview_sdvo = {
> .dot = { .min = 20000, .max = 400000},
> .vco = { .min = 1700000, .max = 3500000 },
> /* Pineview's Ncounter is a ring counter */
> @@ -390,7 +389,7 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
> .p2_slow = 10, .p2_fast = 5 },
> };
>
> -static const intel_limit_t intel_limits_pineview_lvds = {
> +static const struct intel_limit intel_limits_pineview_lvds = {
> .dot = { .min = 20000, .max = 400000 },
> .vco = { .min = 1700000, .max = 3500000 },
> .n = { .min = 3, .max = 6 },
> @@ -408,7 +407,7 @@ static const intel_limit_t intel_limits_pineview_lvds = {
> * We calculate clock using (register_value + 2) for N/M1/M2, so here
> * the range value for them is (actual_value - 2).
> */
> -static const intel_limit_t intel_limits_ironlake_dac = {
> +static const struct intel_limit intel_limits_ironlake_dac = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 1760000, .max = 3510000 },
> .n = { .min = 1, .max = 5 },
> @@ -421,7 +420,7 @@ static const intel_limit_t intel_limits_ironlake_dac = {
> .p2_slow = 10, .p2_fast = 5 },
> };
>
> -static const intel_limit_t intel_limits_ironlake_single_lvds = {
> +static const struct intel_limit intel_limits_ironlake_single_lvds = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 1760000, .max = 3510000 },
> .n = { .min = 1, .max = 3 },
> @@ -434,7 +433,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds = {
> .p2_slow = 14, .p2_fast = 14 },
> };
>
> -static const intel_limit_t intel_limits_ironlake_dual_lvds = {
> +static const struct intel_limit intel_limits_ironlake_dual_lvds = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 1760000, .max = 3510000 },
> .n = { .min = 1, .max = 3 },
> @@ -448,7 +447,7 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds = {
> };
>
> /* LVDS 100mhz refclk limits. */
> -static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
> +static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 1760000, .max = 3510000 },
> .n = { .min = 1, .max = 2 },
> @@ -461,7 +460,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
> .p2_slow = 14, .p2_fast = 14 },
> };
>
> -static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
> +static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
> .dot = { .min = 25000, .max = 350000 },
> .vco = { .min = 1760000, .max = 3510000 },
> .n = { .min = 1, .max = 3 },
> @@ -474,7 +473,7 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
> .p2_slow = 7, .p2_fast = 7 },
> };
>
> -static const intel_limit_t intel_limits_vlv = {
> +static const struct intel_limit intel_limits_vlv = {
> /*
> * These are the data rate limits (measured in fast clocks)
> * since those are the strictest limits we have. The fast
> @@ -490,7 +489,7 @@ static const intel_limit_t intel_limits_vlv = {
> .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
> };
>
> -static const intel_limit_t intel_limits_chv = {
> +static const struct intel_limit intel_limits_chv = {
> /*
> * These are the data rate limits (measured in fast clocks)
> * since those are the strictest limits we have. The fast
> @@ -506,7 +505,7 @@ static const intel_limit_t intel_limits_chv = {
> .p2 = { .p2_slow = 1, .p2_fast = 14 },
> };
>
> -static const intel_limit_t intel_limits_bxt = {
> +static const struct intel_limit intel_limits_bxt = {
> /* FIXME: find real dot limits */
> .dot = { .min = 0, .max = INT_MAX },
> .vco = { .min = 4800000, .max = 6700000 },
> @@ -640,7 +639,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
> */
>
> static bool intel_PLL_is_valid(struct drm_device *dev,
> - const intel_limit_t *limit,
> + const struct intel_limit *limit,
> const struct dpll *clock)
> {
> if (clock->n < limit->n.min || limit->n.max < clock->n)
> @@ -676,7 +675,7 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
> }
>
> static int
> -i9xx_select_p2_div(const intel_limit_t *limit,
> +i9xx_select_p2_div(const struct intel_limit *limit,
> const struct intel_crtc_state *crtc_state,
> int target)
> {
> @@ -711,7 +710,7 @@ i9xx_select_p2_div(const intel_limit_t *limit,
> * divider from @match_clock used for LVDS downclocking.
> */
> static bool
> -i9xx_find_best_dpll(const intel_limit_t *limit,
> +i9xx_find_best_dpll(const struct intel_limit *limit,
> struct intel_crtc_state *crtc_state,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> @@ -768,7 +767,7 @@ i9xx_find_best_dpll(const intel_limit_t *limit,
> * divider from @match_clock used for LVDS downclocking.
> */
> static bool
> -pnv_find_best_dpll(const intel_limit_t *limit,
> +pnv_find_best_dpll(const struct intel_limit *limit,
> struct intel_crtc_state *crtc_state,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> @@ -823,7 +822,7 @@ pnv_find_best_dpll(const intel_limit_t *limit,
> * divider from @match_clock used for LVDS downclocking.
> */
> static bool
> -g4x_find_best_dpll(const intel_limit_t *limit,
> +g4x_find_best_dpll(const struct intel_limit *limit,
> struct intel_crtc_state *crtc_state,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> @@ -916,7 +915,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> */
> static bool
> -vlv_find_best_dpll(const intel_limit_t *limit,
> +vlv_find_best_dpll(const struct intel_limit *limit,
> struct intel_crtc_state *crtc_state,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> @@ -975,7 +974,7 @@ vlv_find_best_dpll(const intel_limit_t *limit,
> * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> */
> static bool
> -chv_find_best_dpll(const intel_limit_t *limit,
> +chv_find_best_dpll(const struct intel_limit *limit,
> struct intel_crtc_state *crtc_state,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> @@ -1036,7 +1035,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
> struct dpll *best_clock)
> {
> int refclk = 100000;
> - const intel_limit_t *limit = &intel_limits_bxt;
> + const struct intel_limit *limit = &intel_limits_bxt;
>
> return chv_find_best_dpll(limit, crtc_state,
> target_clock, refclk, NULL, best_clock);
> @@ -7810,7 +7809,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - const intel_limit_t *limit;
> + const struct intel_limit *limit;
> int refclk = 48000;
>
> memset(&crtc_state->dpll_hw_state, 0,
> @@ -7846,7 +7845,7 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - const intel_limit_t *limit;
> + const struct intel_limit *limit;
> int refclk = 96000;
>
> memset(&crtc_state->dpll_hw_state, 0,
> @@ -7889,7 +7888,7 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - const intel_limit_t *limit;
> + const struct intel_limit *limit;
> int refclk = 96000;
>
> memset(&crtc_state->dpll_hw_state, 0,
> @@ -7923,7 +7922,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - const intel_limit_t *limit;
> + const struct intel_limit *limit;
> int refclk = 96000;
>
> memset(&crtc_state->dpll_hw_state, 0,
> @@ -7956,7 +7955,7 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> int refclk = 100000;
> - const intel_limit_t *limit = &intel_limits_chv;
> + const struct intel_limit *limit = &intel_limits_chv;
>
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
> @@ -7977,7 +7976,7 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> int refclk = 100000;
> - const intel_limit_t *limit = &intel_limits_vlv;
> + const struct intel_limit *limit = &intel_limits_vlv;
>
> memset(&crtc_state->dpll_hw_state, 0,
> sizeof(crtc_state->dpll_hw_state));
> @@ -8898,7 +8897,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> struct dpll reduced_clock;
> bool has_reduced_clock = false;
> struct intel_shared_dpll *pll;
> - const intel_limit_t *limit;
> + const struct intel_limit *limit;
> int refclk = 120000;
>
> memset(&crtc_state->dpll_hw_state, 0,
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] drm/i915: Remove intel_clock_t typedef
2016-05-04 9:11 [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 2/3] drm/i915: Remove intel_range_t and intel_p2_t typedefs Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 3/3] drm/i915: Remove intel_limit_t typedef Ander Conselvan de Oliveira
@ 2016-05-04 9:29 ` Ville Syrjälä
2016-05-04 11:52 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] " Patchwork
2016-05-12 15:12 ` ✗ Ro.CI.BAT: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2016-05-04 9:29 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Wed, May 04, 2016 at 12:11:57PM +0300, Ander Conselvan de Oliveira wrote:
> Just use "struct dpll" everywhere. That's actually shorter than
> intel_clock_t.
I'm thinking we should probably have an intel_ prefix on the thing.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 62 +++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 8 ++---
> 4 files changed, 37 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index de5fb8c..b302cd1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -948,7 +948,7 @@ static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
> {
> struct intel_shared_dpll *pll;
> struct intel_dpll_hw_state *state;
> - intel_clock_t clock;
> + struct dpll clock;
>
> /* For DDI ports we always use a shared PLL. */
> if (WARN_ON(dpll == DPLL_ID_PRIVATE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8262b23..8e41e16 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -582,7 +582,7 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
> * divided-down version of it.
> */
> /* m1 is reserved as 0 in Pineview, n is a ring counter */
> -static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
> +static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
> {
> clock->m = clock->m2 + 2;
> clock->p = clock->p1 * clock->p2;
> @@ -599,7 +599,7 @@ static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
> return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
> }
>
> -static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
> +static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
> {
> clock->m = i9xx_dpll_compute_m(clock);
> clock->p = clock->p1 * clock->p2;
> @@ -611,7 +611,7 @@ static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
> return clock->dot;
> }
>
> -static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
> +static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
> {
> clock->m = clock->m1 * clock->m2;
> clock->p = clock->p1 * clock->p2;
> @@ -623,7 +623,7 @@ static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
> return clock->dot / 5;
> }
>
> -int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
> +int chv_calc_dpll_params(int refclk, struct dpll *clock)
> {
> clock->m = clock->m1 * clock->m2;
> clock->p = clock->p1 * clock->p2;
> @@ -644,7 +644,7 @@ int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
>
> static bool intel_PLL_is_valid(struct drm_device *dev,
> const intel_limit_t *limit,
> - const intel_clock_t *clock)
> + const struct dpll *clock)
> {
> if (clock->n < limit->n.min || limit->n.max < clock->n)
> INTELPllInvalid("n out of range\n");
> @@ -716,11 +716,11 @@ i9xx_select_p2_div(const intel_limit_t *limit,
> static bool
> i9xx_find_best_dpll(const intel_limit_t *limit,
> struct intel_crtc_state *crtc_state,
> - int target, int refclk, intel_clock_t *match_clock,
> - intel_clock_t *best_clock)
> + int target, int refclk, struct dpll *match_clock,
> + struct dpll *best_clock)
> {
> struct drm_device *dev = crtc_state->base.crtc->dev;
> - intel_clock_t clock;
> + struct dpll clock;
> int err = target;
>
> memset(best_clock, 0, sizeof(*best_clock));
> @@ -773,11 +773,11 @@ i9xx_find_best_dpll(const intel_limit_t *limit,
> static bool
> pnv_find_best_dpll(const intel_limit_t *limit,
> struct intel_crtc_state *crtc_state,
> - int target, int refclk, intel_clock_t *match_clock,
> - intel_clock_t *best_clock)
> + int target, int refclk, struct dpll *match_clock,
> + struct dpll *best_clock)
> {
> struct drm_device *dev = crtc_state->base.crtc->dev;
> - intel_clock_t clock;
> + struct dpll clock;
> int err = target;
>
> memset(best_clock, 0, sizeof(*best_clock));
> @@ -828,11 +828,11 @@ pnv_find_best_dpll(const intel_limit_t *limit,
> static bool
> g4x_find_best_dpll(const intel_limit_t *limit,
> struct intel_crtc_state *crtc_state,
> - int target, int refclk, intel_clock_t *match_clock,
> - intel_clock_t *best_clock)
> + int target, int refclk, struct dpll *match_clock,
> + struct dpll *best_clock)
> {
> struct drm_device *dev = crtc_state->base.crtc->dev;
> - intel_clock_t clock;
> + struct dpll clock;
> int max_n;
> bool found = false;
> /* approximately equals target * 0.00585 */
> @@ -878,8 +878,8 @@ g4x_find_best_dpll(const intel_limit_t *limit,
> * best configuration and error found so far. Return the calculated error.
> */
> static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> - const intel_clock_t *calculated_clock,
> - const intel_clock_t *best_clock,
> + const struct dpll *calculated_clock,
> + const struct dpll *best_clock,
> unsigned int best_error_ppm,
> unsigned int *error_ppm)
> {
> @@ -921,12 +921,12 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> static bool
> vlv_find_best_dpll(const intel_limit_t *limit,
> struct intel_crtc_state *crtc_state,
> - int target, int refclk, intel_clock_t *match_clock,
> - intel_clock_t *best_clock)
> + int target, int refclk, struct dpll *match_clock,
> + struct dpll *best_clock)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_device *dev = crtc->base.dev;
> - intel_clock_t clock;
> + struct dpll clock;
> unsigned int bestppm = 1000000;
> /* min update 19.2 MHz */
> int max_n = min(limit->n.max, refclk / 19200);
> @@ -980,13 +980,13 @@ vlv_find_best_dpll(const intel_limit_t *limit,
> static bool
> chv_find_best_dpll(const intel_limit_t *limit,
> struct intel_crtc_state *crtc_state,
> - int target, int refclk, intel_clock_t *match_clock,
> - intel_clock_t *best_clock)
> + int target, int refclk, struct dpll *match_clock,
> + struct dpll *best_clock)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_device *dev = crtc->base.dev;
> unsigned int best_error_ppm;
> - intel_clock_t clock;
> + struct dpll clock;
> uint64_t m2;
> int found = false;
>
> @@ -1036,7 +1036,7 @@ chv_find_best_dpll(const intel_limit_t *limit,
> }
>
> bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
> - intel_clock_t *best_clock)
> + struct dpll *best_clock)
> {
> int refclk = 100000;
> const intel_limit_t *limit = &intel_limits_bxt;
> @@ -7059,7 +7059,7 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
>
> static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state,
> - intel_clock_t *reduced_clock)
> + struct dpll *reduced_clock)
> {
> struct drm_device *dev = crtc->base.dev;
> u32 fp, fp2 = 0;
> @@ -7483,7 +7483,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
>
> static void i9xx_compute_dpll(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state,
> - intel_clock_t *reduced_clock)
> + struct dpll *reduced_clock)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -7559,7 +7559,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
>
> static void i8xx_compute_dpll(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state,
> - intel_clock_t *reduced_clock)
> + struct dpll *reduced_clock)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -8030,7 +8030,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = pipe_config->cpu_transcoder;
> - intel_clock_t clock;
> + struct dpll clock;
> u32 mdiv;
> int refclk = 100000;
>
> @@ -8127,7 +8127,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe = pipe_config->cpu_transcoder;
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> - intel_clock_t clock;
> + struct dpll clock;
> u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
> int refclk = 100000;
>
> @@ -8790,7 +8790,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
>
> static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state,
> - intel_clock_t *reduced_clock)
> + struct dpll *reduced_clock)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> struct drm_device *dev = crtc->dev;
> @@ -8898,7 +8898,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - intel_clock_t reduced_clock;
> + struct dpll reduced_clock;
> bool has_reduced_clock = false;
> struct intel_shared_dpll *pll;
> const intel_limit_t *limit;
> @@ -10628,7 +10628,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> int pipe = pipe_config->cpu_transcoder;
> u32 dpll = pipe_config->dpll_hw_state.dpll;
> u32 fp;
> - intel_clock_t clock;
> + struct dpll clock;
> int port_clock;
> int refclk = i9xx_pll_refclk(dev, pipe_config);
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 639bf02..b57d7ba 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1508,7 +1508,7 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> int clock = crtc_state->port_clock;
>
> if (encoder->type == INTEL_OUTPUT_HDMI) {
> - intel_clock_t best_clock;
> + struct dpll best_clock;
>
> /* Calculate HDMI div */
> /*
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fcc0643..7cdc1e6 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -265,7 +265,7 @@ struct intel_connector {
> struct intel_dp *mst_port;
> };
>
> -typedef struct dpll {
> +struct dpll {
> /* given values */
> int n;
> int m1, m2;
> @@ -275,7 +275,7 @@ typedef struct dpll {
> int vco;
> int m;
> int p;
> -} intel_clock_t;
> +};
>
> struct intel_atomic_state {
> struct drm_atomic_state base;
> @@ -1250,8 +1250,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
> - intel_clock_t *best_clock);
> -int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
> + struct dpll *best_clock);
> +int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
>
> bool intel_crtc_active(struct drm_crtc *crtc);
> void hsw_enable_ips(struct intel_crtc *crtc);
> --
> 2.4.11
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Remove intel_clock_t typedef
2016-05-04 9:11 [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ander Conselvan de Oliveira
` (2 preceding siblings ...)
2016-05-04 9:29 ` [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ville Syrjälä
@ 2016-05-04 11:52 ` Patchwork
2016-05-12 15:12 ` ✗ Ro.CI.BAT: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2016-05-04 11:52 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Remove intel_clock_t typedef
URL : https://patchwork.freedesktop.org/series/6718/
State : failure
== Summary ==
Series 6718v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/6718/revisions/1/mbox/
Test drv_module_reload_basic:
skip -> PASS (bdw-nuci7-2)
Test gem_busy:
Subgroup basic-blt:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-bsd:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-bsd1:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-bsd2:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-parallel-blt:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-parallel-bsd:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-parallel-bsd1:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-parallel-bsd2:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-parallel-render:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-parallel-vebox:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-render:
fail -> PASS (bdw-nuci7-2)
Subgroup basic-vebox:
fail -> PASS (bdw-nuci7-2)
Test gem_cs_tlb:
Subgroup basic-default:
skip -> PASS (bdw-nuci7-2)
Test gem_exec_flush:
Subgroup basic-uc-pro-default:
fail -> PASS (byt-nuc)
Subgroup basic-uc-pro-default-interruptible:
pass -> FAIL (byt-nuc)
Subgroup basic-uc-prw-default:
fail -> PASS (bsw-nuc-2)
Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS (bdw-nuci7-2)
Test gem_sync:
Subgroup basic-each:
dmesg-fail -> PASS (bdw-nuci7-2)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (hsw-gt2)
bdw-nuci7-2 total:231 pass:219 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:231 pass:206 dwarn:0 dfail:0 fail:0 skip:25
bsw-nuc-2 total:230 pass:189 dwarn:0 dfail:0 fail:0 skip:41
byt-nuc total:230 pass:186 dwarn:0 dfail:0 fail:3 skip:41
hsw-brixbox total:231 pass:205 dwarn:0 dfail:0 fail:0 skip:26
hsw-gt2 total:212 pass:191 dwarn:0 dfail:0 fail:1 skip:19
ilk-hp8440p total:231 pass:168 dwarn:0 dfail:0 fail:2 skip:61
skl-i7k-2 total:231 pass:204 dwarn:0 dfail:0 fail:0 skip:27
skl-nuci5 total:231 pass:220 dwarn:0 dfail:0 fail:0 skip:11
snb-x220t total:231 pass:189 dwarn:0 dfail:0 fail:1 skip:41
snb-dellxps failed to collect. IGT log at Patchwork_2134/snb-dellxps/igt.log
Results at /archive/results/CI_IGT_test/Patchwork_2134/
9289da23b38812e3a351eaa1262b93536f81bfa8 drm-intel-nightly: 2016y-05m-04d-10h-35m-24s UTC integration manifest
4fcdcae drm/i915: Remove intel_limit_t typedef
0a7eb2a drm/i915: Remove intel_range_t and intel_p2_t typedefs
b623412 drm/i915: Remove intel_clock_t typedef
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Ro.CI.BAT: failure for series starting with [1/3] drm/i915: Remove intel_clock_t typedef
2016-05-04 9:11 [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ander Conselvan de Oliveira
` (3 preceding siblings ...)
2016-05-04 11:52 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] " Patchwork
@ 2016-05-12 15:12 ` Patchwork
2016-05-13 8:38 ` Conselvan De Oliveira, Ander
4 siblings, 1 reply; 8+ messages in thread
From: Patchwork @ 2016-05-12 15:12 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Remove intel_clock_t typedef
URL : https://patchwork.freedesktop.org/series/6718/
State : failure
== Summary ==
Series 6718v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/6718/revisions/1/mbox
Test core_auth:
Subgroup basic-auth:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test core_prop_blob:
Subgroup basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-subslice-total:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test drv_hangman:
Subgroup error-state-basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test drv_module_reload_basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_basic:
Subgroup bad-close:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup create-close:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup create-fd-close:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_busy:
Subgroup basic-blt:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-bsd:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-bsd1:
skip -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-bsd2:
skip -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-parallel-blt:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-parallel-bsd:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-parallel-bsd1:
skip -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-parallel-bsd2:
skip -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-parallel-render:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-parallel-vebox:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-render:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-vebox:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_close_race:
Subgroup basic-process:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-threads:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_cpu_reloc:
Subgroup basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_cs_prefetch:
Subgroup basic-default:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_cs_tlb:
Subgroup basic-default:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_ctx_basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_ctx_create:
Subgroup basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-files:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_ctx_exec:
Subgroup basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_ctx_param:
Subgroup basic:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-default:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_ctx_switch:
Subgroup basic-default:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Test gem_exec_basic:
Subgroup basic-blt:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-bsd:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-bsd1:
skip -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-bsd2:
skip -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-default:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-render:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup basic-vebox:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
Subgroup gtt-blt:
pass -> INCOMPLETE (ro-hsw-i3-4010u)
WARNING: Long output truncated
fi-snb-i7-2600 failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_863/
86821b8 drm-intel-nightly: 2016y-05m-12d-14h-21m-45s UTC integration manifest
16afcce drm/i915: Remove intel_limit_t typedef
3c45000 drm/i915: Remove intel_range_t and intel_p2_t typedefs
52156a5 drm/i915: Remove intel_clock_t typedef
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: ✗ Ro.CI.BAT: failure for series starting with [1/3] drm/i915: Remove intel_clock_t typedef
2016-05-12 15:12 ` ✗ Ro.CI.BAT: " Patchwork
@ 2016-05-13 8:38 ` Conselvan De Oliveira, Ander
0 siblings, 0 replies; 8+ messages in thread
From: Conselvan De Oliveira, Ander @ 2016-05-13 8:38 UTC (permalink / raw)
To: intel-gfx
On Thu, 2016-05-12 at 15:12 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915: Remove intel_clock_t typedef
> URL : https://patchwork.freedesktop.org/series/6718/
> State : failure
>
> == Summary ==
>
> Series 6718v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/6718/revisions/1/mbox
>
> Test core_auth:
> Subgroup basic-auth:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test core_prop_blob:
> Subgroup basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test drv_getparams_basic:
> Subgroup basic-eu-total:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-subslice-total:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test drv_hangman:
> Subgroup error-state-basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test drv_module_reload_basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_basic:
> Subgroup bad-close:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup create-close:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup create-fd-close:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_busy:
> Subgroup basic-blt:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-bsd:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-bsd1:
> skip -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-bsd2:
> skip -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-parallel-blt:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-parallel-bsd:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-parallel-bsd1:
> skip -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-parallel-bsd2:
> skip -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-parallel-render:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-parallel-vebox:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-render:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-vebox:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_close_race:
> Subgroup basic-process:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-threads:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_cpu_reloc:
> Subgroup basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_cs_prefetch:
> Subgroup basic-default:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_cs_tlb:
> Subgroup basic-default:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_ctx_basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_ctx_create:
> Subgroup basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-files:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_ctx_exec:
> Subgroup basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_ctx_param:
> Subgroup basic:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-default:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_ctx_switch:
> Subgroup basic-default:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Test gem_exec_basic:
> Subgroup basic-blt:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-bsd:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-bsd1:
> skip -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-bsd2:
> skip -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-default:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-render:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup basic-vebox:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
> Subgroup gtt-blt:
> pass -> INCOMPLETE (ro-hsw-i3-4010u)
The dmesg log during the test run is empty.
That shouldn't be caused by renaming a couple of structs, so I pushed the
patches to dinq.
Ander
> WARNING: Long output truncated
> fi-snb-i7-2600 failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_863/
>
> 86821b8 drm-intel-nightly: 2016y-05m-12d-14h-21m-45s UTC integration manifest
> 16afcce drm/i915: Remove intel_limit_t typedef
> 3c45000 drm/i915: Remove intel_range_t and intel_p2_t typedefs
> 52156a5 drm/i915: Remove intel_clock_t typedef
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-05-13 8:38 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-04 9:11 [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 2/3] drm/i915: Remove intel_range_t and intel_p2_t typedefs Ander Conselvan de Oliveira
2016-05-04 9:11 ` [PATCH 3/3] drm/i915: Remove intel_limit_t typedef Ander Conselvan de Oliveira
2016-05-04 9:29 ` Jani Nikula
2016-05-04 9:29 ` [PATCH 1/3] drm/i915: Remove intel_clock_t typedef Ville Syrjälä
2016-05-04 11:52 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] " Patchwork
2016-05-12 15:12 ` ✗ Ro.CI.BAT: " Patchwork
2016-05-13 8:38 ` Conselvan De Oliveira, Ander
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