* [U-Boot] [PATCH] imx: imx7d: fix ahb clock mux 1
@ 2016-05-05 20:42 Stefan Agner
2016-05-09 7:37 ` Stefano Babic
0 siblings, 1 reply; 2+ messages in thread
From: Stefan Agner @ 2016-05-05 20:42 UTC (permalink / raw)
To: u-boot
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
I sent a similar fix to the LKML which has been merged some days
ago:
https://lkml.org/lkml/2016/4/28/767
--
Stefan
arch/arm/cpu/armv7/mx7/clock_slice.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
index ad5d504..1665df9 100644
--- a/arch/arm/cpu/armv7/mx7/clock_slice.c
+++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
@@ -55,7 +55,7 @@ static struct clk_root_map root_array[] = {
PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
},
{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
},
--
2.8.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] imx: imx7d: fix ahb clock mux 1
2016-05-05 20:42 [U-Boot] [PATCH] imx: imx7d: fix ahb clock mux 1 Stefan Agner
@ 2016-05-09 7:37 ` Stefano Babic
0 siblings, 0 replies; 2+ messages in thread
From: Stefano Babic @ 2016-05-09 7:37 UTC (permalink / raw)
To: u-boot
On 05/05/2016 22:42, Stefan Agner wrote:
> The clock parent of the AHB root clock when using mux option 1
> is the SYS PLL 270MHz clock. This is specified in Table 5-11
> Clock Root Table of the i.MX 7Dual Applications Processor
> Reference Manual.
>
> While it could be a documentation error, the 270MHz parent is
> also mentioned in the boot ROM configuration in Table 6-28: The
> clock is by default at 135MHz due to a POST_PODF value of 1
> (=> divider of 2).
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> I sent a similar fix to the LKML which has been merged some days
> ago:
> https://lkml.org/lkml/2016/4/28/767
Thanks for porting this to U-Boot, too.
>
> --
> Stefan
>
> arch/arm/cpu/armv7/mx7/clock_slice.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
> index ad5d504..1665df9 100644
> --- a/arch/arm/cpu/armv7/mx7/clock_slice.c
> +++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
> @@ -55,7 +55,7 @@ static struct clk_root_map root_array[] = {
> PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
> },
> {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
> - {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
> + {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
> PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
> PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
> },
>
Applied to -next, thanks !
Best regards,
Stefano Babic
--
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2016-05-05 20:42 [U-Boot] [PATCH] imx: imx7d: fix ahb clock mux 1 Stefan Agner
2016-05-09 7:37 ` Stefano Babic
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