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From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 5/6] tegra: video: Always use write-through cache on LCD
Date: Sun,  8 May 2016 16:55:21 -0600	[thread overview]
Message-ID: <1462748122-30918-6-git-send-email-sjg@chromium.org> (raw)
In-Reply-To: <1462748122-30918-1-git-send-email-sjg@chromium.org>

This seems to give the best performance, so let's use it always.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
---

Changes in v2: None

 drivers/video/tegra.c | 21 +++------------------
 1 file changed, 3 insertions(+), 18 deletions(-)

diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 5c48c3b..217f05f 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -22,15 +22,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-enum lcd_cache_t {
-	FDT_LCD_CACHE_OFF		= 0,
-	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
-	FDT_LCD_CACHE_WRITE_BACK	= 1 << 1,
-	FDT_LCD_CACHE_FLUSH		= 1 << 2,
-	FDT_LCD_CACHE_WRITE_BACK_FLUSH	= FDT_LCD_CACHE_WRITE_BACK |
-						FDT_LCD_CACHE_FLUSH,
-};
-
 /* Information about the display controller */
 struct tegra_lcd_priv {
 	int width;			/* width in pixels */
@@ -41,7 +32,6 @@ struct tegra_lcd_priv {
 	struct disp_ctlr *disp;		/* Display controller to use */
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
 	unsigned pixel_clock;		/* Pixel clock in Hz */
-	enum lcd_cache_t cache_type;
 };
 
 enum {
@@ -310,7 +300,6 @@ static int tegra_lcd_probe(struct udevice *dev)
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
 	const void *blob = gd->fdt_blob;
-	int type = DCACHE_OFF;
 	int ret;
 
 	/* Initialize the Tegra display controller */
@@ -329,15 +318,11 @@ static int tegra_lcd_probe(struct udevice *dev)
 		return ret;
 	}
 
-	/* Set up the LCD caching as requested */
-	if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
-		type = DCACHE_WRITETHROUGH;
-	else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
-		type = DCACHE_WRITEBACK;
-	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
+	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
+					DCACHE_WRITETHROUGH);
 
 	/* Enable flushing after LCD writes if requested */
-	video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
+	video_set_flush_dcache(dev, true);
 
 	uc_priv->xsize = priv->width;
 	uc_priv->ysize = priv->height;
-- 
2.8.0.rc3.226.g39d4020

  parent reply	other threads:[~2016-05-08 22:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass
2016-05-08 22:55 ` [U-Boot] [PATCH v2 1/6] errno: Add copyright header and header guard Simon Glass
2016-05-08 22:55 ` [U-Boot] [PATCH v2 2/6] errno: Allow errno_str() to be used without CONFIG_ERRNO_STR Simon Glass
2016-05-08 22:55 ` [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux Simon Glass
2016-05-09 17:09   ` Stephen Warren
2016-05-09 19:26     ` Simon Glass
2016-05-10 17:45       ` Stephen Warren
2016-05-13  3:11         ` Simon Glass
2016-05-08 22:55 ` [U-Boot] [PATCH v2 4/6] video: tegra: Move to using simple-panel and pwm-backlight Simon Glass
2016-05-08 22:55 ` Simon Glass [this message]
2016-05-08 22:55 ` [U-Boot] [PATCH v2 6/6] fdt: Drop some unused compatible strings Simon Glass
2016-05-09 16:53 ` [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Stephen Warren

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