From: Eric Anholt <eric@anholt.net> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org> Cc: linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stephen Warren <swarren@wwwdotorg.org>, Lee Jones <lee@kernel.org>, Eric Anholt <eric@anholt.net> Subject: [PATCH 3/3] clk: bcm2835: Skip PLLC clocks when deciding on a new clock parent Date: Mon, 9 May 2016 18:01:30 -0700 [thread overview] Message-ID: <1462842090-2017-4-git-send-email-eric@anholt.net> (raw) In-Reply-To: <1462842090-2017-1-git-send-email-eric@anholt.net> If the firmware had set up a clock to source from PLLC, go along with it. But if we're looking for a new parent, we don't want to switch it to PLLC because the firmware will force PLLC (and thus the AXI bus clock) to different frequencies during over-temp/under-voltage, without notification to Linux. On my system, this moves the Linux-enabled HDMI state machine and DSI1 escape clock over to plld_per from pllc_per. EMMC still ends up on pllc_per, because the firmware had set it up to use that. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") --- No changes, just a resend. drivers/clk/bcm/clk-bcm2835.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 1091012ecec6..1d8f29ea9f69 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1008,16 +1008,28 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, return 0; } +static bool +bcm2835_clk_is_pllc(struct clk_hw *hw) +{ + if (!hw) + return false; + + return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; +} + static int bcm2835_clock_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct clk_hw *parent, *best_parent = NULL; + bool current_parent_is_pllc; unsigned long rate, best_rate = 0; unsigned long prate, best_prate = 0; size_t i; u32 div; + current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); + /* * Select parent clock that results in the closest but lower rate */ @@ -1025,6 +1037,17 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw, parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; + + /* + * Don't choose a PLLC-derived clock as our parent + * unless it had been manually set that way. PLLC's + * frequency gets adjusted by the firmware due to + * over-temp or under-voltage conditions, without + * prior notification to our clock consumer. + */ + if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) + continue; + prate = clk_hw_get_rate(parent); div = bcm2835_clock_choose_div(hw, req->rate, prate, true); rate = bcm2835_clock_rate_from_divisor(clock, prate, div); -- 2.8.0.rc3
WARNING: multiple messages have this Message-ID (diff)
From: eric@anholt.net (Eric Anholt) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] clk: bcm2835: Skip PLLC clocks when deciding on a new clock parent Date: Mon, 9 May 2016 18:01:30 -0700 [thread overview] Message-ID: <1462842090-2017-4-git-send-email-eric@anholt.net> (raw) In-Reply-To: <1462842090-2017-1-git-send-email-eric@anholt.net> If the firmware had set up a clock to source from PLLC, go along with it. But if we're looking for a new parent, we don't want to switch it to PLLC because the firmware will force PLLC (and thus the AXI bus clock) to different frequencies during over-temp/under-voltage, without notification to Linux. On my system, this moves the Linux-enabled HDMI state machine and DSI1 escape clock over to plld_per from pllc_per. EMMC still ends up on pllc_per, because the firmware had set it up to use that. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") --- No changes, just a resend. drivers/clk/bcm/clk-bcm2835.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 1091012ecec6..1d8f29ea9f69 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1008,16 +1008,28 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, return 0; } +static bool +bcm2835_clk_is_pllc(struct clk_hw *hw) +{ + if (!hw) + return false; + + return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; +} + static int bcm2835_clock_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct clk_hw *parent, *best_parent = NULL; + bool current_parent_is_pllc; unsigned long rate, best_rate = 0; unsigned long prate, best_prate = 0; size_t i; u32 div; + current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); + /* * Select parent clock that results in the closest but lower rate */ @@ -1025,6 +1037,17 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw, parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; + + /* + * Don't choose a PLLC-derived clock as our parent + * unless it had been manually set that way. PLLC's + * frequency gets adjusted by the firmware due to + * over-temp or under-voltage conditions, without + * prior notification to our clock consumer. + */ + if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) + continue; + prate = clk_hw_get_rate(parent); div = bcm2835_clock_choose_div(hw, req->rate, prate, true); rate = bcm2835_clock_rate_from_divisor(clock, prate, div); -- 2.8.0.rc3
next prev parent reply other threads:[~2016-05-10 1:02 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-05-10 1:01 [PATCH 0/3] clk: bcm2835: critical clocks and parent selection Eric Anholt 2016-05-10 1:01 ` Eric Anholt 2016-05-10 1:01 ` [PATCH 1/3 v2] clk: bcm2835: Mark the VPU clock as critical Eric Anholt 2016-05-10 1:01 ` Eric Anholt 2016-05-10 1:01 ` [PATCH 2/3] clk: bcm2835: Mark GPIO clocks enabled at boot " Eric Anholt 2016-05-10 1:01 ` Eric Anholt 2016-05-10 1:01 ` Eric Anholt [this message] 2016-05-10 1:01 ` [PATCH 3/3] clk: bcm2835: Skip PLLC clocks when deciding on a new clock parent Eric Anholt 2016-05-11 22:58 ` Stephen Boyd 2016-05-11 22:58 ` Stephen Boyd 2016-05-12 1:45 ` Eric Anholt 2016-05-12 1:45 ` Eric Anholt 2016-05-10 10:32 ` [PATCH 0/3] clk: bcm2835: critical clocks and parent selection Martin Sperl 2016-05-10 10:32 ` Martin Sperl 2016-05-10 17:37 ` Eric Anholt 2016-05-10 17:37 ` Eric Anholt 2016-05-10 19:58 ` Martin Sperl 2016-05-10 19:58 ` Martin Sperl 2016-05-11 8:21 ` Martin Sperl 2016-05-11 8:21 ` Martin Sperl 2016-05-11 16:09 ` Martin Sperl 2016-05-11 16:09 ` Martin Sperl 2016-05-12 18:24 ` Eric Anholt 2016-05-12 18:24 ` Eric Anholt 2016-05-12 18:23 ` Eric Anholt 2016-05-12 18:23 ` Eric Anholt
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